Commit | Line | Data |
---|---|---|
8de50dc2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
e0720416 AT |
2 | /* |
3 | * Copyright (C) Maxime Coquelin 2015 | |
8de50dc2 | 4 | * Copyright (C) STMicroelectronics 2017 |
e0720416 | 5 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
e0720416 AT |
6 | */ |
7 | ||
8 | #include <linux/bitops.h> | |
fb94109b BG |
9 | #include <linux/delay.h> |
10 | #include <linux/hwspinlock.h> | |
e0720416 AT |
11 | #include <linux/interrupt.h> |
12 | #include <linux/io.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/irqchip.h> | |
15 | #include <linux/irqchip/chained_irq.h> | |
16 | #include <linux/irqdomain.h> | |
cfbf9e49 | 17 | #include <linux/module.h> |
e0720416 AT |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
cfbf9e49 | 20 | #include <linux/of_platform.h> |
73958b31 | 21 | #include <linux/syscore_ops.h> |
e0720416 | 22 | |
927abfc4 LB |
23 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
24 | ||
6dd64ee1 LB |
25 | #define IRQS_PER_BANK 32 |
26 | ||
fb94109b | 27 | #define HWSPNLCK_TIMEOUT 1000 /* usec */ |
fb94109b | 28 | |
6dd64ee1 LB |
29 | struct stm32_exti_bank { |
30 | u32 imr_ofst; | |
31 | u32 emr_ofst; | |
32 | u32 rtsr_ofst; | |
33 | u32 ftsr_ofst; | |
34 | u32 swier_ofst; | |
be6230f0 LB |
35 | u32 rpr_ofst; |
36 | u32 fpr_ofst; | |
6dd64ee1 LB |
37 | }; |
38 | ||
be6230f0 LB |
39 | #define UNDEF_REG ~0 |
40 | ||
927abfc4 LB |
41 | struct stm32_desc_irq { |
42 | u32 exti; | |
43 | u32 irq_parent; | |
9d6a5fe1 | 44 | struct irq_chip *chip; |
927abfc4 LB |
45 | }; |
46 | ||
f9fc1745 LB |
47 | struct stm32_exti_drv_data { |
48 | const struct stm32_exti_bank **exti_banks; | |
927abfc4 | 49 | const struct stm32_desc_irq *desc_irqs; |
f9fc1745 | 50 | u32 bank_nr; |
927abfc4 | 51 | u32 irq_nr; |
f9fc1745 LB |
52 | }; |
53 | ||
d9e2b19b | 54 | struct stm32_exti_chip_data { |
f9fc1745 | 55 | struct stm32_exti_host_data *host_data; |
d9e2b19b | 56 | const struct stm32_exti_bank *reg_bank; |
927abfc4 LB |
57 | struct raw_spinlock rlock; |
58 | u32 wake_active; | |
59 | u32 mask_cache; | |
d9e2b19b LB |
60 | u32 rtsr_cache; |
61 | u32 ftsr_cache; | |
62 | }; | |
63 | ||
f9fc1745 LB |
64 | struct stm32_exti_host_data { |
65 | void __iomem *base; | |
66 | struct stm32_exti_chip_data *chips_data; | |
67 | const struct stm32_exti_drv_data *drv_data; | |
fb94109b | 68 | struct hwspinlock *hwlock; |
f9fc1745 | 69 | }; |
d9e2b19b | 70 | |
73958b31 LB |
71 | static struct stm32_exti_host_data *stm32_host_data; |
72 | ||
6dd64ee1 LB |
73 | static const struct stm32_exti_bank stm32f4xx_exti_b1 = { |
74 | .imr_ofst = 0x00, | |
75 | .emr_ofst = 0x04, | |
76 | .rtsr_ofst = 0x08, | |
77 | .ftsr_ofst = 0x0C, | |
78 | .swier_ofst = 0x10, | |
be6230f0 LB |
79 | .rpr_ofst = 0x14, |
80 | .fpr_ofst = UNDEF_REG, | |
6dd64ee1 LB |
81 | }; |
82 | ||
83 | static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { | |
84 | &stm32f4xx_exti_b1, | |
85 | }; | |
86 | ||
f9fc1745 LB |
87 | static const struct stm32_exti_drv_data stm32f4xx_drv_data = { |
88 | .exti_banks = stm32f4xx_exti_banks, | |
89 | .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), | |
90 | }; | |
91 | ||
539c603e LB |
92 | static const struct stm32_exti_bank stm32h7xx_exti_b1 = { |
93 | .imr_ofst = 0x80, | |
94 | .emr_ofst = 0x84, | |
95 | .rtsr_ofst = 0x00, | |
96 | .ftsr_ofst = 0x04, | |
97 | .swier_ofst = 0x08, | |
be6230f0 LB |
98 | .rpr_ofst = 0x88, |
99 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
100 | }; |
101 | ||
102 | static const struct stm32_exti_bank stm32h7xx_exti_b2 = { | |
103 | .imr_ofst = 0x90, | |
104 | .emr_ofst = 0x94, | |
105 | .rtsr_ofst = 0x20, | |
106 | .ftsr_ofst = 0x24, | |
107 | .swier_ofst = 0x28, | |
be6230f0 LB |
108 | .rpr_ofst = 0x98, |
109 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
110 | }; |
111 | ||
112 | static const struct stm32_exti_bank stm32h7xx_exti_b3 = { | |
113 | .imr_ofst = 0xA0, | |
114 | .emr_ofst = 0xA4, | |
115 | .rtsr_ofst = 0x40, | |
116 | .ftsr_ofst = 0x44, | |
117 | .swier_ofst = 0x48, | |
be6230f0 LB |
118 | .rpr_ofst = 0xA8, |
119 | .fpr_ofst = UNDEF_REG, | |
539c603e LB |
120 | }; |
121 | ||
122 | static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { | |
123 | &stm32h7xx_exti_b1, | |
124 | &stm32h7xx_exti_b2, | |
125 | &stm32h7xx_exti_b3, | |
126 | }; | |
127 | ||
f9fc1745 LB |
128 | static const struct stm32_exti_drv_data stm32h7xx_drv_data = { |
129 | .exti_banks = stm32h7xx_exti_banks, | |
130 | .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), | |
131 | }; | |
132 | ||
927abfc4 LB |
133 | static const struct stm32_exti_bank stm32mp1_exti_b1 = { |
134 | .imr_ofst = 0x80, | |
135 | .emr_ofst = 0x84, | |
136 | .rtsr_ofst = 0x00, | |
137 | .ftsr_ofst = 0x04, | |
138 | .swier_ofst = 0x08, | |
139 | .rpr_ofst = 0x0C, | |
140 | .fpr_ofst = 0x10, | |
141 | }; | |
142 | ||
143 | static const struct stm32_exti_bank stm32mp1_exti_b2 = { | |
144 | .imr_ofst = 0x90, | |
145 | .emr_ofst = 0x94, | |
146 | .rtsr_ofst = 0x20, | |
147 | .ftsr_ofst = 0x24, | |
148 | .swier_ofst = 0x28, | |
149 | .rpr_ofst = 0x2C, | |
150 | .fpr_ofst = 0x30, | |
151 | }; | |
152 | ||
153 | static const struct stm32_exti_bank stm32mp1_exti_b3 = { | |
154 | .imr_ofst = 0xA0, | |
155 | .emr_ofst = 0xA4, | |
156 | .rtsr_ofst = 0x40, | |
157 | .ftsr_ofst = 0x44, | |
158 | .swier_ofst = 0x48, | |
159 | .rpr_ofst = 0x4C, | |
160 | .fpr_ofst = 0x50, | |
161 | }; | |
162 | ||
163 | static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { | |
164 | &stm32mp1_exti_b1, | |
165 | &stm32mp1_exti_b2, | |
166 | &stm32mp1_exti_b3, | |
167 | }; | |
168 | ||
9d6a5fe1 AT |
169 | static struct irq_chip stm32_exti_h_chip; |
170 | static struct irq_chip stm32_exti_h_chip_direct; | |
171 | ||
927abfc4 | 172 | static const struct stm32_desc_irq stm32mp1_desc_irq[] = { |
9d6a5fe1 AT |
173 | { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, |
174 | { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, | |
175 | { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, | |
176 | { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, | |
177 | { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, | |
178 | { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip }, | |
179 | { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip }, | |
180 | { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip }, | |
181 | { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip }, | |
182 | { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip }, | |
183 | { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip }, | |
184 | { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip }, | |
185 | { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip }, | |
186 | { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip }, | |
187 | { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip }, | |
188 | { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip }, | |
189 | { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, | |
190 | { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, | |
191 | { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct }, | |
192 | { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct }, | |
193 | { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, | |
194 | { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct }, | |
195 | { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct }, | |
e12c4550 ELR |
196 | { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct }, |
197 | { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct }, | |
198 | { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct }, | |
199 | { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct }, | |
9d6a5fe1 | 200 | { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct }, |
e12c4550 ELR |
201 | { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct }, |
202 | { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct }, | |
203 | { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct }, | |
9d6a5fe1 | 204 | { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, |
a00e85b5 FG |
205 | { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct }, |
206 | { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct }, | |
207 | { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct }, | |
208 | { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct }, | |
9d6a5fe1 AT |
209 | { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct }, |
210 | { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct }, | |
211 | { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip }, | |
212 | { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip }, | |
213 | { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct }, | |
214 | { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, | |
927abfc4 LB |
215 | }; |
216 | ||
217 | static const struct stm32_exti_drv_data stm32mp1_drv_data = { | |
218 | .exti_banks = stm32mp1_exti_banks, | |
219 | .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), | |
220 | .desc_irqs = stm32mp1_desc_irq, | |
221 | .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), | |
222 | }; | |
223 | ||
9d6a5fe1 AT |
224 | static const struct |
225 | stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, | |
226 | irq_hw_number_t hwirq) | |
927abfc4 | 227 | { |
9d6a5fe1 | 228 | const struct stm32_desc_irq *desc = NULL; |
927abfc4 LB |
229 | int i; |
230 | ||
231 | if (!drv_data->desc_irqs) | |
9d6a5fe1 | 232 | return NULL; |
927abfc4 LB |
233 | |
234 | for (i = 0; i < drv_data->irq_nr; i++) { | |
9d6a5fe1 AT |
235 | desc = &drv_data->desc_irqs[i]; |
236 | if (desc->exti == hwirq) | |
237 | break; | |
927abfc4 LB |
238 | } |
239 | ||
9d6a5fe1 | 240 | return desc; |
927abfc4 LB |
241 | } |
242 | ||
6dd64ee1 LB |
243 | static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) |
244 | { | |
d9e2b19b LB |
245 | struct stm32_exti_chip_data *chip_data = gc->private; |
246 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
247 | unsigned long pending; |
248 | ||
249 | pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); | |
250 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
251 | pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); | |
6dd64ee1 | 252 | |
be6230f0 | 253 | return pending; |
6dd64ee1 LB |
254 | } |
255 | ||
e0720416 AT |
256 | static void stm32_irq_handler(struct irq_desc *desc) |
257 | { | |
258 | struct irq_domain *domain = irq_desc_get_handler_data(desc); | |
e0720416 | 259 | struct irq_chip *chip = irq_desc_get_chip(desc); |
6dd64ee1 LB |
260 | unsigned int virq, nbanks = domain->gc->num_chips; |
261 | struct irq_chip_generic *gc; | |
e0720416 | 262 | unsigned long pending; |
6dd64ee1 | 263 | int n, i, irq_base = 0; |
e0720416 AT |
264 | |
265 | chained_irq_enter(chip, desc); | |
266 | ||
6dd64ee1 LB |
267 | for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { |
268 | gc = irq_get_domain_generic_chip(domain, irq_base); | |
6dd64ee1 LB |
269 | |
270 | while ((pending = stm32_exti_pending(gc))) { | |
271 | for_each_set_bit(n, &pending, IRQS_PER_BANK) { | |
272 | virq = irq_find_mapping(domain, irq_base + n); | |
273 | generic_handle_irq(virq); | |
6dd64ee1 | 274 | } |
e0720416 AT |
275 | } |
276 | } | |
277 | ||
278 | chained_irq_exit(chip, desc); | |
279 | } | |
280 | ||
5a2490e0 LB |
281 | static int stm32_exti_set_type(struct irq_data *d, |
282 | unsigned int type, u32 *rtsr, u32 *ftsr) | |
e0720416 | 283 | { |
5a2490e0 | 284 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); |
e0720416 AT |
285 | |
286 | switch (type) { | |
287 | case IRQ_TYPE_EDGE_RISING: | |
5a2490e0 LB |
288 | *rtsr |= mask; |
289 | *ftsr &= ~mask; | |
e0720416 AT |
290 | break; |
291 | case IRQ_TYPE_EDGE_FALLING: | |
5a2490e0 LB |
292 | *rtsr &= ~mask; |
293 | *ftsr |= mask; | |
e0720416 AT |
294 | break; |
295 | case IRQ_TYPE_EDGE_BOTH: | |
5a2490e0 LB |
296 | *rtsr |= mask; |
297 | *ftsr |= mask; | |
e0720416 AT |
298 | break; |
299 | default: | |
e0720416 AT |
300 | return -EINVAL; |
301 | } | |
302 | ||
5a2490e0 LB |
303 | return 0; |
304 | } | |
305 | ||
306 | static int stm32_irq_set_type(struct irq_data *d, unsigned int type) | |
307 | { | |
308 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
309 | struct stm32_exti_chip_data *chip_data = gc->private; | |
310 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
5257169a | 311 | struct hwspinlock *hwlock = chip_data->host_data->hwlock; |
5a2490e0 LB |
312 | u32 rtsr, ftsr; |
313 | int err; | |
314 | ||
315 | irq_gc_lock(gc); | |
316 | ||
5257169a FD |
317 | if (hwlock) { |
318 | err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); | |
319 | if (err) { | |
320 | pr_err("%s can't get hwspinlock (%d)\n", __func__, err); | |
321 | goto unlock; | |
322 | } | |
323 | } | |
fb94109b | 324 | |
5a2490e0 LB |
325 | rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); |
326 | ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); | |
327 | ||
328 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
fb94109b BG |
329 | if (err) |
330 | goto unspinlock; | |
5a2490e0 | 331 | |
6dd64ee1 LB |
332 | irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); |
333 | irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); | |
e0720416 | 334 | |
fb94109b | 335 | unspinlock: |
5257169a FD |
336 | if (hwlock) |
337 | hwspin_unlock_in_atomic(hwlock); | |
fb94109b | 338 | unlock: |
e0720416 AT |
339 | irq_gc_unlock(gc); |
340 | ||
fb94109b | 341 | return err; |
e0720416 AT |
342 | } |
343 | ||
5a2490e0 LB |
344 | static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, |
345 | u32 wake_active) | |
e0720416 | 346 | { |
d9e2b19b | 347 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; |
5a2490e0 | 348 | void __iomem *base = chip_data->host_data->base; |
e0720416 | 349 | |
d9e2b19b | 350 | /* save rtsr, ftsr registers */ |
5a2490e0 LB |
351 | chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); |
352 | chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
d9e2b19b | 353 | |
5a2490e0 LB |
354 | writel_relaxed(wake_active, base + stm32_bank->imr_ofst); |
355 | } | |
e0720416 | 356 | |
5a2490e0 LB |
357 | static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, |
358 | u32 mask_cache) | |
359 | { | |
360 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
361 | void __iomem *base = chip_data->host_data->base; | |
362 | ||
363 | /* restore rtsr, ftsr, registers */ | |
364 | writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); | |
365 | writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); | |
366 | ||
367 | writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); | |
d9e2b19b | 368 | } |
e0720416 | 369 | |
5a2490e0 | 370 | static void stm32_irq_suspend(struct irq_chip_generic *gc) |
d9e2b19b LB |
371 | { |
372 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b LB |
373 | |
374 | irq_gc_lock(gc); | |
5a2490e0 LB |
375 | stm32_chip_suspend(chip_data, gc->wake_active); |
376 | irq_gc_unlock(gc); | |
377 | } | |
d9e2b19b | 378 | |
5a2490e0 LB |
379 | static void stm32_irq_resume(struct irq_chip_generic *gc) |
380 | { | |
381 | struct stm32_exti_chip_data *chip_data = gc->private; | |
d9e2b19b | 382 | |
5a2490e0 LB |
383 | irq_gc_lock(gc); |
384 | stm32_chip_resume(chip_data, gc->mask_cache); | |
d9e2b19b | 385 | irq_gc_unlock(gc); |
e0720416 AT |
386 | } |
387 | ||
388 | static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, | |
389 | unsigned int nr_irqs, void *data) | |
390 | { | |
e0720416 AT |
391 | struct irq_fwspec *fwspec = data; |
392 | irq_hw_number_t hwirq; | |
393 | ||
394 | hwirq = fwspec->param[0]; | |
395 | ||
396 | irq_map_generic_chip(d, virq, hwirq); | |
e0720416 AT |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
401 | static void stm32_exti_free(struct irq_domain *d, unsigned int virq, | |
402 | unsigned int nr_irqs) | |
403 | { | |
404 | struct irq_data *data = irq_domain_get_irq_data(d, virq); | |
405 | ||
406 | irq_domain_reset_irq_data(data); | |
407 | } | |
408 | ||
ea80aa2a | 409 | static const struct irq_domain_ops irq_exti_domain_ops = { |
e0720416 | 410 | .map = irq_map_generic_chip, |
e0720416 AT |
411 | .alloc = stm32_exti_alloc, |
412 | .free = stm32_exti_free, | |
413 | }; | |
414 | ||
be6230f0 LB |
415 | static void stm32_irq_ack(struct irq_data *d) |
416 | { | |
417 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
d9e2b19b LB |
418 | struct stm32_exti_chip_data *chip_data = gc->private; |
419 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
be6230f0 LB |
420 | |
421 | irq_gc_lock(gc); | |
422 | ||
423 | irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); | |
424 | if (stm32_bank->fpr_ofst != UNDEF_REG) | |
425 | irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); | |
426 | ||
427 | irq_gc_unlock(gc); | |
428 | } | |
927abfc4 | 429 | |
e579076a | 430 | /* directly set the target bit without reading first. */ |
431 | static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) | |
432 | { | |
433 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
434 | void __iomem *base = chip_data->host_data->base; | |
435 | u32 val = BIT(d->hwirq % IRQS_PER_BANK); | |
436 | ||
437 | writel_relaxed(val, base + reg); | |
438 | } | |
439 | ||
927abfc4 LB |
440 | static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) |
441 | { | |
442 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
443 | void __iomem *base = chip_data->host_data->base; | |
444 | u32 val; | |
445 | ||
446 | val = readl_relaxed(base + reg); | |
447 | val |= BIT(d->hwirq % IRQS_PER_BANK); | |
448 | writel_relaxed(val, base + reg); | |
449 | ||
450 | return val; | |
451 | } | |
452 | ||
453 | static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) | |
454 | { | |
455 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
456 | void __iomem *base = chip_data->host_data->base; | |
457 | u32 val; | |
458 | ||
459 | val = readl_relaxed(base + reg); | |
460 | val &= ~BIT(d->hwirq % IRQS_PER_BANK); | |
461 | writel_relaxed(val, base + reg); | |
462 | ||
463 | return val; | |
464 | } | |
465 | ||
466 | static void stm32_exti_h_eoi(struct irq_data *d) | |
467 | { | |
468 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
469 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
470 | ||
471 | raw_spin_lock(&chip_data->rlock); | |
472 | ||
e579076a | 473 | stm32_exti_write_bit(d, stm32_bank->rpr_ofst); |
927abfc4 | 474 | if (stm32_bank->fpr_ofst != UNDEF_REG) |
e579076a | 475 | stm32_exti_write_bit(d, stm32_bank->fpr_ofst); |
927abfc4 LB |
476 | |
477 | raw_spin_unlock(&chip_data->rlock); | |
478 | ||
479 | if (d->parent_data->chip) | |
480 | irq_chip_eoi_parent(d); | |
481 | } | |
482 | ||
483 | static void stm32_exti_h_mask(struct irq_data *d) | |
484 | { | |
485 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
486 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
487 | ||
488 | raw_spin_lock(&chip_data->rlock); | |
489 | chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); | |
490 | raw_spin_unlock(&chip_data->rlock); | |
491 | ||
492 | if (d->parent_data->chip) | |
493 | irq_chip_mask_parent(d); | |
494 | } | |
495 | ||
496 | static void stm32_exti_h_unmask(struct irq_data *d) | |
497 | { | |
498 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
499 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
500 | ||
501 | raw_spin_lock(&chip_data->rlock); | |
502 | chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); | |
503 | raw_spin_unlock(&chip_data->rlock); | |
504 | ||
505 | if (d->parent_data->chip) | |
506 | irq_chip_unmask_parent(d); | |
507 | } | |
508 | ||
509 | static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) | |
510 | { | |
511 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
512 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
5257169a | 513 | struct hwspinlock *hwlock = chip_data->host_data->hwlock; |
927abfc4 LB |
514 | void __iomem *base = chip_data->host_data->base; |
515 | u32 rtsr, ftsr; | |
516 | int err; | |
517 | ||
518 | raw_spin_lock(&chip_data->rlock); | |
fb94109b | 519 | |
5257169a FD |
520 | if (hwlock) { |
521 | err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); | |
522 | if (err) { | |
523 | pr_err("%s can't get hwspinlock (%d)\n", __func__, err); | |
524 | goto unlock; | |
525 | } | |
526 | } | |
fb94109b | 527 | |
927abfc4 LB |
528 | rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); |
529 | ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); | |
530 | ||
531 | err = stm32_exti_set_type(d, type, &rtsr, &ftsr); | |
fb94109b BG |
532 | if (err) |
533 | goto unspinlock; | |
927abfc4 LB |
534 | |
535 | writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); | |
536 | writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); | |
fb94109b BG |
537 | |
538 | unspinlock: | |
5257169a FD |
539 | if (hwlock) |
540 | hwspin_unlock_in_atomic(hwlock); | |
fb94109b | 541 | unlock: |
927abfc4 LB |
542 | raw_spin_unlock(&chip_data->rlock); |
543 | ||
fb94109b | 544 | return err; |
927abfc4 LB |
545 | } |
546 | ||
547 | static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) | |
548 | { | |
549 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
550 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); | |
551 | ||
552 | raw_spin_lock(&chip_data->rlock); | |
553 | ||
554 | if (on) | |
555 | chip_data->wake_active |= mask; | |
556 | else | |
557 | chip_data->wake_active &= ~mask; | |
558 | ||
559 | raw_spin_unlock(&chip_data->rlock); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static int stm32_exti_h_set_affinity(struct irq_data *d, | |
565 | const struct cpumask *dest, bool force) | |
566 | { | |
567 | if (d->parent_data->chip) | |
568 | return irq_chip_set_affinity_parent(d, dest, force); | |
569 | ||
570 | return -EINVAL; | |
571 | } | |
572 | ||
cfbf9e49 | 573 | static int __maybe_unused stm32_exti_h_suspend(void) |
73958b31 LB |
574 | { |
575 | struct stm32_exti_chip_data *chip_data; | |
576 | int i; | |
577 | ||
578 | for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { | |
579 | chip_data = &stm32_host_data->chips_data[i]; | |
580 | raw_spin_lock(&chip_data->rlock); | |
581 | stm32_chip_suspend(chip_data, chip_data->wake_active); | |
582 | raw_spin_unlock(&chip_data->rlock); | |
583 | } | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
cfbf9e49 | 588 | static void __maybe_unused stm32_exti_h_resume(void) |
73958b31 LB |
589 | { |
590 | struct stm32_exti_chip_data *chip_data; | |
591 | int i; | |
592 | ||
593 | for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { | |
594 | chip_data = &stm32_host_data->chips_data[i]; | |
595 | raw_spin_lock(&chip_data->rlock); | |
596 | stm32_chip_resume(chip_data, chip_data->mask_cache); | |
597 | raw_spin_unlock(&chip_data->rlock); | |
598 | } | |
599 | } | |
600 | ||
601 | static struct syscore_ops stm32_exti_h_syscore_ops = { | |
cfbf9e49 | 602 | #ifdef CONFIG_PM_SLEEP |
73958b31 LB |
603 | .suspend = stm32_exti_h_suspend, |
604 | .resume = stm32_exti_h_resume, | |
cfbf9e49 | 605 | #endif |
73958b31 LB |
606 | }; |
607 | ||
cfbf9e49 | 608 | static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) |
73958b31 | 609 | { |
cfbf9e49 | 610 | stm32_host_data = host_data; |
73958b31 LB |
611 | register_syscore_ops(&stm32_exti_h_syscore_ops); |
612 | } | |
cfbf9e49 FD |
613 | |
614 | static void stm32_exti_h_syscore_deinit(void) | |
615 | { | |
616 | unregister_syscore_ops(&stm32_exti_h_syscore_ops); | |
617 | } | |
73958b31 | 618 | |
25591d4c AT |
619 | static int stm32_exti_h_retrigger(struct irq_data *d) |
620 | { | |
621 | struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
622 | const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; | |
623 | void __iomem *base = chip_data->host_data->base; | |
624 | u32 mask = BIT(d->hwirq % IRQS_PER_BANK); | |
625 | ||
626 | writel_relaxed(mask, base + stm32_bank->swier_ofst); | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
927abfc4 LB |
631 | static struct irq_chip stm32_exti_h_chip = { |
632 | .name = "stm32-exti-h", | |
633 | .irq_eoi = stm32_exti_h_eoi, | |
634 | .irq_mask = stm32_exti_h_mask, | |
635 | .irq_unmask = stm32_exti_h_unmask, | |
25591d4c | 636 | .irq_retrigger = stm32_exti_h_retrigger, |
927abfc4 LB |
637 | .irq_set_type = stm32_exti_h_set_type, |
638 | .irq_set_wake = stm32_exti_h_set_wake, | |
639 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
a84277bf | 640 | .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, |
927abfc4 LB |
641 | }; |
642 | ||
9d6a5fe1 AT |
643 | static struct irq_chip stm32_exti_h_chip_direct = { |
644 | .name = "stm32-exti-h-direct", | |
645 | .irq_eoi = irq_chip_eoi_parent, | |
646 | .irq_ack = irq_chip_ack_parent, | |
647 | .irq_mask = irq_chip_mask_parent, | |
648 | .irq_unmask = irq_chip_unmask_parent, | |
649 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
650 | .irq_set_type = irq_chip_set_type_parent, | |
651 | .irq_set_wake = stm32_exti_h_set_wake, | |
652 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
653 | .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, | |
654 | }; | |
655 | ||
927abfc4 LB |
656 | static int stm32_exti_h_domain_alloc(struct irq_domain *dm, |
657 | unsigned int virq, | |
658 | unsigned int nr_irqs, void *data) | |
659 | { | |
660 | struct stm32_exti_host_data *host_data = dm->host_data; | |
661 | struct stm32_exti_chip_data *chip_data; | |
9d6a5fe1 | 662 | const struct stm32_desc_irq *desc; |
927abfc4 LB |
663 | struct irq_fwspec *fwspec = data; |
664 | struct irq_fwspec p_fwspec; | |
665 | irq_hw_number_t hwirq; | |
9d6a5fe1 | 666 | int bank; |
927abfc4 LB |
667 | |
668 | hwirq = fwspec->param[0]; | |
669 | bank = hwirq / IRQS_PER_BANK; | |
670 | chip_data = &host_data->chips_data[bank]; | |
671 | ||
927abfc4 | 672 | |
9d6a5fe1 AT |
673 | desc = stm32_exti_get_desc(host_data->drv_data, hwirq); |
674 | if (!desc) | |
675 | return -EINVAL; | |
676 | ||
677 | irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, | |
678 | chip_data); | |
679 | if (desc->irq_parent) { | |
927abfc4 LB |
680 | p_fwspec.fwnode = dm->parent->fwnode; |
681 | p_fwspec.param_count = 3; | |
682 | p_fwspec.param[0] = GIC_SPI; | |
9d6a5fe1 | 683 | p_fwspec.param[1] = desc->irq_parent; |
927abfc4 LB |
684 | p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; |
685 | ||
686 | return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
f9fc1745 LB |
692 | static struct |
693 | stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, | |
694 | struct device_node *node) | |
695 | { | |
696 | struct stm32_exti_host_data *host_data; | |
697 | ||
698 | host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); | |
699 | if (!host_data) | |
700 | return NULL; | |
701 | ||
702 | host_data->drv_data = dd; | |
703 | host_data->chips_data = kcalloc(dd->bank_nr, | |
704 | sizeof(struct stm32_exti_chip_data), | |
705 | GFP_KERNEL); | |
706 | if (!host_data->chips_data) | |
4096165d | 707 | goto free_host_data; |
f9fc1745 LB |
708 | |
709 | host_data->base = of_iomap(node, 0); | |
710 | if (!host_data->base) { | |
711 | pr_err("%pOF: Unable to map registers\n", node); | |
4096165d | 712 | goto free_chips_data; |
f9fc1745 | 713 | } |
be6230f0 | 714 | |
73958b31 LB |
715 | stm32_host_data = host_data; |
716 | ||
f9fc1745 | 717 | return host_data; |
4096165d DC |
718 | |
719 | free_chips_data: | |
720 | kfree(host_data->chips_data); | |
721 | free_host_data: | |
722 | kfree(host_data); | |
723 | ||
724 | return NULL; | |
f9fc1745 LB |
725 | } |
726 | ||
727 | static struct | |
728 | stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, | |
cfbf9e49 FD |
729 | u32 bank_idx, |
730 | struct device_node *node) | |
f9fc1745 LB |
731 | { |
732 | const struct stm32_exti_bank *stm32_bank; | |
733 | struct stm32_exti_chip_data *chip_data; | |
734 | void __iomem *base = h_data->base; | |
f9fc1745 LB |
735 | |
736 | stm32_bank = h_data->drv_data->exti_banks[bank_idx]; | |
737 | chip_data = &h_data->chips_data[bank_idx]; | |
738 | chip_data->host_data = h_data; | |
739 | chip_data->reg_bank = stm32_bank; | |
740 | ||
927abfc4 LB |
741 | raw_spin_lock_init(&chip_data->rlock); |
742 | ||
f9fc1745 LB |
743 | /* |
744 | * This IP has no reset, so after hot reboot we should | |
745 | * clear registers to avoid residue | |
746 | */ | |
747 | writel_relaxed(0, base + stm32_bank->imr_ofst); | |
748 | writel_relaxed(0, base + stm32_bank->emr_ofst); | |
f9fc1745 | 749 | |
cfbf9e49 | 750 | pr_info("%pOF: bank%d\n", node, bank_idx); |
f9fc1745 LB |
751 | |
752 | return chip_data; | |
753 | } | |
754 | ||
755 | static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, | |
756 | struct device_node *node) | |
e0720416 | 757 | { |
f9fc1745 | 758 | struct stm32_exti_host_data *host_data; |
e0720416 | 759 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
f9fc1745 | 760 | int nr_irqs, ret, i; |
e0720416 AT |
761 | struct irq_chip_generic *gc; |
762 | struct irq_domain *domain; | |
e0720416 | 763 | |
f9fc1745 | 764 | host_data = stm32_exti_host_init(drv_data, node); |
4096165d DC |
765 | if (!host_data) |
766 | return -ENOMEM; | |
e0720416 | 767 | |
f9fc1745 | 768 | domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, |
e0720416 AT |
769 | &irq_exti_domain_ops, NULL); |
770 | if (!domain) { | |
f9c75bca YL |
771 | pr_err("%pOFn: Could not register interrupt domain.\n", |
772 | node); | |
e0720416 AT |
773 | ret = -ENOMEM; |
774 | goto out_unmap; | |
775 | } | |
776 | ||
6dd64ee1 | 777 | ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", |
e0720416 AT |
778 | handle_edge_irq, clr, 0, 0); |
779 | if (ret) { | |
e81f54c6 | 780 | pr_err("%pOF: Could not allocate generic interrupt chip.\n", |
ea80aa2a | 781 | node); |
e0720416 AT |
782 | goto out_free_domain; |
783 | } | |
784 | ||
f9fc1745 LB |
785 | for (i = 0; i < drv_data->bank_nr; i++) { |
786 | const struct stm32_exti_bank *stm32_bank; | |
787 | struct stm32_exti_chip_data *chip_data; | |
6dd64ee1 | 788 | |
f9fc1745 | 789 | stm32_bank = drv_data->exti_banks[i]; |
cfbf9e49 | 790 | chip_data = stm32_exti_chip_init(host_data, i, node); |
d9e2b19b | 791 | |
6dd64ee1 LB |
792 | gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); |
793 | ||
f9fc1745 | 794 | gc->reg_base = host_data->base; |
6dd64ee1 | 795 | gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; |
be6230f0 | 796 | gc->chip_types->chip.irq_ack = stm32_irq_ack; |
6dd64ee1 LB |
797 | gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; |
798 | gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; | |
799 | gc->chip_types->chip.irq_set_type = stm32_irq_set_type; | |
d9e2b19b LB |
800 | gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; |
801 | gc->suspend = stm32_irq_suspend; | |
802 | gc->resume = stm32_irq_resume; | |
803 | gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); | |
804 | ||
6dd64ee1 | 805 | gc->chip_types->regs.mask = stm32_bank->imr_ofst; |
d9e2b19b | 806 | gc->private = (void *)chip_data; |
6dd64ee1 | 807 | } |
e0720416 AT |
808 | |
809 | nr_irqs = of_irq_count(node); | |
810 | for (i = 0; i < nr_irqs; i++) { | |
811 | unsigned int irq = irq_of_parse_and_map(node, i); | |
812 | ||
813 | irq_set_handler_data(irq, domain); | |
814 | irq_set_chained_handler(irq, stm32_irq_handler); | |
815 | } | |
816 | ||
817 | return 0; | |
818 | ||
819 | out_free_domain: | |
820 | irq_domain_remove(domain); | |
821 | out_unmap: | |
f9fc1745 | 822 | iounmap(host_data->base); |
f9fc1745 LB |
823 | kfree(host_data->chips_data); |
824 | kfree(host_data); | |
e0720416 AT |
825 | return ret; |
826 | } | |
827 | ||
927abfc4 LB |
828 | static const struct irq_domain_ops stm32_exti_h_domain_ops = { |
829 | .alloc = stm32_exti_h_domain_alloc, | |
830 | .free = irq_domain_free_irqs_common, | |
1d47f48b | 831 | .xlate = irq_domain_xlate_twocell, |
927abfc4 LB |
832 | }; |
833 | ||
cfbf9e49 FD |
834 | static void stm32_exti_remove_irq(void *data) |
835 | { | |
836 | struct irq_domain *domain = data; | |
837 | ||
838 | irq_domain_remove(domain); | |
839 | } | |
840 | ||
841 | static int stm32_exti_remove(struct platform_device *pdev) | |
842 | { | |
843 | stm32_exti_h_syscore_deinit(); | |
844 | return 0; | |
845 | } | |
846 | ||
847 | static int stm32_exti_probe(struct platform_device *pdev) | |
927abfc4 | 848 | { |
cfbf9e49 FD |
849 | int ret, i; |
850 | struct device *dev = &pdev->dev; | |
851 | struct device_node *np = dev->of_node; | |
927abfc4 LB |
852 | struct irq_domain *parent_domain, *domain; |
853 | struct stm32_exti_host_data *host_data; | |
cfbf9e49 FD |
854 | const struct stm32_exti_drv_data *drv_data; |
855 | struct resource *res; | |
927abfc4 | 856 | |
cfbf9e49 FD |
857 | host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); |
858 | if (!host_data) | |
859 | return -ENOMEM; | |
860 | ||
861 | /* check for optional hwspinlock which may be not available yet */ | |
862 | ret = of_hwspin_lock_get_id(np, 0); | |
863 | if (ret == -EPROBE_DEFER) | |
864 | /* hwspinlock framework not yet ready */ | |
865 | return ret; | |
866 | ||
867 | if (ret >= 0) { | |
868 | host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); | |
869 | if (!host_data->hwlock) { | |
870 | dev_err(dev, "Failed to request hwspinlock\n"); | |
871 | return -EINVAL; | |
872 | } | |
873 | } else if (ret != -ENOENT) { | |
874 | /* note: ENOENT is a valid case (means 'no hwspinlock') */ | |
875 | dev_err(dev, "Failed to get hwspinlock\n"); | |
876 | return ret; | |
927abfc4 LB |
877 | } |
878 | ||
cfbf9e49 FD |
879 | /* initialize host_data */ |
880 | drv_data = of_device_get_match_data(dev); | |
881 | if (!drv_data) { | |
882 | dev_err(dev, "no of match data\n"); | |
883 | return -ENODEV; | |
884 | } | |
885 | host_data->drv_data = drv_data; | |
886 | ||
887 | host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, | |
888 | sizeof(*host_data->chips_data), | |
889 | GFP_KERNEL); | |
890 | if (!host_data->chips_data) | |
4096165d | 891 | return -ENOMEM; |
927abfc4 | 892 | |
cfbf9e49 FD |
893 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
894 | host_data->base = devm_ioremap_resource(dev, res); | |
fbb80d5a | 895 | if (IS_ERR(host_data->base)) |
cfbf9e49 | 896 | return PTR_ERR(host_data->base); |
cfbf9e49 | 897 | |
927abfc4 | 898 | for (i = 0; i < drv_data->bank_nr; i++) |
cfbf9e49 FD |
899 | stm32_exti_chip_init(host_data, i, np); |
900 | ||
901 | parent_domain = irq_find_host(of_irq_find_parent(np)); | |
902 | if (!parent_domain) { | |
903 | dev_err(dev, "GIC interrupt-parent not found\n"); | |
904 | return -EINVAL; | |
905 | } | |
927abfc4 LB |
906 | |
907 | domain = irq_domain_add_hierarchy(parent_domain, 0, | |
908 | drv_data->bank_nr * IRQS_PER_BANK, | |
cfbf9e49 | 909 | np, &stm32_exti_h_domain_ops, |
927abfc4 LB |
910 | host_data); |
911 | ||
912 | if (!domain) { | |
cfbf9e49 FD |
913 | dev_err(dev, "Could not register exti domain\n"); |
914 | return -ENOMEM; | |
927abfc4 LB |
915 | } |
916 | ||
cfbf9e49 FD |
917 | ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); |
918 | if (ret) | |
919 | return ret; | |
920 | ||
921 | stm32_exti_h_syscore_init(host_data); | |
73958b31 | 922 | |
927abfc4 | 923 | return 0; |
cfbf9e49 | 924 | } |
927abfc4 | 925 | |
cfbf9e49 FD |
926 | /* platform driver only for MP1 */ |
927 | static const struct of_device_id stm32_exti_ids[] = { | |
928 | { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, | |
929 | {}, | |
930 | }; | |
931 | MODULE_DEVICE_TABLE(of, stm32_exti_ids); | |
932 | ||
933 | static struct platform_driver stm32_exti_driver = { | |
934 | .probe = stm32_exti_probe, | |
935 | .remove = stm32_exti_remove, | |
936 | .driver = { | |
937 | .name = "stm32_exti", | |
938 | .of_match_table = stm32_exti_ids, | |
939 | }, | |
940 | }; | |
941 | ||
942 | static int __init stm32_exti_arch_init(void) | |
943 | { | |
944 | return platform_driver_register(&stm32_exti_driver); | |
927abfc4 LB |
945 | } |
946 | ||
cfbf9e49 FD |
947 | static void __exit stm32_exti_arch_exit(void) |
948 | { | |
949 | return platform_driver_unregister(&stm32_exti_driver); | |
950 | } | |
951 | ||
952 | arch_initcall(stm32_exti_arch_init); | |
953 | module_exit(stm32_exti_arch_exit); | |
954 | ||
955 | /* no platform driver for F4 and H7 */ | |
6dd64ee1 LB |
956 | static int __init stm32f4_exti_of_init(struct device_node *np, |
957 | struct device_node *parent) | |
958 | { | |
f9fc1745 | 959 | return stm32_exti_init(&stm32f4xx_drv_data, np); |
6dd64ee1 LB |
960 | } |
961 | ||
962 | IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); | |
539c603e LB |
963 | |
964 | static int __init stm32h7_exti_of_init(struct device_node *np, | |
965 | struct device_node *parent) | |
966 | { | |
f9fc1745 | 967 | return stm32_exti_init(&stm32h7xx_drv_data, np); |
539c603e LB |
968 | } |
969 | ||
970 | IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); |