[linux-2.6-block.git] / drivers / irqchip / irq-sifive-plic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 SiFive
 * Copyright (C) 2018 Christoph Hellwig
 */
#define pr_fmt(fmt) "plic: " fmt
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <asm/smp.h>

/*
 * This driver implements a version of the RISC-V PLIC with the actual layout
 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
 *
 *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
 *
 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
 * Spec.
 */

#define MAX_DEVICES			1024
#define MAX_CONTEXTS			15872

/*
 * Each interrupt source has a priority register associated with it.
 * We always hardwire it to one in Linux.
 */
#define PRIORITY_BASE			0
#define     PRIORITY_PER_ID		4

/*
 * Each hart context has a vector of interrupt enable bits associated with it.
 * There's one bit for each interrupt source.
 */
#define CONTEXT_ENABLE_BASE		0x2000
#define     CONTEXT_ENABLE_SIZE		0x80

/*
 * Each hart context has a set of control registers associated with it.  Right
 * now there's only two: a source priority threshold over which the hart will
 * take an interrupt, and a register to claim interrupts.
 */
#define CONTEXT_BASE			0x200000
#define     CONTEXT_SIZE		0x1000
#define     CONTEXT_THRESHOLD		0x00
#define     CONTEXT_CLAIM		0x04

#define	PLIC_DISABLE_THRESHOLD		0x7
#define	PLIC_ENABLE_THRESHOLD		0

#define PLIC_QUIRK_EDGE_INTERRUPT	0

struct plic_priv {
	struct cpumask lmask;
	struct irq_domain *irqdomain;
	void __iomem *regs;
	unsigned long plic_quirks;
	unsigned int nr_irqs;
	unsigned long *prio_save;
};

struct plic_handler {
	bool			present;
	void __iomem		*hart_base;
	/*
	 * Protect mask operations on the registers given that we can't
	 * assume atomic memory operations work on them.
	 */
	raw_spinlock_t		enable_lock;
	void __iomem		*enable_base;
	u32			*enable_save;
	struct plic_priv	*priv;
};
static int plic_parent_irq __ro_after_init;
static bool plic_cpuhp_setup_done __ro_after_init;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);

static int plic_irq_set_type(struct irq_data *d, unsigned int type);

static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
	u32 hwirq_mask = 1 << (hwirq % 32);

	if (enable)
		writel(readl(reg) | hwirq_mask, reg);
	else
		writel(readl(reg) & ~hwirq_mask, reg);
}

static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
{
	raw_spin_lock(&handler->enable_lock);
	__plic_toggle(handler->enable_base, hwirq, enable);
	raw_spin_unlock(&handler->enable_lock);
}

static inline void plic_irq_toggle(const struct cpumask *mask,
				   struct irq_data *d, int enable)
{
	int cpu;

	for_each_cpu(cpu, mask) {
		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

		plic_toggle(handler, d->hwirq, enable);
	}
}

static void plic_irq_enable(struct irq_data *d)
{
	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
}

static void plic_irq_disable(struct irq_data *d)
{
	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
}

static void plic_irq_unmask(struct irq_data *d)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
}

static void plic_irq_mask(struct irq_data *d)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
}

static void plic_irq_eoi(struct irq_data *d)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	if (unlikely(irqd_irq_disabled(d))) {
		plic_toggle(handler, d->hwirq, 1);
		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
		plic_toggle(handler, d->hwirq, 0);
	} else {
		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	}
}

#ifdef CONFIG_SMP
static int plic_set_affinity(struct irq_data *d,
			     const struct cpumask *mask_val, bool force)
{
	unsigned int cpu;
	struct cpumask amask;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	cpumask_and(&amask, &priv->lmask, mask_val);

	if (force)
		cpu = cpumask_first(&amask);
	else
		cpu = cpumask_any_and(&amask, cpu_online_mask);

	if (cpu >= nr_cpu_ids)
		return -EINVAL;

	plic_irq_disable(d);

	irq_data_update_effective_affinity(d, cpumask_of(cpu));

	if (!irqd_irq_disabled(d))
		plic_irq_enable(d);

	return IRQ_SET_MASK_OK_DONE;
}
#endif

static struct irq_chip plic_edge_chip = {
	.name		= "SiFive PLIC",
	.irq_enable	= plic_irq_enable,
	.irq_disable	= plic_irq_disable,
	.irq_ack	= plic_irq_eoi,
	.irq_mask	= plic_irq_mask,
	.irq_unmask	= plic_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = plic_set_affinity,
#endif
	.irq_set_type	= plic_irq_set_type,
	.flags		= IRQCHIP_SKIP_SET_WAKE |
			  IRQCHIP_AFFINITY_PRE_STARTUP,
};

static struct irq_chip plic_chip = {
	.name		= "SiFive PLIC",
	.irq_enable	= plic_irq_enable,
	.irq_disable	= plic_irq_disable,
	.irq_mask	= plic_irq_mask,
	.irq_unmask	= plic_irq_unmask,
	.irq_eoi	= plic_irq_eoi,
#ifdef CONFIG_SMP
	.irq_set_affinity = plic_set_affinity,
#endif
	.irq_set_type	= plic_irq_set_type,
	.flags		= IRQCHIP_SKIP_SET_WAKE |
			  IRQCHIP_AFFINITY_PRE_STARTUP,
};

static int plic_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
		return IRQ_SET_MASK_OK_NOCOPY;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irq_set_chip_handler_name_locked(d, &plic_edge_chip,
						 handle_edge_irq, NULL);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_set_chip_handler_name_locked(d, &plic_chip,
						 handle_fasteoi_irq, NULL);
		break;
	default:
		return -EINVAL;
	}

	return IRQ_SET_MASK_OK;
}

static int plic_irq_suspend(void)
{
	unsigned int i, cpu;
	u32 __iomem *reg;
	struct plic_priv *priv;

	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;

	for (i = 0; i < priv->nr_irqs; i++)
		if (readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID))
			__set_bit(i, priv->prio_save);
		else
			__clear_bit(i, priv->prio_save);

	for_each_cpu(cpu, cpu_present_mask) {
		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

		if (!handler->present)
			continue;

		raw_spin_lock(&handler->enable_lock);
		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
			reg = handler->enable_base + i * sizeof(u32);
			handler->enable_save[i] = readl(reg);
		}
		raw_spin_unlock(&handler->enable_lock);
	}

	return 0;
}

static void plic_irq_resume(void)
{
	unsigned int i, index, cpu;
	u32 __iomem *reg;
	struct plic_priv *priv;

	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;

	for (i = 0; i < priv->nr_irqs; i++) {
		index = BIT_WORD(i);
		writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0,
		       priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID);
	}

	for_each_cpu(cpu, cpu_present_mask) {
		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

		if (!handler->present)
			continue;

		raw_spin_lock(&handler->enable_lock);
		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
			reg = handler->enable_base + i * sizeof(u32);
			writel(handler->enable_save[i], reg);
		}
		raw_spin_unlock(&handler->enable_lock);
	}
}

static struct syscore_ops plic_irq_syscore_ops = {
	.suspend	= plic_irq_suspend,
	.resume		= plic_irq_resume,
};

static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	struct plic_priv *priv = d->host_data;

	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
			    handle_fasteoi_irq, NULL, NULL);
	irq_set_noprobe(irq);
	irq_set_affinity(irq, &priv->lmask);
	return 0;
}

static int plic_irq_domain_translate(struct irq_domain *d,
				     struct irq_fwspec *fwspec,
				     unsigned long *hwirq,
				     unsigned int *type)
{
	struct plic_priv *priv = d->host_data;

	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
		return irq_domain_translate_twocell(d, fwspec, hwirq, type);

	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
}

static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				 unsigned int nr_irqs, void *arg)
{
	int i, ret;
	irq_hw_number_t hwirq;
	unsigned int type;
	struct irq_fwspec *fwspec = arg;

	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++) {
		ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct irq_domain_ops plic_irqdomain_ops = {
	.translate	= plic_irq_domain_translate,
	.alloc		= plic_irq_domain_alloc,
	.free		= irq_domain_free_irqs_top,
};

/*
 * Handling an interrupt is a two-step process: first you claim the interrupt
 * by reading the claim register, then you complete the interrupt by writing
 * that source ID back to the same claim register.  This automatically enables
 * and disables the interrupt, so there's nothing else to do.
 */
static void plic_handle_irq(struct irq_desc *desc)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
	irq_hw_number_t hwirq;

	WARN_ON_ONCE(!handler->present);

	chained_irq_enter(chip, desc);

	while ((hwirq = readl(claim))) {
		int err = generic_handle_domain_irq(handler->priv->irqdomain,
						    hwirq);
		if (unlikely(err))
			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
					hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
{
	/* priority must be > threshold to trigger an interrupt */
	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
}

static int plic_dying_cpu(unsigned int cpu)
{
	if (plic_parent_irq)
		disable_percpu_irq(plic_parent_irq);

	return 0;
}

static int plic_starting_cpu(unsigned int cpu)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	if (plic_parent_irq)
		enable_percpu_irq(plic_parent_irq,
				  irq_get_trigger_type(plic_parent_irq));
	else
		pr_warn("cpu%d: parent irq not available\n", cpu);
	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);

	return 0;
}

static int __init __plic_init(struct device_node *node,
			      struct device_node *parent,
			      unsigned long plic_quirks)
{
	int error = 0, nr_contexts, nr_handlers = 0, i;
	u32 nr_irqs;
	struct plic_priv *priv;
	struct plic_handler *handler;
	unsigned int cpu;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->plic_quirks = plic_quirks;

	priv->regs = of_iomap(node, 0);
	if (WARN_ON(!priv->regs)) {
		error = -EIO;
		goto out_free_priv;
	}

	error = -EINVAL;
	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	if (WARN_ON(!nr_irqs))
		goto out_iounmap;

	priv->nr_irqs = nr_irqs;

	priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL);
	if (!priv->prio_save)
		goto out_free_priority_reg;

	nr_contexts = of_irq_count(node);
	if (WARN_ON(!nr_contexts))
		goto out_free_priority_reg;

	error = -ENOMEM;
	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
			&plic_irqdomain_ops, priv);
	if (WARN_ON(!priv->irqdomain))
		goto out_free_priority_reg;

	for (i = 0; i < nr_contexts; i++) {
		struct of_phandle_args parent;
		irq_hw_number_t hwirq;
		int cpu;
		unsigned long hartid;

		if (of_irq_parse_one(node, i, &parent)) {
			pr_err("failed to parse parent for context %d.\n", i);
			continue;
		}

		/*
		 * Skip contexts other than external interrupts for our
		 * privilege level.
		 */
		if (parent.args[0] != RV_IRQ_EXT) {
			/* Disable S-mode enable bits if running in M-mode. */
			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
				void __iomem *enable_base = priv->regs +
					CONTEXT_ENABLE_BASE +
					i * CONTEXT_ENABLE_SIZE;

				for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
					__plic_toggle(enable_base, hwirq, 0);
			}
			continue;
		}

		error = riscv_of_parent_hartid(parent.np, &hartid);
		if (error < 0) {
			pr_warn("failed to parse hart ID for context %d.\n", i);
			continue;
		}

		cpu = riscv_hartid_to_cpuid(hartid);
		if (cpu < 0) {
			pr_warn("Invalid cpuid for context %d\n", i);
			continue;
		}

		/* Find parent domain and register chained handler */
		if (!plic_parent_irq && irq_find_host(parent.np)) {
			plic_parent_irq = irq_of_parse_and_map(node, i);
			if (plic_parent_irq)
				irq_set_chained_handler(plic_parent_irq,
							plic_handle_irq);
		}

		/*
		 * When running in M-mode we need to ignore the S-mode handler.
		 * Here we assume it always comes later, but that might be a
		 * little fragile.
		 */
		handler = per_cpu_ptr(&plic_handlers, cpu);
		if (handler->present) {
			pr_warn("handler already present for context %d.\n", i);
			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
			goto done;
		}

		cpumask_set_cpu(cpu, &priv->lmask);
		handler->present = true;
		handler->hart_base = priv->regs + CONTEXT_BASE +
			i * CONTEXT_SIZE;
		raw_spin_lock_init(&handler->enable_lock);
		handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
			i * CONTEXT_ENABLE_SIZE;
		handler->priv = priv;

		handler->enable_save =  kcalloc(DIV_ROUND_UP(nr_irqs, 32),
						sizeof(*handler->enable_save), GFP_KERNEL);
		if (!handler->enable_save)
			goto out_free_enable_reg;
done:
		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
			plic_toggle(handler, hwirq, 0);
			writel(1, priv->regs + PRIORITY_BASE +
				  hwirq * PRIORITY_PER_ID);
		}
		nr_handlers++;
	}

	/*
	 * We can have multiple PLIC instances so setup cpuhp state
	 * and register syscore operations only when context handler
	 * for current/boot CPU is present.
	 */
	handler = this_cpu_ptr(&plic_handlers);
	if (handler->present && !plic_cpuhp_setup_done) {
		cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
				  "irqchip/sifive/plic:starting",
				  plic_starting_cpu, plic_dying_cpu);
		register_syscore_ops(&plic_irq_syscore_ops);
		plic_cpuhp_setup_done = true;
	}

	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
		" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
	return 0;

out_free_enable_reg:
	for_each_cpu(cpu, cpu_present_mask) {
		handler = per_cpu_ptr(&plic_handlers, cpu);
		kfree(handler->enable_save);
	}
out_free_priority_reg:
	kfree(priv->prio_save);
out_iounmap:
	iounmap(priv->regs);
out_free_priv:
	kfree(priv);
	return error;
}

static int __init plic_init(struct device_node *node,
			    struct device_node *parent)
{
	return __plic_init(node, parent, 0);
}

IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */

static int __init plic_edge_init(struct device_node *node,
				 struct device_node *parent)
{
	return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
}

IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
Commit	Line	Data
8237f8bc CH	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2017 SiFive
	4	* Copyright (C) 2018 Christoph Hellwig
	5	*/
	6	#define pr_fmt(fmt) "plic: " fmt
ccbe80ba	7	#include <linux/cpu.h>
8237f8bc CH	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/irq.h>
	11	#include <linux/irqchip.h>
6b7ce892	12	#include <linux/irqchip/chained_irq.h>
8237f8bc CH	13	#include <linux/irqdomain.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/spinlock.h>
e80f0b6a	20	#include <linux/syscore_ops.h>
f99fb607	21	#include <asm/smp.h>
8237f8bc CH	22
	23	/*
	24	* This driver implements a version of the RISC-V PLIC with the actual layout
	25	* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
	26	*
	27	* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
	28	*
	29	* The largest number supported by devices marked as 'sifive,plic-1.0.0', is
	30	* 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
	31	* Spec.
	32	*/
	33
	34	#define MAX_DEVICES 1024
	35	#define MAX_CONTEXTS 15872
	36
	37	/*
	38	* Each interrupt source has a priority register associated with it.
	39	* We always hardwire it to one in Linux.
	40	*/
	41	#define PRIORITY_BASE 0
	42	#define PRIORITY_PER_ID 4
	43
	44	/*
	45	* Each hart context has a vector of interrupt enable bits associated with it.
	46	* There's one bit for each interrupt source.
	47	*/
0d3616bb NC	48	#define CONTEXT_ENABLE_BASE 0x2000
0d3616bb NC	49	#define CONTEXT_ENABLE_SIZE 0x80
8237f8bc CH	50
	51	/*
	52	* Each hart context has a set of control registers associated with it. Right
	53	* now there's only two: a source priority threshold over which the hart will
	54	* take an interrupt, and a register to claim interrupts.
	55	*/
	56	#define CONTEXT_BASE 0x200000
0d3616bb	57	#define CONTEXT_SIZE 0x1000
8237f8bc CH	58	#define CONTEXT_THRESHOLD 0x00
	59	#define CONTEXT_CLAIM 0x04
	60
d727be7b	61	#define PLIC_DISABLE_THRESHOLD 0x7
ccbe80ba AP	62	#define PLIC_ENABLE_THRESHOLD 0
ccbe80ba AP	63
dd46337c LP	64	#define PLIC_QUIRK_EDGE_INTERRUPT 0
dd46337c LP	65
f1ad1133 AP	66	struct plic_priv {
	67	struct cpumask lmask;
	68	struct irq_domain *irqdomain;
	69	void __iomem *regs;
dd46337c	70	unsigned long plic_quirks;
e80f0b6a MH	71	unsigned int nr_irqs;
e80f0b6a MH	72	unsigned long *prio_save;
f1ad1133	73	};
8237f8bc CH	74
	75	struct plic_handler {
	76	bool present;
86c7cbf1 AP	77	void __iomem *hart_base;
	78	/*
	79	* Protect mask operations on the registers given that we can't
	80	* assume atomic memory operations work on them.
	81	*/
	82	raw_spinlock_t enable_lock;
	83	void __iomem *enable_base;
e80f0b6a	84	u32 *enable_save;
f1ad1133	85	struct plic_priv *priv;
8237f8bc	86	};
e03b7c1b JZ	87	static int plic_parent_irq __ro_after_init;
e03b7c1b JZ	88	static bool plic_cpuhp_setup_done __ro_after_init;
8237f8bc CH	89	static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
8237f8bc CH	90
dd46337c LP	91	static int plic_irq_set_type(struct irq_data *d, unsigned int type);
dd46337c LP	92
098fdbc3	93	static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
8237f8bc	94	{
098fdbc3	95	u32 __iomem reg = enable_base + (hwirq / 32) sizeof(u32);
8237f8bc CH	96	u32 hwirq_mask = 1 << (hwirq % 32);
8237f8bc CH	97
8237f8bc CH	98	if (enable)
	99	writel(readl(reg) \| hwirq_mask, reg);
	100	else
	101	writel(readl(reg) & ~hwirq_mask, reg);
098fdbc3 NC	102	}
	103
	104	static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
	105	{
	106	raw_spin_lock(&handler->enable_lock);
	107	__plic_toggle(handler->enable_base, hwirq, enable);
86c7cbf1	108	raw_spin_unlock(&handler->enable_lock);
8237f8bc CH	109	}
8237f8bc CH	110
cc9f04f9	111	static inline void plic_irq_toggle(const struct cpumask *mask,
f1ad1133	112	struct irq_data *d, int enable)
8237f8bc CH	113	{
	114	int cpu;
	115
cc9f04f9	116	for_each_cpu(cpu, mask) {
8237f8bc CH	117	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
8237f8bc CH	118
de078949	119	plic_toggle(handler, d->hwirq, enable);
8237f8bc CH	120	}
	121	}
	122
a1706a1c	123	static void plic_irq_enable(struct irq_data *d)
8237f8bc	124	{
de078949	125	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
8237f8bc CH	126	}
8237f8bc CH	127
a1706a1c	128	static void plic_irq_disable(struct irq_data *d)
8237f8bc	129	{
de078949	130	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
8237f8bc CH	131	}
8237f8bc CH	132
a1706a1c SH	133	static void plic_irq_unmask(struct irq_data *d)
	134	{
	135	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	136
	137	writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
	138	}
	139
	140	static void plic_irq_mask(struct irq_data *d)
	141	{
	142	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	143
	144	writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
	145	}
	146
	147	static void plic_irq_eoi(struct irq_data *d)
	148	{
	149	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	150
9c92006b NC	151	if (unlikely(irqd_irq_disabled(d))) {
	152	plic_toggle(handler, d->hwirq, 1);
	153	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	154	plic_toggle(handler, d->hwirq, 0);
	155	} else {
	156	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	157	}
a1706a1c SH	158	}
a1706a1c SH	159
cc9f04f9 AP	160	#ifdef CONFIG_SMP
	161	static int plic_set_affinity(struct irq_data *d,
	162	const struct cpumask *mask_val, bool force)
	163	{
	164	unsigned int cpu;
f1ad1133	165	struct cpumask amask;
f9ac7bbd	166	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
f1ad1133 AP	167
f1ad1133 AP	168	cpumask_and(&amask, &priv->lmask, mask_val);
cc9f04f9 AP	169
cc9f04f9 AP	170	if (force)
f1ad1133	171	cpu = cpumask_first(&amask);
cc9f04f9	172	else
f1ad1133	173	cpu = cpumask_any_and(&amask, cpu_online_mask);
cc9f04f9 AP	174
	175	if (cpu >= nr_cpu_ids)
	176	return -EINVAL;
	177
a1706a1c	178	plic_irq_disable(d);
cc9f04f9 AP	179
	180	irq_data_update_effective_affinity(d, cpumask_of(cpu));
	181
a1706a1c SH	182	if (!irqd_irq_disabled(d))
a1706a1c SH	183	plic_irq_enable(d);
de078949	184
cc9f04f9 AP	185	return IRQ_SET_MASK_OK_DONE;
	186	}
	187	#endif
	188
dd46337c LP	189	static struct irq_chip plic_edge_chip = {
dd46337c LP	190	.name = "SiFive PLIC",
a1706a1c SH	191	.irq_enable = plic_irq_enable,
a1706a1c SH	192	.irq_disable = plic_irq_disable,
dd46337c LP	193	.irq_ack = plic_irq_eoi,
	194	.irq_mask = plic_irq_mask,
	195	.irq_unmask = plic_irq_unmask,
	196	#ifdef CONFIG_SMP
	197	.irq_set_affinity = plic_set_affinity,
	198	#endif
	199	.irq_set_type = plic_irq_set_type,
f5259b04 SH	200	.flags = IRQCHIP_SKIP_SET_WAKE \|
f5259b04 SH	201	IRQCHIP_AFFINITY_PRE_STARTUP,
dd46337c LP	202	};
dd46337c LP	203
8237f8bc CH	204	static struct irq_chip plic_chip = {
8237f8bc CH	205	.name = "SiFive PLIC",
a1706a1c SH	206	.irq_enable = plic_irq_enable,
a1706a1c SH	207	.irq_disable = plic_irq_disable,
bb0fed1c MZ	208	.irq_mask = plic_irq_mask,
	209	.irq_unmask = plic_irq_unmask,
	210	.irq_eoi = plic_irq_eoi,
cc9f04f9 AP	211	#ifdef CONFIG_SMP
	212	.irq_set_affinity = plic_set_affinity,
	213	#endif
dd46337c	214	.irq_set_type = plic_irq_set_type,
f5259b04 SH	215	.flags = IRQCHIP_SKIP_SET_WAKE \|
f5259b04 SH	216	IRQCHIP_AFFINITY_PRE_STARTUP,
8237f8bc CH	217	};
8237f8bc CH	218
dd46337c LP	219	static int plic_irq_set_type(struct irq_data *d, unsigned int type)
	220	{
	221	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	222
	223	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
	224	return IRQ_SET_MASK_OK_NOCOPY;
	225
	226	switch (type) {
	227	case IRQ_TYPE_EDGE_RISING:
	228	irq_set_chip_handler_name_locked(d, &plic_edge_chip,
	229	handle_edge_irq, NULL);
	230	break;
	231	case IRQ_TYPE_LEVEL_HIGH:
	232	irq_set_chip_handler_name_locked(d, &plic_chip,
	233	handle_fasteoi_irq, NULL);
	234	break;
	235	default:
	236	return -EINVAL;
	237	}
	238
	239	return IRQ_SET_MASK_OK;
	240	}
	241
e80f0b6a MH	242	static int plic_irq_suspend(void)
	243	{
	244	unsigned int i, cpu;
	245	u32 __iomem *reg;
	246	struct plic_priv *priv;
	247
	248	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;
	249
	250	for (i = 0; i < priv->nr_irqs; i++)
	251	if (readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID))
	252	__set_bit(i, priv->prio_save);
	253	else
	254	__clear_bit(i, priv->prio_save);
	255
	256	for_each_cpu(cpu, cpu_present_mask) {
	257	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
	258
	259	if (!handler->present)
	260	continue;
	261
	262	raw_spin_lock(&handler->enable_lock);
	263	for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
	264	reg = handler->enable_base + i * sizeof(u32);
	265	handler->enable_save[i] = readl(reg);
	266	}
	267	raw_spin_unlock(&handler->enable_lock);
	268	}
	269
	270	return 0;
	271	}
	272
	273	static void plic_irq_resume(void)
	274	{
	275	unsigned int i, index, cpu;
	276	u32 __iomem *reg;
	277	struct plic_priv *priv;
	278
	279	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;
	280
	281	for (i = 0; i < priv->nr_irqs; i++) {
	282	index = BIT_WORD(i);
	283	writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0,
	284	priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID);
	285	}
	286
	287	for_each_cpu(cpu, cpu_present_mask) {
	288	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
	289
	290	if (!handler->present)
	291	continue;
	292
	293	raw_spin_lock(&handler->enable_lock);
	294	for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
	295	reg = handler->enable_base + i * sizeof(u32);
	296	writel(handler->enable_save[i], reg);
	297	}
	298	raw_spin_unlock(&handler->enable_lock);
	299	}
	300	}
	301
	302	static struct syscore_ops plic_irq_syscore_ops = {
	303	.suspend = plic_irq_suspend,
	304	.resume = plic_irq_resume,
	305	};
306
8237f8bc CH	307	static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
	308	irq_hw_number_t hwirq)
	309	{
2458ed31 AP	310	struct plic_priv *priv = d->host_data;
2458ed31 AP	311
466008f9 YS	312	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
466008f9 YS	313	handle_fasteoi_irq, NULL, NULL);
8237f8bc	314	irq_set_noprobe(irq);
2458ed31	315	irq_set_affinity(irq, &priv->lmask);
8237f8bc CH	316	return 0;
	317	}
	318
dd46337c LP	319	static int plic_irq_domain_translate(struct irq_domain *d,
	320	struct irq_fwspec *fwspec,
	321	unsigned long *hwirq,
	322	unsigned int *type)
	323	{
	324	struct plic_priv *priv = d->host_data;
	325
	326	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
	327	return irq_domain_translate_twocell(d, fwspec, hwirq, type);
	328
	329	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
	330	}
	331
466008f9 YS	332	static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	333	unsigned int nr_irqs, void *arg)
	334	{
	335	int i, ret;
	336	irq_hw_number_t hwirq;
	337	unsigned int type;
	338	struct irq_fwspec *fwspec = arg;
	339
dd46337c	340	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
466008f9 YS	341	if (ret)
	342	return ret;
	343
	344	for (i = 0; i < nr_irqs; i++) {
	345	ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
	346	if (ret)
	347	return ret;
	348	}
	349
	350	return 0;
	351	}
	352
8237f8bc	353	static const struct irq_domain_ops plic_irqdomain_ops = {
dd46337c	354	.translate = plic_irq_domain_translate,
466008f9 YS	355	.alloc = plic_irq_domain_alloc,
466008f9 YS	356	.free = irq_domain_free_irqs_top,
8237f8bc CH	357	};
8237f8bc CH	358
8237f8bc CH	359	/*
	360	* Handling an interrupt is a two-step process: first you claim the interrupt
	361	* by reading the claim register, then you complete the interrupt by writing
	362	* that source ID back to the same claim register. This automatically enables
	363	* and disables the interrupt, so there's nothing else to do.
	364	*/
6b7ce892	365	static void plic_handle_irq(struct irq_desc *desc)
8237f8bc CH	366	{
8237f8bc CH	367	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
6b7ce892	368	struct irq_chip *chip = irq_desc_get_chip(desc);
86c7cbf1	369	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
8237f8bc CH	370	irq_hw_number_t hwirq;
	371
	372	WARN_ON_ONCE(!handler->present);
	373
6b7ce892 AP	374	chained_irq_enter(chip, desc);
6b7ce892 AP	375
8237f8bc	376	while ((hwirq = readl(claim))) {
046a6ee2 MZ	377	int err = generic_handle_domain_irq(handler->priv->irqdomain,
	378	hwirq);
	379	if (unlikely(err))
8237f8bc CH	380	pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
8237f8bc CH	381	hwirq);
8237f8bc	382	}
6b7ce892 AP	383
6b7ce892 AP	384	chained_irq_exit(chip, desc);
8237f8bc CH	385	}
8237f8bc CH	386
ccbe80ba AP	387	static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
	388	{
	389	/* priority must be > threshold to trigger an interrupt */
	390	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
	391	}
	392
	393	static int plic_dying_cpu(unsigned int cpu)
	394	{
6b7ce892 AP	395	if (plic_parent_irq)
6b7ce892 AP	396	disable_percpu_irq(plic_parent_irq);
ccbe80ba AP	397
	398	return 0;
	399	}
	400
	401	static int plic_starting_cpu(unsigned int cpu)
	402	{
	403	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	404
6b7ce892 AP	405	if (plic_parent_irq)
	406	enable_percpu_irq(plic_parent_irq,
	407	irq_get_trigger_type(plic_parent_irq));
	408	else
	409	pr_warn("cpu%d: parent irq not available\n", cpu);
ccbe80ba AP	410	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
	411
	412	return 0;
	413	}
	414
dd46337c LP	415	static int __init __plic_init(struct device_node *node,
	416	struct device_node *parent,
	417	unsigned long plic_quirks)
8237f8bc	418	{
6adfe8d2	419	int error = 0, nr_contexts, nr_handlers = 0, i;
8237f8bc	420	u32 nr_irqs;
f1ad1133	421	struct plic_priv *priv;
2234ae84	422	struct plic_handler *handler;
e80f0b6a	423	unsigned int cpu;
8237f8bc	424
f1ad1133 AP	425	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	426	if (!priv)
	427	return -ENOMEM;
8237f8bc	428
dd46337c LP	429	priv->plic_quirks = plic_quirks;
dd46337c LP	430
f1ad1133 AP	431	priv->regs = of_iomap(node, 0);
	432	if (WARN_ON(!priv->regs)) {
	433	error = -EIO;
	434	goto out_free_priv;
	435	}
8237f8bc CH	436
	437	error = -EINVAL;
	438	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	439	if (WARN_ON(!nr_irqs))
	440	goto out_iounmap;
	441
e80f0b6a MH	442	priv->nr_irqs = nr_irqs;
	443
	444	priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL);
	445	if (!priv->prio_save)
	446	goto out_free_priority_reg;
	447
6adfe8d2 AP	448	nr_contexts = of_irq_count(node);
6adfe8d2 AP	449	if (WARN_ON(!nr_contexts))
e80f0b6a	450	goto out_free_priority_reg;
8237f8bc CH	451
8237f8bc CH	452	error = -ENOMEM;
f1ad1133 AP	453	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
	454	&plic_irqdomain_ops, priv);
	455	if (WARN_ON(!priv->irqdomain))
e80f0b6a	456	goto out_free_priority_reg;
8237f8bc	457
6adfe8d2	458	for (i = 0; i < nr_contexts; i++) {
8237f8bc	459	struct of_phandle_args parent;
8237f8bc	460	irq_hw_number_t hwirq;
ad635e72 S	461	int cpu;
ad635e72 S	462	unsigned long hartid;
8237f8bc CH	463
	464	if (of_irq_parse_one(node, i, &parent)) {
	465	pr_err("failed to parse parent for context %d.\n", i);
	466	continue;
	467	}
	468
a4c3733d CH	469	/*
	470	* Skip contexts other than external interrupts for our
	471	* privilege level.
	472	*/
098fdbc3 NC	473	if (parent.args[0] != RV_IRQ_EXT) {
	474	/* Disable S-mode enable bits if running in M-mode. */
	475	if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
	476	void __iomem *enable_base = priv->regs +
	477	CONTEXT_ENABLE_BASE +
	478	i * CONTEXT_ENABLE_SIZE;
	479
	480	for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
	481	__plic_toggle(enable_base, hwirq, 0);
	482	}
8237f8bc	483	continue;
098fdbc3	484	}
8237f8bc	485
ad635e72 S	486	error = riscv_of_parent_hartid(parent.np, &hartid);
ad635e72 S	487	if (error < 0) {
8237f8bc CH	488	pr_warn("failed to parse hart ID for context %d.\n", i);
	489	continue;
	490	}
	491
f99fb607	492	cpu = riscv_hartid_to_cpuid(hartid);
fc03acae AP	493	if (cpu < 0) {
	494	pr_warn("Invalid cpuid for context %d\n", i);
	495	continue;
	496	}
	497
6b7ce892 AP	498	/* Find parent domain and register chained handler */
	499	if (!plic_parent_irq && irq_find_host(parent.np)) {
	500	plic_parent_irq = irq_of_parse_and_map(node, i);
	501	if (plic_parent_irq)
	502	irq_set_chained_handler(plic_parent_irq,
	503	plic_handle_irq);
	504	}
	505
9ce06497 CH	506	/*
	507	* When running in M-mode we need to ignore the S-mode handler.
	508	* Here we assume it always comes later, but that might be a
	509	* little fragile.
	510	*/
8237f8bc	511	handler = per_cpu_ptr(&plic_handlers, cpu);
3fecb5aa AP	512	if (handler->present) {
3fecb5aa AP	513	pr_warn("handler already present for context %d.\n", i);
ccbe80ba	514	plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
9ce06497	515	goto done;
3fecb5aa AP	516	}
3fecb5aa AP	517
f1ad1133	518	cpumask_set_cpu(cpu, &priv->lmask);
8237f8bc	519	handler->present = true;
0d3616bb NC	520	handler->hart_base = priv->regs + CONTEXT_BASE +
0d3616bb NC	521	i * CONTEXT_SIZE;
86c7cbf1	522	raw_spin_lock_init(&handler->enable_lock);
0d3616bb NC	523	handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
0d3616bb NC	524	i * CONTEXT_ENABLE_SIZE;
f1ad1133	525	handler->priv = priv;
e80f0b6a MH	526
	527	handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32),
	528	sizeof(*handler->enable_save), GFP_KERNEL);
	529	if (!handler->enable_save)
	530	goto out_free_enable_reg;
9ce06497	531	done:
a1706a1c	532	for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
86c7cbf1	533	plic_toggle(handler, hwirq, 0);
a1706a1c SH	534	writel(1, priv->regs + PRIORITY_BASE +
	535	hwirq * PRIORITY_PER_ID);
	536	}
6adfe8d2	537	nr_handlers++;
8237f8bc CH	538	}
8237f8bc CH	539
2234ae84	540	/*
f99b926f AP	541	* We can have multiple PLIC instances so setup cpuhp state
	542	* and register syscore operations only when context handler
	543	* for current/boot CPU is present.
2234ae84 AP	544	*/
	545	handler = this_cpu_ptr(&plic_handlers);
	546	if (handler->present && !plic_cpuhp_setup_done) {
	547	cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
ccbe80ba AP	548	"irqchip/sifive/plic:starting",
ccbe80ba AP	549	plic_starting_cpu, plic_dying_cpu);
f99b926f	550	register_syscore_ops(&plic_irq_syscore_ops);
2234ae84 AP	551	plic_cpuhp_setup_done = true;
	552	}
	553
0e375f51 AP	554	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
0e375f51 AP	555	" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
8237f8bc CH	556	return 0;
8237f8bc CH	557
e80f0b6a MH	558	out_free_enable_reg:
	559	for_each_cpu(cpu, cpu_present_mask) {
	560	handler = per_cpu_ptr(&plic_handlers, cpu);
	561	kfree(handler->enable_save);
	562	}
	563	out_free_priority_reg:
	564	kfree(priv->prio_save);
8237f8bc	565	out_iounmap:
f1ad1133 AP	566	iounmap(priv->regs);
	567	out_free_priv:
	568	kfree(priv);
8237f8bc CH	569	return error;
	570	}
	571
dd46337c LP	572	static int __init plic_init(struct device_node *node,
	573	struct device_node *parent)
	574	{
	575	return __plic_init(node, parent, 0);
	576	}
	577
8237f8bc CH	578	IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
8237f8bc CH	579	IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
dd46337c LP	580
	581	static int __init plic_edge_init(struct device_node *node,
	582	struct device_node *parent)
	583	{
	584	return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
	585	}
	586
	587	IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
5873ba55	588	IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);