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8237f8bc CH |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2017 SiFive | |
4 | * Copyright (C) 2018 Christoph Hellwig | |
5 | */ | |
6 | #define pr_fmt(fmt) "plic: " fmt | |
7 | #include <linux/interrupt.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/irq.h> | |
10 | #include <linux/irqchip.h> | |
11 | #include <linux/irqdomain.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_address.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/spinlock.h> | |
f99fb607 | 18 | #include <asm/smp.h> |
8237f8bc CH |
19 | |
20 | /* | |
21 | * This driver implements a version of the RISC-V PLIC with the actual layout | |
22 | * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: | |
23 | * | |
24 | * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf | |
25 | * | |
26 | * The largest number supported by devices marked as 'sifive,plic-1.0.0', is | |
27 | * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged | |
28 | * Spec. | |
29 | */ | |
30 | ||
31 | #define MAX_DEVICES 1024 | |
32 | #define MAX_CONTEXTS 15872 | |
33 | ||
34 | /* | |
35 | * Each interrupt source has a priority register associated with it. | |
36 | * We always hardwire it to one in Linux. | |
37 | */ | |
38 | #define PRIORITY_BASE 0 | |
39 | #define PRIORITY_PER_ID 4 | |
40 | ||
41 | /* | |
42 | * Each hart context has a vector of interrupt enable bits associated with it. | |
43 | * There's one bit for each interrupt source. | |
44 | */ | |
45 | #define ENABLE_BASE 0x2000 | |
46 | #define ENABLE_PER_HART 0x80 | |
47 | ||
48 | /* | |
49 | * Each hart context has a set of control registers associated with it. Right | |
50 | * now there's only two: a source priority threshold over which the hart will | |
51 | * take an interrupt, and a register to claim interrupts. | |
52 | */ | |
53 | #define CONTEXT_BASE 0x200000 | |
54 | #define CONTEXT_PER_HART 0x1000 | |
55 | #define CONTEXT_THRESHOLD 0x00 | |
56 | #define CONTEXT_CLAIM 0x04 | |
57 | ||
58 | static void __iomem *plic_regs; | |
59 | ||
60 | struct plic_handler { | |
61 | bool present; | |
86c7cbf1 AP |
62 | void __iomem *hart_base; |
63 | /* | |
64 | * Protect mask operations on the registers given that we can't | |
65 | * assume atomic memory operations work on them. | |
66 | */ | |
67 | raw_spinlock_t enable_lock; | |
68 | void __iomem *enable_base; | |
8237f8bc CH |
69 | }; |
70 | static DEFINE_PER_CPU(struct plic_handler, plic_handlers); | |
71 | ||
86c7cbf1 AP |
72 | static inline void plic_toggle(struct plic_handler *handler, |
73 | int hwirq, int enable) | |
8237f8bc | 74 | { |
86c7cbf1 | 75 | u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); |
8237f8bc CH |
76 | u32 hwirq_mask = 1 << (hwirq % 32); |
77 | ||
86c7cbf1 | 78 | raw_spin_lock(&handler->enable_lock); |
8237f8bc CH |
79 | if (enable) |
80 | writel(readl(reg) | hwirq_mask, reg); | |
81 | else | |
82 | writel(readl(reg) & ~hwirq_mask, reg); | |
86c7cbf1 | 83 | raw_spin_unlock(&handler->enable_lock); |
8237f8bc CH |
84 | } |
85 | ||
cc9f04f9 AP |
86 | static inline void plic_irq_toggle(const struct cpumask *mask, |
87 | int hwirq, int enable) | |
8237f8bc CH |
88 | { |
89 | int cpu; | |
90 | ||
cc9f04f9 AP |
91 | writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); |
92 | for_each_cpu(cpu, mask) { | |
8237f8bc CH |
93 | struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); |
94 | ||
95 | if (handler->present) | |
cc9f04f9 | 96 | plic_toggle(handler, hwirq, enable); |
8237f8bc CH |
97 | } |
98 | } | |
99 | ||
100 | static void plic_irq_enable(struct irq_data *d) | |
101 | { | |
cc9f04f9 AP |
102 | unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d), |
103 | cpu_online_mask); | |
104 | if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) | |
105 | return; | |
106 | plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); | |
8237f8bc CH |
107 | } |
108 | ||
109 | static void plic_irq_disable(struct irq_data *d) | |
110 | { | |
cc9f04f9 | 111 | plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); |
8237f8bc CH |
112 | } |
113 | ||
cc9f04f9 AP |
114 | #ifdef CONFIG_SMP |
115 | static int plic_set_affinity(struct irq_data *d, | |
116 | const struct cpumask *mask_val, bool force) | |
117 | { | |
118 | unsigned int cpu; | |
119 | ||
120 | if (force) | |
121 | cpu = cpumask_first(mask_val); | |
122 | else | |
123 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
124 | ||
125 | if (cpu >= nr_cpu_ids) | |
126 | return -EINVAL; | |
127 | ||
128 | if (!irqd_irq_disabled(d)) { | |
129 | plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); | |
130 | plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); | |
131 | } | |
132 | ||
133 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
134 | ||
135 | return IRQ_SET_MASK_OK_DONE; | |
136 | } | |
137 | #endif | |
138 | ||
8237f8bc CH |
139 | static struct irq_chip plic_chip = { |
140 | .name = "SiFive PLIC", | |
141 | /* | |
142 | * There is no need to mask/unmask PLIC interrupts. They are "masked" | |
143 | * by reading claim and "unmasked" when writing it back. | |
144 | */ | |
145 | .irq_enable = plic_irq_enable, | |
146 | .irq_disable = plic_irq_disable, | |
cc9f04f9 AP |
147 | #ifdef CONFIG_SMP |
148 | .irq_set_affinity = plic_set_affinity, | |
149 | #endif | |
8237f8bc CH |
150 | }; |
151 | ||
152 | static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
153 | irq_hw_number_t hwirq) | |
154 | { | |
155 | irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq); | |
156 | irq_set_chip_data(irq, NULL); | |
157 | irq_set_noprobe(irq); | |
158 | return 0; | |
159 | } | |
160 | ||
161 | static const struct irq_domain_ops plic_irqdomain_ops = { | |
162 | .map = plic_irqdomain_map, | |
163 | .xlate = irq_domain_xlate_onecell, | |
164 | }; | |
165 | ||
166 | static struct irq_domain *plic_irqdomain; | |
167 | ||
168 | /* | |
169 | * Handling an interrupt is a two-step process: first you claim the interrupt | |
170 | * by reading the claim register, then you complete the interrupt by writing | |
171 | * that source ID back to the same claim register. This automatically enables | |
172 | * and disables the interrupt, so there's nothing else to do. | |
173 | */ | |
174 | static void plic_handle_irq(struct pt_regs *regs) | |
175 | { | |
176 | struct plic_handler *handler = this_cpu_ptr(&plic_handlers); | |
86c7cbf1 | 177 | void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; |
8237f8bc CH |
178 | irq_hw_number_t hwirq; |
179 | ||
180 | WARN_ON_ONCE(!handler->present); | |
181 | ||
182 | csr_clear(sie, SIE_SEIE); | |
183 | while ((hwirq = readl(claim))) { | |
184 | int irq = irq_find_mapping(plic_irqdomain, hwirq); | |
185 | ||
186 | if (unlikely(irq <= 0)) | |
187 | pr_warn_ratelimited("can't find mapping for hwirq %lu\n", | |
188 | hwirq); | |
189 | else | |
190 | generic_handle_irq(irq); | |
191 | writel(hwirq, claim); | |
192 | } | |
193 | csr_set(sie, SIE_SEIE); | |
194 | } | |
195 | ||
196 | /* | |
197 | * Walk up the DT tree until we find an active RISC-V core (HART) node and | |
198 | * extract the cpuid from it. | |
199 | */ | |
200 | static int plic_find_hart_id(struct device_node *node) | |
201 | { | |
202 | for (; node; node = node->parent) { | |
203 | if (of_device_is_compatible(node, "riscv")) | |
b2f8cfa7 | 204 | return riscv_of_processor_hartid(node); |
8237f8bc CH |
205 | } |
206 | ||
207 | return -1; | |
208 | } | |
209 | ||
210 | static int __init plic_init(struct device_node *node, | |
211 | struct device_node *parent) | |
212 | { | |
6adfe8d2 | 213 | int error = 0, nr_contexts, nr_handlers = 0, i; |
8237f8bc CH |
214 | u32 nr_irqs; |
215 | ||
216 | if (plic_regs) { | |
217 | pr_warn("PLIC already present.\n"); | |
218 | return -ENXIO; | |
219 | } | |
220 | ||
221 | plic_regs = of_iomap(node, 0); | |
222 | if (WARN_ON(!plic_regs)) | |
223 | return -EIO; | |
224 | ||
225 | error = -EINVAL; | |
226 | of_property_read_u32(node, "riscv,ndev", &nr_irqs); | |
227 | if (WARN_ON(!nr_irqs)) | |
228 | goto out_iounmap; | |
229 | ||
6adfe8d2 AP |
230 | nr_contexts = of_irq_count(node); |
231 | if (WARN_ON(!nr_contexts)) | |
8237f8bc | 232 | goto out_iounmap; |
6adfe8d2 | 233 | if (WARN_ON(nr_contexts < num_possible_cpus())) |
8237f8bc CH |
234 | goto out_iounmap; |
235 | ||
236 | error = -ENOMEM; | |
237 | plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1, | |
238 | &plic_irqdomain_ops, NULL); | |
239 | if (WARN_ON(!plic_irqdomain)) | |
240 | goto out_iounmap; | |
241 | ||
6adfe8d2 | 242 | for (i = 0; i < nr_contexts; i++) { |
8237f8bc CH |
243 | struct of_phandle_args parent; |
244 | struct plic_handler *handler; | |
245 | irq_hw_number_t hwirq; | |
f99fb607 | 246 | int cpu, hartid; |
8237f8bc CH |
247 | |
248 | if (of_irq_parse_one(node, i, &parent)) { | |
249 | pr_err("failed to parse parent for context %d.\n", i); | |
250 | continue; | |
251 | } | |
252 | ||
253 | /* skip context holes */ | |
254 | if (parent.args[0] == -1) | |
255 | continue; | |
256 | ||
f99fb607 AP |
257 | hartid = plic_find_hart_id(parent.np); |
258 | if (hartid < 0) { | |
8237f8bc CH |
259 | pr_warn("failed to parse hart ID for context %d.\n", i); |
260 | continue; | |
261 | } | |
262 | ||
f99fb607 | 263 | cpu = riscv_hartid_to_cpuid(hartid); |
fc03acae AP |
264 | if (cpu < 0) { |
265 | pr_warn("Invalid cpuid for context %d\n", i); | |
266 | continue; | |
267 | } | |
268 | ||
8237f8bc | 269 | handler = per_cpu_ptr(&plic_handlers, cpu); |
3fecb5aa AP |
270 | if (handler->present) { |
271 | pr_warn("handler already present for context %d.\n", i); | |
272 | continue; | |
273 | } | |
274 | ||
8237f8bc | 275 | handler->present = true; |
86c7cbf1 AP |
276 | handler->hart_base = |
277 | plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; | |
278 | raw_spin_lock_init(&handler->enable_lock); | |
279 | handler->enable_base = | |
280 | plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; | |
8237f8bc CH |
281 | |
282 | /* priority must be > threshold to trigger an interrupt */ | |
86c7cbf1 | 283 | writel(0, handler->hart_base + CONTEXT_THRESHOLD); |
8237f8bc | 284 | for (hwirq = 1; hwirq <= nr_irqs; hwirq++) |
86c7cbf1 | 285 | plic_toggle(handler, hwirq, 0); |
6adfe8d2 | 286 | nr_handlers++; |
8237f8bc CH |
287 | } |
288 | ||
6adfe8d2 AP |
289 | pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", |
290 | nr_irqs, nr_handlers, nr_contexts); | |
8237f8bc CH |
291 | set_handle_irq(plic_handle_irq); |
292 | return 0; | |
293 | ||
294 | out_iounmap: | |
295 | iounmap(plic_regs); | |
296 | return error; | |
297 | } | |
298 | ||
299 | IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); | |
300 | IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ |