[linux-block.git] / drivers / irqchip / irq-sifive-plic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 SiFive
 * Copyright (C) 2018 Christoph Hellwig
 */
#define pr_fmt(fmt) "plic: " fmt
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <asm/smp.h>

/*
 * This driver implements a version of the RISC-V PLIC with the actual layout
 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
 *
 *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
 *
 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
 * Spec.
 */

#define MAX_DEVICES			1024
#define MAX_CONTEXTS			15872

/*
 * Each interrupt source has a priority register associated with it.
 * We always hardwire it to one in Linux.
 */
#define PRIORITY_BASE			0
#define     PRIORITY_PER_ID		4

/*
 * Each hart context has a vector of interrupt enable bits associated with it.
 * There's one bit for each interrupt source.
 */
#define CONTEXT_ENABLE_BASE		0x2000
#define     CONTEXT_ENABLE_SIZE		0x80

/*
 * Each hart context has a set of control registers associated with it.  Right
 * now there's only two: a source priority threshold over which the hart will
 * take an interrupt, and a register to claim interrupts.
 */
#define CONTEXT_BASE			0x200000
#define     CONTEXT_SIZE		0x1000
#define     CONTEXT_THRESHOLD		0x00
#define     CONTEXT_CLAIM		0x04

#define	PLIC_DISABLE_THRESHOLD		0x7
#define	PLIC_ENABLE_THRESHOLD		0

struct plic_priv {
	struct cpumask lmask;
	struct irq_domain *irqdomain;
	void __iomem *regs;
};

struct plic_handler {
	bool			present;
	void __iomem		*hart_base;
	/*
	 * Protect mask operations on the registers given that we can't
	 * assume atomic memory operations work on them.
	 */
	raw_spinlock_t		enable_lock;
	void __iomem		*enable_base;
	struct plic_priv	*priv;
};
static int plic_parent_irq __ro_after_init;
static bool plic_cpuhp_setup_done __ro_after_init;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);

static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
	u32 hwirq_mask = 1 << (hwirq % 32);

	if (enable)
		writel(readl(reg) | hwirq_mask, reg);
	else
		writel(readl(reg) & ~hwirq_mask, reg);
}

static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
{
	raw_spin_lock(&handler->enable_lock);
	__plic_toggle(handler->enable_base, hwirq, enable);
	raw_spin_unlock(&handler->enable_lock);
}

static inline void plic_irq_toggle(const struct cpumask *mask,
				   struct irq_data *d, int enable)
{
	int cpu;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
	for_each_cpu(cpu, mask) {
		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

		if (handler->present &&
		    cpumask_test_cpu(cpu, &handler->priv->lmask))
			plic_toggle(handler, d->hwirq, enable);
	}
}

static void plic_irq_unmask(struct irq_data *d)
{
	struct cpumask amask;
	unsigned int cpu;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	cpumask_and(&amask, &priv->lmask, cpu_online_mask);
	cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
					   &amask);
	if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
		return;
	plic_irq_toggle(cpumask_of(cpu), d, 1);
}

static void plic_irq_mask(struct irq_data *d)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	plic_irq_toggle(&priv->lmask, d, 0);
}

#ifdef CONFIG_SMP
static int plic_set_affinity(struct irq_data *d,
			     const struct cpumask *mask_val, bool force)
{
	unsigned int cpu;
	struct cpumask amask;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	cpumask_and(&amask, &priv->lmask, mask_val);

	if (force)
		cpu = cpumask_first(&amask);
	else
		cpu = cpumask_any_and(&amask, cpu_online_mask);

	if (cpu >= nr_cpu_ids)
		return -EINVAL;

	plic_irq_toggle(&priv->lmask, d, 0);
	plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));

	irq_data_update_effective_affinity(d, cpumask_of(cpu));

	return IRQ_SET_MASK_OK_DONE;
}
#endif

static void plic_irq_eoi(struct irq_data *d)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	if (irqd_irq_masked(d)) {
		plic_irq_unmask(d);
		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
		plic_irq_mask(d);
	} else {
		writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	}
}

static struct irq_chip plic_chip = {
	.name		= "SiFive PLIC",
	.irq_mask	= plic_irq_mask,
	.irq_unmask	= plic_irq_unmask,
	.irq_eoi	= plic_irq_eoi,
#ifdef CONFIG_SMP
	.irq_set_affinity = plic_set_affinity,
#endif
};

static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	struct plic_priv *priv = d->host_data;

	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
			    handle_fasteoi_irq, NULL, NULL);
	irq_set_noprobe(irq);
	irq_set_affinity(irq, &priv->lmask);
	return 0;
}

static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				 unsigned int nr_irqs, void *arg)
{
	int i, ret;
	irq_hw_number_t hwirq;
	unsigned int type;
	struct irq_fwspec *fwspec = arg;

	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++) {
		ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct irq_domain_ops plic_irqdomain_ops = {
	.translate	= irq_domain_translate_onecell,
	.alloc		= plic_irq_domain_alloc,
	.free		= irq_domain_free_irqs_top,
};

/*
 * Handling an interrupt is a two-step process: first you claim the interrupt
 * by reading the claim register, then you complete the interrupt by writing
 * that source ID back to the same claim register.  This automatically enables
 * and disables the interrupt, so there's nothing else to do.
 */
static void plic_handle_irq(struct irq_desc *desc)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
	irq_hw_number_t hwirq;

	WARN_ON_ONCE(!handler->present);

	chained_irq_enter(chip, desc);

	while ((hwirq = readl(claim))) {
		int err = generic_handle_domain_irq(handler->priv->irqdomain,
						    hwirq);
		if (unlikely(err))
			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
					hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
{
	/* priority must be > threshold to trigger an interrupt */
	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
}

static int plic_dying_cpu(unsigned int cpu)
{
	if (plic_parent_irq)
		disable_percpu_irq(plic_parent_irq);

	return 0;
}

static int plic_starting_cpu(unsigned int cpu)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	if (plic_parent_irq)
		enable_percpu_irq(plic_parent_irq,
				  irq_get_trigger_type(plic_parent_irq));
	else
		pr_warn("cpu%d: parent irq not available\n", cpu);
	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);

	return 0;
}

static int __init plic_init(struct device_node *node,
		struct device_node *parent)
{
	int error = 0, nr_contexts, nr_handlers = 0, i;
	u32 nr_irqs;
	struct plic_priv *priv;
	struct plic_handler *handler;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->regs = of_iomap(node, 0);
	if (WARN_ON(!priv->regs)) {
		error = -EIO;
		goto out_free_priv;
	}

	error = -EINVAL;
	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	if (WARN_ON(!nr_irqs))
		goto out_iounmap;

	nr_contexts = of_irq_count(node);
	if (WARN_ON(!nr_contexts))
		goto out_iounmap;

	error = -ENOMEM;
	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
			&plic_irqdomain_ops, priv);
	if (WARN_ON(!priv->irqdomain))
		goto out_iounmap;

	for (i = 0; i < nr_contexts; i++) {
		struct of_phandle_args parent;
		irq_hw_number_t hwirq;
		int cpu, hartid;

		if (of_irq_parse_one(node, i, &parent)) {
			pr_err("failed to parse parent for context %d.\n", i);
			continue;
		}

		/*
		 * Skip contexts other than external interrupts for our
		 * privilege level.
		 */
		if (parent.args[0] != RV_IRQ_EXT) {
			/* Disable S-mode enable bits if running in M-mode. */
			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
				void __iomem *enable_base = priv->regs +
					CONTEXT_ENABLE_BASE +
					i * CONTEXT_ENABLE_SIZE;

				for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
					__plic_toggle(enable_base, hwirq, 0);
			}
			continue;
		}

		hartid = riscv_of_parent_hartid(parent.np);
		if (hartid < 0) {
			pr_warn("failed to parse hart ID for context %d.\n", i);
			continue;
		}

		cpu = riscv_hartid_to_cpuid(hartid);
		if (cpu < 0) {
			pr_warn("Invalid cpuid for context %d\n", i);
			continue;
		}

		/* Find parent domain and register chained handler */
		if (!plic_parent_irq && irq_find_host(parent.np)) {
			plic_parent_irq = irq_of_parse_and_map(node, i);
			if (plic_parent_irq)
				irq_set_chained_handler(plic_parent_irq,
							plic_handle_irq);
		}

		/*
		 * When running in M-mode we need to ignore the S-mode handler.
		 * Here we assume it always comes later, but that might be a
		 * little fragile.
		 */
		handler = per_cpu_ptr(&plic_handlers, cpu);
		if (handler->present) {
			pr_warn("handler already present for context %d.\n", i);
			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
			goto done;
		}

		cpumask_set_cpu(cpu, &priv->lmask);
		handler->present = true;
		handler->hart_base = priv->regs + CONTEXT_BASE +
			i * CONTEXT_SIZE;
		raw_spin_lock_init(&handler->enable_lock);
		handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
			i * CONTEXT_ENABLE_SIZE;
		handler->priv = priv;
done:
		for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
			plic_toggle(handler, hwirq, 0);
		nr_handlers++;
	}

	/*
	 * We can have multiple PLIC instances so setup cpuhp state only
	 * when context handler for current/boot CPU is present.
	 */
	handler = this_cpu_ptr(&plic_handlers);
	if (handler->present && !plic_cpuhp_setup_done) {
		cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
				  "irqchip/sifive/plic:starting",
				  plic_starting_cpu, plic_dying_cpu);
		plic_cpuhp_setup_done = true;
	}

	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
		" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
	return 0;

out_iounmap:
	iounmap(priv->regs);
out_free_priv:
	kfree(priv);
	return error;
}

IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
Commit	Line	Data
8237f8bc CH	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2017 SiFive
	4	* Copyright (C) 2018 Christoph Hellwig
	5	*/
	6	#define pr_fmt(fmt) "plic: " fmt
ccbe80ba	7	#include <linux/cpu.h>
8237f8bc CH	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/irq.h>
	11	#include <linux/irqchip.h>
6b7ce892	12	#include <linux/irqchip/chained_irq.h>
8237f8bc CH	13	#include <linux/irqdomain.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/spinlock.h>
f99fb607	20	#include <asm/smp.h>
8237f8bc CH	21
	22	/*
	23	* This driver implements a version of the RISC-V PLIC with the actual layout
	24	* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
	25	*
	26	* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
	27	*
	28	* The largest number supported by devices marked as 'sifive,plic-1.0.0', is
	29	* 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
	30	* Spec.
	31	*/
	32
	33	#define MAX_DEVICES 1024
	34	#define MAX_CONTEXTS 15872
	35
	36	/*
	37	* Each interrupt source has a priority register associated with it.
	38	* We always hardwire it to one in Linux.
	39	*/
	40	#define PRIORITY_BASE 0
	41	#define PRIORITY_PER_ID 4
	42
	43	/*
	44	* Each hart context has a vector of interrupt enable bits associated with it.
	45	* There's one bit for each interrupt source.
	46	*/
0d3616bb NC	47	#define CONTEXT_ENABLE_BASE 0x2000
0d3616bb NC	48	#define CONTEXT_ENABLE_SIZE 0x80
8237f8bc CH	49
	50	/*
	51	* Each hart context has a set of control registers associated with it. Right
	52	* now there's only two: a source priority threshold over which the hart will
	53	* take an interrupt, and a register to claim interrupts.
	54	*/
	55	#define CONTEXT_BASE 0x200000
0d3616bb	56	#define CONTEXT_SIZE 0x1000
8237f8bc CH	57	#define CONTEXT_THRESHOLD 0x00
	58	#define CONTEXT_CLAIM 0x04
	59
d727be7b	60	#define PLIC_DISABLE_THRESHOLD 0x7
ccbe80ba AP	61	#define PLIC_ENABLE_THRESHOLD 0
ccbe80ba AP	62
f1ad1133 AP	63	struct plic_priv {
	64	struct cpumask lmask;
	65	struct irq_domain *irqdomain;
	66	void __iomem *regs;
	67	};
8237f8bc CH	68
	69	struct plic_handler {
	70	bool present;
86c7cbf1 AP	71	void __iomem *hart_base;
	72	/*
	73	* Protect mask operations on the registers given that we can't
	74	* assume atomic memory operations work on them.
	75	*/
	76	raw_spinlock_t enable_lock;
	77	void __iomem *enable_base;
f1ad1133	78	struct plic_priv *priv;
8237f8bc	79	};
e03b7c1b JZ	80	static int plic_parent_irq __ro_after_init;
e03b7c1b JZ	81	static bool plic_cpuhp_setup_done __ro_after_init;
8237f8bc CH	82	static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
8237f8bc CH	83
098fdbc3	84	static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
8237f8bc	85	{
098fdbc3	86	u32 __iomem reg = enable_base + (hwirq / 32) sizeof(u32);
8237f8bc CH	87	u32 hwirq_mask = 1 << (hwirq % 32);
8237f8bc CH	88
8237f8bc CH	89	if (enable)
	90	writel(readl(reg) \| hwirq_mask, reg);
	91	else
	92	writel(readl(reg) & ~hwirq_mask, reg);
098fdbc3 NC	93	}
	94
	95	static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
	96	{
	97	raw_spin_lock(&handler->enable_lock);
	98	__plic_toggle(handler->enable_base, hwirq, enable);
86c7cbf1	99	raw_spin_unlock(&handler->enable_lock);
8237f8bc CH	100	}
8237f8bc CH	101
cc9f04f9	102	static inline void plic_irq_toggle(const struct cpumask *mask,
f1ad1133	103	struct irq_data *d, int enable)
8237f8bc CH	104	{
8237f8bc CH	105	int cpu;
f9ac7bbd	106	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
8237f8bc	107
f1ad1133	108	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
cc9f04f9	109	for_each_cpu(cpu, mask) {
8237f8bc CH	110	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
8237f8bc CH	111
f1ad1133 AP	112	if (handler->present &&
	113	cpumask_test_cpu(cpu, &handler->priv->lmask))
	114	plic_toggle(handler, d->hwirq, enable);
8237f8bc CH	115	}
	116	}
	117
bb0fed1c	118	static void plic_irq_unmask(struct irq_data *d)
8237f8bc	119	{
f1ad1133 AP	120	struct cpumask amask;
f1ad1133 AP	121	unsigned int cpu;
f9ac7bbd	122	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
f1ad1133 AP	123
	124	cpumask_and(&amask, &priv->lmask, cpu_online_mask);
	125	cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
	126	&amask);
cc9f04f9 AP	127	if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
cc9f04f9 AP	128	return;
f1ad1133	129	plic_irq_toggle(cpumask_of(cpu), d, 1);
8237f8bc CH	130	}
8237f8bc CH	131
bb0fed1c	132	static void plic_irq_mask(struct irq_data *d)
8237f8bc	133	{
f9ac7bbd	134	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
f1ad1133 AP	135
f1ad1133 AP	136	plic_irq_toggle(&priv->lmask, d, 0);
8237f8bc CH	137	}
8237f8bc CH	138
cc9f04f9 AP	139	#ifdef CONFIG_SMP
	140	static int plic_set_affinity(struct irq_data *d,
	141	const struct cpumask *mask_val, bool force)
	142	{
	143	unsigned int cpu;
f1ad1133	144	struct cpumask amask;
f9ac7bbd	145	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
f1ad1133 AP	146
f1ad1133 AP	147	cpumask_and(&amask, &priv->lmask, mask_val);
cc9f04f9 AP	148
cc9f04f9 AP	149	if (force)
f1ad1133	150	cpu = cpumask_first(&amask);
cc9f04f9	151	else
f1ad1133	152	cpu = cpumask_any_and(&amask, cpu_online_mask);
cc9f04f9 AP	153
	154	if (cpu >= nr_cpu_ids)
	155	return -EINVAL;
	156
f1ad1133	157	plic_irq_toggle(&priv->lmask, d, 0);
a7480c5d	158	plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
cc9f04f9 AP	159
	160	irq_data_update_effective_affinity(d, cpumask_of(cpu));
	161
	162	return IRQ_SET_MASK_OK_DONE;
	163	}
	164	#endif
	165
bb0fed1c MZ	166	static void plic_irq_eoi(struct irq_data *d)
	167	{
	168	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	169
69ea4630 GR	170	if (irqd_irq_masked(d)) {
	171	plic_irq_unmask(d);
	172	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	173	plic_irq_mask(d);
	174	} else {
	175	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	176	}
bb0fed1c MZ	177	}
bb0fed1c MZ	178
8237f8bc CH	179	static struct irq_chip plic_chip = {
8237f8bc CH	180	.name = "SiFive PLIC",
bb0fed1c MZ	181	.irq_mask = plic_irq_mask,
	182	.irq_unmask = plic_irq_unmask,
	183	.irq_eoi = plic_irq_eoi,
cc9f04f9 AP	184	#ifdef CONFIG_SMP
	185	.irq_set_affinity = plic_set_affinity,
	186	#endif
8237f8bc CH	187	};
	188
	189	static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
	190	irq_hw_number_t hwirq)
	191	{
2458ed31 AP	192	struct plic_priv *priv = d->host_data;
2458ed31 AP	193
466008f9 YS	194	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
466008f9 YS	195	handle_fasteoi_irq, NULL, NULL);
8237f8bc	196	irq_set_noprobe(irq);
2458ed31	197	irq_set_affinity(irq, &priv->lmask);
8237f8bc CH	198	return 0;
	199	}
	200
466008f9 YS	201	static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	202	unsigned int nr_irqs, void *arg)
	203	{
	204	int i, ret;
	205	irq_hw_number_t hwirq;
	206	unsigned int type;
	207	struct irq_fwspec *fwspec = arg;
	208
	209	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
	210	if (ret)
	211	return ret;
	212
	213	for (i = 0; i < nr_irqs; i++) {
	214	ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
	215	if (ret)
	216	return ret;
	217	}
	218
	219	return 0;
	220	}
	221
8237f8bc	222	static const struct irq_domain_ops plic_irqdomain_ops = {
466008f9 YS	223	.translate = irq_domain_translate_onecell,
	224	.alloc = plic_irq_domain_alloc,
	225	.free = irq_domain_free_irqs_top,
8237f8bc CH	226	};
8237f8bc CH	227
8237f8bc CH	228	/*
	229	* Handling an interrupt is a two-step process: first you claim the interrupt
	230	* by reading the claim register, then you complete the interrupt by writing
	231	* that source ID back to the same claim register. This automatically enables
	232	* and disables the interrupt, so there's nothing else to do.
	233	*/
6b7ce892	234	static void plic_handle_irq(struct irq_desc *desc)
8237f8bc CH	235	{
8237f8bc CH	236	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
6b7ce892	237	struct irq_chip *chip = irq_desc_get_chip(desc);
86c7cbf1	238	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
8237f8bc CH	239	irq_hw_number_t hwirq;
	240
	241	WARN_ON_ONCE(!handler->present);
	242
6b7ce892 AP	243	chained_irq_enter(chip, desc);
6b7ce892 AP	244
8237f8bc	245	while ((hwirq = readl(claim))) {
046a6ee2 MZ	246	int err = generic_handle_domain_irq(handler->priv->irqdomain,
	247	hwirq);
	248	if (unlikely(err))
8237f8bc CH	249	pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
8237f8bc CH	250	hwirq);
8237f8bc	251	}
6b7ce892 AP	252
6b7ce892 AP	253	chained_irq_exit(chip, desc);
8237f8bc CH	254	}
8237f8bc CH	255
ccbe80ba AP	256	static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
	257	{
	258	/* priority must be > threshold to trigger an interrupt */
	259	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
	260	}
	261
	262	static int plic_dying_cpu(unsigned int cpu)
	263	{
6b7ce892 AP	264	if (plic_parent_irq)
6b7ce892 AP	265	disable_percpu_irq(plic_parent_irq);
ccbe80ba AP	266
	267	return 0;
	268	}
	269
	270	static int plic_starting_cpu(unsigned int cpu)
	271	{
	272	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	273
6b7ce892 AP	274	if (plic_parent_irq)
	275	enable_percpu_irq(plic_parent_irq,
	276	irq_get_trigger_type(plic_parent_irq));
	277	else
	278	pr_warn("cpu%d: parent irq not available\n", cpu);
ccbe80ba AP	279	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
	280
	281	return 0;
	282	}
	283
8237f8bc CH	284	static int __init plic_init(struct device_node *node,
	285	struct device_node *parent)
	286	{
6adfe8d2	287	int error = 0, nr_contexts, nr_handlers = 0, i;
8237f8bc	288	u32 nr_irqs;
f1ad1133	289	struct plic_priv *priv;
2234ae84	290	struct plic_handler *handler;
8237f8bc	291
f1ad1133 AP	292	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	293	if (!priv)
	294	return -ENOMEM;
8237f8bc	295
f1ad1133 AP	296	priv->regs = of_iomap(node, 0);
	297	if (WARN_ON(!priv->regs)) {
	298	error = -EIO;
	299	goto out_free_priv;
	300	}
8237f8bc CH	301
	302	error = -EINVAL;
	303	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	304	if (WARN_ON(!nr_irqs))
	305	goto out_iounmap;
	306
6adfe8d2 AP	307	nr_contexts = of_irq_count(node);
6adfe8d2 AP	308	if (WARN_ON(!nr_contexts))
8237f8bc	309	goto out_iounmap;
8237f8bc CH	310
8237f8bc CH	311	error = -ENOMEM;
f1ad1133 AP	312	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
	313	&plic_irqdomain_ops, priv);
	314	if (WARN_ON(!priv->irqdomain))
8237f8bc CH	315	goto out_iounmap;
8237f8bc CH	316
6adfe8d2	317	for (i = 0; i < nr_contexts; i++) {
8237f8bc	318	struct of_phandle_args parent;
8237f8bc	319	irq_hw_number_t hwirq;
f99fb607	320	int cpu, hartid;
8237f8bc CH	321
	322	if (of_irq_parse_one(node, i, &parent)) {
	323	pr_err("failed to parse parent for context %d.\n", i);
	324	continue;
	325	}
	326
a4c3733d CH	327	/*
	328	* Skip contexts other than external interrupts for our
	329	* privilege level.
	330	*/
098fdbc3 NC	331	if (parent.args[0] != RV_IRQ_EXT) {
	332	/* Disable S-mode enable bits if running in M-mode. */
	333	if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
	334	void __iomem *enable_base = priv->regs +
	335	CONTEXT_ENABLE_BASE +
	336	i * CONTEXT_ENABLE_SIZE;
	337
	338	for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
	339	__plic_toggle(enable_base, hwirq, 0);
	340	}
8237f8bc	341	continue;
098fdbc3	342	}
8237f8bc	343
d175d699	344	hartid = riscv_of_parent_hartid(parent.np);
f99fb607	345	if (hartid < 0) {
8237f8bc CH	346	pr_warn("failed to parse hart ID for context %d.\n", i);
	347	continue;
	348	}
	349
f99fb607	350	cpu = riscv_hartid_to_cpuid(hartid);
fc03acae AP	351	if (cpu < 0) {
	352	pr_warn("Invalid cpuid for context %d\n", i);
	353	continue;
	354	}
	355
6b7ce892 AP	356	/* Find parent domain and register chained handler */
	357	if (!plic_parent_irq && irq_find_host(parent.np)) {
	358	plic_parent_irq = irq_of_parse_and_map(node, i);
	359	if (plic_parent_irq)
	360	irq_set_chained_handler(plic_parent_irq,
	361	plic_handle_irq);
	362	}
	363
9ce06497 CH	364	/*
	365	* When running in M-mode we need to ignore the S-mode handler.
	366	* Here we assume it always comes later, but that might be a
	367	* little fragile.
	368	*/
8237f8bc	369	handler = per_cpu_ptr(&plic_handlers, cpu);
3fecb5aa AP	370	if (handler->present) {
3fecb5aa AP	371	pr_warn("handler already present for context %d.\n", i);
ccbe80ba	372	plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
9ce06497	373	goto done;
3fecb5aa AP	374	}
3fecb5aa AP	375
f1ad1133	376	cpumask_set_cpu(cpu, &priv->lmask);
8237f8bc	377	handler->present = true;
0d3616bb NC	378	handler->hart_base = priv->regs + CONTEXT_BASE +
0d3616bb NC	379	i * CONTEXT_SIZE;
86c7cbf1	380	raw_spin_lock_init(&handler->enable_lock);
0d3616bb NC	381	handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
0d3616bb NC	382	i * CONTEXT_ENABLE_SIZE;
f1ad1133	383	handler->priv = priv;
9ce06497	384	done:
8237f8bc	385	for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
86c7cbf1	386	plic_toggle(handler, hwirq, 0);
6adfe8d2	387	nr_handlers++;
8237f8bc CH	388	}
8237f8bc CH	389
2234ae84 AP	390	/*
	391	* We can have multiple PLIC instances so setup cpuhp state only
	392	* when context handler for current/boot CPU is present.
	393	*/
	394	handler = this_cpu_ptr(&plic_handlers);
	395	if (handler->present && !plic_cpuhp_setup_done) {
	396	cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
ccbe80ba AP	397	"irqchip/sifive/plic:starting",
ccbe80ba AP	398	plic_starting_cpu, plic_dying_cpu);
2234ae84 AP	399	plic_cpuhp_setup_done = true;
	400	}
	401
0e375f51 AP	402	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
0e375f51 AP	403	" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
8237f8bc CH	404	return 0;
	405
	406	out_iounmap:
f1ad1133 AP	407	iounmap(priv->regs);
	408	out_free_priv:
	409	kfree(priv);
8237f8bc CH	410	return error;
	411	}
	412
	413	IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
	414	IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
1d4df649	415	IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */