[linux-block.git] / drivers / irqchip / irq-sifive-plic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 SiFive
 * Copyright (C) 2018 Christoph Hellwig
 */
#define pr_fmt(fmt) "plic: " fmt
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <asm/smp.h>

/*
 * This driver implements a version of the RISC-V PLIC with the actual layout
 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
 *
 *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
 *
 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
 * Spec.
 */

#define MAX_DEVICES			1024
#define MAX_CONTEXTS			15872

/*
 * Each interrupt source has a priority register associated with it.
 * We always hardwire it to one in Linux.
 */
#define PRIORITY_BASE			0
#define     PRIORITY_PER_ID		4

/*
 * Each hart context has a vector of interrupt enable bits associated with it.
 * There's one bit for each interrupt source.
 */
#define CONTEXT_ENABLE_BASE		0x2000
#define     CONTEXT_ENABLE_SIZE		0x80

/*
 * Each hart context has a set of control registers associated with it.  Right
 * now there's only two: a source priority threshold over which the hart will
 * take an interrupt, and a register to claim interrupts.
 */
#define CONTEXT_BASE			0x200000
#define     CONTEXT_SIZE		0x1000
#define     CONTEXT_THRESHOLD		0x00
#define     CONTEXT_CLAIM		0x04

#define	PLIC_DISABLE_THRESHOLD		0x7
#define	PLIC_ENABLE_THRESHOLD		0

#define PLIC_QUIRK_EDGE_INTERRUPT	0

struct plic_priv {
	struct cpumask lmask;
	struct irq_domain *irqdomain;
	void __iomem *regs;
	unsigned long plic_quirks;
};

struct plic_handler {
	bool			present;
	void __iomem		*hart_base;
	/*
	 * Protect mask operations on the registers given that we can't
	 * assume atomic memory operations work on them.
	 */
	raw_spinlock_t		enable_lock;
	void __iomem		*enable_base;
	struct plic_priv	*priv;
};
static int plic_parent_irq __ro_after_init;
static bool plic_cpuhp_setup_done __ro_after_init;
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);

static int plic_irq_set_type(struct irq_data *d, unsigned int type);

static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
	u32 hwirq_mask = 1 << (hwirq % 32);

	if (enable)
		writel(readl(reg) | hwirq_mask, reg);
	else
		writel(readl(reg) & ~hwirq_mask, reg);
}

static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
{
	raw_spin_lock(&handler->enable_lock);
	__plic_toggle(handler->enable_base, hwirq, enable);
	raw_spin_unlock(&handler->enable_lock);
}

static inline void plic_irq_toggle(const struct cpumask *mask,
				   struct irq_data *d, int enable)
{
	int cpu;

	for_each_cpu(cpu, mask) {
		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);

		plic_toggle(handler, d->hwirq, enable);
	}
}

static void plic_irq_enable(struct irq_data *d)
{
	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
}

static void plic_irq_disable(struct irq_data *d)
{
	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
}

static void plic_irq_unmask(struct irq_data *d)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
}

static void plic_irq_mask(struct irq_data *d)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
}

static void plic_irq_eoi(struct irq_data *d)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
}

#ifdef CONFIG_SMP
static int plic_set_affinity(struct irq_data *d,
			     const struct cpumask *mask_val, bool force)
{
	unsigned int cpu;
	struct cpumask amask;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	cpumask_and(&amask, &priv->lmask, mask_val);

	if (force)
		cpu = cpumask_first(&amask);
	else
		cpu = cpumask_any_and(&amask, cpu_online_mask);

	if (cpu >= nr_cpu_ids)
		return -EINVAL;

	plic_irq_disable(d);

	irq_data_update_effective_affinity(d, cpumask_of(cpu));

	if (!irqd_irq_disabled(d))
		plic_irq_enable(d);

	return IRQ_SET_MASK_OK_DONE;
}
#endif

static struct irq_chip plic_edge_chip = {
	.name		= "SiFive PLIC",
	.irq_enable	= plic_irq_enable,
	.irq_disable	= plic_irq_disable,
	.irq_ack	= plic_irq_eoi,
	.irq_mask	= plic_irq_mask,
	.irq_unmask	= plic_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = plic_set_affinity,
#endif
	.irq_set_type	= plic_irq_set_type,
	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
};

static struct irq_chip plic_chip = {
	.name		= "SiFive PLIC",
	.irq_enable	= plic_irq_enable,
	.irq_disable	= plic_irq_disable,
	.irq_mask	= plic_irq_mask,
	.irq_unmask	= plic_irq_unmask,
	.irq_eoi	= plic_irq_eoi,
#ifdef CONFIG_SMP
	.irq_set_affinity = plic_set_affinity,
#endif
	.irq_set_type	= plic_irq_set_type,
	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
};

static int plic_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
		return IRQ_SET_MASK_OK_NOCOPY;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irq_set_chip_handler_name_locked(d, &plic_edge_chip,
						 handle_edge_irq, NULL);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_set_chip_handler_name_locked(d, &plic_chip,
						 handle_fasteoi_irq, NULL);
		break;
	default:
		return -EINVAL;
	}

	return IRQ_SET_MASK_OK;
}

static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	struct plic_priv *priv = d->host_data;

	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
			    handle_fasteoi_irq, NULL, NULL);
	irq_set_noprobe(irq);
	irq_set_affinity(irq, &priv->lmask);
	return 0;
}

static int plic_irq_domain_translate(struct irq_domain *d,
				     struct irq_fwspec *fwspec,
				     unsigned long *hwirq,
				     unsigned int *type)
{
	struct plic_priv *priv = d->host_data;

	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
		return irq_domain_translate_twocell(d, fwspec, hwirq, type);

	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
}

static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				 unsigned int nr_irqs, void *arg)
{
	int i, ret;
	irq_hw_number_t hwirq;
	unsigned int type;
	struct irq_fwspec *fwspec = arg;

	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++) {
		ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct irq_domain_ops plic_irqdomain_ops = {
	.translate	= plic_irq_domain_translate,
	.alloc		= plic_irq_domain_alloc,
	.free		= irq_domain_free_irqs_top,
};

/*
 * Handling an interrupt is a two-step process: first you claim the interrupt
 * by reading the claim register, then you complete the interrupt by writing
 * that source ID back to the same claim register.  This automatically enables
 * and disables the interrupt, so there's nothing else to do.
 */
static void plic_handle_irq(struct irq_desc *desc)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
	irq_hw_number_t hwirq;

	WARN_ON_ONCE(!handler->present);

	chained_irq_enter(chip, desc);

	while ((hwirq = readl(claim))) {
		int err = generic_handle_domain_irq(handler->priv->irqdomain,
						    hwirq);
		if (unlikely(err))
			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
					hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
{
	/* priority must be > threshold to trigger an interrupt */
	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
}

static int plic_dying_cpu(unsigned int cpu)
{
	if (plic_parent_irq)
		disable_percpu_irq(plic_parent_irq);

	return 0;
}

static int plic_starting_cpu(unsigned int cpu)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);

	if (plic_parent_irq)
		enable_percpu_irq(plic_parent_irq,
				  irq_get_trigger_type(plic_parent_irq));
	else
		pr_warn("cpu%d: parent irq not available\n", cpu);
	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);

	return 0;
}

static int __init __plic_init(struct device_node *node,
			      struct device_node *parent,
			      unsigned long plic_quirks)
{
	int error = 0, nr_contexts, nr_handlers = 0, i;
	u32 nr_irqs;
	struct plic_priv *priv;
	struct plic_handler *handler;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->plic_quirks = plic_quirks;

	priv->regs = of_iomap(node, 0);
	if (WARN_ON(!priv->regs)) {
		error = -EIO;
		goto out_free_priv;
	}

	error = -EINVAL;
	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	if (WARN_ON(!nr_irqs))
		goto out_iounmap;

	nr_contexts = of_irq_count(node);
	if (WARN_ON(!nr_contexts))
		goto out_iounmap;

	error = -ENOMEM;
	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
			&plic_irqdomain_ops, priv);
	if (WARN_ON(!priv->irqdomain))
		goto out_iounmap;

	for (i = 0; i < nr_contexts; i++) {
		struct of_phandle_args parent;
		irq_hw_number_t hwirq;
		int cpu, hartid;

		if (of_irq_parse_one(node, i, &parent)) {
			pr_err("failed to parse parent for context %d.\n", i);
			continue;
		}

		/*
		 * Skip contexts other than external interrupts for our
		 * privilege level.
		 */
		if (parent.args[0] != RV_IRQ_EXT) {
			/* Disable S-mode enable bits if running in M-mode. */
			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
				void __iomem *enable_base = priv->regs +
					CONTEXT_ENABLE_BASE +
					i * CONTEXT_ENABLE_SIZE;

				for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
					__plic_toggle(enable_base, hwirq, 0);
			}
			continue;
		}

		hartid = riscv_of_parent_hartid(parent.np);
		if (hartid < 0) {
			pr_warn("failed to parse hart ID for context %d.\n", i);
			continue;
		}

		cpu = riscv_hartid_to_cpuid(hartid);
		if (cpu < 0) {
			pr_warn("Invalid cpuid for context %d\n", i);
			continue;
		}

		/* Find parent domain and register chained handler */
		if (!plic_parent_irq && irq_find_host(parent.np)) {
			plic_parent_irq = irq_of_parse_and_map(node, i);
			if (plic_parent_irq)
				irq_set_chained_handler(plic_parent_irq,
							plic_handle_irq);
		}

		/*
		 * When running in M-mode we need to ignore the S-mode handler.
		 * Here we assume it always comes later, but that might be a
		 * little fragile.
		 */
		handler = per_cpu_ptr(&plic_handlers, cpu);
		if (handler->present) {
			pr_warn("handler already present for context %d.\n", i);
			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
			goto done;
		}

		cpumask_set_cpu(cpu, &priv->lmask);
		handler->present = true;
		handler->hart_base = priv->regs + CONTEXT_BASE +
			i * CONTEXT_SIZE;
		raw_spin_lock_init(&handler->enable_lock);
		handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
			i * CONTEXT_ENABLE_SIZE;
		handler->priv = priv;
done:
		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
			plic_toggle(handler, hwirq, 0);
			writel(1, priv->regs + PRIORITY_BASE +
				  hwirq * PRIORITY_PER_ID);
		}
		nr_handlers++;
	}

	/*
	 * We can have multiple PLIC instances so setup cpuhp state only
	 * when context handler for current/boot CPU is present.
	 */
	handler = this_cpu_ptr(&plic_handlers);
	if (handler->present && !plic_cpuhp_setup_done) {
		cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
				  "irqchip/sifive/plic:starting",
				  plic_starting_cpu, plic_dying_cpu);
		plic_cpuhp_setup_done = true;
	}

	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
		" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
	return 0;

out_iounmap:
	iounmap(priv->regs);
out_free_priv:
	kfree(priv);
	return error;
}

static int __init plic_init(struct device_node *node,
			    struct device_node *parent)
{
	return __plic_init(node, parent, 0);
}

IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */

static int __init plic_edge_init(struct device_node *node,
				 struct device_node *parent)
{
	return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
}

IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
Commit	Line	Data
8237f8bc CH	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2017 SiFive
	4	* Copyright (C) 2018 Christoph Hellwig
	5	*/
	6	#define pr_fmt(fmt) "plic: " fmt
ccbe80ba	7	#include <linux/cpu.h>
8237f8bc CH	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/irq.h>
	11	#include <linux/irqchip.h>
6b7ce892	12	#include <linux/irqchip/chained_irq.h>
8237f8bc CH	13	#include <linux/irqdomain.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/spinlock.h>
f99fb607	20	#include <asm/smp.h>
8237f8bc CH	21
	22	/*
	23	* This driver implements a version of the RISC-V PLIC with the actual layout
	24	* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
	25	*
	26	* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
	27	*
	28	* The largest number supported by devices marked as 'sifive,plic-1.0.0', is
	29	* 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
	30	* Spec.
	31	*/
	32
	33	#define MAX_DEVICES 1024
	34	#define MAX_CONTEXTS 15872
	35
	36	/*
	37	* Each interrupt source has a priority register associated with it.
	38	* We always hardwire it to one in Linux.
	39	*/
	40	#define PRIORITY_BASE 0
	41	#define PRIORITY_PER_ID 4
	42
	43	/*
	44	* Each hart context has a vector of interrupt enable bits associated with it.
	45	* There's one bit for each interrupt source.
	46	*/
0d3616bb NC	47	#define CONTEXT_ENABLE_BASE 0x2000
0d3616bb NC	48	#define CONTEXT_ENABLE_SIZE 0x80
8237f8bc CH	49
	50	/*
	51	* Each hart context has a set of control registers associated with it. Right
	52	* now there's only two: a source priority threshold over which the hart will
	53	* take an interrupt, and a register to claim interrupts.
	54	*/
	55	#define CONTEXT_BASE 0x200000
0d3616bb	56	#define CONTEXT_SIZE 0x1000
8237f8bc CH	57	#define CONTEXT_THRESHOLD 0x00
	58	#define CONTEXT_CLAIM 0x04
	59
d727be7b	60	#define PLIC_DISABLE_THRESHOLD 0x7
ccbe80ba AP	61	#define PLIC_ENABLE_THRESHOLD 0
ccbe80ba AP	62
dd46337c LP	63	#define PLIC_QUIRK_EDGE_INTERRUPT 0
dd46337c LP	64
f1ad1133 AP	65	struct plic_priv {
	66	struct cpumask lmask;
	67	struct irq_domain *irqdomain;
	68	void __iomem *regs;
dd46337c	69	unsigned long plic_quirks;
f1ad1133	70	};
8237f8bc CH	71
	72	struct plic_handler {
	73	bool present;
86c7cbf1 AP	74	void __iomem *hart_base;
	75	/*
	76	* Protect mask operations on the registers given that we can't
	77	* assume atomic memory operations work on them.
	78	*/
	79	raw_spinlock_t enable_lock;
	80	void __iomem *enable_base;
f1ad1133	81	struct plic_priv *priv;
8237f8bc	82	};
e03b7c1b JZ	83	static int plic_parent_irq __ro_after_init;
e03b7c1b JZ	84	static bool plic_cpuhp_setup_done __ro_after_init;
8237f8bc CH	85	static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
8237f8bc CH	86
dd46337c LP	87	static int plic_irq_set_type(struct irq_data *d, unsigned int type);
dd46337c LP	88
098fdbc3	89	static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
8237f8bc	90	{
098fdbc3	91	u32 __iomem reg = enable_base + (hwirq / 32) sizeof(u32);
8237f8bc CH	92	u32 hwirq_mask = 1 << (hwirq % 32);
8237f8bc CH	93
8237f8bc CH	94	if (enable)
	95	writel(readl(reg) \| hwirq_mask, reg);
	96	else
	97	writel(readl(reg) & ~hwirq_mask, reg);
098fdbc3 NC	98	}
	99
	100	static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
	101	{
	102	raw_spin_lock(&handler->enable_lock);
	103	__plic_toggle(handler->enable_base, hwirq, enable);
86c7cbf1	104	raw_spin_unlock(&handler->enable_lock);
8237f8bc CH	105	}
8237f8bc CH	106
cc9f04f9	107	static inline void plic_irq_toggle(const struct cpumask *mask,
f1ad1133	108	struct irq_data *d, int enable)
8237f8bc CH	109	{
	110	int cpu;
	111
cc9f04f9	112	for_each_cpu(cpu, mask) {
8237f8bc CH	113	struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
8237f8bc CH	114
de078949	115	plic_toggle(handler, d->hwirq, enable);
8237f8bc CH	116	}
	117	}
	118
a1706a1c	119	static void plic_irq_enable(struct irq_data *d)
8237f8bc	120	{
de078949	121	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1);
8237f8bc CH	122	}
8237f8bc CH	123
a1706a1c	124	static void plic_irq_disable(struct irq_data *d)
8237f8bc	125	{
de078949	126	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
8237f8bc CH	127	}
8237f8bc CH	128
a1706a1c SH	129	static void plic_irq_unmask(struct irq_data *d)
	130	{
	131	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	132
	133	writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
	134	}
	135
	136	static void plic_irq_mask(struct irq_data *d)
	137	{
	138	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	139
	140	writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
	141	}
	142
	143	static void plic_irq_eoi(struct irq_data *d)
	144	{
	145	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	146
	147	writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
	148	}
	149
cc9f04f9 AP	150	#ifdef CONFIG_SMP
	151	static int plic_set_affinity(struct irq_data *d,
	152	const struct cpumask *mask_val, bool force)
	153	{
	154	unsigned int cpu;
f1ad1133	155	struct cpumask amask;
f9ac7bbd	156	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
f1ad1133 AP	157
f1ad1133 AP	158	cpumask_and(&amask, &priv->lmask, mask_val);
cc9f04f9 AP	159
cc9f04f9 AP	160	if (force)
f1ad1133	161	cpu = cpumask_first(&amask);
cc9f04f9	162	else
f1ad1133	163	cpu = cpumask_any_and(&amask, cpu_online_mask);
cc9f04f9 AP	164
	165	if (cpu >= nr_cpu_ids)
	166	return -EINVAL;
	167
a1706a1c	168	plic_irq_disable(d);
cc9f04f9 AP	169
	170	irq_data_update_effective_affinity(d, cpumask_of(cpu));
	171
a1706a1c SH	172	if (!irqd_irq_disabled(d))
a1706a1c SH	173	plic_irq_enable(d);
de078949	174
cc9f04f9 AP	175	return IRQ_SET_MASK_OK_DONE;
	176	}
	177	#endif
	178
dd46337c LP	179	static struct irq_chip plic_edge_chip = {
dd46337c LP	180	.name = "SiFive PLIC",
a1706a1c SH	181	.irq_enable = plic_irq_enable,
a1706a1c SH	182	.irq_disable = plic_irq_disable,
dd46337c LP	183	.irq_ack = plic_irq_eoi,
	184	.irq_mask = plic_irq_mask,
	185	.irq_unmask = plic_irq_unmask,
	186	#ifdef CONFIG_SMP
	187	.irq_set_affinity = plic_set_affinity,
	188	#endif
	189	.irq_set_type = plic_irq_set_type,
de078949	190	.flags = IRQCHIP_AFFINITY_PRE_STARTUP,
dd46337c LP	191	};
dd46337c LP	192
8237f8bc CH	193	static struct irq_chip plic_chip = {
8237f8bc CH	194	.name = "SiFive PLIC",
a1706a1c SH	195	.irq_enable = plic_irq_enable,
a1706a1c SH	196	.irq_disable = plic_irq_disable,
bb0fed1c MZ	197	.irq_mask = plic_irq_mask,
	198	.irq_unmask = plic_irq_unmask,
	199	.irq_eoi = plic_irq_eoi,
cc9f04f9 AP	200	#ifdef CONFIG_SMP
	201	.irq_set_affinity = plic_set_affinity,
	202	#endif
dd46337c	203	.irq_set_type = plic_irq_set_type,
de078949	204	.flags = IRQCHIP_AFFINITY_PRE_STARTUP,
8237f8bc CH	205	};
8237f8bc CH	206
dd46337c LP	207	static int plic_irq_set_type(struct irq_data *d, unsigned int type)
	208	{
	209	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
	210
	211	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
	212	return IRQ_SET_MASK_OK_NOCOPY;
	213
	214	switch (type) {
	215	case IRQ_TYPE_EDGE_RISING:
	216	irq_set_chip_handler_name_locked(d, &plic_edge_chip,
	217	handle_edge_irq, NULL);
	218	break;
	219	case IRQ_TYPE_LEVEL_HIGH:
	220	irq_set_chip_handler_name_locked(d, &plic_chip,
	221	handle_fasteoi_irq, NULL);
	222	break;
	223	default:
	224	return -EINVAL;
	225	}
	226
	227	return IRQ_SET_MASK_OK;
	228	}
	229
8237f8bc CH	230	static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
	231	irq_hw_number_t hwirq)
	232	{
2458ed31 AP	233	struct plic_priv *priv = d->host_data;
2458ed31 AP	234
466008f9 YS	235	irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
466008f9 YS	236	handle_fasteoi_irq, NULL, NULL);
8237f8bc	237	irq_set_noprobe(irq);
2458ed31	238	irq_set_affinity(irq, &priv->lmask);
8237f8bc CH	239	return 0;
	240	}
	241
dd46337c LP	242	static int plic_irq_domain_translate(struct irq_domain *d,
	243	struct irq_fwspec *fwspec,
	244	unsigned long *hwirq,
	245	unsigned int *type)
	246	{
	247	struct plic_priv *priv = d->host_data;
	248
	249	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
	250	return irq_domain_translate_twocell(d, fwspec, hwirq, type);
	251
	252	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
	253	}
	254
466008f9 YS	255	static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	256	unsigned int nr_irqs, void *arg)
	257	{
	258	int i, ret;
	259	irq_hw_number_t hwirq;
	260	unsigned int type;
	261	struct irq_fwspec *fwspec = arg;
	262
dd46337c	263	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
466008f9 YS	264	if (ret)
	265	return ret;
	266
	267	for (i = 0; i < nr_irqs; i++) {
	268	ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
	269	if (ret)
	270	return ret;
	271	}
	272
	273	return 0;
	274	}
	275
8237f8bc	276	static const struct irq_domain_ops plic_irqdomain_ops = {
dd46337c	277	.translate = plic_irq_domain_translate,
466008f9 YS	278	.alloc = plic_irq_domain_alloc,
466008f9 YS	279	.free = irq_domain_free_irqs_top,
8237f8bc CH	280	};
8237f8bc CH	281
8237f8bc CH	282	/*
	283	* Handling an interrupt is a two-step process: first you claim the interrupt
	284	* by reading the claim register, then you complete the interrupt by writing
	285	* that source ID back to the same claim register. This automatically enables
	286	* and disables the interrupt, so there's nothing else to do.
	287	*/
6b7ce892	288	static void plic_handle_irq(struct irq_desc *desc)
8237f8bc CH	289	{
8237f8bc CH	290	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
6b7ce892	291	struct irq_chip *chip = irq_desc_get_chip(desc);
86c7cbf1	292	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
8237f8bc CH	293	irq_hw_number_t hwirq;
	294
	295	WARN_ON_ONCE(!handler->present);
	296
6b7ce892 AP	297	chained_irq_enter(chip, desc);
6b7ce892 AP	298
8237f8bc	299	while ((hwirq = readl(claim))) {
046a6ee2 MZ	300	int err = generic_handle_domain_irq(handler->priv->irqdomain,
	301	hwirq);
	302	if (unlikely(err))
8237f8bc CH	303	pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
8237f8bc CH	304	hwirq);
8237f8bc	305	}
6b7ce892 AP	306
6b7ce892 AP	307	chained_irq_exit(chip, desc);
8237f8bc CH	308	}
8237f8bc CH	309
ccbe80ba AP	310	static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
	311	{
	312	/* priority must be > threshold to trigger an interrupt */
	313	writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
	314	}
	315
	316	static int plic_dying_cpu(unsigned int cpu)
	317	{
6b7ce892 AP	318	if (plic_parent_irq)
6b7ce892 AP	319	disable_percpu_irq(plic_parent_irq);
ccbe80ba AP	320
	321	return 0;
	322	}
	323
	324	static int plic_starting_cpu(unsigned int cpu)
	325	{
	326	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	327
6b7ce892 AP	328	if (plic_parent_irq)
	329	enable_percpu_irq(plic_parent_irq,
	330	irq_get_trigger_type(plic_parent_irq));
	331	else
	332	pr_warn("cpu%d: parent irq not available\n", cpu);
ccbe80ba AP	333	plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
	334
	335	return 0;
	336	}
	337
dd46337c LP	338	static int __init __plic_init(struct device_node *node,
	339	struct device_node *parent,
	340	unsigned long plic_quirks)
8237f8bc	341	{
6adfe8d2	342	int error = 0, nr_contexts, nr_handlers = 0, i;
8237f8bc	343	u32 nr_irqs;
f1ad1133	344	struct plic_priv *priv;
2234ae84	345	struct plic_handler *handler;
8237f8bc	346
f1ad1133 AP	347	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	348	if (!priv)
	349	return -ENOMEM;
8237f8bc	350
dd46337c LP	351	priv->plic_quirks = plic_quirks;
dd46337c LP	352
f1ad1133 AP	353	priv->regs = of_iomap(node, 0);
	354	if (WARN_ON(!priv->regs)) {
	355	error = -EIO;
	356	goto out_free_priv;
	357	}
8237f8bc CH	358
	359	error = -EINVAL;
	360	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	361	if (WARN_ON(!nr_irqs))
	362	goto out_iounmap;
	363
6adfe8d2 AP	364	nr_contexts = of_irq_count(node);
6adfe8d2 AP	365	if (WARN_ON(!nr_contexts))
8237f8bc	366	goto out_iounmap;
8237f8bc CH	367
8237f8bc CH	368	error = -ENOMEM;
f1ad1133 AP	369	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
	370	&plic_irqdomain_ops, priv);
	371	if (WARN_ON(!priv->irqdomain))
8237f8bc CH	372	goto out_iounmap;
8237f8bc CH	373
6adfe8d2	374	for (i = 0; i < nr_contexts; i++) {
8237f8bc	375	struct of_phandle_args parent;
8237f8bc	376	irq_hw_number_t hwirq;
f99fb607	377	int cpu, hartid;
8237f8bc CH	378
	379	if (of_irq_parse_one(node, i, &parent)) {
	380	pr_err("failed to parse parent for context %d.\n", i);
	381	continue;
	382	}
	383
a4c3733d CH	384	/*
	385	* Skip contexts other than external interrupts for our
	386	* privilege level.
	387	*/
098fdbc3 NC	388	if (parent.args[0] != RV_IRQ_EXT) {
	389	/* Disable S-mode enable bits if running in M-mode. */
	390	if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
	391	void __iomem *enable_base = priv->regs +
	392	CONTEXT_ENABLE_BASE +
	393	i * CONTEXT_ENABLE_SIZE;
	394
	395	for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
	396	__plic_toggle(enable_base, hwirq, 0);
	397	}
8237f8bc	398	continue;
098fdbc3	399	}
8237f8bc	400
d175d699	401	hartid = riscv_of_parent_hartid(parent.np);
f99fb607	402	if (hartid < 0) {
8237f8bc CH	403	pr_warn("failed to parse hart ID for context %d.\n", i);
	404	continue;
	405	}
	406
f99fb607	407	cpu = riscv_hartid_to_cpuid(hartid);
fc03acae AP	408	if (cpu < 0) {
	409	pr_warn("Invalid cpuid for context %d\n", i);
	410	continue;
	411	}
	412
6b7ce892 AP	413	/* Find parent domain and register chained handler */
	414	if (!plic_parent_irq && irq_find_host(parent.np)) {
	415	plic_parent_irq = irq_of_parse_and_map(node, i);
	416	if (plic_parent_irq)
	417	irq_set_chained_handler(plic_parent_irq,
	418	plic_handle_irq);
	419	}
	420
9ce06497 CH	421	/*
	422	* When running in M-mode we need to ignore the S-mode handler.
	423	* Here we assume it always comes later, but that might be a
	424	* little fragile.
	425	*/
8237f8bc	426	handler = per_cpu_ptr(&plic_handlers, cpu);
3fecb5aa AP	427	if (handler->present) {
3fecb5aa AP	428	pr_warn("handler already present for context %d.\n", i);
ccbe80ba	429	plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
9ce06497	430	goto done;
3fecb5aa AP	431	}
3fecb5aa AP	432
f1ad1133	433	cpumask_set_cpu(cpu, &priv->lmask);
8237f8bc	434	handler->present = true;
0d3616bb NC	435	handler->hart_base = priv->regs + CONTEXT_BASE +
0d3616bb NC	436	i * CONTEXT_SIZE;
86c7cbf1	437	raw_spin_lock_init(&handler->enable_lock);
0d3616bb NC	438	handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
0d3616bb NC	439	i * CONTEXT_ENABLE_SIZE;
f1ad1133	440	handler->priv = priv;
9ce06497	441	done:
a1706a1c	442	for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
86c7cbf1	443	plic_toggle(handler, hwirq, 0);
a1706a1c SH	444	writel(1, priv->regs + PRIORITY_BASE +
	445	hwirq * PRIORITY_PER_ID);
	446	}
6adfe8d2	447	nr_handlers++;
8237f8bc CH	448	}
8237f8bc CH	449
2234ae84 AP	450	/*
	451	* We can have multiple PLIC instances so setup cpuhp state only
	452	* when context handler for current/boot CPU is present.
	453	*/
	454	handler = this_cpu_ptr(&plic_handlers);
	455	if (handler->present && !plic_cpuhp_setup_done) {
	456	cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
ccbe80ba AP	457	"irqchip/sifive/plic:starting",
ccbe80ba AP	458	plic_starting_cpu, plic_dying_cpu);
2234ae84 AP	459	plic_cpuhp_setup_done = true;
	460	}
	461
0e375f51 AP	462	pr_info("%pOFP: mapped %d interrupts with %d handlers for"
0e375f51 AP	463	" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
8237f8bc CH	464	return 0;
	465
	466	out_iounmap:
f1ad1133 AP	467	iounmap(priv->regs);
	468	out_free_priv:
	469	kfree(priv);
8237f8bc CH	470	return error;
	471	}
	472
dd46337c LP	473	static int __init plic_init(struct device_node *node,
	474	struct device_node *parent)
	475	{
	476	return __plic_init(node, parent, 0);
	477	}
	478
8237f8bc CH	479	IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
8237f8bc CH	480	IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
dd46337c LP	481
	482	static int __init plic_edge_init(struct device_node *node,
	483	struct device_node *parent)
	484	{
	485	return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
	486	}
	487
	488	IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
5873ba55	489	IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);