[linux-2.6-block.git] / drivers / irqchip / irq-sa11x0.c

/*
 * Copyright (C) 2015 Dmitry Eremin-Solenikov
 * Copyright (C) 1999-2001 Nicolas Pitre
 *
 * Generic IRQ handling for the SA11x0.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <linux/irqchip/irq-sa11x0.h>

#include <soc/sa1100/pwer.h>

#include <asm/exception.h>

#define ICIP	0x00  /* IC IRQ Pending reg. */
#define ICMR	0x04  /* IC Mask Reg.        */
#define ICLR	0x08  /* IC Level Reg.       */
#define ICCR	0x0C  /* IC Control Reg.     */
#define ICFP	0x10  /* IC FIQ Pending reg. */
#define ICPR	0x20  /* IC Pending Reg.     */

static void __iomem *iobase;

/*
 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
 */
static void sa1100_mask_irq(struct irq_data *d)
{
	u32 reg;

	reg = readl_relaxed(iobase + ICMR);
	reg &= ~BIT(d->hwirq);
	writel_relaxed(reg, iobase + ICMR);
}

static void sa1100_unmask_irq(struct irq_data *d)
{
	u32 reg;

	reg = readl_relaxed(iobase + ICMR);
	reg |= BIT(d->hwirq);
	writel_relaxed(reg, iobase + ICMR);
}

static int sa1100_set_wake(struct irq_data *d, unsigned int on)
{
	return sa11x0_sc_set_wake(d->hwirq, on);
}

static struct irq_chip sa1100_normal_chip = {
	.name		= "SC",
	.irq_ack	= sa1100_mask_irq,
	.irq_mask	= sa1100_mask_irq,
	.irq_unmask	= sa1100_unmask_irq,
	.irq_set_wake	= sa1100_set_wake,
};

static int sa1100_normal_irqdomain_map(struct irq_domain *d,
		unsigned int irq, irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
				 handle_level_irq);
	set_irq_flags(irq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops sa1100_normal_irqdomain_ops = {
	.map = sa1100_normal_irqdomain_map,
	.xlate = irq_domain_xlate_onetwocell,
};

static struct irq_domain *sa1100_normal_irqdomain;

static struct sa1100irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} sa1100irq_state;

static int sa1100irq_suspend(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	st->saved = 1;
	st->icmr = readl_relaxed(iobase + ICMR);
	st->iclr = readl_relaxed(iobase + ICLR);
	st->iccr = readl_relaxed(iobase + ICCR);

	/*
	 * Disable all GPIO-based interrupts.
	 */
	writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);

	return 0;
}

static void sa1100irq_resume(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	if (st->saved) {
		writel_relaxed(st->iccr, iobase + ICCR);
		writel_relaxed(st->iclr, iobase + ICLR);

		writel_relaxed(st->icmr, iobase + ICMR);
	}
}

static struct syscore_ops sa1100irq_syscore_ops = {
	.suspend	= sa1100irq_suspend,
	.resume		= sa1100irq_resume,
};

static int __init sa1100irq_init_devicefs(void)
{
	register_syscore_ops(&sa1100irq_syscore_ops);
	return 0;
}

device_initcall(sa1100irq_init_devicefs);

static asmlinkage void __exception_irq_entry
sa1100_handle_irq(struct pt_regs *regs)
{
	uint32_t icip, icmr, mask;

	do {
		icip = readl_relaxed(iobase + ICIP);
		icmr = readl_relaxed(iobase + ICMR);
		mask = icip & icmr;

		if (mask == 0)
			break;

		handle_domain_irq(sa1100_normal_irqdomain,
				ffs(mask) - 1, regs);
	} while (1);
}

void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
{
	iobase = ioremap(io_start, SZ_64K);
	if (WARN_ON(!iobase))
		return;

	/* disable all IRQs */
	writel_relaxed(0, iobase + ICMR);

	/* all IRQs are IRQ, not FIQ */
	writel_relaxed(0, iobase + ICLR);

	/*
	 * Whatever the doc says, this has to be set for the wait-on-irq
	 * instruction to work... on a SA1100 rev 9 at least.
	 */
	writel_relaxed(1, iobase + ICCR);

	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
			32, irq_start,
			&sa1100_normal_irqdomain_ops, NULL);

	set_handle_irq(sa1100_handle_irq);
}
Commit	Line	Data
1da177e4	1	/*
85e6f097	2	* Copyright (C) 2015 Dmitry Eremin-Solenikov
1da177e4 LT	3	* Copyright (C) 1999-2001 Nicolas Pitre
1da177e4 LT	4	*
85e6f097	5	* Generic IRQ handling for the SA11x0.
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/module.h>
119c641c	13	#include <linux/interrupt.h>
3169663a	14	#include <linux/io.h>
119c641c	15	#include <linux/irq.h>
1eca42b4	16	#include <linux/irqdomain.h>
90533980	17	#include <linux/syscore_ops.h>
85e6f097	18	#include <linux/irqchip/irq-sa11x0.h>
1da177e4	19
a657d7f6	20	#include <soc/sa1100/pwer.h>
1da177e4	21
affcab32	22	#include <asm/exception.h>
1da177e4	23
60c06c4c DES	24	#define ICIP 0x00 /* IC IRQ Pending reg. */
	25	#define ICMR 0x04 /* IC Mask Reg. */
	26	#define ICLR 0x08 /* IC Level Reg. */
	27	#define ICCR 0x0C /* IC Control Reg. */
	28	#define ICFP 0x10 /* IC FIQ Pending reg. */
	29	#define ICPR 0x20 /* IC Pending Reg. */
1da177e4	30
60c06c4c	31	static void __iomem *iobase;
1da177e4	32
ab71f99f DES	33	/*
	34	* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
	35	* this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
	36	*/
	37	static void sa1100_mask_irq(struct irq_data *d)
	38	{
60c06c4c DES	39	u32 reg;
	40
	41	reg = readl_relaxed(iobase + ICMR);
	42	reg &= ~BIT(d->hwirq);
	43	writel_relaxed(reg, iobase + ICMR);
ab71f99f DES	44	}
	45
	46	static void sa1100_unmask_irq(struct irq_data *d)
	47	{
60c06c4c DES	48	u32 reg;
	49
	50	reg = readl_relaxed(iobase + ICMR);
	51	reg \|= BIT(d->hwirq);
	52	writel_relaxed(reg, iobase + ICMR);
ab71f99f DES	53	}
ab71f99f DES	54
ab71f99f DES	55	static int sa1100_set_wake(struct irq_data *d, unsigned int on)
ab71f99f DES	56	{
a657d7f6	57	return sa11x0_sc_set_wake(d->hwirq, on);
ab71f99f DES	58	}
	59
	60	static struct irq_chip sa1100_normal_chip = {
	61	.name = "SC",
	62	.irq_ack = sa1100_mask_irq,
	63	.irq_mask = sa1100_mask_irq,
	64	.irq_unmask = sa1100_unmask_irq,
	65	.irq_set_wake = sa1100_set_wake,
	66	};
	67
	68	static int sa1100_normal_irqdomain_map(struct irq_domain *d,
	69	unsigned int irq, irq_hw_number_t hwirq)
	70	{
	71	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
	72	handle_level_irq);
	73	set_irq_flags(irq, IRQF_VALID);
	74
	75	return 0;
	76	}
	77
9827e8e5	78	static const struct irq_domain_ops sa1100_normal_irqdomain_ops = {
ab71f99f DES	79	.map = sa1100_normal_irqdomain_map,
	80	.xlate = irq_domain_xlate_onetwocell,
	81	};
	82
	83	static struct irq_domain *sa1100_normal_irqdomain;
	84
1da177e4 LT	85	static struct sa1100irq_state {
	86	unsigned int saved;
	87	unsigned int icmr;
	88	unsigned int iclr;
	89	unsigned int iccr;
	90	} sa1100irq_state;
	91
90533980	92	static int sa1100irq_suspend(void)
1da177e4 LT	93	{
	94	struct sa1100irq_state *st = &sa1100irq_state;
	95
	96	st->saved = 1;
60c06c4c DES	97	st->icmr = readl_relaxed(iobase + ICMR);
	98	st->iclr = readl_relaxed(iobase + ICLR);
	99	st->iccr = readl_relaxed(iobase + ICCR);
1da177e4 LT	100
	101	/*
	102	* Disable all GPIO-based interrupts.
	103	*/
60c06c4c	104	writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
1da177e4	105
1da177e4 LT	106	return 0;
	107	}
	108
90533980	109	static void sa1100irq_resume(void)
1da177e4 LT	110	{
	111	struct sa1100irq_state *st = &sa1100irq_state;
	112
	113	if (st->saved) {
60c06c4c DES	114	writel_relaxed(st->iccr, iobase + ICCR);
60c06c4c DES	115	writel_relaxed(st->iclr, iobase + ICLR);
1da177e4	116
60c06c4c	117	writel_relaxed(st->icmr, iobase + ICMR);
1da177e4	118	}
1da177e4 LT	119	}
1da177e4 LT	120
90533980	121	static struct syscore_ops sa1100irq_syscore_ops = {
1da177e4 LT	122	.suspend = sa1100irq_suspend,
	123	.resume = sa1100irq_resume,
	124	};
	125
1da177e4 LT	126	static int __init sa1100irq_init_devicefs(void)
1da177e4 LT	127	{
90533980 RW	128	register_syscore_ops(&sa1100irq_syscore_ops);
90533980 RW	129	return 0;
1da177e4 LT	130	}
	131
	132	device_initcall(sa1100irq_init_devicefs);
	133
affcab32 DES	134	static asmlinkage void __exception_irq_entry
	135	sa1100_handle_irq(struct pt_regs *regs)
	136	{
	137	uint32_t icip, icmr, mask;
	138
	139	do {
60c06c4c DES	140	icip = readl_relaxed(iobase + ICIP);
60c06c4c DES	141	icmr = readl_relaxed(iobase + ICMR);
affcab32 DES	142	mask = icip & icmr;
	143
	144	if (mask == 0)
	145	break;
	146
364e3869 DES	147	handle_domain_irq(sa1100_normal_irqdomain,
364e3869 DES	148	ffs(mask) - 1, regs);
affcab32 DES	149	} while (1);
	150	}
	151
85e6f097	152	void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
1da177e4	153	{
85e6f097	154	iobase = ioremap(io_start, SZ_64K);
60c06c4c DES	155	if (WARN_ON(!iobase))
60c06c4c DES	156	return;
1da177e4 LT	157
1da177e4 LT	158	/* disable all IRQs */
60c06c4c	159	writel_relaxed(0, iobase + ICMR);
1da177e4 LT	160
1da177e4 LT	161	/* all IRQs are IRQ, not FIQ */
60c06c4c	162	writel_relaxed(0, iobase + ICLR);
1da177e4	163
1da177e4 LT	164	/*
	165	* Whatever the doc says, this has to be set for the wait-on-irq
	166	* instruction to work... on a SA1100 rev 9 at least.
	167	*/
60c06c4c	168	writel_relaxed(1, iobase + ICCR);
1da177e4	169
a82be3f0	170	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
85e6f097	171	32, irq_start,
83508093 DES	172	&sa1100_normal_irqdomain_ops, NULL);
83508093 DES	173
affcab32	174	set_handle_irq(sa1100_handle_irq);
1da177e4	175	}