Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1f629b7a HS |
2 | /* |
3 | * S3C24XX IRQ handling | |
a21765a7 | 4 | * |
e02f8664 | 5 | * Copyright (c) 2003-2004 Simtec Electronics |
a21765a7 | 6 | * Ben Dooks <ben@simtec.co.uk> |
1f629b7a | 7 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> |
a21765a7 BD |
8 | */ |
9 | ||
10 | #include <linux/init.h> | |
1f629b7a | 11 | #include <linux/slab.h> |
a21765a7 | 12 | #include <linux/module.h> |
1f629b7a HS |
13 | #include <linux/io.h> |
14 | #include <linux/err.h> | |
a21765a7 BD |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioport.h> | |
edbaa603 | 17 | #include <linux/device.h> |
1f629b7a | 18 | #include <linux/irqdomain.h> |
41a83e06 | 19 | #include <linux/irqchip.h> |
de88cbb7 | 20 | #include <linux/irqchip/chained_irq.h> |
f0774d41 HS |
21 | #include <linux/of.h> |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_address.h> | |
a21765a7 | 24 | |
17453dd2 | 25 | #include <asm/exception.h> |
a21765a7 BD |
26 | #include <asm/mach/irq.h> |
27 | ||
1f629b7a HS |
28 | #include <mach/regs-irq.h> |
29 | #include <mach/regs-gpio.h> | |
a21765a7 | 30 | |
a2b7ba9c | 31 | #include <plat/cpu.h> |
1f629b7a | 32 | #include <plat/regs-irqtype.h> |
a2b7ba9c | 33 | #include <plat/pm.h> |
a21765a7 | 34 | |
1f629b7a HS |
35 | #define S3C_IRQTYPE_NONE 0 |
36 | #define S3C_IRQTYPE_EINT 1 | |
37 | #define S3C_IRQTYPE_EDGE 2 | |
38 | #define S3C_IRQTYPE_LEVEL 3 | |
a21765a7 | 39 | |
1f629b7a HS |
40 | struct s3c_irq_data { |
41 | unsigned int type; | |
f5a25524 | 42 | unsigned long offset; |
1f629b7a | 43 | unsigned long parent_irq; |
a21765a7 | 44 | |
1f629b7a HS |
45 | /* data gets filled during init */ |
46 | struct s3c_irq_intc *intc; | |
47 | unsigned long sub_bits; | |
48 | struct s3c_irq_intc *sub_intc; | |
a21765a7 BD |
49 | }; |
50 | ||
1f629b7a | 51 | /* |
c5f48c0a | 52 | * Structure holding the controller data |
1f629b7a HS |
53 | * @reg_pending register holding pending irqs |
54 | * @reg_intpnd special register intpnd in main intc | |
55 | * @reg_mask mask register | |
56 | * @domain irq_domain of the controller | |
57 | * @parent parent controller for ext and sub irqs | |
58 | * @irqs irq-data, always s3c_irq_data[32] | |
59 | */ | |
60 | struct s3c_irq_intc { | |
61 | void __iomem *reg_pending; | |
62 | void __iomem *reg_intpnd; | |
63 | void __iomem *reg_mask; | |
64 | struct irq_domain *domain; | |
65 | struct s3c_irq_intc *parent; | |
66 | struct s3c_irq_data *irqs; | |
a21765a7 BD |
67 | }; |
68 | ||
658dc8fb HS |
69 | /* |
70 | * Array holding pointers to the global controller structs | |
71 | * [0] ... main_intc | |
72 | * [1] ... sub_intc | |
73 | * [2] ... main_intc2 on s3c2416 | |
74 | */ | |
75 | static struct s3c_irq_intc *s3c_intc[3]; | |
76 | ||
1f629b7a | 77 | static void s3c_irq_mask(struct irq_data *data) |
a21765a7 | 78 | { |
f5a25524 HS |
79 | struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); |
80 | struct s3c_irq_intc *intc = irq_data->intc; | |
1f629b7a | 81 | struct s3c_irq_intc *parent_intc = intc->parent; |
1f629b7a | 82 | struct s3c_irq_data *parent_data; |
a21765a7 | 83 | unsigned long mask; |
1f629b7a HS |
84 | unsigned int irqno; |
85 | ||
35333285 | 86 | mask = readl_relaxed(intc->reg_mask); |
f5a25524 | 87 | mask |= (1UL << irq_data->offset); |
35333285 | 88 | writel_relaxed(mask, intc->reg_mask); |
1f629b7a | 89 | |
0fe3cb1e | 90 | if (parent_intc) { |
1f629b7a | 91 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; |
a21765a7 | 92 | |
f0774d41 HS |
93 | /* check to see if we need to mask the parent IRQ |
94 | * The parent_irq is always in main_intc, so the hwirq | |
95 | * for find_mapping does not need an offset in any case. | |
96 | */ | |
1f629b7a HS |
97 | if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { |
98 | irqno = irq_find_mapping(parent_intc->domain, | |
99 | irq_data->parent_irq); | |
100 | s3c_irq_mask(irq_get_irq_data(irqno)); | |
101 | } | |
102 | } | |
a21765a7 BD |
103 | } |
104 | ||
1f629b7a | 105 | static void s3c_irq_unmask(struct irq_data *data) |
a21765a7 | 106 | { |
f5a25524 HS |
107 | struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); |
108 | struct s3c_irq_intc *intc = irq_data->intc; | |
1f629b7a | 109 | struct s3c_irq_intc *parent_intc = intc->parent; |
a21765a7 | 110 | unsigned long mask; |
1f629b7a | 111 | unsigned int irqno; |
a21765a7 | 112 | |
35333285 | 113 | mask = readl_relaxed(intc->reg_mask); |
f5a25524 | 114 | mask &= ~(1UL << irq_data->offset); |
35333285 | 115 | writel_relaxed(mask, intc->reg_mask); |
a21765a7 | 116 | |
0fe3cb1e | 117 | if (parent_intc) { |
1f629b7a HS |
118 | irqno = irq_find_mapping(parent_intc->domain, |
119 | irq_data->parent_irq); | |
120 | s3c_irq_unmask(irq_get_irq_data(irqno)); | |
a21765a7 BD |
121 | } |
122 | } | |
123 | ||
1f629b7a | 124 | static inline void s3c_irq_ack(struct irq_data *data) |
a21765a7 | 125 | { |
f5a25524 HS |
126 | struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); |
127 | struct s3c_irq_intc *intc = irq_data->intc; | |
128 | unsigned long bitval = 1UL << irq_data->offset; | |
a21765a7 | 129 | |
35333285 | 130 | writel_relaxed(bitval, intc->reg_pending); |
1f629b7a | 131 | if (intc->reg_intpnd) |
35333285 | 132 | writel_relaxed(bitval, intc->reg_intpnd); |
a21765a7 BD |
133 | } |
134 | ||
bd7c0da2 HS |
135 | static int s3c_irq_type(struct irq_data *data, unsigned int type) |
136 | { | |
137 | switch (type) { | |
138 | case IRQ_TYPE_NONE: | |
139 | break; | |
140 | case IRQ_TYPE_EDGE_RISING: | |
141 | case IRQ_TYPE_EDGE_FALLING: | |
142 | case IRQ_TYPE_EDGE_BOTH: | |
143 | irq_set_handler(data->irq, handle_edge_irq); | |
144 | break; | |
145 | case IRQ_TYPE_LEVEL_LOW: | |
146 | case IRQ_TYPE_LEVEL_HIGH: | |
147 | irq_set_handler(data->irq, handle_level_irq); | |
148 | break; | |
149 | default: | |
6b15e085 | 150 | pr_err("No such irq type %d\n", type); |
bd7c0da2 HS |
151 | return -EINVAL; |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
1f629b7a HS |
157 | static int s3c_irqext_type_set(void __iomem *gpcon_reg, |
158 | void __iomem *extint_reg, | |
159 | unsigned long gpcon_offset, | |
160 | unsigned long extint_offset, | |
161 | unsigned int type) | |
a21765a7 | 162 | { |
a21765a7 BD |
163 | unsigned long newvalue = 0, value; |
164 | ||
a21765a7 | 165 | /* Set the GPIO to external interrupt mode */ |
35333285 | 166 | value = readl_relaxed(gpcon_reg); |
a21765a7 | 167 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
35333285 | 168 | writel_relaxed(value, gpcon_reg); |
a21765a7 BD |
169 | |
170 | /* Set the external interrupt to pointed trigger type */ | |
171 | switch (type) | |
172 | { | |
6cab4860 | 173 | case IRQ_TYPE_NONE: |
1f629b7a | 174 | pr_warn("No edge setting!\n"); |
a21765a7 BD |
175 | break; |
176 | ||
6cab4860 | 177 | case IRQ_TYPE_EDGE_RISING: |
a21765a7 BD |
178 | newvalue = S3C2410_EXTINT_RISEEDGE; |
179 | break; | |
180 | ||
6cab4860 | 181 | case IRQ_TYPE_EDGE_FALLING: |
a21765a7 BD |
182 | newvalue = S3C2410_EXTINT_FALLEDGE; |
183 | break; | |
184 | ||
6cab4860 | 185 | case IRQ_TYPE_EDGE_BOTH: |
a21765a7 BD |
186 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
187 | break; | |
188 | ||
6cab4860 | 189 | case IRQ_TYPE_LEVEL_LOW: |
a21765a7 BD |
190 | newvalue = S3C2410_EXTINT_LOWLEV; |
191 | break; | |
192 | ||
6cab4860 | 193 | case IRQ_TYPE_LEVEL_HIGH: |
a21765a7 BD |
194 | newvalue = S3C2410_EXTINT_HILEV; |
195 | break; | |
196 | ||
197 | default: | |
6b15e085 | 198 | pr_err("No such irq type %d\n", type); |
1f629b7a | 199 | return -EINVAL; |
a21765a7 BD |
200 | } |
201 | ||
35333285 | 202 | value = readl_relaxed(extint_reg); |
a21765a7 | 203 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
35333285 | 204 | writel_relaxed(value, extint_reg); |
a21765a7 BD |
205 | |
206 | return 0; | |
207 | } | |
208 | ||
dc1a3538 | 209 | static int s3c_irqext_type(struct irq_data *data, unsigned int type) |
a21765a7 | 210 | { |
1f629b7a HS |
211 | void __iomem *extint_reg; |
212 | void __iomem *gpcon_reg; | |
213 | unsigned long gpcon_offset, extint_offset; | |
a21765a7 | 214 | |
1f629b7a HS |
215 | if ((data->hwirq >= 4) && (data->hwirq <= 7)) { |
216 | gpcon_reg = S3C2410_GPFCON; | |
217 | extint_reg = S3C24XX_EXTINT0; | |
218 | gpcon_offset = (data->hwirq) * 2; | |
219 | extint_offset = (data->hwirq) * 4; | |
220 | } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { | |
221 | gpcon_reg = S3C2410_GPGCON; | |
222 | extint_reg = S3C24XX_EXTINT1; | |
223 | gpcon_offset = (data->hwirq - 8) * 2; | |
224 | extint_offset = (data->hwirq - 8) * 4; | |
225 | } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { | |
226 | gpcon_reg = S3C2410_GPGCON; | |
227 | extint_reg = S3C24XX_EXTINT2; | |
228 | gpcon_offset = (data->hwirq - 8) * 2; | |
229 | extint_offset = (data->hwirq - 16) * 4; | |
230 | } else { | |
231 | return -EINVAL; | |
232 | } | |
a21765a7 | 233 | |
1f629b7a HS |
234 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
235 | extint_offset, type); | |
a21765a7 BD |
236 | } |
237 | ||
1f629b7a | 238 | static int s3c_irqext0_type(struct irq_data *data, unsigned int type) |
a21765a7 | 239 | { |
1f629b7a HS |
240 | void __iomem *extint_reg; |
241 | void __iomem *gpcon_reg; | |
242 | unsigned long gpcon_offset, extint_offset; | |
a21765a7 | 243 | |
f3b28362 | 244 | if (data->hwirq <= 3) { |
1f629b7a HS |
245 | gpcon_reg = S3C2410_GPFCON; |
246 | extint_reg = S3C24XX_EXTINT0; | |
247 | gpcon_offset = (data->hwirq) * 2; | |
248 | extint_offset = (data->hwirq) * 4; | |
249 | } else { | |
250 | return -EINVAL; | |
251 | } | |
a21765a7 | 252 | |
1f629b7a HS |
253 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
254 | extint_offset, type); | |
a21765a7 BD |
255 | } |
256 | ||
dc1a3538 | 257 | static struct irq_chip s3c_irq_chip = { |
1f629b7a HS |
258 | .name = "s3c", |
259 | .irq_ack = s3c_irq_ack, | |
260 | .irq_mask = s3c_irq_mask, | |
261 | .irq_unmask = s3c_irq_unmask, | |
bd7c0da2 | 262 | .irq_set_type = s3c_irq_type, |
1f629b7a | 263 | .irq_set_wake = s3c_irq_wake |
a21765a7 BD |
264 | }; |
265 | ||
dc1a3538 | 266 | static struct irq_chip s3c_irq_level_chip = { |
1f629b7a HS |
267 | .name = "s3c-level", |
268 | .irq_mask = s3c_irq_mask, | |
269 | .irq_unmask = s3c_irq_unmask, | |
270 | .irq_ack = s3c_irq_ack, | |
bd7c0da2 | 271 | .irq_set_type = s3c_irq_type, |
a21765a7 BD |
272 | }; |
273 | ||
1f629b7a HS |
274 | static struct irq_chip s3c_irqext_chip = { |
275 | .name = "s3c-ext", | |
276 | .irq_mask = s3c_irq_mask, | |
277 | .irq_unmask = s3c_irq_unmask, | |
278 | .irq_ack = s3c_irq_ack, | |
279 | .irq_set_type = s3c_irqext_type, | |
280 | .irq_set_wake = s3c_irqext_wake | |
a21765a7 BD |
281 | }; |
282 | ||
1f629b7a HS |
283 | static struct irq_chip s3c_irq_eint0t4 = { |
284 | .name = "s3c-ext0", | |
285 | .irq_ack = s3c_irq_ack, | |
286 | .irq_mask = s3c_irq_mask, | |
287 | .irq_unmask = s3c_irq_unmask, | |
288 | .irq_set_wake = s3c_irq_wake, | |
289 | .irq_set_type = s3c_irqext0_type, | |
290 | }; | |
a21765a7 | 291 | |
bd0b9ac4 | 292 | static void s3c_irq_demux(struct irq_desc *desc) |
a21765a7 | 293 | { |
1f629b7a | 294 | struct irq_chip *chip = irq_desc_get_chip(desc); |
f5a25524 | 295 | struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc); |
f0774d41 | 296 | struct s3c_irq_intc *intc = irq_data->intc; |
1f629b7a | 297 | struct s3c_irq_intc *sub_intc = irq_data->sub_intc; |
4df18a66 TG |
298 | unsigned int n, offset, irq; |
299 | unsigned long src, msk; | |
f0774d41 HS |
300 | |
301 | /* we're using individual domains for the non-dt case | |
302 | * and one big domain for the dt case where the subintc | |
303 | * starts at hwirq number 32. | |
304 | */ | |
5d4c9bc7 | 305 | offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; |
1f629b7a HS |
306 | |
307 | chained_irq_enter(chip, desc); | |
308 | ||
35333285 BD |
309 | src = readl_relaxed(sub_intc->reg_pending); |
310 | msk = readl_relaxed(sub_intc->reg_mask); | |
1f629b7a HS |
311 | |
312 | src &= ~msk; | |
313 | src &= irq_data->sub_bits; | |
314 | ||
315 | while (src) { | |
316 | n = __ffs(src); | |
317 | src &= ~(1 << n); | |
f0774d41 HS |
318 | irq = irq_find_mapping(sub_intc->domain, offset + n); |
319 | generic_handle_irq(irq); | |
a21765a7 BD |
320 | } |
321 | ||
1f629b7a | 322 | chained_irq_exit(chip, desc); |
a21765a7 BD |
323 | } |
324 | ||
17453dd2 | 325 | static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, |
f0774d41 | 326 | struct pt_regs *regs, int intc_offset) |
17453dd2 HS |
327 | { |
328 | int pnd; | |
329 | int offset; | |
17453dd2 | 330 | |
35333285 | 331 | pnd = readl_relaxed(intc->reg_intpnd); |
17453dd2 HS |
332 | if (!pnd) |
333 | return false; | |
334 | ||
f0774d41 | 335 | /* non-dt machines use individual domains */ |
5d4c9bc7 | 336 | if (!irq_domain_get_of_node(intc->domain)) |
f0774d41 HS |
337 | intc_offset = 0; |
338 | ||
17453dd2 HS |
339 | /* We have a problem that the INTOFFSET register does not always |
340 | * show one interrupt. Occasionally we get two interrupts through | |
341 | * the prioritiser, and this causes the INTOFFSET register to show | |
342 | * what looks like the logical-or of the two interrupt numbers. | |
343 | * | |
344 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | |
345 | */ | |
35333285 | 346 | offset = readl_relaxed(intc->reg_intpnd + 4); |
17453dd2 HS |
347 | |
348 | /* Find the bit manually, when the offset is wrong. | |
349 | * The pending register only ever contains the one bit of the next | |
350 | * interrupt to handle. | |
351 | */ | |
352 | if (!(pnd & (1 << offset))) | |
353 | offset = __ffs(pnd); | |
354 | ||
cf86bfdd | 355 | handle_domain_irq(intc->domain, intc_offset + offset, regs); |
17453dd2 HS |
356 | return true; |
357 | } | |
358 | ||
359 | asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) | |
360 | { | |
361 | do { | |
658dc8fb | 362 | if (likely(s3c_intc[0])) |
f0774d41 | 363 | if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) |
17453dd2 HS |
364 | continue; |
365 | ||
658dc8fb | 366 | if (s3c_intc[2]) |
f0774d41 | 367 | if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) |
17453dd2 HS |
368 | continue; |
369 | ||
370 | break; | |
371 | } while (1); | |
372 | } | |
373 | ||
229fd8ff BD |
374 | #ifdef CONFIG_FIQ |
375 | /** | |
376 | * s3c24xx_set_fiq - set the FIQ routing | |
377 | * @irq: IRQ number to route to FIQ on processor. | |
378 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. | |
379 | * | |
380 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If | |
381 | * @on is true, the @irq is checked to see if it can be routed and the | |
382 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ | |
383 | * routing is cleared, regardless of which @irq is specified. | |
384 | */ | |
385 | int s3c24xx_set_fiq(unsigned int irq, bool on) | |
386 | { | |
387 | u32 intmod; | |
388 | unsigned offs; | |
389 | ||
390 | if (on) { | |
391 | offs = irq - FIQ_START; | |
392 | if (offs > 31) | |
393 | return -EINVAL; | |
394 | ||
395 | intmod = 1 << offs; | |
396 | } else { | |
397 | intmod = 0; | |
398 | } | |
399 | ||
35333285 | 400 | writel_relaxed(intmod, S3C2410_INTMOD); |
229fd8ff BD |
401 | return 0; |
402 | } | |
0f13c824 BD |
403 | |
404 | EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); | |
229fd8ff BD |
405 | #endif |
406 | ||
1f629b7a HS |
407 | static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, |
408 | irq_hw_number_t hw) | |
a21765a7 | 409 | { |
1f629b7a HS |
410 | struct s3c_irq_intc *intc = h->host_data; |
411 | struct s3c_irq_data *irq_data = &intc->irqs[hw]; | |
412 | struct s3c_irq_intc *parent_intc; | |
413 | struct s3c_irq_data *parent_irq_data; | |
414 | unsigned int irqno; | |
415 | ||
1f629b7a HS |
416 | /* attach controller pointer to irq_data */ |
417 | irq_data->intc = intc; | |
f5a25524 | 418 | irq_data->offset = hw; |
a21765a7 | 419 | |
0fe3cb1e | 420 | parent_intc = intc->parent; |
a21765a7 | 421 | |
1f629b7a HS |
422 | /* set handler and flags */ |
423 | switch (irq_data->type) { | |
424 | case S3C_IRQTYPE_NONE: | |
425 | return 0; | |
426 | case S3C_IRQTYPE_EINT: | |
1c8408e3 HS |
427 | /* On the S3C2412, the EINT0to3 have a parent irq |
428 | * but need the s3c_irq_eint0t4 chip | |
429 | */ | |
0fe3cb1e | 430 | if (parent_intc && (!soc_is_s3c2412() || hw >= 4)) |
1f629b7a HS |
431 | irq_set_chip_and_handler(virq, &s3c_irqext_chip, |
432 | handle_edge_irq); | |
433 | else | |
434 | irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, | |
435 | handle_edge_irq); | |
436 | break; | |
437 | case S3C_IRQTYPE_EDGE: | |
0fe3cb1e | 438 | if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) |
1f629b7a HS |
439 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
440 | handle_edge_irq); | |
441 | else | |
442 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | |
443 | handle_edge_irq); | |
444 | break; | |
445 | case S3C_IRQTYPE_LEVEL: | |
0fe3cb1e | 446 | if (parent_intc) |
1f629b7a HS |
447 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
448 | handle_level_irq); | |
449 | else | |
450 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | |
451 | handle_level_irq); | |
452 | break; | |
453 | default: | |
454 | pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); | |
455 | return -EINVAL; | |
a21765a7 | 456 | } |
f5a25524 HS |
457 | |
458 | irq_set_chip_data(virq, irq_data); | |
459 | ||
0fe3cb1e | 460 | if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { |
502a2989 HS |
461 | if (irq_data->parent_irq > 31) { |
462 | pr_err("irq-s3c24xx: parent irq %lu is out of range\n", | |
463 | irq_data->parent_irq); | |
d17cab44 | 464 | return -EINVAL; |
1f629b7a | 465 | } |
a21765a7 | 466 | |
1f629b7a | 467 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; |
1f629b7a HS |
468 | parent_irq_data->sub_intc = intc; |
469 | parent_irq_data->sub_bits |= (1UL << hw); | |
a21765a7 | 470 | |
1f629b7a HS |
471 | /* attach the demuxer to the parent irq */ |
472 | irqno = irq_find_mapping(parent_intc->domain, | |
473 | irq_data->parent_irq); | |
474 | if (!irqno) { | |
475 | pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", | |
476 | irq_data->parent_irq); | |
d17cab44 | 477 | return -EINVAL; |
1f629b7a HS |
478 | } |
479 | irq_set_chained_handler(irqno, s3c_irq_demux); | |
a21765a7 BD |
480 | } |
481 | ||
1f629b7a | 482 | return 0; |
1f629b7a | 483 | } |
a21765a7 | 484 | |
96009736 | 485 | static const struct irq_domain_ops s3c24xx_irq_ops = { |
1f629b7a HS |
486 | .map = s3c24xx_irq_map, |
487 | .xlate = irq_domain_xlate_twocell, | |
488 | }; | |
a21765a7 | 489 | |
1f629b7a HS |
490 | static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) |
491 | { | |
492 | void __iomem *reg_source; | |
493 | unsigned long pend; | |
494 | unsigned long last; | |
495 | int i; | |
a21765a7 | 496 | |
1f629b7a HS |
497 | /* if intpnd is set, read the next pending irq from there */ |
498 | reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; | |
a21765a7 | 499 | |
1f629b7a HS |
500 | last = 0; |
501 | for (i = 0; i < 4; i++) { | |
35333285 | 502 | pend = readl_relaxed(reg_source); |
a21765a7 | 503 | |
1f629b7a | 504 | if (pend == 0 || pend == last) |
a21765a7 BD |
505 | break; |
506 | ||
35333285 | 507 | writel_relaxed(pend, intc->reg_pending); |
1f629b7a | 508 | if (intc->reg_intpnd) |
35333285 | 509 | writel_relaxed(pend, intc->reg_intpnd); |
a21765a7 | 510 | |
1f629b7a HS |
511 | pr_info("irq: clearing pending status %08x\n", (int)pend); |
512 | last = pend; | |
a21765a7 | 513 | } |
1f629b7a | 514 | } |
a21765a7 | 515 | |
bc8fd900 | 516 | static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np, |
1f629b7a HS |
517 | struct s3c_irq_data *irq_data, |
518 | struct s3c_irq_intc *parent, | |
519 | unsigned long address) | |
520 | { | |
521 | struct s3c_irq_intc *intc; | |
522 | void __iomem *base = (void *)0xf6000000; /* static mapping */ | |
523 | int irq_num; | |
524 | int irq_start; | |
1f629b7a HS |
525 | int ret; |
526 | ||
527 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); | |
528 | if (!intc) | |
529 | return ERR_PTR(-ENOMEM); | |
530 | ||
531 | intc->irqs = irq_data; | |
532 | ||
533 | if (parent) | |
534 | intc->parent = parent; | |
535 | ||
536 | /* select the correct data for the controller. | |
537 | * Need to hard code the irq num start and offset | |
538 | * to preserve the static mapping for now | |
539 | */ | |
540 | switch (address) { | |
541 | case 0x4a000000: | |
542 | pr_debug("irq: found main intc\n"); | |
543 | intc->reg_pending = base; | |
544 | intc->reg_mask = base + 0x08; | |
545 | intc->reg_intpnd = base + 0x10; | |
546 | irq_num = 32; | |
547 | irq_start = S3C2410_IRQ(0); | |
1f629b7a HS |
548 | break; |
549 | case 0x4a000018: | |
550 | pr_debug("irq: found subintc\n"); | |
551 | intc->reg_pending = base + 0x18; | |
552 | intc->reg_mask = base + 0x1c; | |
553 | irq_num = 29; | |
554 | irq_start = S3C2410_IRQSUB(0); | |
1f629b7a HS |
555 | break; |
556 | case 0x4a000040: | |
557 | pr_debug("irq: found intc2\n"); | |
558 | intc->reg_pending = base + 0x40; | |
559 | intc->reg_mask = base + 0x48; | |
560 | intc->reg_intpnd = base + 0x50; | |
561 | irq_num = 8; | |
562 | irq_start = S3C2416_IRQ(0); | |
1f629b7a HS |
563 | break; |
564 | case 0x560000a4: | |
565 | pr_debug("irq: found eintc\n"); | |
566 | base = (void *)0xfd000000; | |
567 | ||
568 | intc->reg_mask = base + 0xa4; | |
646dd2f0 | 569 | intc->reg_pending = base + 0xa8; |
5424f218 | 570 | irq_num = 24; |
1f629b7a | 571 | irq_start = S3C2410_IRQ(32); |
1f629b7a HS |
572 | break; |
573 | default: | |
574 | pr_err("irq: unsupported controller address\n"); | |
575 | ret = -EINVAL; | |
576 | goto err; | |
577 | } | |
a21765a7 | 578 | |
1f629b7a HS |
579 | /* now that all the data is complete, init the irq-domain */ |
580 | s3c24xx_clear_intc(intc); | |
581 | intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, | |
5424f218 | 582 | 0, &s3c24xx_irq_ops, |
1f629b7a HS |
583 | intc); |
584 | if (!intc->domain) { | |
585 | pr_err("irq: could not create irq-domain\n"); | |
586 | ret = -EINVAL; | |
587 | goto err; | |
588 | } | |
a21765a7 | 589 | |
17453dd2 HS |
590 | set_handle_irq(s3c24xx_handle_irq); |
591 | ||
1f629b7a | 592 | return intc; |
a21765a7 | 593 | |
1f629b7a HS |
594 | err: |
595 | kfree(intc); | |
596 | return ERR_PTR(ret); | |
597 | } | |
a21765a7 | 598 | |
eb249a11 | 599 | static struct s3c_irq_data __maybe_unused init_eint[32] = { |
f182aa1d HS |
600 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
601 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
602 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
603 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
604 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ | |
605 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ | |
606 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ | |
607 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ | |
608 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ | |
609 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ | |
610 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ | |
611 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ | |
612 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ | |
613 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ | |
614 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ | |
615 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ | |
616 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ | |
617 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ | |
618 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ | |
619 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ | |
620 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ | |
621 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ | |
622 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ | |
623 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ | |
624 | }; | |
a21765a7 | 625 | |
f182aa1d HS |
626 | #ifdef CONFIG_CPU_S3C2410 |
627 | static struct s3c_irq_data init_s3c2410base[32] = { | |
1f629b7a HS |
628 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
629 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
630 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
631 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
632 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
633 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
634 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
635 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
636 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
637 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | |
638 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
639 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
640 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
641 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
642 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
643 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
644 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | |
645 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | |
646 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | |
647 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | |
648 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | |
649 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | |
650 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
651 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
652 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
653 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
654 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
655 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
656 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
657 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
658 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
659 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
660 | }; | |
a21765a7 | 661 | |
f182aa1d | 662 | static struct s3c_irq_data init_s3c2410subint[32] = { |
1f629b7a HS |
663 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
664 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
665 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
666 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
667 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
668 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
669 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
670 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
671 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
672 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
673 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
674 | }; | |
a21765a7 | 675 | |
f182aa1d | 676 | void __init s3c2410_init_irq(void) |
1f629b7a | 677 | { |
1f629b7a HS |
678 | #ifdef CONFIG_FIQ |
679 | init_FIQ(FIQ_START); | |
680 | #endif | |
a21765a7 | 681 | |
658dc8fb HS |
682 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, |
683 | 0x4a000000); | |
684 | if (IS_ERR(s3c_intc[0])) { | |
1f629b7a HS |
685 | pr_err("irq: could not create main interrupt controller\n"); |
686 | return; | |
a21765a7 BD |
687 | } |
688 | ||
658dc8fb HS |
689 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], |
690 | s3c_intc[0], 0x4a000018); | |
691 | s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); | |
a21765a7 | 692 | } |
f182aa1d | 693 | #endif |
ef602eb5 | 694 | |
d3d5a2c9 | 695 | #ifdef CONFIG_CPU_S3C2412 |
4245944c | 696 | static struct s3c_irq_data init_s3c2412base[32] = { |
1c8408e3 HS |
697 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ |
698 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ | |
699 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ | |
700 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ | |
4245944c HS |
701 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
702 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
1f629b7a | 703 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
4245944c HS |
704 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
705 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
706 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | |
707 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
708 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
709 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
710 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
711 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
712 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
713 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | |
714 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | |
715 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | |
716 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | |
717 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | |
718 | { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ | |
719 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
720 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
1f629b7a | 721 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
4245944c HS |
722 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
723 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
724 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
725 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
726 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
727 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
728 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
729 | }; | |
d3d5a2c9 | 730 | |
1c8408e3 HS |
731 | static struct s3c_irq_data init_s3c2412eint[32] = { |
732 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ | |
733 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ | |
734 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ | |
735 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ | |
1f629b7a HS |
736 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ |
737 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ | |
738 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ | |
739 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ | |
740 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ | |
741 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ | |
742 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ | |
743 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ | |
744 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ | |
745 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ | |
746 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ | |
747 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ | |
748 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ | |
749 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ | |
750 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ | |
751 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ | |
752 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ | |
753 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ | |
754 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ | |
755 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ | |
756 | }; | |
a21765a7 | 757 | |
4245944c | 758 | static struct s3c_irq_data init_s3c2412subint[32] = { |
1f629b7a HS |
759 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
760 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
761 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
762 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
763 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
764 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
765 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
766 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
767 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
768 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
769 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
4245944c HS |
770 | { .type = S3C_IRQTYPE_NONE, }, |
771 | { .type = S3C_IRQTYPE_NONE, }, | |
772 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ | |
773 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ | |
1f629b7a | 774 | }; |
a21765a7 | 775 | |
bc8fd900 | 776 | void __init s3c2412_init_irq(void) |
1f629b7a | 777 | { |
4245944c | 778 | pr_info("S3C2412: IRQ Support\n"); |
a21765a7 | 779 | |
1f629b7a HS |
780 | #ifdef CONFIG_FIQ |
781 | init_FIQ(FIQ_START); | |
782 | #endif | |
a21765a7 | 783 | |
658dc8fb HS |
784 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, |
785 | 0x4a000000); | |
786 | if (IS_ERR(s3c_intc[0])) { | |
1f629b7a HS |
787 | pr_err("irq: could not create main interrupt controller\n"); |
788 | return; | |
a21765a7 BD |
789 | } |
790 | ||
658dc8fb HS |
791 | s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); |
792 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], | |
793 | s3c_intc[0], 0x4a000018); | |
a21765a7 | 794 | } |
d3d5a2c9 | 795 | #endif |
ef602eb5 HS |
796 | |
797 | #ifdef CONFIG_CPU_S3C2416 | |
20f6c781 HS |
798 | static struct s3c_irq_data init_s3c2416base[32] = { |
799 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | |
800 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
801 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
802 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
803 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
804 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
805 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
806 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
807 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
808 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | |
809 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
810 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
811 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
812 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
813 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
814 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
815 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ | |
816 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ | |
817 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ | |
818 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
819 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ | |
820 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ | |
821 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
822 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
823 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ | |
824 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
825 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
826 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
827 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
828 | { .type = S3C_IRQTYPE_NONE, }, | |
829 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
830 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
ef602eb5 HS |
831 | }; |
832 | ||
20f6c781 HS |
833 | static struct s3c_irq_data init_s3c2416subint[32] = { |
834 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | |
835 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
836 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
837 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
838 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
839 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
840 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
841 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
842 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
843 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
844 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
845 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
846 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
847 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
848 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
849 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ | |
850 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ | |
851 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ | |
852 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ | |
853 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ | |
854 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ | |
855 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ | |
856 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ | |
857 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ | |
858 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ | |
859 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ | |
860 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ | |
861 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ | |
862 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | |
ef602eb5 HS |
863 | }; |
864 | ||
20f6c781 HS |
865 | static struct s3c_irq_data init_s3c2416_second[32] = { |
866 | { .type = S3C_IRQTYPE_EDGE }, /* 2D */ | |
1ebc7e83 | 867 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
20f6c781 HS |
868 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
869 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
870 | { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ | |
1ebc7e83 | 871 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
20f6c781 | 872 | { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ |
ef602eb5 HS |
873 | }; |
874 | ||
4a282dd3 | 875 | void __init s3c2416_init_irq(void) |
ef602eb5 | 876 | { |
20f6c781 | 877 | pr_info("S3C2416: IRQ Support\n"); |
ef602eb5 | 878 | |
20f6c781 HS |
879 | #ifdef CONFIG_FIQ |
880 | init_FIQ(FIQ_START); | |
881 | #endif | |
ef602eb5 | 882 | |
658dc8fb HS |
883 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, |
884 | 0x4a000000); | |
885 | if (IS_ERR(s3c_intc[0])) { | |
20f6c781 HS |
886 | pr_err("irq: could not create main interrupt controller\n"); |
887 | return; | |
888 | } | |
ef602eb5 | 889 | |
658dc8fb HS |
890 | s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); |
891 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], | |
892 | s3c_intc[0], 0x4a000018); | |
ef602eb5 | 893 | |
658dc8fb HS |
894 | s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], |
895 | NULL, 0x4a000040); | |
ef602eb5 HS |
896 | } |
897 | ||
ef602eb5 | 898 | #endif |
6b628917 | 899 | |
ce6c164b | 900 | #ifdef CONFIG_CPU_S3C2440 |
f0301673 HS |
901 | static struct s3c_irq_data init_s3c2440base[32] = { |
902 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | |
903 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
904 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
905 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
906 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
907 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
908 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | |
909 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
910 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
911 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | |
912 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
913 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
914 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
915 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
916 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
917 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
918 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | |
919 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | |
920 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | |
921 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | |
922 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | |
923 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | |
924 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
925 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
926 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ | |
927 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
928 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
929 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
930 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
931 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
932 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
933 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
934 | }; | |
2286cf46 | 935 | |
f0301673 HS |
936 | static struct s3c_irq_data init_s3c2440subint[32] = { |
937 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | |
938 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
939 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
940 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
941 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
942 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
943 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
944 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
945 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
946 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
947 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
e2714f79 HS |
948 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ |
949 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ | |
f0301673 HS |
950 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ |
951 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | |
2286cf46 HS |
952 | }; |
953 | ||
7cefed5e | 954 | void __init s3c2440_init_irq(void) |
2286cf46 | 955 | { |
f0301673 | 956 | pr_info("S3C2440: IRQ Support\n"); |
ef602eb5 | 957 | |
f0301673 HS |
958 | #ifdef CONFIG_FIQ |
959 | init_FIQ(FIQ_START); | |
960 | #endif | |
6f8d7ea2 | 961 | |
658dc8fb HS |
962 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, |
963 | 0x4a000000); | |
964 | if (IS_ERR(s3c_intc[0])) { | |
f0301673 HS |
965 | pr_err("irq: could not create main interrupt controller\n"); |
966 | return; | |
6f8d7ea2 | 967 | } |
7cefed5e | 968 | |
658dc8fb HS |
969 | s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); |
970 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], | |
971 | s3c_intc[0], 0x4a000018); | |
ef602eb5 | 972 | } |
ce6c164b | 973 | #endif |
ef602eb5 | 974 | |
ce6c164b | 975 | #ifdef CONFIG_CPU_S3C2442 |
70644ade HS |
976 | static struct s3c_irq_data init_s3c2442base[32] = { |
977 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | |
978 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
979 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
980 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
981 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
982 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
983 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | |
984 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
985 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
986 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | |
987 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
988 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
989 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
990 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
991 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
992 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
993 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | |
994 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | |
995 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | |
996 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | |
997 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | |
998 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | |
999 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
1000 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
1001 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ | |
1002 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
1003 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
1004 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
1005 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
1006 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
1007 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
1008 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
1009 | }; | |
6f8d7ea2 | 1010 | |
70644ade HS |
1011 | static struct s3c_irq_data init_s3c2442subint[32] = { |
1012 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | |
1013 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
1014 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
1015 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
1016 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
1017 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
1018 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
1019 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
1020 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
1021 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
1022 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
e2714f79 HS |
1023 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ |
1024 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ | |
70644ade | 1025 | }; |
6f8d7ea2 | 1026 | |
70644ade HS |
1027 | void __init s3c2442_init_irq(void) |
1028 | { | |
70644ade | 1029 | pr_info("S3C2442: IRQ Support\n"); |
6f8d7ea2 | 1030 | |
70644ade HS |
1031 | #ifdef CONFIG_FIQ |
1032 | init_FIQ(FIQ_START); | |
1033 | #endif | |
ce6c164b | 1034 | |
658dc8fb HS |
1035 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, |
1036 | 0x4a000000); | |
1037 | if (IS_ERR(s3c_intc[0])) { | |
70644ade HS |
1038 | pr_err("irq: could not create main interrupt controller\n"); |
1039 | return; | |
ce6c164b | 1040 | } |
70644ade | 1041 | |
658dc8fb HS |
1042 | s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); |
1043 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], | |
1044 | s3c_intc[0], 0x4a000018); | |
6f8d7ea2 | 1045 | } |
ef602eb5 | 1046 | #endif |
6b628917 HS |
1047 | |
1048 | #ifdef CONFIG_CPU_S3C2443 | |
f44ddba3 HS |
1049 | static struct s3c_irq_data init_s3c2443base[32] = { |
1050 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | |
1051 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
1052 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
1053 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
1054 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
1055 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
1056 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ | |
1057 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
1058 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
1059 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ | |
1060 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
1061 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
1062 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
1063 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
1064 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
1065 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
1066 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ | |
1067 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ | |
1068 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ | |
1069 | { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ | |
1070 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ | |
1071 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ | |
1072 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
1073 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
1074 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ | |
1075 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
1076 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
1077 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
1078 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
1079 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
1080 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
1081 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
6b628917 HS |
1082 | }; |
1083 | ||
6b628917 | 1084 | |
f44ddba3 HS |
1085 | static struct s3c_irq_data init_s3c2443subint[32] = { |
1086 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | |
1087 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
1088 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
1089 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
1090 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
1091 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
1092 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
1093 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
1094 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
1095 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
1096 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
1097 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ | |
1098 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ | |
1099 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ | |
1100 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ | |
1101 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ | |
1102 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ | |
1103 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ | |
1104 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ | |
1105 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ | |
1106 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ | |
1107 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ | |
1108 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ | |
1109 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ | |
1110 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ | |
1111 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ | |
1112 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ | |
1113 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ | |
1114 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ | |
6b628917 HS |
1115 | }; |
1116 | ||
b499b7a8 | 1117 | void __init s3c2443_init_irq(void) |
6b628917 | 1118 | { |
f44ddba3 | 1119 | pr_info("S3C2443: IRQ Support\n"); |
6b628917 | 1120 | |
f44ddba3 HS |
1121 | #ifdef CONFIG_FIQ |
1122 | init_FIQ(FIQ_START); | |
1123 | #endif | |
6b628917 | 1124 | |
658dc8fb HS |
1125 | s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, |
1126 | 0x4a000000); | |
1127 | if (IS_ERR(s3c_intc[0])) { | |
f44ddba3 HS |
1128 | pr_err("irq: could not create main interrupt controller\n"); |
1129 | return; | |
1130 | } | |
6b628917 | 1131 | |
658dc8fb HS |
1132 | s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); |
1133 | s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], | |
1134 | s3c_intc[0], 0x4a000018); | |
6b628917 | 1135 | } |
6b628917 | 1136 | #endif |
f0774d41 HS |
1137 | |
1138 | #ifdef CONFIG_OF | |
1139 | static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq, | |
1140 | irq_hw_number_t hw) | |
1141 | { | |
1142 | unsigned int ctrl_num = hw / 32; | |
1143 | unsigned int intc_hw = hw % 32; | |
1144 | struct s3c_irq_intc *intc = s3c_intc[ctrl_num]; | |
1145 | struct s3c_irq_intc *parent_intc = intc->parent; | |
1146 | struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; | |
1147 | ||
1148 | /* attach controller pointer to irq_data */ | |
1149 | irq_data->intc = intc; | |
1150 | irq_data->offset = intc_hw; | |
1151 | ||
1152 | if (!parent_intc) | |
1153 | irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); | |
1154 | else | |
1155 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, | |
1156 | handle_edge_irq); | |
1157 | ||
1158 | irq_set_chip_data(virq, irq_data); | |
1159 | ||
f0774d41 HS |
1160 | return 0; |
1161 | } | |
1162 | ||
1163 | /* Translate our of irq notation | |
1164 | * format: <ctrl_num ctrl_irq parent_irq type> | |
1165 | */ | |
1166 | static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n, | |
1167 | const u32 *intspec, unsigned int intsize, | |
1168 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | |
1169 | { | |
1170 | struct s3c_irq_intc *intc; | |
1171 | struct s3c_irq_intc *parent_intc; | |
1172 | struct s3c_irq_data *irq_data; | |
1173 | struct s3c_irq_data *parent_irq_data; | |
1174 | int irqno; | |
1175 | ||
1176 | if (WARN_ON(intsize < 4)) | |
1177 | return -EINVAL; | |
1178 | ||
1179 | if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { | |
1180 | pr_err("controller number %d invalid\n", intspec[0]); | |
1181 | return -EINVAL; | |
1182 | } | |
1183 | intc = s3c_intc[intspec[0]]; | |
1184 | ||
1185 | *out_hwirq = intspec[0] * 32 + intspec[2]; | |
1186 | *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; | |
1187 | ||
1188 | parent_intc = intc->parent; | |
1189 | if (parent_intc) { | |
1190 | irq_data = &intc->irqs[intspec[2]]; | |
1191 | irq_data->parent_irq = intspec[1]; | |
1192 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; | |
1193 | parent_irq_data->sub_intc = intc; | |
1194 | parent_irq_data->sub_bits |= (1UL << intspec[2]); | |
1195 | ||
1196 | /* parent_intc is always s3c_intc[0], so no offset */ | |
1197 | irqno = irq_create_mapping(parent_intc->domain, intspec[1]); | |
1198 | if (irqno < 0) { | |
1199 | pr_err("irq: could not map parent interrupt\n"); | |
1200 | return irqno; | |
1201 | } | |
1202 | ||
1203 | irq_set_chained_handler(irqno, s3c_irq_demux); | |
1204 | } | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
96009736 | 1209 | static const struct irq_domain_ops s3c24xx_irq_ops_of = { |
f0774d41 HS |
1210 | .map = s3c24xx_irq_map_of, |
1211 | .xlate = s3c24xx_irq_xlate_of, | |
1212 | }; | |
1213 | ||
1214 | struct s3c24xx_irq_of_ctrl { | |
1215 | char *name; | |
1216 | unsigned long offset; | |
1217 | struct s3c_irq_intc **handle; | |
1218 | struct s3c_irq_intc **parent; | |
1219 | struct irq_domain_ops *ops; | |
1220 | }; | |
1221 | ||
1222 | static int __init s3c_init_intc_of(struct device_node *np, | |
1223 | struct device_node *interrupt_parent, | |
1224 | struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl) | |
1225 | { | |
1226 | struct s3c_irq_intc *intc; | |
1227 | struct s3c24xx_irq_of_ctrl *ctrl; | |
1228 | struct irq_domain *domain; | |
1229 | void __iomem *reg_base; | |
1230 | int i; | |
1231 | ||
1232 | reg_base = of_iomap(np, 0); | |
1233 | if (!reg_base) { | |
1234 | pr_err("irq-s3c24xx: could not map irq registers\n"); | |
1235 | return -EINVAL; | |
1236 | } | |
1237 | ||
1238 | domain = irq_domain_add_linear(np, num_ctrl * 32, | |
1239 | &s3c24xx_irq_ops_of, NULL); | |
1240 | if (!domain) { | |
1241 | pr_err("irq: could not create irq-domain\n"); | |
1242 | return -EINVAL; | |
1243 | } | |
1244 | ||
1245 | for (i = 0; i < num_ctrl; i++) { | |
1246 | ctrl = &s3c_ctrl[i]; | |
1247 | ||
1248 | pr_debug("irq: found controller %s\n", ctrl->name); | |
1249 | ||
1250 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); | |
1251 | if (!intc) | |
1252 | return -ENOMEM; | |
1253 | ||
1254 | intc->domain = domain; | |
6396bb22 | 1255 | intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data), |
f0774d41 HS |
1256 | GFP_KERNEL); |
1257 | if (!intc->irqs) { | |
1258 | kfree(intc); | |
1259 | return -ENOMEM; | |
1260 | } | |
1261 | ||
1262 | if (ctrl->parent) { | |
1263 | intc->reg_pending = reg_base + ctrl->offset; | |
1264 | intc->reg_mask = reg_base + ctrl->offset + 0x4; | |
1265 | ||
1266 | if (*(ctrl->parent)) { | |
1267 | intc->parent = *(ctrl->parent); | |
1268 | } else { | |
1269 | pr_warn("irq: parent of %s missing\n", | |
1270 | ctrl->name); | |
1271 | kfree(intc->irqs); | |
1272 | kfree(intc); | |
1273 | continue; | |
1274 | } | |
1275 | } else { | |
1276 | intc->reg_pending = reg_base + ctrl->offset; | |
1277 | intc->reg_mask = reg_base + ctrl->offset + 0x08; | |
1278 | intc->reg_intpnd = reg_base + ctrl->offset + 0x10; | |
1279 | } | |
1280 | ||
1281 | s3c24xx_clear_intc(intc); | |
1282 | s3c_intc[i] = intc; | |
1283 | } | |
1284 | ||
1285 | set_handle_irq(s3c24xx_handle_irq); | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { | |
1291 | { | |
1292 | .name = "intc", | |
1293 | .offset = 0, | |
1294 | }, { | |
1295 | .name = "subintc", | |
1296 | .offset = 0x18, | |
1297 | .parent = &s3c_intc[0], | |
1298 | } | |
1299 | }; | |
1300 | ||
1301 | int __init s3c2410_init_intc_of(struct device_node *np, | |
4f41083b | 1302 | struct device_node *interrupt_parent) |
f0774d41 HS |
1303 | { |
1304 | return s3c_init_intc_of(np, interrupt_parent, | |
1305 | s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl)); | |
1306 | } | |
1307 | IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of); | |
1308 | ||
1309 | static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { | |
1310 | { | |
1311 | .name = "intc", | |
1312 | .offset = 0, | |
1313 | }, { | |
1314 | .name = "subintc", | |
1315 | .offset = 0x18, | |
1316 | .parent = &s3c_intc[0], | |
1317 | }, { | |
1318 | .name = "intc2", | |
1319 | .offset = 0x40, | |
1320 | } | |
1321 | }; | |
1322 | ||
1323 | int __init s3c2416_init_intc_of(struct device_node *np, | |
4f41083b | 1324 | struct device_node *interrupt_parent) |
f0774d41 HS |
1325 | { |
1326 | return s3c_init_intc_of(np, interrupt_parent, | |
1327 | s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl)); | |
6b628917 | 1328 | } |
f0774d41 | 1329 | IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of); |
6b628917 | 1330 | #endif |