[linux-block.git] / drivers / irqchip / irq-riscv-intc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2012 Regents of the University of California
 * Copyright (C) 2017-2018 SiFive
 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
 */

#define pr_fmt(fmt) "riscv-intc: " fmt
#include <linux/atomic.h>
#include <linux/bits.h>
#include <linux/cpu.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>

static struct irq_domain *intc_domain;

static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;

	if (unlikely(cause >= BITS_PER_LONG))
		panic("unexpected interrupt cause");

	switch (cause) {
#ifdef CONFIG_SMP
	case RV_IRQ_SOFT:
		/*
		 * We only use software interrupts to pass IPIs, so if a
		 * non-SMP system gets one, then we don't know what to do.
		 */
		handle_IPI(regs);
		break;
#endif
	default:
		generic_handle_domain_irq(intc_domain, cause);
		break;
	}
}

/*
 * On RISC-V systems local interrupts are masked or unmasked by writing
 * the SIE (Supervisor Interrupt Enable) CSR.  As CSRs can only be written
 * on the local hart, these functions can only be called on the hart that
 * corresponds to the IRQ chip.
 */

static void riscv_intc_irq_mask(struct irq_data *d)
{
	csr_clear(CSR_IE, BIT(d->hwirq));
}

static void riscv_intc_irq_unmask(struct irq_data *d)
{
	csr_set(CSR_IE, BIT(d->hwirq));
}

static int riscv_intc_cpu_starting(unsigned int cpu)
{
	csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
	return 0;
}

static int riscv_intc_cpu_dying(unsigned int cpu)
{
	csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
	return 0;
}

static struct irq_chip riscv_intc_chip = {
	.name = "RISC-V INTC",
	.irq_mask = riscv_intc_irq_mask,
	.irq_unmask = riscv_intc_irq_unmask,
};

static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	irq_set_percpu_devid(irq);
	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
			    handle_percpu_devid_irq, NULL, NULL);

	return 0;
}

static const struct irq_domain_ops riscv_intc_domain_ops = {
	.map	= riscv_intc_domain_map,
	.xlate	= irq_domain_xlate_onecell,
};

static int __init riscv_intc_init(struct device_node *node,
				  struct device_node *parent)
{
	int rc;
	unsigned long hartid;

	rc = riscv_of_parent_hartid(node, &hartid);
	if (rc < 0) {
		pr_warn("unable to find hart id for %pOF\n", node);
		return 0;
	}

	/*
	 * The DT will have one INTC DT node under each CPU (or HART)
	 * DT node so riscv_intc_init() function will be called once
	 * for each INTC DT node. We only need to do INTC initialization
	 * for the INTC DT node belonging to boot CPU (or boot HART).
	 */
	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
		return 0;

	intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
					    &riscv_intc_domain_ops, NULL);
	if (!intc_domain) {
		pr_err("unable to add IRQ domain\n");
		return -ENXIO;
	}

	rc = set_handle_irq(&riscv_intc_irq);
	if (rc) {
		pr_err("failed to set irq handler\n");
		return rc;
	}

	cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
			  "irqchip/riscv/intc:starting",
			  riscv_intc_cpu_starting,
			  riscv_intc_cpu_dying);

	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);

	return 0;
}

IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
Commit	Line	Data
6b7ce892 AP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2012 Regents of the University of California
	4	* Copyright (C) 2017-2018 SiFive
	5	* Copyright (C) 2020 Western Digital Corporation or its affiliates.
	6	*/
	7
	8	#define pr_fmt(fmt) "riscv-intc: " fmt
	9	#include <linux/atomic.h>
	10	#include <linux/bits.h>
	11	#include <linux/cpu.h>
	12	#include <linux/irq.h>
	13	#include <linux/irqchip.h>
	14	#include <linux/irqdomain.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/smp.h>
	19
	20	static struct irq_domain *intc_domain;
	21
	22	static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
	23	{
6b7ce892 AP	24	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
	25
	26	if (unlikely(cause >= BITS_PER_LONG))
	27	panic("unexpected interrupt cause");
	28
	29	switch (cause) {
6b7ce892 AP	30	#ifdef CONFIG_SMP
	31	case RV_IRQ_SOFT:
	32	/*
	33	* We only use software interrupts to pass IPIs, so if a
	34	* non-SMP system gets one, then we don't know what to do.
	35	*/
	36	handle_IPI(regs);
	37	break;
	38	#endif
	39	default:
0953fb26	40	generic_handle_domain_irq(intc_domain, cause);
6b7ce892 AP	41	break;
	42	}
	43	}
	44
	45	/*
	46	* On RISC-V systems local interrupts are masked or unmasked by writing
	47	* the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written
	48	* on the local hart, these functions can only be called on the hart that
	49	* corresponds to the IRQ chip.
	50	*/
	51
	52	static void riscv_intc_irq_mask(struct irq_data *d)
	53	{
	54	csr_clear(CSR_IE, BIT(d->hwirq));
	55	}
	56
	57	static void riscv_intc_irq_unmask(struct irq_data *d)
	58	{
	59	csr_set(CSR_IE, BIT(d->hwirq));
	60	}
	61
	62	static int riscv_intc_cpu_starting(unsigned int cpu)
	63	{
	64	csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
	65	return 0;
	66	}
	67
	68	static int riscv_intc_cpu_dying(unsigned int cpu)
	69	{
	70	csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
	71	return 0;
	72	}
	73
	74	static struct irq_chip riscv_intc_chip = {
	75	.name = "RISC-V INTC",
	76	.irq_mask = riscv_intc_irq_mask,
	77	.irq_unmask = riscv_intc_irq_unmask,
	78	};
	79
	80	static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
	81	irq_hw_number_t hwirq)
	82	{
	83	irq_set_percpu_devid(irq);
	84	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
	85	handle_percpu_devid_irq, NULL, NULL);
	86
	87	return 0;
	88	}
	89
	90	static const struct irq_domain_ops riscv_intc_domain_ops = {
	91	.map = riscv_intc_domain_map,
	92	.xlate = irq_domain_xlate_onecell,
	93	};
	94
	95	static int __init riscv_intc_init(struct device_node *node,
	96	struct device_node *parent)
	97	{
ad635e72 S	98	int rc;
ad635e72 S	99	unsigned long hartid;
6b7ce892	100
ad635e72 S	101	rc = riscv_of_parent_hartid(node, &hartid);
ad635e72 S	102	if (rc < 0) {
559fe74b	103	pr_warn("unable to find hart id for %pOF\n", node);
6b7ce892 AP	104	return 0;
	105	}
	106
	107	/*
	108	* The DT will have one INTC DT node under each CPU (or HART)
	109	* DT node so riscv_intc_init() function will be called once
	110	* for each INTC DT node. We only need to do INTC initialization
	111	* for the INTC DT node belonging to boot CPU (or boot HART).
	112	*/
	113	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
	114	return 0;
	115
	116	intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
	117	&riscv_intc_domain_ops, NULL);
	118	if (!intc_domain) {
	119	pr_err("unable to add IRQ domain\n");
	120	return -ENXIO;
	121	}
	122
	123	rc = set_handle_irq(&riscv_intc_irq);
	124	if (rc) {
	125	pr_err("failed to set irq handler\n");
	126	return rc;
	127	}
	128
	129	cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
	130	"irqchip/riscv/intc:starting",
	131	riscv_intc_cpu_starting,
	132	riscv_intc_cpu_dying);
	133
	134	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
	135
	136	return 0;
	137	}
	138
	139	IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);