[linux-2.6-block.git] / drivers / irqchip / irq-renesas-irqc.c

/*
 * Renesas IRQC Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_data/irq-renesas-irqc.h>

#define IRQC_IRQ_MAX	32	/* maximum 32 interrupts per driver instance */

#define IRQC_REQ_STS	0x00	/* Interrupt Request Status Register */
#define IRQC_EN_STS	0x04	/* Interrupt Enable Status Register */
#define IRQC_EN_SET	0x08	/* Interrupt Enable Set Register */
#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
				/* SYS-CPU vs. RT-CPU */
#define DETECT_STATUS	0x100	/* IRQn Detect Status Register */
#define MONITOR		0x104	/* IRQn Signal Level Monitor Register */
#define HLVL_STS	0x108	/* IRQn High Level Detect Status Register */
#define LLVL_STS	0x10c	/* IRQn Low Level Detect Status Register */
#define S_R_EDGE_STS	0x110	/* IRQn Sync Rising Edge Detect Status Reg. */
#define S_F_EDGE_STS	0x114	/* IRQn Sync Falling Edge Detect Status Reg. */
#define A_R_EDGE_STS	0x118	/* IRQn Async Rising Edge Detect Status Reg. */
#define A_F_EDGE_STS	0x11c	/* IRQn Async Falling Edge Detect Status Reg. */
#define CHTEN_STS	0x120	/* Chattering Reduction Status Register */
#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
				/* IRQn Configuration Register */

struct irqc_irq {
	int hw_irq;
	int requested_irq;
	int domain_irq;
	struct irqc_priv *p;
};

struct irqc_priv {
	void __iomem *iomem;
	void __iomem *cpu_int_base;
	struct irqc_irq irq[IRQC_IRQ_MAX];
	struct renesas_irqc_config config;
	unsigned int number_of_irqs;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

static void irqc_dbg(struct irqc_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->requested_irq, i->hw_irq, i->domain_irq);
}

static void irqc_irq_enable(struct irq_data *d)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irqc_dbg(&p->irq[hw_irq], "enable");
	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
}

static void irqc_irq_disable(struct irq_data *d)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irqc_dbg(&p->irq[hw_irq], "disable");
	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
}

static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_LEVEL_LOW]	= 0x01,
	[IRQ_TYPE_LEVEL_HIGH]	= 0x02,
	[IRQ_TYPE_EDGE_FALLING]	= 0x04,	/* Synchronous */
	[IRQ_TYPE_EDGE_RISING]	= 0x08,	/* Synchronous */
	[IRQ_TYPE_EDGE_BOTH]	= 0x0c,	/* Synchronous */
};

static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);
	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
	unsigned long tmp;

	irqc_dbg(&p->irq[hw_irq], "sense");

	if (!value)
		return -EINVAL;

	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	tmp &= ~0x3f;
	tmp |= value;
	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	return 0;
}

static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
{
	struct irqc_irq *i = dev_id;
	struct irqc_priv *p = i->p;
	unsigned long bit = BIT(i->hw_irq);

	irqc_dbg(i, "demux1");

	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
		iowrite32(bit, p->iomem + DETECT_STATUS);
		irqc_dbg(i, "demux2");
		generic_handle_irq(i->domain_irq);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
			       irq_hw_number_t hw)
{
	struct irqc_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	irqc_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops irqc_irq_domain_ops = {
	.map	= irqc_irq_domain_map,
	.xlate  = irq_domain_xlate_twocell,
};

static int irqc_probe(struct platform_device *pdev)
{
	struct renesas_irqc_config *pdata = pdev->dev.platform_data;
	struct irqc_priv *p;
	struct resource *io;
	struct resource *irq;
	struct irq_chip *irq_chip;
	const char *name = dev_name(&pdev->dev);
	int ret;
	int k;

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		ret = -ENOMEM;
		goto err0;
	}

	/* deal with driver instance configuration */
	if (pdata)
		memcpy(&p->config, pdata, sizeof(*pdata));

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	/* get hold of manadatory IOMEM */
	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!io) {
		dev_err(&pdev->dev, "not enough IOMEM resources\n");
		ret = -EINVAL;
		goto err1;
	}

	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	for (k = 0; k < IRQC_IRQ_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].p = p;
		p->irq[k].requested_irq = irq->start;
	}

	p->number_of_irqs = k;
	if (p->number_of_irqs < 1) {
		dev_err(&pdev->dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err1;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	p->iomem = ioremap_nocache(io->start, resource_size(io));
	if (!p->iomem) {
		dev_err(&pdev->dev, "failed to remap IOMEM\n");
		ret = -ENXIO;
		goto err2;
	}

	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = irqc_irq_disable;
	irq_chip->irq_unmask = irqc_irq_enable;
	irq_chip->irq_set_type = irqc_irq_set_type;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      p->number_of_irqs,
					      p->config.irq_base,
					      &irqc_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err2;
	}

	/* request interrupts one by one */
	for (k = 0; k < p->number_of_irqs; k++) {
		if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
				0, name, &p->irq[k])) {
			dev_err(&pdev->dev, "failed to request IRQ\n");
			ret = -ENOENT;
			goto err3;
		}
	}

	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);

	/* warn in case of mismatch if irq base is specified */
	if (p->config.irq_base) {
		if (p->config.irq_base != p->irq[0].domain_irq)
			dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
				 p->config.irq_base, p->irq[0].domain_irq);
	}

	return 0;
err3:
	while (--k >= 0)
		free_irq(p->irq[k].requested_irq, &p->irq[k]);

	irq_domain_remove(p->irq_domain);
err2:
	iounmap(p->iomem);
err1:
	kfree(p);
err0:
	return ret;
}

static int irqc_remove(struct platform_device *pdev)
{
	struct irqc_priv *p = platform_get_drvdata(pdev);
	int k;

	for (k = 0; k < p->number_of_irqs; k++)
		free_irq(p->irq[k].requested_irq, &p->irq[k]);

	irq_domain_remove(p->irq_domain);
	iounmap(p->iomem);
	kfree(p);
	return 0;
}

static const struct of_device_id irqc_dt_ids[] = {
	{ .compatible = "renesas,irqc", },
	{},
};
MODULE_DEVICE_TABLE(of, irqc_dt_ids);

static struct platform_driver irqc_device_driver = {
	.probe		= irqc_probe,
	.remove		= irqc_remove,
	.driver		= {
		.name	= "renesas_irqc",
		.of_match_table	= irqc_dt_ids,
	}
};

static int __init irqc_init(void)
{
	return platform_driver_register(&irqc_device_driver);
}
postcore_initcall(irqc_init);

static void __exit irqc_exit(void)
{
	platform_driver_unregister(&irqc_device_driver);
}
module_exit(irqc_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas IRQC Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fbc83b7f MD	1	/*
	2	* Renesas IRQC Driver
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/irqdomain.h>
	28	#include <linux/err.h>
	29	#include <linux/slab.h>
	30	#include <linux/module.h>
	31	#include <linux/platform_data/irq-renesas-irqc.h>
	32
1cd5ec73	33	#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
fbc83b7f	34
1cd5ec73 GU	35	#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
	36	#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
	37	#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
fbc83b7f	38	#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
1cd5ec73 GU	39	/* SYS-CPU vs. RT-CPU */
	40	#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
	41	#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
	42	#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
	43	#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
	44	#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
	45	#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
	46	#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
	47	#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
	48	#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
fbc83b7f	49	#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
1cd5ec73	50	/* IRQn Configuration Register */
fbc83b7f MD	51
	52	struct irqc_irq {
	53	int hw_irq;
	54	int requested_irq;
	55	int domain_irq;
	56	struct irqc_priv *p;
	57	};
	58
	59	struct irqc_priv {
	60	void __iomem *iomem;
	61	void __iomem *cpu_int_base;
	62	struct irqc_irq irq[IRQC_IRQ_MAX];
	63	struct renesas_irqc_config config;
	64	unsigned int number_of_irqs;
	65	struct platform_device *pdev;
	66	struct irq_chip irq_chip;
	67	struct irq_domain *irq_domain;
	68	};
	69
	70	static void irqc_dbg(struct irqc_irq i, char str)
	71	{
	72	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
	73	str, i->requested_irq, i->hw_irq, i->domain_irq);
	74	}
	75
	76	static void irqc_irq_enable(struct irq_data *d)
	77	{
	78	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	79	int hw_irq = irqd_to_hwirq(d);
	80
	81	irqc_dbg(&p->irq[hw_irq], "enable");
	82	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
	83	}
	84
	85	static void irqc_irq_disable(struct irq_data *d)
	86	{
	87	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	88	int hw_irq = irqd_to_hwirq(d);
	89
	90	irqc_dbg(&p->irq[hw_irq], "disable");
	91	iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
	92	}
	93
fbc83b7f	94	static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
ce70af18 SS	95	[IRQ_TYPE_LEVEL_LOW] = 0x01,
	96	[IRQ_TYPE_LEVEL_HIGH] = 0x02,
	97	[IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
	98	[IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
	99	[IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
fbc83b7f MD	100	};
	101
	102	static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
	103	{
	104	struct irqc_priv *p = irq_data_get_irq_chip_data(d);
	105	int hw_irq = irqd_to_hwirq(d);
	106	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
	107	unsigned long tmp;
	108
	109	irqc_dbg(&p->irq[hw_irq], "sense");
	110
ce70af18	111	if (!value)
fbc83b7f MD	112	return -EINVAL;
	113
	114	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	115	tmp &= ~0x3f;
ce70af18	116	tmp \|= value;
fbc83b7f MD	117	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	118	return 0;
	119	}
	120
	121	static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
	122	{
	123	struct irqc_irq *i = dev_id;
	124	struct irqc_priv *p = i->p;
	125	unsigned long bit = BIT(i->hw_irq);
	126
	127	irqc_dbg(i, "demux1");
	128
	129	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
	130	iowrite32(bit, p->iomem + DETECT_STATUS);
	131	irqc_dbg(i, "demux2");
	132	generic_handle_irq(i->domain_irq);
	133	return IRQ_HANDLED;
	134	}
	135	return IRQ_NONE;
	136	}
	137
	138	static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
	139	irq_hw_number_t hw)
	140	{
	141	struct irqc_priv *p = h->host_data;
	142
	143	p->irq[hw].domain_irq = virq;
	144	p->irq[hw].hw_irq = hw;
	145
	146	irqc_dbg(&p->irq[hw], "map");
	147	irq_set_chip_data(virq, h->host_data);
	148	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	149	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	150	return 0;
	151	}
	152
	153	static struct irq_domain_ops irqc_irq_domain_ops = {
	154	.map = irqc_irq_domain_map,
3b8dfa7c	155	.xlate = irq_domain_xlate_twocell,
fbc83b7f MD	156	};
	157
	158	static int irqc_probe(struct platform_device *pdev)
	159	{
	160	struct renesas_irqc_config *pdata = pdev->dev.platform_data;
	161	struct irqc_priv *p;
	162	struct resource *io;
	163	struct resource *irq;
	164	struct irq_chip *irq_chip;
	165	const char *name = dev_name(&pdev->dev);
	166	int ret;
	167	int k;
	168
	169	p = kzalloc(sizeof(*p), GFP_KERNEL);
	170	if (!p) {
	171	dev_err(&pdev->dev, "failed to allocate driver data\n");
	172	ret = -ENOMEM;
	173	goto err0;
	174	}
	175
	176	/* deal with driver instance configuration */
	177	if (pdata)
	178	memcpy(&p->config, pdata, sizeof(*pdata));
	179
	180	p->pdev = pdev;
	181	platform_set_drvdata(pdev, p);
	182
	183	/* get hold of manadatory IOMEM */
	184	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	185	if (!io) {
	186	dev_err(&pdev->dev, "not enough IOMEM resources\n");
	187	ret = -EINVAL;
	188	goto err1;
	189	}
	190
	191	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	192	for (k = 0; k < IRQC_IRQ_MAX; k++) {
	193	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
	194	if (!irq)
	195	break;
	196
	197	p->irq[k].p = p;
	198	p->irq[k].requested_irq = irq->start;
	199	}
	200
	201	p->number_of_irqs = k;
	202	if (p->number_of_irqs < 1) {
	203	dev_err(&pdev->dev, "not enough IRQ resources\n");
	204	ret = -EINVAL;
	205	goto err1;
	206	}
	207
	208	/* ioremap IOMEM and setup read/write callbacks */
	209	p->iomem = ioremap_nocache(io->start, resource_size(io));
	210	if (!p->iomem) {
	211	dev_err(&pdev->dev, "failed to remap IOMEM\n");
	212	ret = -ENXIO;
	213	goto err2;
	214	}
	215
	216	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
	217
	218	irq_chip = &p->irq_chip;
	219	irq_chip->name = name;
220	irq_chip->irq_mask = irqc_irq_disable;
221	irq_chip->irq_unmask = irqc_irq_enable;
fbc83b7f	222	irq_chip->irq_set_type = irqc_irq_set_type;
6a7e3b30	223	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND;
fbc83b7f MD	224
	225	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
	226	p->number_of_irqs,
	227	p->config.irq_base,
	228	&irqc_irq_domain_ops, p);
	229	if (!p->irq_domain) {
	230	ret = -ENXIO;
	231	dev_err(&pdev->dev, "cannot initialize irq domain\n");
	232	goto err2;
	233	}
	234
	235	/* request interrupts one by one */
	236	for (k = 0; k < p->number_of_irqs; k++) {
	237	if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
	238	0, name, &p->irq[k])) {
	239	dev_err(&pdev->dev, "failed to request IRQ\n");
	240	ret = -ENOENT;
	241	goto err3;
	242	}
	243	}
	244
	245	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
	246
	247	/* warn in case of mismatch if irq base is specified */
	248	if (p->config.irq_base) {
	249	if (p->config.irq_base != p->irq[0].domain_irq)
	250	dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
	251	p->config.irq_base, p->irq[0].domain_irq);
	252	}
	253
	254	return 0;
	255	err3:
dfaf820a AL	256	while (--k >= 0)
dfaf820a AL	257	free_irq(p->irq[k].requested_irq, &p->irq[k]);
fbc83b7f MD	258
	259	irq_domain_remove(p->irq_domain);
	260	err2:
	261	iounmap(p->iomem);
	262	err1:
	263	kfree(p);
	264	err0:
	265	return ret;
	266	}
	267
	268	static int irqc_remove(struct platform_device *pdev)
	269	{
	270	struct irqc_priv *p = platform_get_drvdata(pdev);
	271	int k;
	272
	273	for (k = 0; k < p->number_of_irqs; k++)
	274	free_irq(p->irq[k].requested_irq, &p->irq[k]);
	275
	276	irq_domain_remove(p->irq_domain);
	277	iounmap(p->iomem);
	278	kfree(p);
	279	return 0;
	280	}
	281
3b8dfa7c MD	282	static const struct of_device_id irqc_dt_ids[] = {
	283	{ .compatible = "renesas,irqc", },
	284	{},
	285	};
	286	MODULE_DEVICE_TABLE(of, irqc_dt_ids);
	287
fbc83b7f MD	288	static struct platform_driver irqc_device_driver = {
	289	.probe = irqc_probe,
	290	.remove = irqc_remove,
	291	.driver = {
	292	.name = "renesas_irqc",
3b8dfa7c	293	.of_match_table = irqc_dt_ids,
fbc83b7f MD	294	}
	295	};
	296
	297	static int __init irqc_init(void)
	298	{
	299	return platform_driver_register(&irqc_device_driver);
	300	}
	301	postcore_initcall(irqc_init);
	302
	303	static void __exit irqc_exit(void)
	304	{
	305	platform_driver_unregister(&irqc_device_driver);
	306	}
	307	module_exit(irqc_exit);
	308
	309	MODULE_AUTHOR("Magnus Damm");
	310	MODULE_DESCRIPTION("Renesas IRQC Driver");
	311	MODULE_LICENSE("GPL v2");