[linux-2.6-block.git] / drivers / irqchip / irq-renesas-irqc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas IRQC Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>

#define IRQC_IRQ_MAX	32	/* maximum 32 interrupts per driver instance */

#define IRQC_REQ_STS	0x00	/* Interrupt Request Status Register */
#define IRQC_EN_STS	0x04	/* Interrupt Enable Status Register */
#define IRQC_EN_SET	0x08	/* Interrupt Enable Set Register */
#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
				/* SYS-CPU vs. RT-CPU */
#define DETECT_STATUS	0x100	/* IRQn Detect Status Register */
#define MONITOR		0x104	/* IRQn Signal Level Monitor Register */
#define HLVL_STS	0x108	/* IRQn High Level Detect Status Register */
#define LLVL_STS	0x10c	/* IRQn Low Level Detect Status Register */
#define S_R_EDGE_STS	0x110	/* IRQn Sync Rising Edge Detect Status Reg. */
#define S_F_EDGE_STS	0x114	/* IRQn Sync Falling Edge Detect Status Reg. */
#define A_R_EDGE_STS	0x118	/* IRQn Async Rising Edge Detect Status Reg. */
#define A_F_EDGE_STS	0x11c	/* IRQn Async Falling Edge Detect Status Reg. */
#define CHTEN_STS	0x120	/* Chattering Reduction Status Register */
#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
				/* IRQn Configuration Register */

struct irqc_irq {
	int hw_irq;
	int requested_irq;
	struct irqc_priv *p;
};

struct irqc_priv {
	void __iomem *iomem;
	void __iomem *cpu_int_base;
	struct irqc_irq irq[IRQC_IRQ_MAX];
	unsigned int number_of_irqs;
	struct device *dev;
	struct irq_chip_generic *gc;
	struct irq_domain *irq_domain;
	atomic_t wakeup_path;
};

static struct irqc_priv *irq_data_to_priv(struct irq_data *data)
{
	return data->domain->host_data;
}

static void irqc_dbg(struct irqc_irq *i, char *str)
{
	dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq);
}

static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_LEVEL_LOW]	= 0x01,
	[IRQ_TYPE_LEVEL_HIGH]	= 0x02,
	[IRQ_TYPE_EDGE_FALLING]	= 0x04,	/* Synchronous */
	[IRQ_TYPE_EDGE_RISING]	= 0x08,	/* Synchronous */
	[IRQ_TYPE_EDGE_BOTH]	= 0x0c,	/* Synchronous */
};

static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct irqc_priv *p = irq_data_to_priv(d);
	int hw_irq = irqd_to_hwirq(d);
	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
	u32 tmp;

	irqc_dbg(&p->irq[hw_irq], "sense");

	if (!value)
		return -EINVAL;

	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	tmp &= ~0x3f;
	tmp |= value;
	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	return 0;
}

static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct irqc_priv *p = irq_data_to_priv(d);
	int hw_irq = irqd_to_hwirq(d);

	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
{
	struct irqc_irq *i = dev_id;
	struct irqc_priv *p = i->p;
	u32 bit = BIT(i->hw_irq);

	irqc_dbg(i, "demux1");

	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
		iowrite32(bit, p->iomem + DETECT_STATUS);
		irqc_dbg(i, "demux2");
		generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static int irqc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	struct irqc_priv *p;
	struct resource *irq;
	int ret;
	int k;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->dev = dev;
	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	for (k = 0; k < IRQC_IRQ_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].p = p;
		p->irq[k].hw_irq = k;
		p->irq[k].requested_irq = irq->start;
	}

	p->number_of_irqs = k;
	if (p->number_of_irqs < 1) {
		dev_err(dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err_runtime_pm_disable;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	p->iomem = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(p->iomem)) {
		ret = PTR_ERR(p->iomem);
		goto err_runtime_pm_disable;
	}

	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */

	p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs,
					      &irq_generic_chip_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(dev, "cannot initialize irq domain\n");
		goto err_runtime_pm_disable;
	}

	ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,
					     1, "irqc", handle_level_irq,
					     0, 0, IRQ_GC_INIT_NESTED_LOCK);
	if (ret) {
		dev_err(dev, "cannot allocate generic chip\n");
		goto err_remove_domain;
	}

	p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);
	p->gc->reg_base = p->cpu_int_base;
	p->gc->chip_types[0].regs.enable = IRQC_EN_SET;
	p->gc->chip_types[0].regs.disable = IRQC_EN_STS;
	p->gc->chip_types[0].chip.parent_device = dev;
	p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
	p->gc->chip_types[0].chip.irq_set_type	= irqc_irq_set_type;
	p->gc->chip_types[0].chip.irq_set_wake	= irqc_irq_set_wake;
	p->gc->chip_types[0].chip.flags	= IRQCHIP_MASK_ON_SUSPEND;

	/* request interrupts one by one */
	for (k = 0; k < p->number_of_irqs; k++) {
		if (devm_request_irq(dev, p->irq[k].requested_irq,
				     irqc_irq_handler, 0, name, &p->irq[k])) {
			dev_err(dev, "failed to request IRQ\n");
			ret = -ENOENT;
			goto err_remove_domain;
		}
	}

	dev_info(dev, "driving %d irqs\n", p->number_of_irqs);

	return 0;

err_remove_domain:
	irq_domain_remove(p->irq_domain);
err_runtime_pm_disable:
	pm_runtime_put(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int irqc_remove(struct platform_device *pdev)
{
	struct irqc_priv *p = platform_get_drvdata(pdev);

	irq_domain_remove(p->irq_domain);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static int __maybe_unused irqc_suspend(struct device *dev)
{
	struct irqc_priv *p = dev_get_drvdata(dev);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);

static const struct of_device_id irqc_dt_ids[] = {
	{ .compatible = "renesas,irqc", },
	{},
};
MODULE_DEVICE_TABLE(of, irqc_dt_ids);

static struct platform_driver irqc_device_driver = {
	.probe		= irqc_probe,
	.remove		= irqc_remove,
	.driver		= {
		.name	= "renesas_irqc",
		.of_match_table	= irqc_dt_ids,
		.pm	= &irqc_pm_ops,
	}
};

static int __init irqc_init(void)
{
	return platform_driver_register(&irqc_device_driver);
}
postcore_initcall(irqc_init);

static void __exit irqc_exit(void)
{
	platform_driver_unregister(&irqc_device_driver);
}
module_exit(irqc_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas IRQC Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e25a96d7	1	// SPDX-License-Identifier: GPL-2.0
fbc83b7f MD	2	/*
	3	* Renesas IRQC Driver
	4	*
	5	* Copyright (C) 2013 Magnus Damm
fbc83b7f MD	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/platform_device.h>
fbc83b7f MD	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
	12	#include <linux/io.h>
	13	#include <linux/irq.h>
	14	#include <linux/irqdomain.h>
	15	#include <linux/err.h>
	16	#include <linux/slab.h>
	17	#include <linux/module.h>
51b05f6b	18	#include <linux/pm_runtime.h>
fbc83b7f	19
1cd5ec73	20	#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
fbc83b7f	21
1cd5ec73 GU	22	#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
	23	#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
	24	#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
fbc83b7f	25	#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
1cd5ec73 GU	26	/* SYS-CPU vs. RT-CPU */
	27	#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
	28	#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
	29	#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
	30	#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
	31	#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
	32	#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
	33	#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
	34	#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
	35	#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
fbc83b7f	36	#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
1cd5ec73	37	/* IRQn Configuration Register */
fbc83b7f MD	38
	39	struct irqc_irq {
	40	int hw_irq;
	41	int requested_irq;
fbc83b7f MD	42	struct irqc_priv *p;
	43	};
	44
	45	struct irqc_priv {
	46	void __iomem *iomem;
	47	void __iomem *cpu_int_base;
	48	struct irqc_irq irq[IRQC_IRQ_MAX];
fbc83b7f	49	unsigned int number_of_irqs;
000e20c5	50	struct device *dev;
99c221df	51	struct irq_chip_generic *gc;
fbc83b7f	52	struct irq_domain *irq_domain;
734e036a	53	atomic_t wakeup_path;
fbc83b7f MD	54	};
fbc83b7f MD	55
99c221df	56	static struct irqc_priv irq_data_to_priv(struct irq_data data)
fbc83b7f	57	{
99c221df	58	return data->domain->host_data;
fbc83b7f MD	59	}
fbc83b7f MD	60
99c221df	61	static void irqc_dbg(struct irqc_irq i, char str)
fbc83b7f	62	{
000e20c5	63	dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq);
fbc83b7f MD	64	}
fbc83b7f MD	65
fbc83b7f	66	static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
ce70af18 SS	67	[IRQ_TYPE_LEVEL_LOW] = 0x01,
	68	[IRQ_TYPE_LEVEL_HIGH] = 0x02,
	69	[IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
	70	[IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
	71	[IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
fbc83b7f MD	72	};
	73
	74	static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
	75	{
99c221df	76	struct irqc_priv *p = irq_data_to_priv(d);
fbc83b7f MD	77	int hw_irq = irqd_to_hwirq(d);
fbc83b7f MD	78	unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
f791e3c1	79	u32 tmp;
fbc83b7f MD	80
	81	irqc_dbg(&p->irq[hw_irq], "sense");
	82
ce70af18	83	if (!value)
fbc83b7f MD	84	return -EINVAL;
	85
	86	tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
	87	tmp &= ~0x3f;
ce70af18	88	tmp \|= value;
fbc83b7f MD	89	iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
	90	return 0;
	91	}
	92
6f46aedb GU	93	static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
6f46aedb GU	94	{
99c221df	95	struct irqc_priv *p = irq_data_to_priv(d);
4cd7863e GU	96	int hw_irq = irqd_to_hwirq(d);
	97
	98	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
6f46aedb	99	if (on)
734e036a	100	atomic_inc(&p->wakeup_path);
6f46aedb	101	else
734e036a	102	atomic_dec(&p->wakeup_path);
6f46aedb GU	103
	104	return 0;
	105	}
	106
fbc83b7f MD	107	static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
	108	{
	109	struct irqc_irq *i = dev_id;
	110	struct irqc_priv *p = i->p;
f791e3c1	111	u32 bit = BIT(i->hw_irq);
fbc83b7f MD	112
	113	irqc_dbg(i, "demux1");
	114
	115	if (ioread32(p->iomem + DETECT_STATUS) & bit) {
	116	iowrite32(bit, p->iomem + DETECT_STATUS);
	117	irqc_dbg(i, "demux2");
e10fc03c	118	generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
fbc83b7f MD	119	return IRQ_HANDLED;
	120	}
	121	return IRQ_NONE;
	122	}
	123
fbc83b7f MD	124	static int irqc_probe(struct platform_device *pdev)
fbc83b7f MD	125	{
9ae48bc0 GU	126	struct device *dev = &pdev->dev;
9ae48bc0 GU	127	const char *name = dev_name(dev);
fbc83b7f	128	struct irqc_priv *p;
fbc83b7f	129	struct resource *irq;
fbc83b7f MD	130	int ret;
	131	int k;
	132
4770533f GU	133	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	134	if (!p)
	135	return -ENOMEM;
fbc83b7f	136
000e20c5	137	p->dev = dev;
fbc83b7f MD	138	platform_set_drvdata(pdev, p);
fbc83b7f MD	139
9ae48bc0 GU	140	pm_runtime_enable(dev);
9ae48bc0 GU	141	pm_runtime_get_sync(dev);
51b05f6b	142
fbc83b7f MD	143	/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
	144	for (k = 0; k < IRQC_IRQ_MAX; k++) {
	145	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
	146	if (!irq)
	147	break;
	148
	149	p->irq[k].p = p;
e10fc03c	150	p->irq[k].hw_irq = k;
fbc83b7f MD	151	p->irq[k].requested_irq = irq->start;
	152	}
	153
	154	p->number_of_irqs = k;
	155	if (p->number_of_irqs < 1) {
9ae48bc0	156	dev_err(dev, "not enough IRQ resources\n");
fbc83b7f	157	ret = -EINVAL;
4770533f	158	goto err_runtime_pm_disable;
fbc83b7f MD	159	}
	160
	161	/* ioremap IOMEM and setup read/write callbacks */
4770533f GU	162	p->iomem = devm_platform_ioremap_resource(pdev, 0);
	163	if (IS_ERR(p->iomem)) {
	164	ret = PTR_ERR(p->iomem);
	165	goto err_runtime_pm_disable;
fbc83b7f MD	166	}
	167
	168	p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
	169
9ae48bc0	170	p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs,
99c221df	171	&irq_generic_chip_ops, p);
fbc83b7f MD	172	if (!p->irq_domain) {
fbc83b7f MD	173	ret = -ENXIO;
9ae48bc0	174	dev_err(dev, "cannot initialize irq domain\n");
4770533f	175	goto err_runtime_pm_disable;
fbc83b7f MD	176	}
fbc83b7f MD	177
99c221df	178	ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,
17c88892	179	1, "irqc", handle_level_irq,
99c221df MD	180	0, 0, IRQ_GC_INIT_NESTED_LOCK);
99c221df MD	181	if (ret) {
9ae48bc0	182	dev_err(dev, "cannot allocate generic chip\n");
4770533f	183	goto err_remove_domain;
99c221df MD	184	}
	185
	186	p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);
	187	p->gc->reg_base = p->cpu_int_base;
	188	p->gc->chip_types[0].regs.enable = IRQC_EN_SET;
	189	p->gc->chip_types[0].regs.disable = IRQC_EN_STS;
17c88892	190	p->gc->chip_types[0].chip.parent_device = dev;
99c221df MD	191	p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	192	p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
	193	p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type;
	194	p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake;
	195	p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
	196
fbc83b7f MD	197	/* request interrupts one by one */
fbc83b7f MD	198	for (k = 0; k < p->number_of_irqs; k++) {
4770533f GU	199	if (devm_request_irq(dev, p->irq[k].requested_irq,
4770533f GU	200	irqc_irq_handler, 0, name, &p->irq[k])) {
9ae48bc0	201	dev_err(dev, "failed to request IRQ\n");
fbc83b7f	202	ret = -ENOENT;
4770533f	203	goto err_remove_domain;
fbc83b7f MD	204	}
	205	}
	206
9ae48bc0	207	dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
fbc83b7f	208
fbc83b7f	209	return 0;
fbc83b7f	210
4770533f	211	err_remove_domain:
fbc83b7f	212	irq_domain_remove(p->irq_domain);
4770533f	213	err_runtime_pm_disable:
9ae48bc0 GU	214	pm_runtime_put(dev);
9ae48bc0 GU	215	pm_runtime_disable(dev);
fbc83b7f MD	216	return ret;
	217	}
	218
	219	static int irqc_remove(struct platform_device *pdev)
	220	{
	221	struct irqc_priv *p = platform_get_drvdata(pdev);
fbc83b7f MD	222
fbc83b7f MD	223	irq_domain_remove(p->irq_domain);
51b05f6b GU	224	pm_runtime_put(&pdev->dev);
51b05f6b GU	225	pm_runtime_disable(&pdev->dev);
fbc83b7f MD	226	return 0;
	227	}
	228
734e036a GU	229	static int __maybe_unused irqc_suspend(struct device *dev)
	230	{
	231	struct irqc_priv *p = dev_get_drvdata(dev);
	232
	233	if (atomic_read(&p->wakeup_path))
	234	device_set_wakeup_path(dev);
	235
	236	return 0;
	237	}
	238
	239	static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);
	240
3b8dfa7c MD	241	static const struct of_device_id irqc_dt_ids[] = {
	242	{ .compatible = "renesas,irqc", },
	243	{},
	244	};
	245	MODULE_DEVICE_TABLE(of, irqc_dt_ids);
	246
fbc83b7f MD	247	static struct platform_driver irqc_device_driver = {
	248	.probe = irqc_probe,
	249	.remove = irqc_remove,
	250	.driver = {
	251	.name = "renesas_irqc",
3b8dfa7c	252	.of_match_table = irqc_dt_ids,
734e036a	253	.pm = &irqc_pm_ops,
fbc83b7f MD	254	}
	255	};
	256
	257	static int __init irqc_init(void)
	258	{
	259	return platform_driver_register(&irqc_device_driver);
	260	}
	261	postcore_initcall(irqc_init);
	262
	263	static void __exit irqc_exit(void)
	264	{
	265	platform_driver_unregister(&irqc_device_driver);
	266	}
	267	module_exit(irqc_exit);
	268
	269	MODULE_AUTHOR("Magnus Damm");
	270	MODULE_DESCRIPTION("Renesas IRQC Driver");
	271	MODULE_LICENSE("GPL v2");