[linux-2.6-block.git] / drivers / irqchip / irq-pic32-evic.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Cristian Birsan <cristian.birsan@microchip.com>
 * Joshua Henderson <joshua.henderson@microchip.com>
 * Copyright (C) 2016 Microchip Technology Inc.  All rights reserved.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irq.h>

#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/mach-pic32/pic32.h>

#define REG_INTCON	0x0000
#define REG_INTSTAT	0x0020
#define REG_IFS_OFFSET	0x0040
#define REG_IEC_OFFSET	0x00C0
#define REG_IPC_OFFSET	0x0140
#define REG_OFF_OFFSET	0x0540

#define MAJPRI_MASK	0x07
#define SUBPRI_MASK	0x03
#define PRIORITY_MASK	0x1F

#define PIC32_INT_PRI(pri, subpri)				\
	((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK))

struct evic_chip_data {
	u32 irq_types[NR_IRQS];
	u32 ext_irqs[8];
};

static struct irq_domain *evic_irq_domain;
static void __iomem *evic_base;

asmlinkage void __weak plat_irq_dispatch(void)
{
	unsigned int irq, hwirq;

	hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
	irq = irq_linear_revmap(evic_irq_domain, hwirq);
	do_IRQ(irq);
}

static struct evic_chip_data *irqd_to_priv(struct irq_data *data)
{
	return (struct evic_chip_data *)data->domain->host_data;
}

static int pic32_set_ext_polarity(int bit, u32 type)
{
	/*
	 * External interrupts can be either edge rising or edge falling,
	 * but not both.
	 */
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
		break;
	case IRQ_TYPE_EDGE_FALLING:
		writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int pic32_set_type_edge(struct irq_data *data,
			       unsigned int flow_type)
{
	struct evic_chip_data *priv = irqd_to_priv(data);
	int ret;
	int i;

	if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
		return -EBADR;

	/* set polarity for external interrupts only */
	for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
		if (priv->ext_irqs[i] == data->hwirq) {
			ret = pic32_set_ext_polarity(i, flow_type);
			if (ret)
				return ret;
		}
	}

	irqd_set_trigger_type(data, flow_type);

	return IRQ_SET_MASK_OK;
}

static void pic32_bind_evic_interrupt(int irq, int set)
{
	writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
}

static void pic32_set_irq_priority(int irq, int priority)
{
	u32 reg, shift;

	reg = irq / 4;
	shift = (irq % 4) * 8;

	writel(PRIORITY_MASK << shift,
		evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
	writel(priority << shift,
		evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
}

#define IRQ_REG_MASK(_hwirq, _reg, _mask)		       \
	do {						       \
		_reg = _hwirq / 32;			       \
		_mask = 1 << (_hwirq % 32);		       \
	} while (0)

static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hw)
{
	struct evic_chip_data *priv = d->host_data;
	struct irq_data *data;
	int ret;
	u32 iecclr, ifsclr;
	u32 reg, mask;

	ret = irq_map_generic_chip(d, virq, hw);
	if (ret)
		return ret;

	/*
	 * Piggyback on xlate function to move to an alternate chip as necessary
	 * at time of mapping instead of allowing the flow handler/chip to be
	 * changed later. This requires all interrupts to be configured through
	 * DT.
	 */
	if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
		data = irq_domain_get_irq_data(d, virq);
		irqd_set_trigger_type(data, priv->irq_types[hw]);
		irq_setup_alt_chip(data, priv->irq_types[hw]);
	}

	IRQ_REG_MASK(hw, reg, mask);

	iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
	ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);

	/* mask and clear flag */
	writel(mask, evic_base + iecclr);
	writel(mask, evic_base + ifsclr);

	/* default priority is required */
	pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));

	return ret;
}

int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
			   const u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_type)
{
	struct evic_chip_data *priv = d->host_data;

	if (WARN_ON(intsize < 2))
		return -EINVAL;

	if (WARN_ON(intspec[0] >= NR_IRQS))
		return -EINVAL;

	*out_hwirq = intspec[0];
	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;

	priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;

	return 0;
}

static const struct irq_domain_ops pic32_irq_domain_ops = {
	.map	= pic32_irq_domain_map,
	.xlate	= pic32_irq_domain_xlate,
};

static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
{
	struct device_node *node = irq_domain_get_of_node(domain);
	struct evic_chip_data *priv = domain->host_data;
	struct property *prop;
	const __le32 *p;
	u32 hwirq;
	int i = 0;
	const char *pname = "microchip,external-irqs";

	of_property_for_each_u32(node, pname, prop, p, hwirq) {
		if (i >= ARRAY_SIZE(priv->ext_irqs)) {
			pr_warn("More than %d external irq, skip rest\n",
				ARRAY_SIZE(priv->ext_irqs));
			break;
		}

		priv->ext_irqs[i] = hwirq;
		i++;
	}
}

static int __init pic32_of_init(struct device_node *node,
				struct device_node *parent)
{
	struct irq_chip_generic *gc;
	struct evic_chip_data *priv;
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	int nchips, ret;
	int i;

	nchips = DIV_ROUND_UP(NR_IRQS, 32);

	evic_base = of_iomap(node, 0);
	if (!evic_base)
		return -ENOMEM;

	priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
						&pic32_irq_domain_ops,
						priv);
	if (!evic_irq_domain) {
		ret = -ENOMEM;
		goto err_free_priv;
	}

	/*
	 * The PIC32 EVIC has a linear list of irqs and the type of each
	 * irq is determined by the hardware peripheral the EVIC is arbitrating.
	 * These irq types are defined in the datasheet as "persistent" and
	 * "non-persistent" which are mapped here to level and edge
	 * respectively. To manage the different flow handler requirements of
	 * each irq type, different chip_types are used.
	 */
	ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
					     "evic-level", handle_level_irq,
					     clr, 0, 0);
	if (ret)
		goto err_domain_remove;

	board_bind_eic_interrupt = &pic32_bind_evic_interrupt;

	for (i = 0; i < nchips; i++) {
		u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
		u32 iec = REG_IEC_OFFSET + (i * 0x10);

		gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);

		gc->reg_base = evic_base;
		gc->unused = 0;

		/*
		 * Level/persistent interrupts have a special requirement that
		 * the condition generating the interrupt be cleared before the
		 * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
		 * complete the interrupt with an ack.
		 */
		gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
		gc->chip_types[0].handler		= handle_fasteoi_irq;
		gc->chip_types[0].regs.ack		= ifsclr;
		gc->chip_types[0].regs.mask		= iec;
		gc->chip_types[0].chip.name		= "evic-level";
		gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;
		gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
		gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
		gc->chip_types[0].chip.flags		= IRQCHIP_SKIP_SET_WAKE;

		/* Edge interrupts */
		gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
		gc->chip_types[1].handler		= handle_edge_irq;
		gc->chip_types[1].regs.ack		= ifsclr;
		gc->chip_types[1].regs.mask		= iec;
		gc->chip_types[1].chip.name		= "evic-edge";
		gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
		gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
		gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
		gc->chip_types[1].chip.irq_set_type	= pic32_set_type_edge;
		gc->chip_types[1].chip.flags		= IRQCHIP_SKIP_SET_WAKE;

		gc->private = &priv[i];
	}

	irq_set_default_host(evic_irq_domain);

	/*
	 * External interrupts have software configurable edge polarity. These
	 * interrupts are defined in DT allowing polarity to be configured only
	 * for these interrupts when requested.
	 */
	pic32_ext_irq_of_init(evic_irq_domain);

	return 0;

err_domain_remove:
	irq_domain_remove(evic_irq_domain);

err_free_priv:
	kfree(priv);

err_iounmap:
	iounmap(evic_base);

	return ret;
}

IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
aaa8666a CB	2	/*
	3	* Cristian Birsan <cristian.birsan@microchip.com>
	4	* Joshua Henderson <joshua.henderson@microchip.com>
	5	* Copyright (C) 2016 Microchip Technology Inc. All rights reserved.
aaa8666a CB	6	*/
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/irqdomain.h>
	11	#include <linux/of_address.h>
	12	#include <linux/slab.h>
	13	#include <linux/io.h>
	14	#include <linux/irqchip.h>
	15	#include <linux/irq.h>
	16
	17	#include <asm/irq.h>
	18	#include <asm/traps.h>
	19	#include <asm/mach-pic32/pic32.h>
	20
	21	#define REG_INTCON 0x0000
	22	#define REG_INTSTAT 0x0020
	23	#define REG_IFS_OFFSET 0x0040
	24	#define REG_IEC_OFFSET 0x00C0
	25	#define REG_IPC_OFFSET 0x0140
	26	#define REG_OFF_OFFSET 0x0540
	27
	28	#define MAJPRI_MASK 0x07
	29	#define SUBPRI_MASK 0x03
	30	#define PRIORITY_MASK 0x1F
	31
	32	#define PIC32_INT_PRI(pri, subpri) \
	33	((((pri) & MAJPRI_MASK) << 2) \| ((subpri) & SUBPRI_MASK))
	34
	35	struct evic_chip_data {
	36	u32 irq_types[NR_IRQS];
	37	u32 ext_irqs[8];
	38	};
	39
	40	static struct irq_domain *evic_irq_domain;
	41	static void __iomem *evic_base;
	42
	43	asmlinkage void __weak plat_irq_dispatch(void)
	44	{
	45	unsigned int irq, hwirq;
	46
	47	hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
	48	irq = irq_linear_revmap(evic_irq_domain, hwirq);
	49	do_IRQ(irq);
	50	}
	51
	52	static struct evic_chip_data irqd_to_priv(struct irq_data data)
	53	{
	54	return (struct evic_chip_data *)data->domain->host_data;
	55	}
	56
	57	static int pic32_set_ext_polarity(int bit, u32 type)
	58	{
	59	/*
	60	* External interrupts can be either edge rising or edge falling,
	61	* but not both.
	62	*/
	63	switch (type) {
	64	case IRQ_TYPE_EDGE_RISING:
	65	writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
	66	break;
	67	case IRQ_TYPE_EDGE_FALLING:
	68	writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
	69	break;
70	default:
71	return -EINVAL;
72	}
73
74	return 0;
75	}
76
77	static int pic32_set_type_edge(struct irq_data *data,
78	unsigned int flow_type)
79	{
80	struct evic_chip_data *priv = irqd_to_priv(data);
81	int ret;
82	int i;
83
84	if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
85	return -EBADR;
86
87	/* set polarity for external interrupts only */
88	for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
89	if (priv->ext_irqs[i] == data->hwirq) {
0de6b997	90	ret = pic32_set_ext_polarity(i, flow_type);
aaa8666a CB	91	if (ret)
	92	return ret;
	93	}
	94	}
	95
	96	irqd_set_trigger_type(data, flow_type);
	97
	98	return IRQ_SET_MASK_OK;
	99	}
	100
	101	static void pic32_bind_evic_interrupt(int irq, int set)
	102	{
	103	writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
	104	}
	105
	106	static void pic32_set_irq_priority(int irq, int priority)
	107	{
	108	u32 reg, shift;
	109
	110	reg = irq / 4;
	111	shift = (irq % 4) * 8;
	112
	113	writel(PRIORITY_MASK << shift,
	114	evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
	115	writel(priority << shift,
	116	evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
	117	}
	118
	119	#define IRQ_REG_MASK(_hwirq, _reg, _mask) \
	120	do { \
	121	_reg = _hwirq / 32; \
	122	_mask = 1 << (_hwirq % 32); \
	123	} while (0)
	124
	125	static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
	126	irq_hw_number_t hw)
	127	{
	128	struct evic_chip_data *priv = d->host_data;
	129	struct irq_data *data;
	130	int ret;
	131	u32 iecclr, ifsclr;
	132	u32 reg, mask;
	133
	134	ret = irq_map_generic_chip(d, virq, hw);
	135	if (ret)
	136	return ret;
	137
	138	/*
	139	* Piggyback on xlate function to move to an alternate chip as necessary
	140	* at time of mapping instead of allowing the flow handler/chip to be
	141	* changed later. This requires all interrupts to be configured through
	142	* DT.
	143	*/
	144	if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
	145	data = irq_domain_get_irq_data(d, virq);
	146	irqd_set_trigger_type(data, priv->irq_types[hw]);
	147	irq_setup_alt_chip(data, priv->irq_types[hw]);
	148	}
	149
	150	IRQ_REG_MASK(hw, reg, mask);
	151
	152	iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
	153	ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);
	154
155	/* mask and clear flag */
156	writel(mask, evic_base + iecclr);
157	writel(mask, evic_base + ifsclr);
158
159	/* default priority is required */
160	pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));
161
162	return ret;
163	}
164
165	int pic32_irq_domain_xlate(struct irq_domain d, struct device_node ctrlr,
166	const u32 *intspec, unsigned int intsize,
167	irq_hw_number_t out_hwirq, unsigned int out_type)
168	{
169	struct evic_chip_data *priv = d->host_data;
170
171	if (WARN_ON(intsize < 2))
172	return -EINVAL;
173
174	if (WARN_ON(intspec[0] >= NR_IRQS))
175	return -EINVAL;
176
177	*out_hwirq = intspec[0];
178	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
179
180	priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;
181
182	return 0;
183	}
184
185	static const struct irq_domain_ops pic32_irq_domain_ops = {
186	.map = pic32_irq_domain_map,
187	.xlate = pic32_irq_domain_xlate,
188	};
189
190	static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
191	{
192	struct device_node *node = irq_domain_get_of_node(domain);
193	struct evic_chip_data *priv = domain->host_data;
194	struct property *prop;
195	const __le32 *p;
196	u32 hwirq;
197	int i = 0;
198	const char *pname = "microchip,external-irqs";
199
200	of_property_for_each_u32(node, pname, prop, p, hwirq) {
201	if (i >= ARRAY_SIZE(priv->ext_irqs)) {
202	pr_warn("More than %d external irq, skip rest\n",
203	ARRAY_SIZE(priv->ext_irqs));
204	break;
205	}
206
207	priv->ext_irqs[i] = hwirq;
208	i++;
209	}
210	}
211
212	static int __init pic32_of_init(struct device_node *node,
213	struct device_node *parent)
214	{
215	struct irq_chip_generic *gc;
216	struct evic_chip_data *priv;
217	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
218	int nchips, ret;
219	int i;
220
221	nchips = DIV_ROUND_UP(NR_IRQS, 32);
222
223	evic_base = of_iomap(node, 0);
224	if (!evic_base)
225	return -ENOMEM;
226
227	priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
228	if (!priv) {
229	ret = -ENOMEM;
230	goto err_iounmap;
231	}
232
233	evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
234	&pic32_irq_domain_ops,
235	priv);
236	if (!evic_irq_domain) {
237	ret = -ENOMEM;
238	goto err_free_priv;
239	}
240
241	/*
242	* The PIC32 EVIC has a linear list of irqs and the type of each
243	* irq is determined by the hardware peripheral the EVIC is arbitrating.
244	* These irq types are defined in the datasheet as "persistent" and
245	* "non-persistent" which are mapped here to level and edge
246	* respectively. To manage the different flow handler requirements of
247	* each irq type, different chip_types are used.
248	*/
249	ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
250	"evic-level", handle_level_irq,
251	clr, 0, 0);
252	if (ret)
253	goto err_domain_remove;
254
255	board_bind_eic_interrupt = &pic32_bind_evic_interrupt;
256
257	for (i = 0; i < nchips; i++) {
258	u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
259	u32 iec = REG_IEC_OFFSET + (i * 0x10);
260
261	gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);
262
263	gc->reg_base = evic_base;
264	gc->unused = 0;
265
266	/*
267	* Level/persistent interrupts have a special requirement that
268	* the condition generating the interrupt be cleared before the
269	* interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
270	* complete the interrupt with an ack.
271	*/
272	gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
273	gc->chip_types[0].handler = handle_fasteoi_irq;
274	gc->chip_types[0].regs.ack = ifsclr;
275	gc->chip_types[0].regs.mask = iec;
276	gc->chip_types[0].chip.name = "evic-level";
277	gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
278	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
279	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
280	gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE;
281
282	/* Edge interrupts */
283	gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
284	gc->chip_types[1].handler = handle_edge_irq;
285	gc->chip_types[1].regs.ack = ifsclr;
286	gc->chip_types[1].regs.mask = iec;
287	gc->chip_types[1].chip.name = "evic-edge";
288	gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
289	gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
290	gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
291	gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge;
292	gc->chip_types[1].chip.flags = IRQCHIP_SKIP_SET_WAKE;
293
294	gc->private = &priv[i];
295	}
296
297	irq_set_default_host(evic_irq_domain);
298
299	/*
300	* External interrupts have software configurable edge polarity. These
301	* interrupts are defined in DT allowing polarity to be configured only
302	* for these interrupts when requested.
303	*/
304	pic32_ext_irq_of_init(evic_irq_domain);
305
306	return 0;
307
308	err_domain_remove:
309	irq_domain_remove(evic_irq_domain);
310
311	err_free_priv:
312	kfree(priv);
313
314	err_iounmap:
315	iounmap(evic_base);
316
317	return ret;
318	}
319
320	IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);