[linux-2.6-block.git] / drivers / irqchip / irq-omap-intc.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "irqchip.h"

/* Define these here for now until we drop all board-files */
#define OMAP24XX_IC_BASE	0x480fe000
#define OMAP34XX_IC_BASE	0x48200000

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_PENDING_IRQ1	0x00b8
#define INTC_PENDING_IRQ2	0x00d8
#define INTC_PENDING_IRQ3	0x00f8
#define INTC_ILR0		0x0100

#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
#define INTCPS_NR_ILR_REGS	128
#define INTCPS_NR_MIR_REGS	4

#define INTC_IDLE_FUNCIDLE	(1 << 0)
#define INTC_IDLE_TURBO		(1 << 1)

#define INTC_PROTECTION_ENABLE	(1 << 0)

struct omap_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_ILR_REGS];
	u32 mir[INTCPS_NR_MIR_REGS];
};
static struct omap_intc_regs intc_context;

static struct irq_domain *domain;
static void __iomem *omap_irq_base;
static int omap_nr_pending = 3;
static int omap_nr_irqs = 96;

static void intc_writel(u32 reg, u32 val)
{
	writel_relaxed(val, omap_irq_base + reg);
}

static u32 intc_readl(u32 reg)
{
	return readl_relaxed(omap_irq_base + reg);
}

void omap_intc_save_context(void)
{
	int i;

	intc_context.sysconfig =
		intc_readl(INTC_SYSCONFIG);
	intc_context.protection =
		intc_readl(INTC_PROTECTION);
	intc_context.idle =
		intc_readl(INTC_IDLE);
	intc_context.threshold =
		intc_readl(INTC_THRESHOLD);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_context.ilr[i] =
			intc_readl((INTC_ILR0 + 0x4 * i));
	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_context.mir[i] =
			intc_readl(INTC_MIR0 + (0x20 * i));
}

void omap_intc_restore_context(void)
{
	int i;

	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	intc_writel(INTC_PROTECTION, intc_context.protection);
	intc_writel(INTC_IDLE, intc_context.idle);
	intc_writel(INTC_THRESHOLD, intc_context.threshold);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_writel(INTC_ILR0 + 0x4 * i,
				intc_context.ilr[i]);

	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_writel(INTC_MIR0 + 0x20 * i,
			intc_context.mir[i]);
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_writel(INTC_SYSCONFIG, 0);
	intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1);
	intc_writel(INTC_IDLE, 0);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_writel(INTC_CONTROL, 0x1);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_soft_reset(void)
{
	unsigned long tmp;

	tmp = intc_readl(INTC_REVISION) & 0xff;

	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
		omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);

	tmp = intc_readl(INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_writel(INTC_SYSCONFIG, tmp);

	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1 << 0);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < omap_nr_pending; i++)
		if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
			return 1;
	return 0;
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
{
	int ret;
	int i;

	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
			handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
			IRQ_LEVEL, 0);
	if (ret) {
		pr_warn("Failed to allocate irq chips\n");
		return ret;
	}

	for (i = 0; i < omap_nr_pending; i++) {
		struct irq_chip_generic *gc;
		struct irq_chip_type *ct;

		gc = irq_get_domain_generic_chip(d, 32 * i);
		gc->reg_base = base;
		ct = gc->chip_types;

		ct->type = IRQ_TYPE_LEVEL_MASK;
		ct->handler = handle_level_irq;

		ct->chip.irq_ack = omap_mask_ack_irq;
		ct->chip.irq_mask = irq_gc_mask_disable_reg;
		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

		ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

		ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
		ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	}

	return 0;
}

static void __init omap_alloc_gc_legacy(void __iomem *base,
		unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
			handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int __init omap_init_irq_of(struct device_node *node)
{
	int ret;

	omap_irq_base = of_iomap(node, 0);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	domain = irq_domain_add_linear(node, omap_nr_irqs,
			&irq_generic_chip_ops, NULL);

	omap_irq_soft_reset();

	ret = omap_alloc_gc_of(domain, omap_irq_base);
	if (ret < 0)
		irq_domain_remove(domain);

	return ret;
}

static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
{
	int j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
			&irq_domain_simple_ops, NULL);

	omap_irq_soft_reset();

	for (j = 0; j < omap_nr_irqs; j += 32)
		omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);

	return 0;
}

static void __init omap_irq_enable_protection(void)
{
	u32 reg;

	reg = intc_readl(INTC_PROTECTION);
	reg |= INTC_PROTECTION_ENABLE;
	intc_writel(INTC_PROTECTION, reg);
}

static int __init omap_init_irq(u32 base, struct device_node *node)
{
	int ret;

	/*
	 * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
	 * depends is still not ready for linear IRQ domains; because of that
	 * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
	 * linear IRQ Domain until that driver is finally fixed.
	 */
	if (of_device_is_compatible(node, "ti,omap2-intc") ||
			of_device_is_compatible(node, "ti,omap3-intc")) {
		struct resource res;

		if (of_address_to_resource(node, 0, &res))
			return -ENOMEM;

		base = res.start;
		ret = omap_init_irq_legacy(base, node);
	} else if (node) {
		ret = omap_init_irq_of(node);
	} else {
		ret = omap_init_irq_legacy(base, NULL);
	}

	if (ret == 0)
		omap_irq_enable_protection();

	return ret;
}

static asmlinkage void __exception_irq_entry
omap_intc_handle_irq(struct pt_regs *regs)
{
	u32 irqnr = 0;
	int handled_irq = 0;
	int i;

	do {
		for (i = 0; i < omap_nr_pending; i++) {
			irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
			if (irqnr)
				goto out;
		}

out:
		if (!irqnr)
			break;

		irqnr = intc_readl(INTC_SIR);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
			handle_domain_irq(domain, irqnr, regs);
			handled_irq = 1;
		}
	} while (irqnr);

	/*
	 * If an irq is masked or deasserted while active, we will
	 * keep ending up here with no irq handled. So remove it from
	 * the INTC with an ack.
	 */
	if (!handled_irq)
		omap_ack_irq(NULL);
}

void __init omap3_init_irq(void)
{
	omap_nr_irqs = 96;
	omap_nr_pending = 3;
	omap_init_irq(OMAP34XX_IC_BASE, NULL);
	set_handle_irq(omap_intc_handle_irq);
}

static int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	int ret;

	omap_nr_pending = 3;
	omap_nr_irqs = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_device_is_compatible(node, "ti,dm814-intc") ||
	    of_device_is_compatible(node, "ti,dm816-intc") ||
	    of_device_is_compatible(node, "ti,am33xx-intc")) {
		omap_nr_irqs = 128;
		omap_nr_pending = 4;
	}

	ret = omap_init_irq(-1, of_node_get(node));
	if (ret < 0)
		return ret;

	set_handle_irq(omap_intc_handle_irq);

	return 0;
}

IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
52fa2120 BC	20	#include <linux/irqdomain.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
c4082d49	23	#include <linux/of_irq.h>
1dbae815	24
8598066c FB	25	#include "irqchip.h"
	26
	27	/* Define these here for now until we drop all board-files */
	28	#define OMAP24XX_IC_BASE 0x480fe000
	29	#define OMAP34XX_IC_BASE 0x48200000
2e7509e5 PW	30
	31	/* selected INTC register offsets */
	32
	33	#define INTC_REVISION 0x0000
	34	#define INTC_SYSCONFIG 0x0010
	35	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	36	#define INTC_SIR 0x0040
2e7509e5	37	#define INTC_CONTROL 0x0048
0addd61b RN	38	#define INTC_PROTECTION 0x004C
	39	#define INTC_IDLE 0x0050
	40	#define INTC_THRESHOLD 0x0068
	41	#define INTC_MIR0 0x0084
2e7509e5 PW	42	#define INTC_MIR_CLEAR0 0x0088
	43	#define INTC_MIR_SET0 0x008c
	44	#define INTC_PENDING_IRQ0 0x0098
11983656 FB	45	#define INTC_PENDING_IRQ1 0x00b8
	46	#define INTC_PENDING_IRQ2 0x00d8
	47	#define INTC_PENDING_IRQ3 0x00f8
33c7c7b7	48	#define INTC_ILR0 0x0100
1dbae815	49
2db14997	50	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
a88ab430	51	#define INTCPS_NR_ILR_REGS 128
74b6c8ef	52	#define INTCPS_NR_MIR_REGS 4
2db14997	53
b3079149 FB	54	#define INTC_IDLE_FUNCIDLE (1 << 0)
	55	#define INTC_IDLE_TURBO (1 << 1)
	56
9836ee9f FB	57	#define INTC_PROTECTION_ENABLE (1 << 0)
9836ee9f FB	58
272a8b04	59	struct omap_intc_regs {
0addd61b RN	60	u32 sysconfig;
	61	u32 protection;
	62	u32 idle;
	63	u32 threshold;
a88ab430	64	u32 ilr[INTCPS_NR_ILR_REGS];
0addd61b RN	65	u32 mir[INTCPS_NR_MIR_REGS];
0addd61b RN	66	};
131b48c0 FB	67	static struct omap_intc_regs intc_context;
	68
	69	static struct irq_domain *domain;
	70	static void __iomem *omap_irq_base;
52b1e129	71	static int omap_nr_pending = 3;
131b48c0	72	static int omap_nr_irqs = 96;
0addd61b	73
71be00c9	74	static void intc_writel(u32 reg, u32 val)
2e7509e5	75	{
71be00c9	76	writel_relaxed(val, omap_irq_base + reg);
2e7509e5 PW	77	}
2e7509e5 PW	78
71be00c9	79	static u32 intc_readl(u32 reg)
2e7509e5	80	{
71be00c9	81	return readl_relaxed(omap_irq_base + reg);
2e7509e5 PW	82	}
2e7509e5 PW	83
131b48c0 FB	84	void omap_intc_save_context(void)
	85	{
	86	int i;
	87
	88	intc_context.sysconfig =
	89	intc_readl(INTC_SYSCONFIG);
	90	intc_context.protection =
	91	intc_readl(INTC_PROTECTION);
	92	intc_context.idle =
	93	intc_readl(INTC_IDLE);
	94	intc_context.threshold =
	95	intc_readl(INTC_THRESHOLD);
	96
	97	for (i = 0; i < omap_nr_irqs; i++)
	98	intc_context.ilr[i] =
	99	intc_readl((INTC_ILR0 + 0x4 * i));
	100	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	101	intc_context.mir[i] =
	102	intc_readl(INTC_MIR0 + (0x20 * i));
	103	}
	104
	105	void omap_intc_restore_context(void)
	106	{
	107	int i;
	108
	109	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	110	intc_writel(INTC_PROTECTION, intc_context.protection);
	111	intc_writel(INTC_IDLE, intc_context.idle);
	112	intc_writel(INTC_THRESHOLD, intc_context.threshold);
	113
	114	for (i = 0; i < omap_nr_irqs; i++)
	115	intc_writel(INTC_ILR0 + 0x4 * i,
	116	intc_context.ilr[i]);
	117
	118	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	119	intc_writel(INTC_MIR0 + 0x20 * i,
	120	intc_context.mir[i]);
	121	/* MIRs are saved and restore with other PRCM registers */
	122	}
	123
	124	void omap3_intc_prepare_idle(void)
	125	{
	126	/*
	127	* Disable autoidle as it can stall interrupt controller,
	128	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	129	*/
	130	intc_writel(INTC_SYSCONFIG, 0);
b3079149	131	intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
131b48c0 FB	132	}
	133
	134	void omap3_intc_resume_idle(void)
	135	{
	136	/* Re-enable autoidle */
	137	intc_writel(INTC_SYSCONFIG, 1);
b3079149	138	intc_writel(INTC_IDLE, 0);
131b48c0 FB	139	}
131b48c0 FB	140
1dbae815	141	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	142	static void omap_ack_irq(struct irq_data *d)
1dbae815	143	{
71be00c9	144	intc_writel(INTC_CONTROL, 0x1);
1dbae815 TL	145	}
1dbae815 TL	146
df303477	147	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	148	{
667a11fa	149	irq_gc_mask_disable_reg(d);
df303477	150	omap_ack_irq(d);
1dbae815 TL	151	}
1dbae815 TL	152
a88ab430	153	static void __init omap_irq_soft_reset(void)
1dbae815 TL	154	{
	155	unsigned long tmp;
	156
71be00c9	157	tmp = intc_readl(INTC_REVISION) & 0xff;
a88ab430	158
7852ec05	159	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
a88ab430	160	omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
1dbae815	161
71be00c9	162	tmp = intc_readl(INTC_SYSCONFIG);
1dbae815	163	tmp \|= 1 << 1; /* soft reset */
71be00c9	164	intc_writel(INTC_SYSCONFIG, tmp);
1dbae815	165
71be00c9	166	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
1dbae815	167	/* Wait for reset to complete */;
375e12ab JY	168
375e12ab JY	169	/* Enable autoidle */
71be00c9	170	intc_writel(INTC_SYSCONFIG, 1 << 0);
1dbae815 TL	171	}
1dbae815 TL	172
94434535 JH	173	int omap_irq_pending(void)
94434535 JH	174	{
6bd0f16e	175	int i;
94434535	176
6bd0f16e FB	177	for (i = 0; i < omap_nr_pending; i++)
6bd0f16e FB	178	if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
a88ab430	179	return 1;
94434535 JH	180	return 0;
	181	}
	182
131b48c0 FB	183	void omap3_intc_suspend(void)
	184	{
	185	/* A pending interrupt would prevent OMAP from entering suspend */
	186	omap_ack_irq(NULL);
	187	}
	188
55601c9f FB	189	static int __init omap_alloc_gc_of(struct irq_domain d, void __iomem base)
	190	{
	191	int ret;
	192	int i;
	193
	194	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
	195	handle_level_irq, IRQ_NOREQUEST \| IRQ_NOPROBE,
	196	IRQ_LEVEL, 0);
	197	if (ret) {
	198	pr_warn("Failed to allocate irq chips\n");
	199	return ret;
	200	}
	201
	202	for (i = 0; i < omap_nr_pending; i++) {
	203	struct irq_chip_generic *gc;
	204	struct irq_chip_type *ct;
	205
	206	gc = irq_get_domain_generic_chip(d, 32 * i);
	207	gc->reg_base = base;
	208	ct = gc->chip_types;
	209
	210	ct->type = IRQ_TYPE_LEVEL_MASK;
	211	ct->handler = handle_level_irq;
	212
	213	ct->chip.irq_ack = omap_mask_ack_irq;
	214	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	215	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	216
	217	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
	218
	219	ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
	220	ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	221	}
	222
	223	return 0;
	224	}
	225
	226	static void __init omap_alloc_gc_legacy(void __iomem *base,
	227	unsigned int irq_start, unsigned int num)
667a11fa TL	228	{
	229	struct irq_chip_generic *gc;
	230	struct irq_chip_type *ct;
	231
	232	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
55601c9f	233	handle_level_irq);
667a11fa TL	234	ct = gc->chip_types;
	235	ct->chip.irq_ack = omap_mask_ack_irq;
	236	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	237	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
e3c83c2d	238	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
667a11fa	239
667a11fa TL	240	ct->regs.enable = INTC_MIR_CLEAR0;
	241	ct->regs.disable = INTC_MIR_SET0;
	242	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
55601c9f	243	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
667a11fa TL	244	}
667a11fa TL	245
55601c9f FB	246	static int __init omap_init_irq_of(struct device_node *node)
	247	{
	248	int ret;
	249
	250	omap_irq_base = of_iomap(node, 0);
	251	if (WARN_ON(!omap_irq_base))
	252	return -ENOMEM;
	253
	254	domain = irq_domain_add_linear(node, omap_nr_irqs,
	255	&irq_generic_chip_ops, NULL);
	256
	257	omap_irq_soft_reset();
	258
	259	ret = omap_alloc_gc_of(domain, omap_irq_base);
	260	if (ret < 0)
	261	irq_domain_remove(domain);
	262
	263	return ret;
	264	}
	265
4b149e41	266	static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
1dbae815	267	{
a88ab430	268	int j, irq_base;
1dbae815	269
741e3a89 TL	270	omap_irq_base = ioremap(base, SZ_4K);
741e3a89 TL	271	if (WARN_ON(!omap_irq_base))
55601c9f	272	return -ENOMEM;
741e3a89	273
a74f0a17	274	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
52fa2120 BC	275	if (irq_base < 0) {
	276	pr_warn("Couldn't allocate IRQ numbers\n");
	277	irq_base = 0;
	278	}
	279
4b149e41	280	domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
a88ab430	281	&irq_domain_simple_ops, NULL);
1dbae815	282
a88ab430	283	omap_irq_soft_reset();
667a11fa	284
a88ab430	285	for (j = 0; j < omap_nr_irqs; j += 32)
55601c9f FB	286	omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
	287
	288	return 0;
	289	}
	290
9836ee9f FB	291	static void __init omap_irq_enable_protection(void)
	292	{
	293	u32 reg;
	294
	295	reg = intc_readl(INTC_PROTECTION);
	296	reg \|= INTC_PROTECTION_ENABLE;
	297	intc_writel(INTC_PROTECTION, reg);
	298	}
	299
55601c9f FB	300	static int __init omap_init_irq(u32 base, struct device_node *node)
55601c9f FB	301	{
9836ee9f FB	302	int ret;
9836ee9f FB	303
4b149e41 FB	304	/*
	305	* FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
	306	* depends is still not ready for linear IRQ domains; because of that
	307	* we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
	308	* linear IRQ Domain until that driver is finally fixed.
	309	*/
	310	if (of_device_is_compatible(node, "ti,omap2-intc") \|\|
	311	of_device_is_compatible(node, "ti,omap3-intc")) {
	312	struct resource res;
	313
	314	if (of_address_to_resource(node, 0, &res))
	315	return -ENOMEM;
	316
	317	base = res.start;
	318	ret = omap_init_irq_legacy(base, node);
	319	} else if (node) {
9836ee9f	320	ret = omap_init_irq_of(node);
4b149e41 FB	321	} else {
	322	ret = omap_init_irq_legacy(base, NULL);
	323	}
9836ee9f FB	324
	325	if (ret == 0)
	326	omap_irq_enable_protection();
	327
	328	return ret;
1dbae815 TL	329	}
1dbae815 TL	330
2aced892 FB	331	static asmlinkage void __exception_irq_entry
2aced892 FB	332	omap_intc_handle_irq(struct pt_regs *regs)
2db14997	333	{
d6a7c5c8	334	u32 irqnr = 0;
698b4853	335	int handled_irq = 0;
d6a7c5c8	336	int i;
2db14997 MZ	337
2db14997 MZ	338	do {
d6a7c5c8 FB	339	for (i = 0; i < omap_nr_pending; i++) {
	340	irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
	341	if (irqnr)
	342	goto out;
	343	}
2db14997 MZ	344
	345	out:
	346	if (!irqnr)
	347	break;
	348
11983656	349	irqnr = intc_readl(INTC_SIR);
2db14997 MZ	350	irqnr &= ACTIVEIRQ_MASK;
2db14997 MZ	351
52fa2120	352	if (irqnr) {
782d59c5	353	handle_domain_irq(domain, irqnr, regs);
698b4853	354	handled_irq = 1;
52fa2120	355	}
2db14997	356	} while (irqnr);
698b4853	357
503b8d12 FB	358	/*
503b8d12 FB	359	* If an irq is masked or deasserted while active, we will
698b4853	360	* keep ending up here with no irq handled. So remove it from
503b8d12 FB	361	* the INTC with an ack.
503b8d12 FB	362	*/
698b4853 SS	363	if (!handled_irq)
698b4853 SS	364	omap_ack_irq(NULL);
2db14997 MZ	365	}
2db14997 MZ	366
a4d3c5d9 FB	367	void __init omap3_init_irq(void)
a4d3c5d9 FB	368	{
a74f0a17	369	omap_nr_irqs = 96;
52b1e129	370	omap_nr_pending = 3;
a74f0a17	371	omap_init_irq(OMAP34XX_IC_BASE, NULL);
2aced892	372	set_handle_irq(omap_intc_handle_irq);
a4d3c5d9 FB	373	}
a4d3c5d9 FB	374
00b6b031	375	static int __init intc_of_init(struct device_node *node,
52fa2120 BC	376	struct device_node *parent)
52fa2120 BC	377	{
55601c9f	378	int ret;
a74f0a17	379
52b1e129	380	omap_nr_pending = 3;
a74f0a17	381	omap_nr_irqs = 96;
52fa2120 BC	382
	383	if (WARN_ON(!node))
	384	return -ENODEV;
	385
19f92b23 TL	386	if (of_device_is_compatible(node, "ti,dm814-intc") \|\|
	387	of_device_is_compatible(node, "ti,dm816-intc") \|\|
	388	of_device_is_compatible(node, "ti,am33xx-intc")) {
a74f0a17	389	omap_nr_irqs = 128;
52b1e129 FB	390	omap_nr_pending = 4;
52b1e129 FB	391	}
470f30de	392
55601c9f FB	393	ret = omap_init_irq(-1, of_node_get(node));
	394	if (ret < 0)
	395	return ret;
52fa2120	396
2aced892	397	set_handle_irq(omap_intc_handle_irq);
b15c76b7	398
52fa2120 BC	399	return 0;
	400	}
	401
a35db9a4 FB	402	IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
a35db9a4 FB	403	IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
19f92b23 TL	404	IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
19f92b23 TL	405	IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
a35db9a4	406	IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);