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292ec080 UKK |
1 | /* |
2 | * drivers/irq/irq-nvic.c | |
3 | * | |
4 | * Copyright (C) 2008 ARM Limited, All Rights Reserved. | |
5 | * Copyright (C) 2013 Pengutronix | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Support for the Nested Vectored Interrupt Controller found on the | |
12 | * ARMv7-M CPUs (Cortex-M3/M4) | |
13 | */ | |
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/irq.h> | |
41a83e06 | 24 | #include <linux/irqchip.h> |
292ec080 UKK |
25 | #include <linux/irqdomain.h> |
26 | ||
27 | #include <asm/v7m.h> | |
28 | #include <asm/exception.h> | |
29 | ||
292ec080 UKK |
30 | #define NVIC_ISER 0x000 |
31 | #define NVIC_ICER 0x080 | |
32 | #define NVIC_IPR 0x300 | |
33 | ||
34 | #define NVIC_MAX_BANKS 16 | |
35 | /* | |
36 | * Each bank handles 32 irqs. Only the 16th (= last) bank handles only | |
37 | * 16 irqs. | |
38 | */ | |
39 | #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16) | |
40 | ||
41 | static struct irq_domain *nvic_irq_domain; | |
42 | ||
43 | asmlinkage void __exception_irq_entry | |
44 | nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs) | |
45 | { | |
46 | unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq); | |
47 | ||
48 | handle_IRQ(irq, regs); | |
49 | } | |
50 | ||
2d9f59f7 SA |
51 | static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
52 | unsigned int nr_irqs, void *arg) | |
53 | { | |
54 | int i, ret; | |
55 | irq_hw_number_t hwirq; | |
56 | unsigned int type = IRQ_TYPE_NONE; | |
57 | struct of_phandle_args *irq_data = arg; | |
58 | ||
59 | ret = irq_domain_xlate_onecell(domain, irq_data->np, irq_data->args, | |
60 | irq_data->args_count, &hwirq, &type); | |
61 | if (ret) | |
62 | return ret; | |
63 | ||
64 | for (i = 0; i < nr_irqs; i++) | |
65 | irq_map_generic_chip(domain, virq + i, hwirq + i); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | static const struct irq_domain_ops nvic_irq_domain_ops = { | |
71 | .xlate = irq_domain_xlate_onecell, | |
72 | .alloc = nvic_irq_domain_alloc, | |
73 | .free = irq_domain_free_irqs_top, | |
74 | }; | |
75 | ||
292ec080 UKK |
76 | static int __init nvic_of_init(struct device_node *node, |
77 | struct device_node *parent) | |
78 | { | |
79 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
80 | unsigned int irqs, i, ret, numbanks; | |
81 | void __iomem *nvic_base; | |
82 | ||
83 | numbanks = (readl_relaxed(V7M_SCS_ICTR) & | |
84 | V7M_SCS_ICTR_INTLINESNUM_MASK) + 1; | |
85 | ||
86 | nvic_base = of_iomap(node, 0); | |
87 | if (!nvic_base) { | |
88 | pr_warn("unable to map nvic registers\n"); | |
89 | return -ENOMEM; | |
90 | } | |
91 | ||
92 | irqs = numbanks * 32; | |
93 | if (irqs > NVIC_MAX_IRQ) | |
94 | irqs = NVIC_MAX_IRQ; | |
95 | ||
96 | nvic_irq_domain = | |
2d9f59f7 SA |
97 | irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL); |
98 | ||
292ec080 UKK |
99 | if (!nvic_irq_domain) { |
100 | pr_warn("Failed to allocate irq domain\n"); | |
101 | return -ENOMEM; | |
102 | } | |
103 | ||
5b8aae48 | 104 | ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1, |
292ec080 UKK |
105 | "nvic_irq", handle_fasteoi_irq, |
106 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
107 | if (ret) { | |
108 | pr_warn("Failed to allocate irq chips\n"); | |
109 | irq_domain_remove(nvic_irq_domain); | |
110 | return ret; | |
111 | } | |
112 | ||
113 | for (i = 0; i < numbanks; ++i) { | |
114 | struct irq_chip_generic *gc; | |
115 | ||
116 | gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i); | |
117 | gc->reg_base = nvic_base + 4 * i; | |
118 | gc->chip_types[0].regs.enable = NVIC_ISER; | |
119 | gc->chip_types[0].regs.disable = NVIC_ICER; | |
120 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; | |
121 | gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; | |
8b53ec26 DT |
122 | /* This is a no-op as end of interrupt is signaled by the |
123 | * exception return sequence. | |
124 | */ | |
125 | gc->chip_types[0].chip.irq_eoi = irq_gc_noop; | |
292ec080 UKK |
126 | |
127 | /* disable interrupts */ | |
128 | writel_relaxed(~0, gc->reg_base + NVIC_ICER); | |
129 | } | |
130 | ||
131 | /* Set priority on all interrupts */ | |
132 | for (i = 0; i < irqs; i += 4) | |
133 | writel_relaxed(0, nvic_base + NVIC_IPR + i); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init); |