[linux-block.git] / drivers / irqchip / irq-nvic.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/irq/irq-nvic.c
 *
 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
 * Copyright (C) 2013 Pengutronix
 *
 * Support for the Nested Vectored Interrupt Controller found on the
 * ARMv7-M CPUs (Cortex-M3/M4)
 */
#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>

#include <asm/v7m.h>
#include <asm/exception.h>

#define NVIC_ISER		0x000
#define NVIC_ICER		0x080
#define NVIC_IPR		0x400

#define NVIC_MAX_BANKS		16
/*
 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
 * 16 irqs.
 */
#define NVIC_MAX_IRQ		((NVIC_MAX_BANKS - 1) * 32 + 16)

static struct irq_domain *nvic_irq_domain;

static void __nvic_handle_irq(irq_hw_number_t hwirq)
{
	generic_handle_domain_irq(nvic_irq_domain, hwirq);
}

/*
 * TODO: restructure the ARMv7M entry logic so that this entry logic can live
 * in arch code.
 */
asmlinkage void __exception_irq_entry
nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
{
	struct pt_regs *old_regs;

	irq_enter();
	old_regs = set_irq_regs(regs);
	__nvic_handle_irq(hwirq);
	set_irq_regs(old_regs);
	irq_exit();
}

static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				unsigned int nr_irqs, void *arg)
{
	int i, ret;
	irq_hw_number_t hwirq;
	unsigned int type = IRQ_TYPE_NONE;
	struct irq_fwspec *fwspec = arg;

	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++)
		irq_map_generic_chip(domain, virq + i, hwirq + i);

	return 0;
}

static const struct irq_domain_ops nvic_irq_domain_ops = {
	.translate = irq_domain_translate_onecell,
	.alloc = nvic_irq_domain_alloc,
	.free = irq_domain_free_irqs_top,
};

static int __init nvic_of_init(struct device_node *node,
			       struct device_node *parent)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int irqs, i, ret, numbanks;
	void __iomem *nvic_base;

	numbanks = (readl_relaxed(V7M_SCS_ICTR) &
		    V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;

	nvic_base = of_iomap(node, 0);
	if (!nvic_base) {
		pr_warn("unable to map nvic registers\n");
		return -ENOMEM;
	}

	irqs = numbanks * 32;
	if (irqs > NVIC_MAX_IRQ)
		irqs = NVIC_MAX_IRQ;

	nvic_irq_domain =
		irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);

	if (!nvic_irq_domain) {
		pr_warn("Failed to allocate irq domain\n");
		return -ENOMEM;
	}

	ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
					     "nvic_irq", handle_fasteoi_irq,
					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_warn("Failed to allocate irq chips\n");
		irq_domain_remove(nvic_irq_domain);
		return ret;
	}

	for (i = 0; i < numbanks; ++i) {
		struct irq_chip_generic *gc;

		gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
		gc->reg_base = nvic_base + 4 * i;
		gc->chip_types[0].regs.enable = NVIC_ISER;
		gc->chip_types[0].regs.disable = NVIC_ICER;
		gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
		gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
		/* This is a no-op as end of interrupt is signaled by the
		 * exception return sequence.
		 */
		gc->chip_types[0].chip.irq_eoi = irq_gc_noop;

		/* disable interrupts */
		writel_relaxed(~0, gc->reg_base + NVIC_ICER);
	}

	/* Set priority on all interrupts */
	for (i = 0; i < irqs; i += 4)
		writel_relaxed(0, nvic_base + NVIC_IPR + i);

	return 0;
}
IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
292ec080 UKK	2	/*
	3	* drivers/irq/irq-nvic.c
	4	*
	5	* Copyright (C) 2008 ARM Limited, All Rights Reserved.
	6	* Copyright (C) 2013 Pengutronix
	7	*
292ec080 UKK	8	* Support for the Nested Vectored Interrupt Controller found on the
	9	* ARMv7-M CPUs (Cortex-M3/M4)
	10	*/
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
	15	#include <linux/slab.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/irq.h>
41a83e06	21	#include <linux/irqchip.h>
292ec080 UKK	22	#include <linux/irqdomain.h>
	23
	24	#include <asm/v7m.h>
	25	#include <asm/exception.h>
	26
292ec080 UKK	27	#define NVIC_ISER 0x000
292ec080 UKK	28	#define NVIC_ICER 0x080
c5e0cbe2	29	#define NVIC_IPR 0x400
292ec080 UKK	30
	31	#define NVIC_MAX_BANKS 16
	32	/*
	33	* Each bank handles 32 irqs. Only the 16th (= last) bank handles only
	34	* 16 irqs.
	35	*/
	36	#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
	37
	38	static struct irq_domain *nvic_irq_domain;
	39
0953fb26	40	static void __nvic_handle_irq(irq_hw_number_t hwirq)
a7b0872e	41	{
0953fb26	42	generic_handle_domain_irq(nvic_irq_domain, hwirq);
a7b0872e MR	43	}
	44
	45	/*
	46	* TODO: restructure the ARMv7M entry logic so that this entry logic can live
	47	* in arch code.
	48	*/
292ec080 UKK	49	asmlinkage void __exception_irq_entry
	50	nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
	51	{
a7b0872e MR	52	struct pt_regs *old_regs;
	53
	54	irq_enter();
	55	old_regs = set_irq_regs(regs);
0953fb26	56	__nvic_handle_irq(hwirq);
a7b0872e MR	57	set_irq_regs(old_regs);
a7b0872e MR	58	irq_exit();
292ec080 UKK	59	}
292ec080 UKK	60
2d9f59f7 SA	61	static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	62	unsigned int nr_irqs, void *arg)
	63	{
	64	int i, ret;
	65	irq_hw_number_t hwirq;
	66	unsigned int type = IRQ_TYPE_NONE;
f833f57f	67	struct irq_fwspec *fwspec = arg;
2d9f59f7	68
459c3bc8	69	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
2d9f59f7 SA	70	if (ret)
	71	return ret;
	72
	73	for (i = 0; i < nr_irqs; i++)
	74	irq_map_generic_chip(domain, virq + i, hwirq + i);
	75
	76	return 0;
	77	}
	78
	79	static const struct irq_domain_ops nvic_irq_domain_ops = {
459c3bc8	80	.translate = irq_domain_translate_onecell,
2d9f59f7 SA	81	.alloc = nvic_irq_domain_alloc,
	82	.free = irq_domain_free_irqs_top,
	83	};
	84
292ec080 UKK	85	static int __init nvic_of_init(struct device_node *node,
	86	struct device_node *parent)
	87	{
	88	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	89	unsigned int irqs, i, ret, numbanks;
	90	void __iomem *nvic_base;
	91
	92	numbanks = (readl_relaxed(V7M_SCS_ICTR) &
	93	V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
	94
	95	nvic_base = of_iomap(node, 0);
	96	if (!nvic_base) {
	97	pr_warn("unable to map nvic registers\n");
	98	return -ENOMEM;
	99	}
	100
	101	irqs = numbanks * 32;
	102	if (irqs > NVIC_MAX_IRQ)
	103	irqs = NVIC_MAX_IRQ;
	104
	105	nvic_irq_domain =
2d9f59f7 SA	106	irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
2d9f59f7 SA	107
292ec080 UKK	108	if (!nvic_irq_domain) {
	109	pr_warn("Failed to allocate irq domain\n");
	110	return -ENOMEM;
	111	}
	112
5b8aae48	113	ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
292ec080 UKK	114	"nvic_irq", handle_fasteoi_irq,
	115	clr, 0, IRQ_GC_INIT_MASK_CACHE);
	116	if (ret) {
	117	pr_warn("Failed to allocate irq chips\n");
	118	irq_domain_remove(nvic_irq_domain);
	119	return ret;
	120	}
	121
	122	for (i = 0; i < numbanks; ++i) {
	123	struct irq_chip_generic *gc;
	124
	125	gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
	126	gc->reg_base = nvic_base + 4 * i;
	127	gc->chip_types[0].regs.enable = NVIC_ISER;
	128	gc->chip_types[0].regs.disable = NVIC_ICER;
	129	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	130	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
8b53ec26 DT	131	/* This is a no-op as end of interrupt is signaled by the
	132	* exception return sequence.
	133	*/
	134	gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
292ec080 UKK	135
	136	/* disable interrupts */
	137	writel_relaxed(~0, gc->reg_base + NVIC_ICER);
	138	}
	139
	140	/* Set priority on all interrupts */
	141	for (i = 0; i < irqs; i += 4)
	142	writel_relaxed(0, nvic_base + NVIC_IPR + i);
	143
	144	return 0;
	145	}
	146	IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);