[linux-2.6-block.git] / drivers / irqchip / irq-nvic.c

/*
 * drivers/irq/irq-nvic.c
 *
 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
 * Copyright (C) 2013 Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Support for the Nested Vectored Interrupt Controller found on the
 * ARMv7-M CPUs (Cortex-M3/M4)
 */
#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>

#include <asm/v7m.h>
#include <asm/exception.h>

#include "irqchip.h"

#define NVIC_ISER		0x000
#define NVIC_ICER		0x080
#define NVIC_IPR		0x300

#define NVIC_MAX_BANKS		16
/*
 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
 * 16 irqs.
 */
#define NVIC_MAX_IRQ		((NVIC_MAX_BANKS - 1) * 32 + 16)

static struct irq_domain *nvic_irq_domain;

asmlinkage void __exception_irq_entry
nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
{
	unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);

	handle_IRQ(irq, regs);
}

static int __init nvic_of_init(struct device_node *node,
			       struct device_node *parent)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int irqs, i, ret, numbanks;
	void __iomem *nvic_base;

	numbanks = (readl_relaxed(V7M_SCS_ICTR) &
		    V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;

	nvic_base = of_iomap(node, 0);
	if (!nvic_base) {
		pr_warn("unable to map nvic registers\n");
		return -ENOMEM;
	}

	irqs = numbanks * 32;
	if (irqs > NVIC_MAX_IRQ)
		irqs = NVIC_MAX_IRQ;

	nvic_irq_domain =
		irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
	if (!nvic_irq_domain) {
		pr_warn("Failed to allocate irq domain\n");
		return -ENOMEM;
	}

	ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
					     "nvic_irq", handle_fasteoi_irq,
					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_warn("Failed to allocate irq chips\n");
		irq_domain_remove(nvic_irq_domain);
		return ret;
	}

	for (i = 0; i < numbanks; ++i) {
		struct irq_chip_generic *gc;

		gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
		gc->reg_base = nvic_base + 4 * i;
		gc->chip_types[0].regs.enable = NVIC_ISER;
		gc->chip_types[0].regs.disable = NVIC_ICER;
		gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
		gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
		/* This is a no-op as end of interrupt is signaled by the
		 * exception return sequence.
		 */
		gc->chip_types[0].chip.irq_eoi = irq_gc_noop;

		/* disable interrupts */
		writel_relaxed(~0, gc->reg_base + NVIC_ICER);
	}

	/* Set priority on all interrupts */
	for (i = 0; i < irqs; i += 4)
		writel_relaxed(0, nvic_base + NVIC_IPR + i);

	return 0;
}
IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
Commit	Line	Data
292ec080 UKK	1	/*
	2	* drivers/irq/irq-nvic.c
	3	*
	4	* Copyright (C) 2008 ARM Limited, All Rights Reserved.
	5	* Copyright (C) 2013 Pengutronix
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Support for the Nested Vectored Interrupt Controller found on the
	12	* ARMv7-M CPUs (Cortex-M3/M4)
	13	*/
	14	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	15
	16	#include <linux/init.h>
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/err.h>
	20	#include <linux/io.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/irq.h>
	24	#include <linux/irqdomain.h>
	25
	26	#include <asm/v7m.h>
	27	#include <asm/exception.h>
	28
	29	#include "irqchip.h"
	30
	31	#define NVIC_ISER 0x000
	32	#define NVIC_ICER 0x080
	33	#define NVIC_IPR 0x300
	34
	35	#define NVIC_MAX_BANKS 16
	36	/*
	37	* Each bank handles 32 irqs. Only the 16th (= last) bank handles only
	38	* 16 irqs.
	39	*/
	40	#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
	41
	42	static struct irq_domain *nvic_irq_domain;
	43
	44	asmlinkage void __exception_irq_entry
	45	nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
	46	{
	47	unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
	48
	49	handle_IRQ(irq, regs);
	50	}
	51
292ec080 UKK	52	static int __init nvic_of_init(struct device_node *node,
	53	struct device_node *parent)
	54	{
	55	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	56	unsigned int irqs, i, ret, numbanks;
	57	void __iomem *nvic_base;
	58
	59	numbanks = (readl_relaxed(V7M_SCS_ICTR) &
	60	V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
	61
	62	nvic_base = of_iomap(node, 0);
	63	if (!nvic_base) {
	64	pr_warn("unable to map nvic registers\n");
	65	return -ENOMEM;
	66	}
	67
	68	irqs = numbanks * 32;
	69	if (irqs > NVIC_MAX_IRQ)
	70	irqs = NVIC_MAX_IRQ;
	71
	72	nvic_irq_domain =
	73	irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
	74	if (!nvic_irq_domain) {
	75	pr_warn("Failed to allocate irq domain\n");
	76	return -ENOMEM;
	77	}
	78
5b8aae48	79	ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
292ec080 UKK	80	"nvic_irq", handle_fasteoi_irq,
	81	clr, 0, IRQ_GC_INIT_MASK_CACHE);
	82	if (ret) {
	83	pr_warn("Failed to allocate irq chips\n");
	84	irq_domain_remove(nvic_irq_domain);
	85	return ret;
	86	}
	87
	88	for (i = 0; i < numbanks; ++i) {
	89	struct irq_chip_generic *gc;
	90
	91	gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
	92	gc->reg_base = nvic_base + 4 * i;
	93	gc->chip_types[0].regs.enable = NVIC_ISER;
	94	gc->chip_types[0].regs.disable = NVIC_ICER;
	95	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
	96	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
8b53ec26 DT	97	/* This is a no-op as end of interrupt is signaled by the
	98	* exception return sequence.
	99	*/
	100	gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
292ec080 UKK	101
	102	/* disable interrupts */
	103	writel_relaxed(~0, gc->reg_base + NVIC_ICER);
	104	}
	105
	106	/* Set priority on all interrupts */
	107	for (i = 0; i < irqs; i += 4)
	108	writel_relaxed(0, nvic_base + NVIC_IPR + i);
	109
	110	return 0;
	111	}
	112	IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);