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16216333 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
289569f9 SG |
2 | /* |
3 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
7e4ac676 OR |
4 | * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> |
5 | * Add Alphascale ASM9260 support. | |
289569f9 SG |
6 | */ |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/irq.h> | |
41a83e06 | 11 | #include <linux/irqchip.h> |
83a84efc | 12 | #include <linux/irqdomain.h> |
289569f9 | 13 | #include <linux/io.h> |
83a84efc | 14 | #include <linux/of.h> |
8256aa71 | 15 | #include <linux/of_address.h> |
83a84efc | 16 | #include <linux/of_irq.h> |
cec6bae8 | 17 | #include <linux/stmp_device.h> |
4e0a1b8c | 18 | #include <asm/exception.h> |
289569f9 | 19 | |
7e4ac676 OR |
20 | #include "alphascale_asm9260-icoll.h" |
21 | ||
25e34b44 OR |
22 | /* |
23 | * this device provide 4 offsets for each register: | |
24 | * 0x0 - plain read write mode | |
25 | * 0x4 - set mode, OR logic. | |
26 | * 0x8 - clr mode, XOR logic. | |
27 | * 0xc - togle mode. | |
28 | */ | |
29 | #define SET_REG 4 | |
30 | #define CLR_REG 8 | |
31 | ||
289569f9 SG |
32 | #define HW_ICOLL_VECTOR 0x0000 |
33 | #define HW_ICOLL_LEVELACK 0x0010 | |
34 | #define HW_ICOLL_CTRL 0x0020 | |
4e0a1b8c | 35 | #define HW_ICOLL_STAT_OFFSET 0x0070 |
25e34b44 OR |
36 | #define HW_ICOLL_INTERRUPT0 0x0120 |
37 | #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) | |
38 | #define BM_ICOLL_INTR_ENABLE BIT(2) | |
289569f9 SG |
39 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 |
40 | ||
83a84efc SG |
41 | #define ICOLL_NUM_IRQS 128 |
42 | ||
7e4ac676 OR |
43 | enum icoll_type { |
44 | ICOLL, | |
45 | ASM9260_ICOLL, | |
46 | }; | |
47 | ||
25e34b44 OR |
48 | struct icoll_priv { |
49 | void __iomem *vector; | |
50 | void __iomem *levelack; | |
51 | void __iomem *ctrl; | |
52 | void __iomem *stat; | |
53 | void __iomem *intr; | |
7e4ac676 OR |
54 | void __iomem *clear; |
55 | enum icoll_type type; | |
25e34b44 OR |
56 | }; |
57 | ||
58 | static struct icoll_priv icoll_priv; | |
83a84efc | 59 | static struct irq_domain *icoll_domain; |
289569f9 | 60 | |
a359f757 | 61 | /* calculate bit offset depending on number of interrupt per register */ |
7e4ac676 OR |
62 | static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) |
63 | { | |
64 | /* | |
65 | * mask lower part of hwirq to convert it | |
66 | * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3) | |
67 | */ | |
68 | return bit << ((d->hwirq & 3) << 3); | |
69 | } | |
70 | ||
a359f757 | 71 | /* calculate mem offset depending on number of interrupt per register */ |
7e4ac676 OR |
72 | static void __iomem *icoll_intr_reg(struct irq_data *d) |
73 | { | |
74 | /* offset = hwirq / intr_per_reg * 0x10 */ | |
75 | return icoll_priv.intr + ((d->hwirq >> 2) * 0x10); | |
76 | } | |
77 | ||
bf0c1118 | 78 | static void icoll_ack_irq(struct irq_data *d) |
289569f9 SG |
79 | { |
80 | /* | |
81 | * The Interrupt Collector is able to prioritize irqs. | |
82 | * Currently only level 0 is used. So acking can use | |
83 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. | |
84 | */ | |
85 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, | |
25e34b44 | 86 | icoll_priv.levelack); |
289569f9 SG |
87 | } |
88 | ||
bf0c1118 | 89 | static void icoll_mask_irq(struct irq_data *d) |
289569f9 | 90 | { |
25e34b44 OR |
91 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
92 | icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
93 | } |
94 | ||
bf0c1118 | 95 | static void icoll_unmask_irq(struct irq_data *d) |
289569f9 | 96 | { |
25e34b44 OR |
97 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
98 | icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
99 | } |
100 | ||
7e4ac676 OR |
101 | static void asm9260_mask_irq(struct irq_data *d) |
102 | { | |
103 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), | |
104 | icoll_intr_reg(d) + CLR_REG); | |
105 | } | |
106 | ||
107 | static void asm9260_unmask_irq(struct irq_data *d) | |
108 | { | |
109 | __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq), | |
110 | icoll_priv.clear + | |
111 | ASM9260_HW_ICOLL_CLEARn(d->hwirq)); | |
112 | ||
113 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), | |
114 | icoll_intr_reg(d) + SET_REG); | |
115 | } | |
116 | ||
289569f9 | 117 | static struct irq_chip mxs_icoll_chip = { |
bf0c1118 UKK |
118 | .irq_ack = icoll_ack_irq, |
119 | .irq_mask = icoll_mask_irq, | |
120 | .irq_unmask = icoll_unmask_irq, | |
88e20c74 SW |
121 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
122 | IRQCHIP_SKIP_SET_WAKE, | |
289569f9 SG |
123 | }; |
124 | ||
7e4ac676 OR |
125 | static struct irq_chip asm9260_icoll_chip = { |
126 | .irq_ack = icoll_ack_irq, | |
127 | .irq_mask = asm9260_mask_irq, | |
128 | .irq_unmask = asm9260_unmask_irq, | |
88e20c74 SW |
129 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
130 | IRQCHIP_SKIP_SET_WAKE, | |
7e4ac676 OR |
131 | }; |
132 | ||
4e0a1b8c SG |
133 | asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) |
134 | { | |
135 | u32 irqnr; | |
136 | ||
25e34b44 OR |
137 | irqnr = __raw_readl(icoll_priv.stat); |
138 | __raw_writel(irqnr, icoll_priv.vector); | |
0953fb26 | 139 | generic_handle_domain_irq(icoll_domain, irqnr); |
4e0a1b8c SG |
140 | } |
141 | ||
83a84efc SG |
142 | static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, |
143 | irq_hw_number_t hw) | |
289569f9 | 144 | { |
7e4ac676 OR |
145 | struct irq_chip *chip; |
146 | ||
147 | if (icoll_priv.type == ICOLL) | |
148 | chip = &mxs_icoll_chip; | |
149 | else | |
150 | chip = &asm9260_icoll_chip; | |
151 | ||
152 | irq_set_chip_and_handler(virq, chip, handle_level_irq); | |
83a84efc SG |
153 | |
154 | return 0; | |
155 | } | |
289569f9 | 156 | |
96009736 | 157 | static const struct irq_domain_ops icoll_irq_domain_ops = { |
83a84efc SG |
158 | .map = icoll_irq_domain_map, |
159 | .xlate = irq_domain_xlate_onecell, | |
160 | }; | |
161 | ||
25e34b44 OR |
162 | static void __init icoll_add_domain(struct device_node *np, |
163 | int num) | |
164 | { | |
165 | icoll_domain = irq_domain_add_linear(np, num, | |
166 | &icoll_irq_domain_ops, NULL); | |
167 | ||
168 | if (!icoll_domain) | |
e81f54c6 | 169 | panic("%pOF: unable to create irq domain", np); |
25e34b44 OR |
170 | } |
171 | ||
172 | static void __iomem * __init icoll_init_iobase(struct device_node *np) | |
83a84efc | 173 | { |
25e34b44 OR |
174 | void __iomem *icoll_base; |
175 | ||
176 | icoll_base = of_io_request_and_map(np, 0, np->name); | |
edf8fcdc | 177 | if (IS_ERR(icoll_base)) |
e81f54c6 | 178 | panic("%pOF: unable to map resource", np); |
25e34b44 OR |
179 | return icoll_base; |
180 | } | |
181 | ||
182 | static int __init icoll_of_init(struct device_node *np, | |
183 | struct device_node *interrupt_parent) | |
184 | { | |
185 | void __iomem *icoll_base; | |
186 | ||
7e4ac676 OR |
187 | icoll_priv.type = ICOLL; |
188 | ||
25e34b44 OR |
189 | icoll_base = icoll_init_iobase(np); |
190 | icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; | |
191 | icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; | |
192 | icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; | |
193 | icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; | |
194 | icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; | |
7e4ac676 | 195 | icoll_priv.clear = NULL; |
8256aa71 | 196 | |
289569f9 SG |
197 | /* |
198 | * Interrupt Collector reset, which initializes the priority | |
199 | * for each irq to level 0. | |
200 | */ | |
25e34b44 | 201 | stmp_reset_block(icoll_priv.ctrl); |
289569f9 | 202 | |
25e34b44 | 203 | icoll_add_domain(np, ICOLL_NUM_IRQS); |
5bb578a0 | 204 | set_handle_irq(icoll_handle_irq); |
e59a8451 OR |
205 | |
206 | return 0; | |
83a84efc | 207 | } |
6a8e95b0 | 208 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); |
7e4ac676 OR |
209 | |
210 | static int __init asm9260_of_init(struct device_node *np, | |
211 | struct device_node *interrupt_parent) | |
212 | { | |
213 | void __iomem *icoll_base; | |
214 | int i; | |
215 | ||
216 | icoll_priv.type = ASM9260_ICOLL; | |
217 | ||
218 | icoll_base = icoll_init_iobase(np); | |
219 | icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR; | |
220 | icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK; | |
221 | icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL; | |
222 | icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET; | |
223 | icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0; | |
224 | icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0; | |
225 | ||
226 | writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE, | |
227 | icoll_priv.ctrl); | |
228 | /* | |
229 | * ASM9260 don't provide reset bit. So, we need to set level 0 | |
230 | * manually. | |
231 | */ | |
232 | for (i = 0; i < 16 * 0x10; i += 0x10) | |
233 | writel(0, icoll_priv.intr + i); | |
234 | ||
235 | icoll_add_domain(np, ASM9260_NUM_IRQS); | |
c5b63520 | 236 | set_handle_irq(icoll_handle_irq); |
7e4ac676 OR |
237 | |
238 | return 0; | |
239 | } | |
240 | IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init); |