[linux-block.git] / drivers / irqchip / irq-mxs.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
 *	Add Alphascale ASM9260 support.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/stmp_device.h>
#include <asm/exception.h>

#include "alphascale_asm9260-icoll.h"

/*
 * this device provide 4 offsets for each register:
 * 0x0 - plain read write mode
 * 0x4 - set mode, OR logic.
 * 0x8 - clr mode, XOR logic.
 * 0xc - togle mode.
 */
#define SET_REG 4
#define CLR_REG 8

#define HW_ICOLL_VECTOR				0x0000
#define HW_ICOLL_LEVELACK			0x0010
#define HW_ICOLL_CTRL				0x0020
#define HW_ICOLL_STAT_OFFSET			0x0070
#define HW_ICOLL_INTERRUPT0			0x0120
#define HW_ICOLL_INTERRUPTn(n)			((n) * 0x10)
#define BM_ICOLL_INTR_ENABLE			BIT(2)
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0	0x1

#define ICOLL_NUM_IRQS		128

enum icoll_type {
	ICOLL,
	ASM9260_ICOLL,
};

struct icoll_priv {
	void __iomem *vector;
	void __iomem *levelack;
	void __iomem *ctrl;
	void __iomem *stat;
	void __iomem *intr;
	void __iomem *clear;
	enum icoll_type type;
};

static struct icoll_priv icoll_priv;
static struct irq_domain *icoll_domain;

/* calculate bit offset depending on number of interrupt per register */
static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
{
	/*
	 * mask lower part of hwirq to convert it
	 * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
	 */
	return bit << ((d->hwirq & 3) << 3);
}

/* calculate mem offset depending on number of interrupt per register */
static void __iomem *icoll_intr_reg(struct irq_data *d)
{
	/* offset = hwirq / intr_per_reg * 0x10 */
	return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
}

static void icoll_ack_irq(struct irq_data *d)
{
	/*
	 * The Interrupt Collector is able to prioritize irqs.
	 * Currently only level 0 is used. So acking can use
	 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
	 */
	__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
			icoll_priv.levelack);
}

static void icoll_mask_irq(struct irq_data *d)
{
	__raw_writel(BM_ICOLL_INTR_ENABLE,
			icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
}

static void icoll_unmask_irq(struct irq_data *d)
{
	__raw_writel(BM_ICOLL_INTR_ENABLE,
			icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
}

static void asm9260_mask_irq(struct irq_data *d)
{
	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
			icoll_intr_reg(d) + CLR_REG);
}

static void asm9260_unmask_irq(struct irq_data *d)
{
	__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
		     icoll_priv.clear +
		     ASM9260_HW_ICOLL_CLEARn(d->hwirq));

	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
			icoll_intr_reg(d) + SET_REG);
}

static struct irq_chip mxs_icoll_chip = {
	.irq_ack = icoll_ack_irq,
	.irq_mask = icoll_mask_irq,
	.irq_unmask = icoll_unmask_irq,
	.flags = IRQCHIP_MASK_ON_SUSPEND |
		 IRQCHIP_SKIP_SET_WAKE,
};

static struct irq_chip asm9260_icoll_chip = {
	.irq_ack = icoll_ack_irq,
	.irq_mask = asm9260_mask_irq,
	.irq_unmask = asm9260_unmask_irq,
	.flags = IRQCHIP_MASK_ON_SUSPEND |
		 IRQCHIP_SKIP_SET_WAKE,
};

asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
{
	u32 irqnr;

	irqnr = __raw_readl(icoll_priv.stat);
	__raw_writel(irqnr, icoll_priv.vector);
	generic_handle_domain_irq(icoll_domain, irqnr);
}

static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hw)
{
	struct irq_chip *chip;

	if (icoll_priv.type == ICOLL)
		chip = &mxs_icoll_chip;
	else
		chip = &asm9260_icoll_chip;

	irq_set_chip_and_handler(virq, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops icoll_irq_domain_ops = {
	.map = icoll_irq_domain_map,
	.xlate = irq_domain_xlate_onecell,
};

static void __init icoll_add_domain(struct device_node *np,
			  int num)
{
	icoll_domain = irq_domain_add_linear(np, num,
					     &icoll_irq_domain_ops, NULL);

	if (!icoll_domain)
		panic("%pOF: unable to create irq domain", np);
}

static void __iomem * __init icoll_init_iobase(struct device_node *np)
{
	void __iomem *icoll_base;

	icoll_base = of_io_request_and_map(np, 0, np->name);
	if (IS_ERR(icoll_base))
		panic("%pOF: unable to map resource", np);
	return icoll_base;
}

static int __init icoll_of_init(struct device_node *np,
			  struct device_node *interrupt_parent)
{
	void __iomem *icoll_base;

	icoll_priv.type = ICOLL;

	icoll_base		= icoll_init_iobase(np);
	icoll_priv.vector	= icoll_base + HW_ICOLL_VECTOR;
	icoll_priv.levelack	= icoll_base + HW_ICOLL_LEVELACK;
	icoll_priv.ctrl		= icoll_base + HW_ICOLL_CTRL;
	icoll_priv.stat		= icoll_base + HW_ICOLL_STAT_OFFSET;
	icoll_priv.intr		= icoll_base + HW_ICOLL_INTERRUPT0;
	icoll_priv.clear	= NULL;

	/*
	 * Interrupt Collector reset, which initializes the priority
	 * for each irq to level 0.
	 */
	stmp_reset_block(icoll_priv.ctrl);

	icoll_add_domain(np, ICOLL_NUM_IRQS);

	return 0;
}
IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);

static int __init asm9260_of_init(struct device_node *np,
			  struct device_node *interrupt_parent)
{
	void __iomem *icoll_base;
	int i;

	icoll_priv.type = ASM9260_ICOLL;

	icoll_base = icoll_init_iobase(np);
	icoll_priv.vector	= icoll_base + ASM9260_HW_ICOLL_VECTOR;
	icoll_priv.levelack	= icoll_base + ASM9260_HW_ICOLL_LEVELACK;
	icoll_priv.ctrl		= icoll_base + ASM9260_HW_ICOLL_CTRL;
	icoll_priv.stat		= icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
	icoll_priv.intr		= icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
	icoll_priv.clear	= icoll_base + ASM9260_HW_ICOLL_CLEAR0;

	writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
			icoll_priv.ctrl);
	/*
	 * ASM9260 don't provide reset bit. So, we need to set level 0
	 * manually.
	 */
	for (i = 0; i < 16 * 0x10; i += 0x10)
		writel(0, icoll_priv.intr + i);

	icoll_add_domain(np, ASM9260_NUM_IRQS);
	set_handle_irq(icoll_handle_irq);

	return 0;
}
IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
289569f9 SG	2	/*
289569f9 SG	3	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7e4ac676 OR	4	* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
7e4ac676 OR	5	* Add Alphascale ASM9260 support.
289569f9 SG	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/init.h>
	10	#include <linux/irq.h>
41a83e06	11	#include <linux/irqchip.h>
83a84efc	12	#include <linux/irqdomain.h>
289569f9	13	#include <linux/io.h>
83a84efc	14	#include <linux/of.h>
8256aa71	15	#include <linux/of_address.h>
83a84efc	16	#include <linux/of_irq.h>
cec6bae8	17	#include <linux/stmp_device.h>
4e0a1b8c	18	#include <asm/exception.h>
289569f9	19
7e4ac676 OR	20	#include "alphascale_asm9260-icoll.h"
7e4ac676 OR	21
25e34b44 OR	22	/*
	23	* this device provide 4 offsets for each register:
	24	* 0x0 - plain read write mode
	25	* 0x4 - set mode, OR logic.
	26	* 0x8 - clr mode, XOR logic.
	27	* 0xc - togle mode.
	28	*/
	29	#define SET_REG 4
	30	#define CLR_REG 8
	31
289569f9 SG	32	#define HW_ICOLL_VECTOR 0x0000
	33	#define HW_ICOLL_LEVELACK 0x0010
	34	#define HW_ICOLL_CTRL 0x0020
4e0a1b8c	35	#define HW_ICOLL_STAT_OFFSET 0x0070
25e34b44 OR	36	#define HW_ICOLL_INTERRUPT0 0x0120
	37	#define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
	38	#define BM_ICOLL_INTR_ENABLE BIT(2)
289569f9 SG	39	#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
289569f9 SG	40
83a84efc SG	41	#define ICOLL_NUM_IRQS 128
83a84efc SG	42
7e4ac676 OR	43	enum icoll_type {
	44	ICOLL,
	45	ASM9260_ICOLL,
	46	};
	47
25e34b44 OR	48	struct icoll_priv {
	49	void __iomem *vector;
	50	void __iomem *levelack;
	51	void __iomem *ctrl;
	52	void __iomem *stat;
	53	void __iomem *intr;
7e4ac676 OR	54	void __iomem *clear;
7e4ac676 OR	55	enum icoll_type type;
25e34b44 OR	56	};
	57
	58	static struct icoll_priv icoll_priv;
83a84efc	59	static struct irq_domain *icoll_domain;
289569f9	60
a359f757	61	/* calculate bit offset depending on number of interrupt per register */
7e4ac676 OR	62	static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
	63	{
	64	/*
	65	* mask lower part of hwirq to convert it
	66	* in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
	67	*/
	68	return bit << ((d->hwirq & 3) << 3);
	69	}
	70
a359f757	71	/* calculate mem offset depending on number of interrupt per register */
7e4ac676 OR	72	static void __iomem icoll_intr_reg(struct irq_data d)
	73	{
	74	/* offset = hwirq / intr_per_reg * 0x10 */
	75	return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
	76	}
	77
bf0c1118	78	static void icoll_ack_irq(struct irq_data *d)
289569f9 SG	79	{
	80	/*
	81	* The Interrupt Collector is able to prioritize irqs.
	82	* Currently only level 0 is used. So acking can use
	83	* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
	84	*/
	85	__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
25e34b44	86	icoll_priv.levelack);
289569f9 SG	87	}
289569f9 SG	88
bf0c1118	89	static void icoll_mask_irq(struct irq_data *d)
289569f9	90	{
25e34b44 OR	91	__raw_writel(BM_ICOLL_INTR_ENABLE,
25e34b44 OR	92	icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
289569f9 SG	93	}
289569f9 SG	94
bf0c1118	95	static void icoll_unmask_irq(struct irq_data *d)
289569f9	96	{
25e34b44 OR	97	__raw_writel(BM_ICOLL_INTR_ENABLE,
25e34b44 OR	98	icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
289569f9 SG	99	}
289569f9 SG	100
7e4ac676 OR	101	static void asm9260_mask_irq(struct irq_data *d)
	102	{
	103	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
	104	icoll_intr_reg(d) + CLR_REG);
	105	}
	106
	107	static void asm9260_unmask_irq(struct irq_data *d)
	108	{
	109	__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
	110	icoll_priv.clear +
	111	ASM9260_HW_ICOLL_CLEARn(d->hwirq));
	112
	113	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
	114	icoll_intr_reg(d) + SET_REG);
	115	}
	116
289569f9	117	static struct irq_chip mxs_icoll_chip = {
bf0c1118 UKK	118	.irq_ack = icoll_ack_irq,
	119	.irq_mask = icoll_mask_irq,
	120	.irq_unmask = icoll_unmask_irq,
88e20c74 SW	121	.flags = IRQCHIP_MASK_ON_SUSPEND \|
88e20c74 SW	122	IRQCHIP_SKIP_SET_WAKE,
289569f9 SG	123	};
289569f9 SG	124
7e4ac676 OR	125	static struct irq_chip asm9260_icoll_chip = {
	126	.irq_ack = icoll_ack_irq,
	127	.irq_mask = asm9260_mask_irq,
	128	.irq_unmask = asm9260_unmask_irq,
88e20c74 SW	129	.flags = IRQCHIP_MASK_ON_SUSPEND \|
88e20c74 SW	130	IRQCHIP_SKIP_SET_WAKE,
7e4ac676 OR	131	};
7e4ac676 OR	132
4e0a1b8c SG	133	asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
	134	{
	135	u32 irqnr;
	136
25e34b44 OR	137	irqnr = __raw_readl(icoll_priv.stat);
25e34b44 OR	138	__raw_writel(irqnr, icoll_priv.vector);
0953fb26	139	generic_handle_domain_irq(icoll_domain, irqnr);
4e0a1b8c SG	140	}
4e0a1b8c SG	141
83a84efc SG	142	static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
83a84efc SG	143	irq_hw_number_t hw)
289569f9	144	{
7e4ac676 OR	145	struct irq_chip *chip;
	146
	147	if (icoll_priv.type == ICOLL)
	148	chip = &mxs_icoll_chip;
	149	else
	150	chip = &asm9260_icoll_chip;
	151
	152	irq_set_chip_and_handler(virq, chip, handle_level_irq);
83a84efc SG	153
	154	return 0;
	155	}
289569f9	156
96009736	157	static const struct irq_domain_ops icoll_irq_domain_ops = {
83a84efc SG	158	.map = icoll_irq_domain_map,
	159	.xlate = irq_domain_xlate_onecell,
	160	};
	161
25e34b44 OR	162	static void __init icoll_add_domain(struct device_node *np,
	163	int num)
	164	{
	165	icoll_domain = irq_domain_add_linear(np, num,
	166	&icoll_irq_domain_ops, NULL);
	167
	168	if (!icoll_domain)
e81f54c6	169	panic("%pOF: unable to create irq domain", np);
25e34b44 OR	170	}
	171
	172	static void __iomem * __init icoll_init_iobase(struct device_node *np)
83a84efc	173	{
25e34b44 OR	174	void __iomem *icoll_base;
	175
	176	icoll_base = of_io_request_and_map(np, 0, np->name);
edf8fcdc	177	if (IS_ERR(icoll_base))
e81f54c6	178	panic("%pOF: unable to map resource", np);
25e34b44 OR	179	return icoll_base;
	180	}
	181
	182	static int __init icoll_of_init(struct device_node *np,
	183	struct device_node *interrupt_parent)
	184	{
	185	void __iomem *icoll_base;
	186
7e4ac676 OR	187	icoll_priv.type = ICOLL;
7e4ac676 OR	188
25e34b44 OR	189	icoll_base = icoll_init_iobase(np);
	190	icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
	191	icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
	192	icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
	193	icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
	194	icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
7e4ac676	195	icoll_priv.clear = NULL;
8256aa71	196
289569f9 SG	197	/*
	198	* Interrupt Collector reset, which initializes the priority
	199	* for each irq to level 0.
	200	*/
25e34b44	201	stmp_reset_block(icoll_priv.ctrl);
289569f9	202
25e34b44	203	icoll_add_domain(np, ICOLL_NUM_IRQS);
e59a8451 OR	204
e59a8451 OR	205	return 0;
83a84efc	206	}
6a8e95b0	207	IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
7e4ac676 OR	208
	209	static int __init asm9260_of_init(struct device_node *np,
	210	struct device_node *interrupt_parent)
	211	{
	212	void __iomem *icoll_base;
	213	int i;
	214
	215	icoll_priv.type = ASM9260_ICOLL;
	216
	217	icoll_base = icoll_init_iobase(np);
	218	icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
	219	icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
	220	icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
	221	icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
	222	icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
	223	icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
	224
	225	writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
	226	icoll_priv.ctrl);
	227	/*
	228	* ASM9260 don't provide reset bit. So, we need to set level 0
	229	* manually.
	230	*/
	231	for (i = 0; i < 16 * 0x10; i += 0x10)
	232	writel(0, icoll_priv.intr + i);
	233
	234	icoll_add_domain(np, ASM9260_NUM_IRQS);
c5b63520	235	set_handle_irq(icoll_handle_irq);
7e4ac676 OR	236
	237	return 0;
	238	}
	239	IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);