[linux-2.6-block.git] / drivers / irqchip / irq-mmp.c

/*
 *  linux/arch/arm/mach-mmp/irq.c
 *
 *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
 *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
 *
 *  Author:	Bin Yang <bin.yang@marvell.com>
 *              Haojian Zhuang <haojian.zhuang@gmail.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/exception.h>
#include <asm/hardirq.h>

#define MAX_ICU_NR		16

#define PJ1_INT_SEL		0x10c
#define PJ4_INT_SEL		0x104

/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
#define SEL_INT_PENDING		(1 << 6)
#define SEL_INT_NUM_MASK	0x3f

#define MMP2_ICU_INT_ROUTE_PJ4_IRQ	(1 << 5)
#define MMP2_ICU_INT_ROUTE_PJ4_FIQ	(1 << 6)

struct icu_chip_data {
	int			nr_irqs;
	unsigned int		virq_base;
	unsigned int		cascade_irq;
	void __iomem		*reg_status;
	void __iomem		*reg_mask;
	unsigned int		conf_enable;
	unsigned int		conf_disable;
	unsigned int		conf_mask;
	unsigned int		clr_mfp_irq_base;
	unsigned int		clr_mfp_hwirq;
	struct irq_domain	*domain;
};

struct mmp_intc_conf {
	unsigned int	conf_enable;
	unsigned int	conf_disable;
	unsigned int	conf_mask;
};

static void __iomem *mmp_icu_base;
static struct icu_chip_data icu_data[MAX_ICU_NR];
static int max_icu_nr;

extern void mmp2_clear_pmic_int(void);

static void icu_mask_ack_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
#ifdef CONFIG_CPU_MMP2
		if ((data->virq_base == data->clr_mfp_irq_base)
			&& (hwirq == data->clr_mfp_hwirq))
			mmp2_clear_pmic_int();
#endif
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_mask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_unmask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_enable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

struct irq_chip icu_irq_chip = {
	.name		= "icu_irq",
	.irq_mask	= icu_mask_irq,
	.irq_mask_ack	= icu_mask_ack_irq,
	.irq_unmask	= icu_unmask_irq,
};

static void icu_mux_irq_demux(struct irq_desc *desc)
{
	unsigned int irq = irq_desc_get_irq(desc);
	struct irq_domain *domain;
	struct icu_chip_data *data;
	int i;
	unsigned long mask, status, n;

	for (i = 1; i < max_icu_nr; i++) {
		if (irq == icu_data[i].cascade_irq) {
			domain = icu_data[i].domain;
			data = (struct icu_chip_data *)domain->host_data;
			break;
		}
	}
	if (i >= max_icu_nr) {
		pr_err("Spurious irq %d in MMP INTC\n", irq);
		return;
	}

	mask = readl_relaxed(data->reg_mask);
	while (1) {
		status = readl_relaxed(data->reg_status) & ~mask;
		if (status == 0)
			break;
		for_each_set_bit(n, &status, BITS_PER_LONG) {
			generic_handle_irq(icu_data[i].virq_base + n);
		}
	}
}

static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	return 0;
}

static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
				const u32 *intspec, unsigned int intsize,
				unsigned long *out_hwirq,
				unsigned int *out_type)
{
	*out_hwirq = intspec[0];
	return 0;
}

static const struct irq_domain_ops mmp_irq_domain_ops = {
	.map		= mmp_irq_domain_map,
	.xlate		= mmp_irq_domain_xlate,
};

static const struct mmp_intc_conf mmp_conf = {
	.conf_enable	= 0x51,
	.conf_disable	= 0x0,
	.conf_mask	= 0x7f,
};

static const struct mmp_intc_conf mmp2_conf = {
	.conf_enable	= 0x20,
	.conf_disable	= 0x0,
	.conf_mask	= MMP2_ICU_INT_ROUTE_PJ4_IRQ |
			  MMP2_ICU_INT_ROUTE_PJ4_FIQ,
};

static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
{
	int hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	handle_domain_irq(icu_data[0].domain, hwirq, regs);
}

static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
{
	int hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	handle_domain_irq(icu_data[0].domain, hwirq, regs);
}

/* MMP (ARMv5) */
void __init icu_init_irq(void)
{
	int irq;

	max_icu_nr = 1;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	for (irq = 0; irq < 64; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
}

/* MMP2 (ARMv7) */
void __init mmp2_init_icu(void)
{
	int irq, end;

	max_icu_nr = 8;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	icu_data[1].reg_status = mmp_icu_base + 0x150;
	icu_data[1].reg_mask = mmp_icu_base + 0x168;
	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
				icu_data[0].nr_irqs;
	icu_data[1].clr_mfp_hwirq = 1;		/* offset to IRQ_MMP2_PMIC_BASE */
	icu_data[1].nr_irqs = 2;
	icu_data[1].cascade_irq = 4;
	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
						   icu_data[1].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[1]);
	icu_data[2].reg_status = mmp_icu_base + 0x154;
	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	icu_data[2].nr_irqs = 2;
	icu_data[2].cascade_irq = 5;
	icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
						   icu_data[2].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[2]);
	icu_data[3].reg_status = mmp_icu_base + 0x180;
	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	icu_data[3].nr_irqs = 3;
	icu_data[3].cascade_irq = 9;
	icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
						   icu_data[3].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[3]);
	icu_data[4].reg_status = mmp_icu_base + 0x158;
	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	icu_data[4].nr_irqs = 5;
	icu_data[4].cascade_irq = 17;
	icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
						   icu_data[4].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[4]);
	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	icu_data[5].nr_irqs = 15;
	icu_data[5].cascade_irq = 35;
	icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
						   icu_data[5].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[5]);
	icu_data[6].reg_status = mmp_icu_base + 0x160;
	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	icu_data[6].nr_irqs = 2;
	icu_data[6].cascade_irq = 51;
	icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
						   icu_data[6].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[6]);
	icu_data[7].reg_status = mmp_icu_base + 0x188;
	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	icu_data[7].nr_irqs = 2;
	icu_data[7].cascade_irq = 55;
	icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
						   icu_data[7].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[7]);
	end = icu_data[7].virq_base + icu_data[7].nr_irqs;
	for (irq = 0; irq < end; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		if (irq == icu_data[1].cascade_irq ||
		    irq == icu_data[2].cascade_irq ||
		    irq == icu_data[3].cascade_irq ||
		    irq == icu_data[4].cascade_irq ||
		    irq == icu_data[5].cascade_irq ||
		    irq == icu_data[6].cascade_irq ||
		    irq == icu_data[7].cascade_irq) {
			irq_set_chip(irq, &icu_irq_chip);
			irq_set_chained_handler(irq, icu_mux_irq_demux);
		} else {
			irq_set_chip_and_handler(irq, &icu_irq_chip,
						 handle_level_irq);
		}
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
}

#ifdef CONFIG_OF
static int __init mmp_init_bases(struct device_node *node)
{
	int ret, nr_irqs, irq, i = 0;

	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return ret;
	}

	mmp_icu_base = of_iomap(node, 0);
	if (!mmp_icu_base) {
		pr_err("Failed to get interrupt controller register\n");
		return -ENOMEM;
	}

	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[0]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[0].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[0].virq_base = ret;
	}
	icu_data[0].nr_irqs = nr_irqs;
	return 0;
err:
	if (icu_data[0].virq_base) {
		for (i = 0; i < irq; i++)
			irq_dispose_mapping(icu_data[0].virq_base + i);
	}
	irq_domain_remove(icu_data[0].domain);
	iounmap(mmp_icu_base);
	return -EINVAL;
}

static int __init mmp_of_init(struct device_node *node,
			      struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);

static int __init mmp2_of_init(struct device_node *node,
			       struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);

static int __init mmp2_mux_of_init(struct device_node *node,
				   struct device_node *parent)
{
	struct resource res;
	int i, ret, irq, j = 0;
	u32 nr_irqs, mfp_irq;

	if (!parent)
		return -ENODEV;

	i = max_icu_nr;
	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
				   &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return -EINVAL;
	}
	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_status = mmp_icu_base + res.start;
	ret = of_address_to_resource(node, 1, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_mask = mmp_icu_base + res.start;
	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	if (!icu_data[i].cascade_irq)
		return -EINVAL;

	icu_data[i].virq_base = 0;
	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[i]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[i].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[i].virq_base = ret;
	}
	icu_data[i].nr_irqs = nr_irqs;
	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
				  &mfp_irq)) {
		icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
		icu_data[i].clr_mfp_hwirq = mfp_irq;
	}
	irq_set_chained_handler(icu_data[i].cascade_irq,
				icu_mux_irq_demux);
	max_icu_nr++;
	return 0;
err:
	if (icu_data[i].virq_base) {
		for (j = 0; j < irq; j++)
			irq_dispose_mapping(icu_data[i].virq_base + j);
	}
	irq_domain_remove(icu_data[i].domain);
	return -EINVAL;
}
IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
#endif
Commit	Line	Data
c24b3114 HZ	1	/*
	2	* linux/arch/arm/mach-mmp/irq.c
	3	*
	4	* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
	5	* Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
	6	*
	7	* Author: Bin Yang <bin.yang@marvell.com>
	8	* Haojian Zhuang <haojian.zhuang@gmail.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/init.h>
	17	#include <linux/irq.h>
41a83e06	18	#include <linux/irqchip.h>
c24b3114 HZ	19	#include <linux/irqdomain.h>
	20	#include <linux/io.h>
	21	#include <linux/ioport.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24
0f374561	25	#include <asm/exception.h>
13dde818	26	#include <asm/hardirq.h>
0f374561	27
c24b3114 HZ	28	#define MAX_ICU_NR 16
c24b3114 HZ	29
0f374561 HZ	30	#define PJ1_INT_SEL 0x10c
	31	#define PJ4_INT_SEL 0x104
	32
	33	/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
	34	#define SEL_INT_PENDING (1 << 6)
	35	#define SEL_INT_NUM_MASK 0x3f
	36
2380a22b LR	37	#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
	38	#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
	39
c24b3114 HZ	40	struct icu_chip_data {
	41	int nr_irqs;
	42	unsigned int virq_base;
	43	unsigned int cascade_irq;
	44	void __iomem *reg_status;
	45	void __iomem *reg_mask;
	46	unsigned int conf_enable;
	47	unsigned int conf_disable;
	48	unsigned int conf_mask;
	49	unsigned int clr_mfp_irq_base;
	50	unsigned int clr_mfp_hwirq;
	51	struct irq_domain *domain;
	52	};
	53
	54	struct mmp_intc_conf {
	55	unsigned int conf_enable;
	56	unsigned int conf_disable;
	57	unsigned int conf_mask;
	58	};
	59
0f374561	60	static void __iomem *mmp_icu_base;
c24b3114 HZ	61	static struct icu_chip_data icu_data[MAX_ICU_NR];
	62	static int max_icu_nr;
	63
	64	extern void mmp2_clear_pmic_int(void);
	65
	66	static void icu_mask_ack_irq(struct irq_data *d)
	67	{
	68	struct irq_domain *domain = d->domain;
	69	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	70	int hwirq;
	71	u32 r;
	72
	73	hwirq = d->irq - data->virq_base;
	74	if (data == &icu_data[0]) {
	75	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	76	r &= ~data->conf_mask;
	77	r \|= data->conf_disable;
	78	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	79	} else {
	80	#ifdef CONFIG_CPU_MMP2
	81	if ((data->virq_base == data->clr_mfp_irq_base)
	82	&& (hwirq == data->clr_mfp_hwirq))
	83	mmp2_clear_pmic_int();
	84	#endif
	85	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	86	writel_relaxed(r, data->reg_mask);
	87	}
	88	}
	89
	90	static void icu_mask_irq(struct irq_data *d)
	91	{
	92	struct irq_domain *domain = d->domain;
	93	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	94	int hwirq;
	95	u32 r;
	96
	97	hwirq = d->irq - data->virq_base;
	98	if (data == &icu_data[0]) {
	99	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	100	r &= ~data->conf_mask;
	101	r \|= data->conf_disable;
	102	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	103	} else {
	104	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	105	writel_relaxed(r, data->reg_mask);
	106	}
	107	}
	108
	109	static void icu_unmask_irq(struct irq_data *d)
	110	{
	111	struct irq_domain *domain = d->domain;
	112	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	113	int hwirq;
	114	u32 r;
	115
	116	hwirq = d->irq - data->virq_base;
	117	if (data == &icu_data[0]) {
	118	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	119	r &= ~data->conf_mask;
	120	r \|= data->conf_enable;
	121	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	122	} else {
	123	r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
	124	writel_relaxed(r, data->reg_mask);
125	}
126	}
127
0f102b6c	128	struct irq_chip icu_irq_chip = {
c24b3114 HZ	129	.name = "icu_irq",
	130	.irq_mask = icu_mask_irq,
	131	.irq_mask_ack = icu_mask_ack_irq,
	132	.irq_unmask = icu_unmask_irq,
	133	};
	134
bd0b9ac4	135	static void icu_mux_irq_demux(struct irq_desc *desc)
c24b3114	136	{
14873aa1	137	unsigned int irq = irq_desc_get_irq(desc);
c24b3114 HZ	138	struct irq_domain *domain;
	139	struct icu_chip_data *data;
	140	int i;
	141	unsigned long mask, status, n;
	142
	143	for (i = 1; i < max_icu_nr; i++) {
	144	if (irq == icu_data[i].cascade_irq) {
	145	domain = icu_data[i].domain;
	146	data = (struct icu_chip_data *)domain->host_data;
	147	break;
	148	}
	149	}
	150	if (i >= max_icu_nr) {
	151	pr_err("Spurious irq %d in MMP INTC\n", irq);
	152	return;
	153	}
	154
	155	mask = readl_relaxed(data->reg_mask);
	156	while (1) {
	157	status = readl_relaxed(data->reg_status) & ~mask;
	158	if (status == 0)
	159	break;
93d429a7	160	for_each_set_bit(n, &status, BITS_PER_LONG) {
c24b3114	161	generic_handle_irq(icu_data[i].virq_base + n);
c24b3114 HZ	162	}
	163	}
	164	}
	165
	166	static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
	167	irq_hw_number_t hw)
	168	{
	169	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
c24b3114 HZ	170	return 0;
	171	}
	172
	173	static int mmp_irq_domain_xlate(struct irq_domain d, struct device_node node,
	174	const u32 *intspec, unsigned int intsize,
	175	unsigned long *out_hwirq,
	176	unsigned int *out_type)
	177	{
	178	*out_hwirq = intspec[0];
	179	return 0;
	180	}
	181
096048cb	182	static const struct irq_domain_ops mmp_irq_domain_ops = {
c24b3114 HZ	183	.map = mmp_irq_domain_map,
	184	.xlate = mmp_irq_domain_xlate,
	185	};
	186
c8c7d93d	187	static const struct mmp_intc_conf mmp_conf = {
c24b3114 HZ	188	.conf_enable = 0x51,
	189	.conf_disable = 0x0,
	190	.conf_mask = 0x7f,
	191	};
	192
c8c7d93d	193	static const struct mmp_intc_conf mmp2_conf = {
c24b3114 HZ	194	.conf_enable = 0x20,
c24b3114 HZ	195	.conf_disable = 0x0,
2380a22b LR	196	.conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ \|
2380a22b LR	197	MMP2_ICU_INT_ROUTE_PJ4_FIQ,
c24b3114 HZ	198	};
c24b3114 HZ	199
8783dd3a	200	static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
0f374561	201	{
b918402c	202	int hwirq;
0f374561 HZ	203
	204	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	205	if (!(hwirq & SEL_INT_PENDING))
	206	return;
	207	hwirq &= SEL_INT_NUM_MASK;
b918402c	208	handle_domain_irq(icu_data[0].domain, hwirq, regs);
0f374561 HZ	209	}
0f374561 HZ	210
8783dd3a	211	static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
0f374561	212	{
b918402c	213	int hwirq;
0f374561 HZ	214
	215	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	216	if (!(hwirq & SEL_INT_PENDING))
	217	return;
	218	hwirq &= SEL_INT_NUM_MASK;
b918402c	219	handle_domain_irq(icu_data[0].domain, hwirq, regs);
0f374561 HZ	220	}
0f374561 HZ	221
c24b3114 HZ	222	/* MMP (ARMv5) */
	223	void __init icu_init_irq(void)
	224	{
	225	int irq;
	226
	227	max_icu_nr = 1;
	228	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	229	icu_data[0].conf_enable = mmp_conf.conf_enable;
	230	icu_data[0].conf_disable = mmp_conf.conf_disable;
	231	icu_data[0].conf_mask = mmp_conf.conf_mask;
	232	icu_data[0].nr_irqs = 64;
	233	icu_data[0].virq_base = 0;
	234	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	235	&irq_domain_simple_ops,
	236	&icu_data[0]);
	237	for (irq = 0; irq < 64; irq++) {
	238	icu_mask_irq(irq_get_irq_data(irq));
	239	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
c24b3114 HZ	240	}
c24b3114 HZ	241	irq_set_default_host(icu_data[0].domain);
0f374561	242	set_handle_irq(mmp_handle_irq);
c24b3114 HZ	243	}
	244
	245	/* MMP2 (ARMv7) */
	246	void __init mmp2_init_icu(void)
	247	{
942f4221	248	int irq, end;
c24b3114 HZ	249
	250	max_icu_nr = 8;
	251	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	252	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	253	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	254	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	255	icu_data[0].nr_irqs = 64;
	256	icu_data[0].virq_base = 0;
	257	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	258	&irq_domain_simple_ops,
	259	&icu_data[0]);
	260	icu_data[1].reg_status = mmp_icu_base + 0x150;
	261	icu_data[1].reg_mask = mmp_icu_base + 0x168;
942f4221 HZ	262	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
	263	icu_data[0].nr_irqs;
	264	icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
c24b3114	265	icu_data[1].nr_irqs = 2;
10bd21c0	266	icu_data[1].cascade_irq = 4;
942f4221	267	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
c24b3114 HZ	268	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
	269	icu_data[1].virq_base, 0,
	270	&irq_domain_simple_ops,
	271	&icu_data[1]);
	272	icu_data[2].reg_status = mmp_icu_base + 0x154;
	273	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	274	icu_data[2].nr_irqs = 2;
10bd21c0	275	icu_data[2].cascade_irq = 5;
942f4221	276	icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
c24b3114 HZ	277	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
	278	icu_data[2].virq_base, 0,
	279	&irq_domain_simple_ops,
	280	&icu_data[2]);
	281	icu_data[3].reg_status = mmp_icu_base + 0x180;
	282	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	283	icu_data[3].nr_irqs = 3;
10bd21c0	284	icu_data[3].cascade_irq = 9;
942f4221	285	icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
c24b3114 HZ	286	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
	287	icu_data[3].virq_base, 0,
	288	&irq_domain_simple_ops,
	289	&icu_data[3]);
	290	icu_data[4].reg_status = mmp_icu_base + 0x158;
	291	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	292	icu_data[4].nr_irqs = 5;
10bd21c0	293	icu_data[4].cascade_irq = 17;
942f4221	294	icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
c24b3114 HZ	295	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
	296	icu_data[4].virq_base, 0,
	297	&irq_domain_simple_ops,
	298	&icu_data[4]);
	299	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	300	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	301	icu_data[5].nr_irqs = 15;
10bd21c0	302	icu_data[5].cascade_irq = 35;
942f4221	303	icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
c24b3114 HZ	304	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
	305	icu_data[5].virq_base, 0,
	306	&irq_domain_simple_ops,
	307	&icu_data[5]);
	308	icu_data[6].reg_status = mmp_icu_base + 0x160;
	309	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	310	icu_data[6].nr_irqs = 2;
10bd21c0	311	icu_data[6].cascade_irq = 51;
942f4221	312	icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
c24b3114 HZ	313	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
	314	icu_data[6].virq_base, 0,
	315	&irq_domain_simple_ops,
	316	&icu_data[6]);
	317	icu_data[7].reg_status = mmp_icu_base + 0x188;
	318	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	319	icu_data[7].nr_irqs = 2;
10bd21c0	320	icu_data[7].cascade_irq = 55;
942f4221	321	icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
c24b3114 HZ	322	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
	323	icu_data[7].virq_base, 0,
	324	&irq_domain_simple_ops,
	325	&icu_data[7]);
942f4221 HZ	326	end = icu_data[7].virq_base + icu_data[7].nr_irqs;
942f4221 HZ	327	for (irq = 0; irq < end; irq++) {
c24b3114	328	icu_mask_irq(irq_get_irq_data(irq));
942f4221 HZ	329	if (irq == icu_data[1].cascade_irq \|\|
	330	irq == icu_data[2].cascade_irq \|\|
	331	irq == icu_data[3].cascade_irq \|\|
	332	irq == icu_data[4].cascade_irq \|\|
	333	irq == icu_data[5].cascade_irq \|\|
	334	irq == icu_data[6].cascade_irq \|\|
	335	irq == icu_data[7].cascade_irq) {
c24b3114 HZ	336	irq_set_chip(irq, &icu_irq_chip);
c24b3114 HZ	337	irq_set_chained_handler(irq, icu_mux_irq_demux);
942f4221	338	} else {
c24b3114 HZ	339	irq_set_chip_and_handler(irq, &icu_irq_chip,
c24b3114 HZ	340	handle_level_irq);
c24b3114	341	}
c24b3114 HZ	342	}
c24b3114 HZ	343	irq_set_default_host(icu_data[0].domain);
0f374561	344	set_handle_irq(mmp2_handle_irq);
c24b3114 HZ	345	}
	346
	347	#ifdef CONFIG_OF
0f374561	348	static int __init mmp_init_bases(struct device_node *node)
c24b3114	349	{
0f374561	350	int ret, nr_irqs, irq, i = 0;
c24b3114	351
0f374561 HZ	352	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	353	if (ret) {
	354	pr_err("Not found mrvl,intc-nr-irqs property\n");
	355	return ret;
	356	}
c24b3114	357
0f374561 HZ	358	mmp_icu_base = of_iomap(node, 0);
	359	if (!mmp_icu_base) {
	360	pr_err("Failed to get interrupt controller register\n");
	361	return -ENOMEM;
	362	}
	363
	364	icu_data[0].virq_base = 0;
	365	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
	366	&mmp_irq_domain_ops,
	367	&icu_data[0]);
	368	for (irq = 0; irq < nr_irqs; irq++) {
	369	ret = irq_create_mapping(icu_data[0].domain, irq);
	370	if (!ret) {
	371	pr_err("Failed to mapping hwirq\n");
c24b3114 HZ	372	goto err;
c24b3114 HZ	373	}
0f374561 HZ	374	if (!irq)
0f374561 HZ	375	icu_data[0].virq_base = ret;
c24b3114	376	}
0f374561	377	icu_data[0].nr_irqs = nr_irqs;
c24b3114 HZ	378	return 0;
c24b3114 HZ	379	err:
0f374561 HZ	380	if (icu_data[0].virq_base) {
	381	for (i = 0; i < irq; i++)
	382	irq_dispose_mapping(icu_data[0].virq_base + i);
	383	}
	384	irq_domain_remove(icu_data[0].domain);
	385	iounmap(mmp_icu_base);
	386	return -EINVAL;
c24b3114 HZ	387	}
c24b3114 HZ	388
0f374561 HZ	389	static int __init mmp_of_init(struct device_node *node,
0f374561 HZ	390	struct device_node *parent)
c24b3114	391	{
0f374561	392	int ret;
c24b3114	393
0f374561 HZ	394	ret = mmp_init_bases(node);
	395	if (ret < 0)
	396	return ret;
	397
	398	icu_data[0].conf_enable = mmp_conf.conf_enable;
	399	icu_data[0].conf_disable = mmp_conf.conf_disable;
	400	icu_data[0].conf_mask = mmp_conf.conf_mask;
	401	irq_set_default_host(icu_data[0].domain);
	402	set_handle_irq(mmp_handle_irq);
	403	max_icu_nr = 1;
	404	return 0;
	405	}
	406	IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
	407
	408	static int __init mmp2_of_init(struct device_node *node,
	409	struct device_node *parent)
	410	{
	411	int ret;
	412
	413	ret = mmp_init_bases(node);
	414	if (ret < 0)
	415	return ret;
	416
	417	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	418	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	419	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	420	irq_set_default_host(icu_data[0].domain);
	421	set_handle_irq(mmp2_handle_irq);
	422	max_icu_nr = 1;
	423	return 0;
	424	}
	425	IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
	426
	427	static int __init mmp2_mux_of_init(struct device_node *node,
	428	struct device_node *parent)
	429	{
	430	struct resource res;
	431	int i, ret, irq, j = 0;
	432	u32 nr_irqs, mfp_irq;
	433
	434	if (!parent)
	435	return -ENODEV;
	436
	437	i = max_icu_nr;
	438	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
	439	&nr_irqs);
c24b3114 HZ	440	if (ret) {
c24b3114 HZ	441	pr_err("Not found mrvl,intc-nr-irqs property\n");
0f374561	442	return -EINVAL;
c24b3114	443	}
0f374561 HZ	444	ret = of_address_to_resource(node, 0, &res);
	445	if (ret < 0) {
	446	pr_err("Not found reg property\n");
	447	return -EINVAL;
c24b3114	448	}
0f374561 HZ	449	icu_data[i].reg_status = mmp_icu_base + res.start;
	450	ret = of_address_to_resource(node, 1, &res);
	451	if (ret < 0) {
	452	pr_err("Not found reg property\n");
	453	return -EINVAL;
c24b3114	454	}
0f374561 HZ	455	icu_data[i].reg_mask = mmp_icu_base + res.start;
	456	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	457	if (!icu_data[i].cascade_irq)
	458	return -EINVAL;
	459
	460	icu_data[i].virq_base = 0;
	461	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
c24b3114	462	&mmp_irq_domain_ops,
0f374561 HZ	463	&icu_data[i]);
	464	for (irq = 0; irq < nr_irqs; irq++) {
	465	ret = irq_create_mapping(icu_data[i].domain, irq);
	466	if (!ret) {
	467	pr_err("Failed to mapping hwirq\n");
	468	goto err;
	469	}
	470	if (!irq)
	471	icu_data[i].virq_base = ret;
	472	}
	473	icu_data[i].nr_irqs = nr_irqs;
	474	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
	475	&mfp_irq)) {
	476	icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
	477	icu_data[i].clr_mfp_hwirq = mfp_irq;
	478	}
	479	irq_set_chained_handler(icu_data[i].cascade_irq,
	480	icu_mux_irq_demux);
	481	max_icu_nr++;
	482	return 0;
c24b3114	483	err:
0f374561 HZ	484	if (icu_data[i].virq_base) {
	485	for (j = 0; j < irq; j++)
	486	irq_dispose_mapping(icu_data[i].virq_base + j);
	487	}
	488	irq_domain_remove(icu_data[i].domain);
	489	return -EINVAL;
c24b3114	490	}
0f374561	491	IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
c24b3114	492	#endif