[linux-2.6-block.git] / drivers / irqchip / irq-mmp.c

/*
 *  linux/arch/arm/mach-mmp/irq.c
 *
 *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
 *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
 *
 *  Author:	Bin Yang <bin.yang@marvell.com>
 *              Haojian Zhuang <haojian.zhuang@gmail.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/exception.h>
#include <asm/hardirq.h>

#include "irqchip.h"

#define MAX_ICU_NR		16

#define PJ1_INT_SEL		0x10c
#define PJ4_INT_SEL		0x104

/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
#define SEL_INT_PENDING		(1 << 6)
#define SEL_INT_NUM_MASK	0x3f

struct icu_chip_data {
	int			nr_irqs;
	unsigned int		virq_base;
	unsigned int		cascade_irq;
	void __iomem		*reg_status;
	void __iomem		*reg_mask;
	unsigned int		conf_enable;
	unsigned int		conf_disable;
	unsigned int		conf_mask;
	unsigned int		clr_mfp_irq_base;
	unsigned int		clr_mfp_hwirq;
	struct irq_domain	*domain;
};

struct mmp_intc_conf {
	unsigned int	conf_enable;
	unsigned int	conf_disable;
	unsigned int	conf_mask;
};

static void __iomem *mmp_icu_base;
static struct icu_chip_data icu_data[MAX_ICU_NR];
static int max_icu_nr;

extern void mmp2_clear_pmic_int(void);

static void icu_mask_ack_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
#ifdef CONFIG_CPU_MMP2
		if ((data->virq_base == data->clr_mfp_irq_base)
			&& (hwirq == data->clr_mfp_hwirq))
			mmp2_clear_pmic_int();
#endif
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_mask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_disable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) | (1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

static void icu_unmask_irq(struct irq_data *d)
{
	struct irq_domain *domain = d->domain;
	struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
	int hwirq;
	u32 r;

	hwirq = d->irq - data->virq_base;
	if (data == &icu_data[0]) {
		r = readl_relaxed(mmp_icu_base + (hwirq << 2));
		r &= ~data->conf_mask;
		r |= data->conf_enable;
		writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	} else {
		r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
		writel_relaxed(r, data->reg_mask);
	}
}

struct irq_chip icu_irq_chip = {
	.name		= "icu_irq",
	.irq_mask	= icu_mask_irq,
	.irq_mask_ack	= icu_mask_ack_irq,
	.irq_unmask	= icu_unmask_irq,
};

static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct irq_domain *domain;
	struct icu_chip_data *data;
	int i;
	unsigned long mask, status, n;

	for (i = 1; i < max_icu_nr; i++) {
		if (irq == icu_data[i].cascade_irq) {
			domain = icu_data[i].domain;
			data = (struct icu_chip_data *)domain->host_data;
			break;
		}
	}
	if (i >= max_icu_nr) {
		pr_err("Spurious irq %d in MMP INTC\n", irq);
		return;
	}

	mask = readl_relaxed(data->reg_mask);
	while (1) {
		status = readl_relaxed(data->reg_status) & ~mask;
		if (status == 0)
			break;
		for_each_set_bit(n, &status, BITS_PER_LONG) {
			generic_handle_irq(icu_data[i].virq_base + n);
		}
	}
}

static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	set_irq_flags(irq, IRQF_VALID);
	return 0;
}

static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
				const u32 *intspec, unsigned int intsize,
				unsigned long *out_hwirq,
				unsigned int *out_type)
{
	*out_hwirq = intspec[0];
	return 0;
}

const struct irq_domain_ops mmp_irq_domain_ops = {
	.map		= mmp_irq_domain_map,
	.xlate		= mmp_irq_domain_xlate,
};

static struct mmp_intc_conf mmp_conf = {
	.conf_enable	= 0x51,
	.conf_disable	= 0x0,
	.conf_mask	= 0x7f,
};

static struct mmp_intc_conf mmp2_conf = {
	.conf_enable	= 0x20,
	.conf_disable	= 0x0,
	.conf_mask	= 0x7f,
};

static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
{
	int irq, hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	handle_IRQ(irq, regs);
}

static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
{
	int irq, hwirq;

	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	if (!(hwirq & SEL_INT_PENDING))
		return;
	hwirq &= SEL_INT_NUM_MASK;
	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	handle_IRQ(irq, regs);
}

/* MMP (ARMv5) */
void __init icu_init_irq(void)
{
	int irq;

	max_icu_nr = 1;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	for (irq = 0; irq < 64; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
}

/* MMP2 (ARMv7) */
void __init mmp2_init_icu(void)
{
	int irq, end;

	max_icu_nr = 8;
	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	icu_data[0].nr_irqs = 64;
	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
						   &irq_domain_simple_ops,
						   &icu_data[0]);
	icu_data[1].reg_status = mmp_icu_base + 0x150;
	icu_data[1].reg_mask = mmp_icu_base + 0x168;
	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
				icu_data[0].nr_irqs;
	icu_data[1].clr_mfp_hwirq = 1;		/* offset to IRQ_MMP2_PMIC_BASE */
	icu_data[1].nr_irqs = 2;
	icu_data[1].cascade_irq = 4;
	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
						   icu_data[1].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[1]);
	icu_data[2].reg_status = mmp_icu_base + 0x154;
	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	icu_data[2].nr_irqs = 2;
	icu_data[2].cascade_irq = 5;
	icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
						   icu_data[2].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[2]);
	icu_data[3].reg_status = mmp_icu_base + 0x180;
	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	icu_data[3].nr_irqs = 3;
	icu_data[3].cascade_irq = 9;
	icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
						   icu_data[3].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[3]);
	icu_data[4].reg_status = mmp_icu_base + 0x158;
	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	icu_data[4].nr_irqs = 5;
	icu_data[4].cascade_irq = 17;
	icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
						   icu_data[4].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[4]);
	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	icu_data[5].nr_irqs = 15;
	icu_data[5].cascade_irq = 35;
	icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
						   icu_data[5].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[5]);
	icu_data[6].reg_status = mmp_icu_base + 0x160;
	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	icu_data[6].nr_irqs = 2;
	icu_data[6].cascade_irq = 51;
	icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
						   icu_data[6].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[6]);
	icu_data[7].reg_status = mmp_icu_base + 0x188;
	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	icu_data[7].nr_irqs = 2;
	icu_data[7].cascade_irq = 55;
	icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
						   icu_data[7].virq_base, 0,
						   &irq_domain_simple_ops,
						   &icu_data[7]);
	end = icu_data[7].virq_base + icu_data[7].nr_irqs;
	for (irq = 0; irq < end; irq++) {
		icu_mask_irq(irq_get_irq_data(irq));
		if (irq == icu_data[1].cascade_irq ||
		    irq == icu_data[2].cascade_irq ||
		    irq == icu_data[3].cascade_irq ||
		    irq == icu_data[4].cascade_irq ||
		    irq == icu_data[5].cascade_irq ||
		    irq == icu_data[6].cascade_irq ||
		    irq == icu_data[7].cascade_irq) {
			irq_set_chip(irq, &icu_irq_chip);
			irq_set_chained_handler(irq, icu_mux_irq_demux);
		} else {
			irq_set_chip_and_handler(irq, &icu_irq_chip,
						 handle_level_irq);
		}
		set_irq_flags(irq, IRQF_VALID);
	}
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
}

#ifdef CONFIG_OF
static int __init mmp_init_bases(struct device_node *node)
{
	int ret, nr_irqs, irq, i = 0;

	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return ret;
	}

	mmp_icu_base = of_iomap(node, 0);
	if (!mmp_icu_base) {
		pr_err("Failed to get interrupt controller register\n");
		return -ENOMEM;
	}

	icu_data[0].virq_base = 0;
	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[0]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[0].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[0].virq_base = ret;
	}
	icu_data[0].nr_irqs = nr_irqs;
	return 0;
err:
	if (icu_data[0].virq_base) {
		for (i = 0; i < irq; i++)
			irq_dispose_mapping(icu_data[0].virq_base + i);
	}
	irq_domain_remove(icu_data[0].domain);
	iounmap(mmp_icu_base);
	return -EINVAL;
}

static int __init mmp_of_init(struct device_node *node,
			      struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp_conf.conf_enable;
	icu_data[0].conf_disable = mmp_conf.conf_disable;
	icu_data[0].conf_mask = mmp_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);

static int __init mmp2_of_init(struct device_node *node,
			       struct device_node *parent)
{
	int ret;

	ret = mmp_init_bases(node);
	if (ret < 0)
		return ret;

	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	irq_set_default_host(icu_data[0].domain);
	set_handle_irq(mmp2_handle_irq);
	max_icu_nr = 1;
	return 0;
}
IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);

static int __init mmp2_mux_of_init(struct device_node *node,
				   struct device_node *parent)
{
	struct resource res;
	int i, ret, irq, j = 0;
	u32 nr_irqs, mfp_irq;

	if (!parent)
		return -ENODEV;

	i = max_icu_nr;
	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
				   &nr_irqs);
	if (ret) {
		pr_err("Not found mrvl,intc-nr-irqs property\n");
		return -EINVAL;
	}
	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_status = mmp_icu_base + res.start;
	ret = of_address_to_resource(node, 1, &res);
	if (ret < 0) {
		pr_err("Not found reg property\n");
		return -EINVAL;
	}
	icu_data[i].reg_mask = mmp_icu_base + res.start;
	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	if (!icu_data[i].cascade_irq)
		return -EINVAL;

	icu_data[i].virq_base = 0;
	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
						   &mmp_irq_domain_ops,
						   &icu_data[i]);
	for (irq = 0; irq < nr_irqs; irq++) {
		ret = irq_create_mapping(icu_data[i].domain, irq);
		if (!ret) {
			pr_err("Failed to mapping hwirq\n");
			goto err;
		}
		if (!irq)
			icu_data[i].virq_base = ret;
	}
	icu_data[i].nr_irqs = nr_irqs;
	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
				  &mfp_irq)) {
		icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
		icu_data[i].clr_mfp_hwirq = mfp_irq;
	}
	irq_set_chained_handler(icu_data[i].cascade_irq,
				icu_mux_irq_demux);
	max_icu_nr++;
	return 0;
err:
	if (icu_data[i].virq_base) {
		for (j = 0; j < irq; j++)
			irq_dispose_mapping(icu_data[i].virq_base + j);
	}
	irq_domain_remove(icu_data[i].domain);
	return -EINVAL;
}
IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
#endif
Commit	Line	Data
c24b3114 HZ	1	/*
	2	* linux/arch/arm/mach-mmp/irq.c
	3	*
	4	* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
	5	* Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
	6	*
	7	* Author: Bin Yang <bin.yang@marvell.com>
	8	* Haojian Zhuang <haojian.zhuang@gmail.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/init.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqdomain.h>
	19	#include <linux/io.h>
	20	#include <linux/ioport.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23
0f374561	24	#include <asm/exception.h>
13dde818	25	#include <asm/hardirq.h>
0f374561	26
0f374561 HZ	27	#include "irqchip.h"
0f374561 HZ	28
c24b3114 HZ	29	#define MAX_ICU_NR 16
c24b3114 HZ	30
0f374561 HZ	31	#define PJ1_INT_SEL 0x10c
	32	#define PJ4_INT_SEL 0x104
	33
	34	/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
	35	#define SEL_INT_PENDING (1 << 6)
	36	#define SEL_INT_NUM_MASK 0x3f
	37
c24b3114 HZ	38	struct icu_chip_data {
	39	int nr_irqs;
	40	unsigned int virq_base;
	41	unsigned int cascade_irq;
	42	void __iomem *reg_status;
	43	void __iomem *reg_mask;
	44	unsigned int conf_enable;
	45	unsigned int conf_disable;
	46	unsigned int conf_mask;
	47	unsigned int clr_mfp_irq_base;
	48	unsigned int clr_mfp_hwirq;
	49	struct irq_domain *domain;
	50	};
	51
	52	struct mmp_intc_conf {
	53	unsigned int conf_enable;
	54	unsigned int conf_disable;
	55	unsigned int conf_mask;
	56	};
	57
0f374561	58	static void __iomem *mmp_icu_base;
c24b3114 HZ	59	static struct icu_chip_data icu_data[MAX_ICU_NR];
	60	static int max_icu_nr;
	61
	62	extern void mmp2_clear_pmic_int(void);
	63
	64	static void icu_mask_ack_irq(struct irq_data *d)
	65	{
	66	struct irq_domain *domain = d->domain;
	67	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	68	int hwirq;
	69	u32 r;
	70
	71	hwirq = d->irq - data->virq_base;
	72	if (data == &icu_data[0]) {
	73	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	74	r &= ~data->conf_mask;
	75	r \|= data->conf_disable;
	76	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	77	} else {
	78	#ifdef CONFIG_CPU_MMP2
	79	if ((data->virq_base == data->clr_mfp_irq_base)
	80	&& (hwirq == data->clr_mfp_hwirq))
	81	mmp2_clear_pmic_int();
	82	#endif
	83	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	84	writel_relaxed(r, data->reg_mask);
	85	}
	86	}
	87
	88	static void icu_mask_irq(struct irq_data *d)
	89	{
	90	struct irq_domain *domain = d->domain;
	91	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	92	int hwirq;
	93	u32 r;
	94
	95	hwirq = d->irq - data->virq_base;
	96	if (data == &icu_data[0]) {
	97	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	98	r &= ~data->conf_mask;
	99	r \|= data->conf_disable;
	100	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	101	} else {
	102	r = readl_relaxed(data->reg_mask) \| (1 << hwirq);
	103	writel_relaxed(r, data->reg_mask);
	104	}
	105	}
	106
	107	static void icu_unmask_irq(struct irq_data *d)
	108	{
	109	struct irq_domain *domain = d->domain;
	110	struct icu_chip_data data = (struct icu_chip_data )domain->host_data;
	111	int hwirq;
	112	u32 r;
	113
	114	hwirq = d->irq - data->virq_base;
	115	if (data == &icu_data[0]) {
	116	r = readl_relaxed(mmp_icu_base + (hwirq << 2));
	117	r &= ~data->conf_mask;
	118	r \|= data->conf_enable;
	119	writel_relaxed(r, mmp_icu_base + (hwirq << 2));
	120	} else {
	121	r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
	122	writel_relaxed(r, data->reg_mask);
123	}
124	}
125
0f102b6c	126	struct irq_chip icu_irq_chip = {
c24b3114 HZ	127	.name = "icu_irq",
	128	.irq_mask = icu_mask_irq,
	129	.irq_mask_ack = icu_mask_ack_irq,
	130	.irq_unmask = icu_unmask_irq,
	131	};
	132
	133	static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
	134	{
	135	struct irq_domain *domain;
	136	struct icu_chip_data *data;
	137	int i;
	138	unsigned long mask, status, n;
	139
	140	for (i = 1; i < max_icu_nr; i++) {
	141	if (irq == icu_data[i].cascade_irq) {
	142	domain = icu_data[i].domain;
	143	data = (struct icu_chip_data *)domain->host_data;
	144	break;
	145	}
	146	}
	147	if (i >= max_icu_nr) {
	148	pr_err("Spurious irq %d in MMP INTC\n", irq);
	149	return;
	150	}
	151
	152	mask = readl_relaxed(data->reg_mask);
	153	while (1) {
	154	status = readl_relaxed(data->reg_status) & ~mask;
	155	if (status == 0)
	156	break;
93d429a7	157	for_each_set_bit(n, &status, BITS_PER_LONG) {
c24b3114	158	generic_handle_irq(icu_data[i].virq_base + n);
c24b3114 HZ	159	}
	160	}
	161	}
	162
	163	static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
	164	irq_hw_number_t hw)
	165	{
	166	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	167	set_irq_flags(irq, IRQF_VALID);
	168	return 0;
	169	}
	170
	171	static int mmp_irq_domain_xlate(struct irq_domain d, struct device_node node,
	172	const u32 *intspec, unsigned int intsize,
	173	unsigned long *out_hwirq,
	174	unsigned int *out_type)
	175	{
	176	*out_hwirq = intspec[0];
	177	return 0;
	178	}
	179
	180	const struct irq_domain_ops mmp_irq_domain_ops = {
	181	.map = mmp_irq_domain_map,
	182	.xlate = mmp_irq_domain_xlate,
	183	};
	184
	185	static struct mmp_intc_conf mmp_conf = {
	186	.conf_enable = 0x51,
	187	.conf_disable = 0x0,
	188	.conf_mask = 0x7f,
	189	};
	190
	191	static struct mmp_intc_conf mmp2_conf = {
	192	.conf_enable = 0x20,
	193	.conf_disable = 0x0,
	194	.conf_mask = 0x7f,
	195	};
	196
8783dd3a	197	static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
0f374561 HZ	198	{
	199	int irq, hwirq;
	200
	201	hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
	202	if (!(hwirq & SEL_INT_PENDING))
	203	return;
	204	hwirq &= SEL_INT_NUM_MASK;
	205	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	206	handle_IRQ(irq, regs);
	207	}
	208
8783dd3a	209	static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
0f374561 HZ	210	{
	211	int irq, hwirq;
	212
	213	hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
	214	if (!(hwirq & SEL_INT_PENDING))
	215	return;
	216	hwirq &= SEL_INT_NUM_MASK;
	217	irq = irq_find_mapping(icu_data[0].domain, hwirq);
	218	handle_IRQ(irq, regs);
	219	}
	220
c24b3114 HZ	221	/* MMP (ARMv5) */
	222	void __init icu_init_irq(void)
	223	{
	224	int irq;
	225
	226	max_icu_nr = 1;
	227	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	228	icu_data[0].conf_enable = mmp_conf.conf_enable;
	229	icu_data[0].conf_disable = mmp_conf.conf_disable;
	230	icu_data[0].conf_mask = mmp_conf.conf_mask;
	231	icu_data[0].nr_irqs = 64;
	232	icu_data[0].virq_base = 0;
	233	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	234	&irq_domain_simple_ops,
	235	&icu_data[0]);
	236	for (irq = 0; irq < 64; irq++) {
	237	icu_mask_irq(irq_get_irq_data(irq));
	238	irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
	239	set_irq_flags(irq, IRQF_VALID);
	240	}
	241	irq_set_default_host(icu_data[0].domain);
0f374561	242	set_handle_irq(mmp_handle_irq);
c24b3114 HZ	243	}
	244
	245	/* MMP2 (ARMv7) */
	246	void __init mmp2_init_icu(void)
	247	{
942f4221	248	int irq, end;
c24b3114 HZ	249
	250	max_icu_nr = 8;
	251	mmp_icu_base = ioremap(0xd4282000, 0x1000);
	252	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	253	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	254	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	255	icu_data[0].nr_irqs = 64;
	256	icu_data[0].virq_base = 0;
	257	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
	258	&irq_domain_simple_ops,
	259	&icu_data[0]);
	260	icu_data[1].reg_status = mmp_icu_base + 0x150;
	261	icu_data[1].reg_mask = mmp_icu_base + 0x168;
942f4221 HZ	262	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
	263	icu_data[0].nr_irqs;
	264	icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
c24b3114	265	icu_data[1].nr_irqs = 2;
10bd21c0	266	icu_data[1].cascade_irq = 4;
942f4221	267	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
c24b3114 HZ	268	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
	269	icu_data[1].virq_base, 0,
	270	&irq_domain_simple_ops,
	271	&icu_data[1]);
	272	icu_data[2].reg_status = mmp_icu_base + 0x154;
	273	icu_data[2].reg_mask = mmp_icu_base + 0x16c;
	274	icu_data[2].nr_irqs = 2;
10bd21c0	275	icu_data[2].cascade_irq = 5;
942f4221	276	icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
c24b3114 HZ	277	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
	278	icu_data[2].virq_base, 0,
	279	&irq_domain_simple_ops,
	280	&icu_data[2]);
	281	icu_data[3].reg_status = mmp_icu_base + 0x180;
	282	icu_data[3].reg_mask = mmp_icu_base + 0x17c;
	283	icu_data[3].nr_irqs = 3;
10bd21c0	284	icu_data[3].cascade_irq = 9;
942f4221	285	icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
c24b3114 HZ	286	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
	287	icu_data[3].virq_base, 0,
	288	&irq_domain_simple_ops,
	289	&icu_data[3]);
	290	icu_data[4].reg_status = mmp_icu_base + 0x158;
	291	icu_data[4].reg_mask = mmp_icu_base + 0x170;
	292	icu_data[4].nr_irqs = 5;
10bd21c0	293	icu_data[4].cascade_irq = 17;
942f4221	294	icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
c24b3114 HZ	295	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
	296	icu_data[4].virq_base, 0,
	297	&irq_domain_simple_ops,
	298	&icu_data[4]);
	299	icu_data[5].reg_status = mmp_icu_base + 0x15c;
	300	icu_data[5].reg_mask = mmp_icu_base + 0x174;
	301	icu_data[5].nr_irqs = 15;
10bd21c0	302	icu_data[5].cascade_irq = 35;
942f4221	303	icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
c24b3114 HZ	304	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
	305	icu_data[5].virq_base, 0,
	306	&irq_domain_simple_ops,
	307	&icu_data[5]);
	308	icu_data[6].reg_status = mmp_icu_base + 0x160;
	309	icu_data[6].reg_mask = mmp_icu_base + 0x178;
	310	icu_data[6].nr_irqs = 2;
10bd21c0	311	icu_data[6].cascade_irq = 51;
942f4221	312	icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
c24b3114 HZ	313	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
	314	icu_data[6].virq_base, 0,
	315	&irq_domain_simple_ops,
	316	&icu_data[6]);
	317	icu_data[7].reg_status = mmp_icu_base + 0x188;
	318	icu_data[7].reg_mask = mmp_icu_base + 0x184;
	319	icu_data[7].nr_irqs = 2;
10bd21c0	320	icu_data[7].cascade_irq = 55;
942f4221	321	icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
c24b3114 HZ	322	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
	323	icu_data[7].virq_base, 0,
	324	&irq_domain_simple_ops,
	325	&icu_data[7]);
942f4221 HZ	326	end = icu_data[7].virq_base + icu_data[7].nr_irqs;
942f4221 HZ	327	for (irq = 0; irq < end; irq++) {
c24b3114	328	icu_mask_irq(irq_get_irq_data(irq));
942f4221 HZ	329	if (irq == icu_data[1].cascade_irq \|\|
	330	irq == icu_data[2].cascade_irq \|\|
	331	irq == icu_data[3].cascade_irq \|\|
	332	irq == icu_data[4].cascade_irq \|\|
	333	irq == icu_data[5].cascade_irq \|\|
	334	irq == icu_data[6].cascade_irq \|\|
	335	irq == icu_data[7].cascade_irq) {
c24b3114 HZ	336	irq_set_chip(irq, &icu_irq_chip);
c24b3114 HZ	337	irq_set_chained_handler(irq, icu_mux_irq_demux);
942f4221	338	} else {
c24b3114 HZ	339	irq_set_chip_and_handler(irq, &icu_irq_chip,
c24b3114 HZ	340	handle_level_irq);
c24b3114 HZ	341	}
	342	set_irq_flags(irq, IRQF_VALID);
	343	}
	344	irq_set_default_host(icu_data[0].domain);
0f374561	345	set_handle_irq(mmp2_handle_irq);
c24b3114 HZ	346	}
	347
	348	#ifdef CONFIG_OF
0f374561	349	static int __init mmp_init_bases(struct device_node *node)
c24b3114	350	{
0f374561	351	int ret, nr_irqs, irq, i = 0;
c24b3114	352
0f374561 HZ	353	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
	354	if (ret) {
	355	pr_err("Not found mrvl,intc-nr-irqs property\n");
	356	return ret;
	357	}
c24b3114	358
0f374561 HZ	359	mmp_icu_base = of_iomap(node, 0);
	360	if (!mmp_icu_base) {
	361	pr_err("Failed to get interrupt controller register\n");
	362	return -ENOMEM;
	363	}
	364
	365	icu_data[0].virq_base = 0;
	366	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
	367	&mmp_irq_domain_ops,
	368	&icu_data[0]);
	369	for (irq = 0; irq < nr_irqs; irq++) {
	370	ret = irq_create_mapping(icu_data[0].domain, irq);
	371	if (!ret) {
	372	pr_err("Failed to mapping hwirq\n");
c24b3114 HZ	373	goto err;
c24b3114 HZ	374	}
0f374561 HZ	375	if (!irq)
0f374561 HZ	376	icu_data[0].virq_base = ret;
c24b3114	377	}
0f374561	378	icu_data[0].nr_irqs = nr_irqs;
c24b3114 HZ	379	return 0;
c24b3114 HZ	380	err:
0f374561 HZ	381	if (icu_data[0].virq_base) {
	382	for (i = 0; i < irq; i++)
	383	irq_dispose_mapping(icu_data[0].virq_base + i);
	384	}
	385	irq_domain_remove(icu_data[0].domain);
	386	iounmap(mmp_icu_base);
	387	return -EINVAL;
c24b3114 HZ	388	}
c24b3114 HZ	389
0f374561 HZ	390	static int __init mmp_of_init(struct device_node *node,
0f374561 HZ	391	struct device_node *parent)
c24b3114	392	{
0f374561	393	int ret;
c24b3114	394
0f374561 HZ	395	ret = mmp_init_bases(node);
	396	if (ret < 0)
	397	return ret;
	398
	399	icu_data[0].conf_enable = mmp_conf.conf_enable;
	400	icu_data[0].conf_disable = mmp_conf.conf_disable;
	401	icu_data[0].conf_mask = mmp_conf.conf_mask;
	402	irq_set_default_host(icu_data[0].domain);
	403	set_handle_irq(mmp_handle_irq);
	404	max_icu_nr = 1;
	405	return 0;
	406	}
	407	IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
	408
	409	static int __init mmp2_of_init(struct device_node *node,
	410	struct device_node *parent)
	411	{
	412	int ret;
	413
	414	ret = mmp_init_bases(node);
	415	if (ret < 0)
	416	return ret;
	417
	418	icu_data[0].conf_enable = mmp2_conf.conf_enable;
	419	icu_data[0].conf_disable = mmp2_conf.conf_disable;
	420	icu_data[0].conf_mask = mmp2_conf.conf_mask;
	421	irq_set_default_host(icu_data[0].domain);
	422	set_handle_irq(mmp2_handle_irq);
	423	max_icu_nr = 1;
	424	return 0;
	425	}
	426	IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
	427
	428	static int __init mmp2_mux_of_init(struct device_node *node,
	429	struct device_node *parent)
	430	{
	431	struct resource res;
	432	int i, ret, irq, j = 0;
	433	u32 nr_irqs, mfp_irq;
	434
	435	if (!parent)
	436	return -ENODEV;
	437
	438	i = max_icu_nr;
	439	ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
	440	&nr_irqs);
c24b3114 HZ	441	if (ret) {
c24b3114 HZ	442	pr_err("Not found mrvl,intc-nr-irqs property\n");
0f374561	443	return -EINVAL;
c24b3114	444	}
0f374561 HZ	445	ret = of_address_to_resource(node, 0, &res);
	446	if (ret < 0) {
	447	pr_err("Not found reg property\n");
	448	return -EINVAL;
c24b3114	449	}
0f374561 HZ	450	icu_data[i].reg_status = mmp_icu_base + res.start;
	451	ret = of_address_to_resource(node, 1, &res);
	452	if (ret < 0) {
	453	pr_err("Not found reg property\n");
	454	return -EINVAL;
c24b3114	455	}
0f374561 HZ	456	icu_data[i].reg_mask = mmp_icu_base + res.start;
	457	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
	458	if (!icu_data[i].cascade_irq)
	459	return -EINVAL;
	460
	461	icu_data[i].virq_base = 0;
	462	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
c24b3114	463	&mmp_irq_domain_ops,
0f374561 HZ	464	&icu_data[i]);
	465	for (irq = 0; irq < nr_irqs; irq++) {
	466	ret = irq_create_mapping(icu_data[i].domain, irq);
	467	if (!ret) {
	468	pr_err("Failed to mapping hwirq\n");
	469	goto err;
	470	}
	471	if (!irq)
	472	icu_data[i].virq_base = ret;
	473	}
	474	icu_data[i].nr_irqs = nr_irqs;
	475	if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
	476	&mfp_irq)) {
	477	icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
	478	icu_data[i].clr_mfp_hwirq = mfp_irq;
	479	}
	480	irq_set_chained_handler(icu_data[i].cascade_irq,
	481	icu_mux_irq_demux);
	482	max_icu_nr++;
	483	return 0;
c24b3114	484	err:
0f374561 HZ	485	if (icu_data[i].virq_base) {
	486	for (j = 0; j < irq; j++)
	487	irq_dispose_mapping(icu_data[i].virq_base + j);
	488	}
	489	irq_domain_remove(icu_data[i].domain);
	490	return -EINVAL;
c24b3114	491	}
0f374561	492	IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
c24b3114	493	#endif