Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
1f19aee0 MR |
9 | |
10 | #define pr_fmt(fmt) "irq-mips-gic: " fmt | |
11 | ||
39b8d525 | 12 | #include <linux/bitmap.h> |
fb8f7be1 | 13 | #include <linux/clocksource.h> |
da61fcf9 | 14 | #include <linux/cpuhotplug.h> |
39b8d525 | 15 | #include <linux/init.h> |
18743d27 | 16 | #include <linux/interrupt.h> |
fb8f7be1 | 17 | #include <linux/irq.h> |
41a83e06 | 18 | #include <linux/irqchip.h> |
a7057270 | 19 | #include <linux/of_address.h> |
aa493737 | 20 | #include <linux/percpu.h> |
18743d27 | 21 | #include <linux/sched.h> |
631330f5 | 22 | #include <linux/smp.h> |
39b8d525 | 23 | |
e83f7e02 | 24 | #include <asm/mips-cps.h> |
98b67c37 SH |
25 | #include <asm/setup.h> |
26 | #include <asm/traps.h> | |
39b8d525 | 27 | |
a7057270 AB |
28 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
29 | ||
b11d4c1f | 30 | #define GIC_MAX_INTRS 256 |
aa493737 | 31 | #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) |
98b67c37 | 32 | |
b11d4c1f PB |
33 | /* Add 2 to convert GIC CPU pin to core interrupt */ |
34 | #define GIC_CPU_PIN_OFFSET 2 | |
35 | ||
36 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ | |
37 | #define GIC_PIN_TO_VEC_OFFSET 1 | |
38 | ||
39 | /* Convert between local/shared IRQ number and GIC HW IRQ number. */ | |
40 | #define GIC_LOCAL_HWIRQ_BASE 0 | |
41 | #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) | |
42 | #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) | |
43 | #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS | |
44 | #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) | |
45 | #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) | |
46 | ||
582e2b4a | 47 | void __iomem *mips_gic_base; |
822350bc | 48 | |
b0e453ff | 49 | static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); |
2af70a96 | 50 | |
95150ae8 | 51 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 52 | static struct irq_domain *gic_irq_domain; |
2af70a96 | 53 | static struct irq_domain *gic_ipi_domain; |
fbd55241 | 54 | static int gic_shared_intrs; |
3263d085 | 55 | static unsigned int gic_cpu_pin; |
1b6af71a | 56 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 57 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
61dc367e PB |
58 | static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
59 | static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); | |
39b8d525 | 60 | |
da61fcf9 PB |
61 | static struct gic_all_vpes_chip_data { |
62 | u32 map; | |
63 | bool mask; | |
64 | } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; | |
65 | ||
7778c4b2 | 66 | static void gic_clear_pcpu_masks(unsigned int intr) |
8fa4b930 | 67 | { |
7778c4b2 | 68 | unsigned int i; |
835d2b45 | 69 | |
7778c4b2 PB |
70 | /* Clear the interrupt's bit in all pcpu_masks */ |
71 | for_each_possible_cpu(i) | |
72 | clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); | |
835d2b45 PB |
73 | } |
74 | ||
e9de688d AB |
75 | static bool gic_local_irq_is_routable(int intr) |
76 | { | |
77 | u32 vpe_ctl; | |
78 | ||
79 | /* All local interrupts are routable in EIC mode. */ | |
80 | if (cpu_has_veic) | |
81 | return true; | |
82 | ||
0d0cf58c | 83 | vpe_ctl = read_gic_vl_ctl(); |
e9de688d AB |
84 | switch (intr) { |
85 | case GIC_LOCAL_INT_TIMER: | |
0d0cf58c | 86 | return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; |
e9de688d | 87 | case GIC_LOCAL_INT_PERFCTR: |
0d0cf58c | 88 | return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; |
e9de688d | 89 | case GIC_LOCAL_INT_FDC: |
0d0cf58c | 90 | return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; |
e9de688d AB |
91 | case GIC_LOCAL_INT_SWINT0: |
92 | case GIC_LOCAL_INT_SWINT1: | |
0d0cf58c | 93 | return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; |
e9de688d AB |
94 | default: |
95 | return true; | |
96 | } | |
97 | } | |
98 | ||
3263d085 | 99 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
100 | { |
101 | /* Convert irq vector # to hw int # */ | |
102 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
103 | ||
104 | /* Set irq to use shadow set */ | |
0d0cf58c | 105 | write_gic_vl_eic_shadow_set(irq, set); |
98b67c37 SH |
106 | } |
107 | ||
bb11cff3 | 108 | static void gic_send_ipi(struct irq_data *d, unsigned int cpu) |
39b8d525 | 109 | { |
bb11cff3 QY |
110 | irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); |
111 | ||
3680746a | 112 | write_gic_wedge(GIC_WEDGE_RW | hwirq); |
39b8d525 RB |
113 | } |
114 | ||
e9de688d AB |
115 | int gic_get_c0_compare_int(void) |
116 | { | |
117 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
118 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
119 | return irq_create_mapping(gic_irq_domain, | |
120 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
121 | } | |
122 | ||
123 | int gic_get_c0_perfcount_int(void) | |
124 | { | |
125 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 126 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
127 | if (cp0_perfcount_irq < 0) |
128 | return -1; | |
129 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
130 | } | |
131 | return irq_create_mapping(gic_irq_domain, | |
132 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
133 | } | |
134 | ||
6429e2b6 JH |
135 | int gic_get_c0_fdc_int(void) |
136 | { | |
137 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
138 | /* Is the FDC IRQ even present? */ | |
139 | if (cp0_fdc_irq < 0) | |
140 | return -1; | |
141 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
142 | } | |
143 | ||
6429e2b6 JH |
144 | return irq_create_mapping(gic_irq_domain, |
145 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
146 | } | |
147 | ||
1b3ed367 | 148 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 149 | { |
e98fcb2a | 150 | unsigned int intr, virq; |
8f5ee79c | 151 | unsigned long *pcpu_mask; |
8f5ee79c | 152 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
39b8d525 RB |
153 | |
154 | /* Get per-cpu bitmaps */ | |
aa493737 | 155 | pcpu_mask = this_cpu_ptr(pcpu_masks); |
d77d5ac9 | 156 | |
7778c4b2 | 157 | if (mips_cm_is64) |
e98fcb2a PB |
158 | __ioread64_copy(pending, addr_gic_pend(), |
159 | DIV_ROUND_UP(gic_shared_intrs, 64)); | |
7778c4b2 | 160 | else |
e98fcb2a PB |
161 | __ioread32_copy(pending, addr_gic_pend(), |
162 | DIV_ROUND_UP(gic_shared_intrs, 32)); | |
39b8d525 | 163 | |
fbd55241 | 164 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); |
39b8d525 | 165 | |
cae750ba | 166 | for_each_set_bit(intr, pending, gic_shared_intrs) { |
d7eb4f2e QY |
167 | virq = irq_linear_revmap(gic_irq_domain, |
168 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
169 | if (chained) |
170 | generic_handle_irq(virq); | |
171 | else | |
172 | do_IRQ(virq); | |
d7eb4f2e | 173 | } |
39b8d525 RB |
174 | } |
175 | ||
161d049e | 176 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 177 | { |
7778c4b2 PB |
178 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
179 | ||
90019f8f | 180 | write_gic_rmask(intr); |
7778c4b2 | 181 | gic_clear_pcpu_masks(intr); |
39b8d525 RB |
182 | } |
183 | ||
161d049e | 184 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 185 | { |
7778c4b2 PB |
186 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
187 | unsigned int cpu; | |
188 | ||
90019f8f | 189 | write_gic_smask(intr); |
7778c4b2 PB |
190 | |
191 | gic_clear_pcpu_masks(intr); | |
d9f82930 | 192 | cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); |
7778c4b2 | 193 | set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 RB |
194 | } |
195 | ||
5561c9e4 AB |
196 | static void gic_ack_irq(struct irq_data *d) |
197 | { | |
e9de688d | 198 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 199 | |
3680746a | 200 | write_gic_wedge(irq); |
5561c9e4 AB |
201 | } |
202 | ||
95150ae8 AB |
203 | static int gic_set_type(struct irq_data *d, unsigned int type) |
204 | { | |
5af3e93e | 205 | unsigned int irq, pol, trig, dual; |
95150ae8 | 206 | unsigned long flags; |
5af3e93e PB |
207 | |
208 | irq = GIC_HWIRQ_TO_SHARED(d->hwirq); | |
95150ae8 AB |
209 | |
210 | spin_lock_irqsave(&gic_lock, flags); | |
211 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
212 | case IRQ_TYPE_EDGE_FALLING: | |
5af3e93e PB |
213 | pol = GIC_POL_FALLING_EDGE; |
214 | trig = GIC_TRIG_EDGE; | |
215 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
216 | break; |
217 | case IRQ_TYPE_EDGE_RISING: | |
5af3e93e PB |
218 | pol = GIC_POL_RISING_EDGE; |
219 | trig = GIC_TRIG_EDGE; | |
220 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
221 | break; |
222 | case IRQ_TYPE_EDGE_BOTH: | |
5af3e93e PB |
223 | pol = 0; /* Doesn't matter */ |
224 | trig = GIC_TRIG_EDGE; | |
225 | dual = GIC_DUAL_DUAL; | |
95150ae8 AB |
226 | break; |
227 | case IRQ_TYPE_LEVEL_LOW: | |
5af3e93e PB |
228 | pol = GIC_POL_ACTIVE_LOW; |
229 | trig = GIC_TRIG_LEVEL; | |
230 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
231 | break; |
232 | case IRQ_TYPE_LEVEL_HIGH: | |
233 | default: | |
5af3e93e PB |
234 | pol = GIC_POL_ACTIVE_HIGH; |
235 | trig = GIC_TRIG_LEVEL; | |
236 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
237 | break; |
238 | } | |
239 | ||
5af3e93e PB |
240 | change_gic_pol(irq, pol); |
241 | change_gic_trig(irq, trig); | |
242 | change_gic_dual(irq, dual); | |
243 | ||
244 | if (trig == GIC_TRIG_EDGE) | |
a595fc51 TG |
245 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, |
246 | handle_edge_irq, NULL); | |
247 | else | |
248 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
249 | handle_level_irq, NULL); | |
95150ae8 | 250 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 251 | |
95150ae8 AB |
252 | return 0; |
253 | } | |
254 | ||
255 | #ifdef CONFIG_SMP | |
161d049e TG |
256 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
257 | bool force) | |
39b8d525 | 258 | { |
e9de688d | 259 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
07df8bfe PB |
260 | unsigned long flags; |
261 | unsigned int cpu; | |
39b8d525 | 262 | |
07df8bfe PB |
263 | cpu = cpumask_first_and(cpumask, cpu_online_mask); |
264 | if (cpu >= NR_CPUS) | |
14d160ab | 265 | return -EINVAL; |
39b8d525 RB |
266 | |
267 | /* Assumption : cpumask refers to a single CPU */ | |
268 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 269 | |
c214c035 | 270 | /* Re-route this IRQ */ |
07df8bfe | 271 | write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); |
c214c035 TW |
272 | |
273 | /* Update the pcpu_masks */ | |
7778c4b2 PB |
274 | gic_clear_pcpu_masks(irq); |
275 | if (read_gic_mask(irq)) | |
07df8bfe | 276 | set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 | 277 | |
18416e45 | 278 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
39b8d525 RB |
279 | spin_unlock_irqrestore(&gic_lock, flags); |
280 | ||
7f15a648 | 281 | return IRQ_SET_MASK_OK; |
39b8d525 RB |
282 | } |
283 | #endif | |
284 | ||
4a6a3ea3 AB |
285 | static struct irq_chip gic_level_irq_controller = { |
286 | .name = "MIPS GIC", | |
287 | .irq_mask = gic_mask_irq, | |
288 | .irq_unmask = gic_unmask_irq, | |
289 | .irq_set_type = gic_set_type, | |
290 | #ifdef CONFIG_SMP | |
291 | .irq_set_affinity = gic_set_affinity, | |
292 | #endif | |
293 | }; | |
294 | ||
295 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 296 | .name = "MIPS GIC", |
5561c9e4 | 297 | .irq_ack = gic_ack_irq, |
161d049e | 298 | .irq_mask = gic_mask_irq, |
161d049e | 299 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 300 | .irq_set_type = gic_set_type, |
39b8d525 | 301 | #ifdef CONFIG_SMP |
161d049e | 302 | .irq_set_affinity = gic_set_affinity, |
39b8d525 | 303 | #endif |
bb11cff3 | 304 | .ipi_send_single = gic_send_ipi, |
39b8d525 RB |
305 | }; |
306 | ||
1b3ed367 | 307 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
308 | { |
309 | unsigned long pending, masked; | |
d7eb4f2e | 310 | unsigned int intr, virq; |
e9de688d | 311 | |
9da3c645 PB |
312 | pending = read_gic_vl_pend(); |
313 | masked = read_gic_vl_mask(); | |
e9de688d AB |
314 | |
315 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
316 | ||
0f4ed158 | 317 | for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { |
d7eb4f2e QY |
318 | virq = irq_linear_revmap(gic_irq_domain, |
319 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
320 | if (chained) |
321 | generic_handle_irq(virq); | |
322 | else | |
323 | do_IRQ(virq); | |
d7eb4f2e | 324 | } |
e9de688d AB |
325 | } |
326 | ||
327 | static void gic_mask_local_irq(struct irq_data *d) | |
328 | { | |
329 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
330 | ||
9da3c645 | 331 | write_gic_vl_rmask(BIT(intr)); |
e9de688d AB |
332 | } |
333 | ||
334 | static void gic_unmask_local_irq(struct irq_data *d) | |
335 | { | |
336 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
337 | ||
9da3c645 | 338 | write_gic_vl_smask(BIT(intr)); |
e9de688d AB |
339 | } |
340 | ||
341 | static struct irq_chip gic_local_irq_controller = { | |
342 | .name = "MIPS GIC Local", | |
343 | .irq_mask = gic_mask_local_irq, | |
344 | .irq_unmask = gic_unmask_local_irq, | |
345 | }; | |
346 | ||
347 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
348 | { | |
da61fcf9 | 349 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 350 | unsigned long flags; |
da61fcf9 PB |
351 | int intr, cpu; |
352 | ||
353 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
354 | cd = irq_data_get_irq_chip_data(d); | |
355 | cd->mask = false; | |
e9de688d AB |
356 | |
357 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
358 | for_each_online_cpu(cpu) { |
359 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 360 | write_gic_vo_rmask(BIT(intr)); |
e9de688d AB |
361 | } |
362 | spin_unlock_irqrestore(&gic_lock, flags); | |
363 | } | |
364 | ||
365 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
366 | { | |
da61fcf9 | 367 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 368 | unsigned long flags; |
da61fcf9 PB |
369 | int intr, cpu; |
370 | ||
371 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
372 | cd = irq_data_get_irq_chip_data(d); | |
373 | cd->mask = true; | |
e9de688d AB |
374 | |
375 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
376 | for_each_online_cpu(cpu) { |
377 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 378 | write_gic_vo_smask(BIT(intr)); |
e9de688d AB |
379 | } |
380 | spin_unlock_irqrestore(&gic_lock, flags); | |
381 | } | |
382 | ||
da61fcf9 PB |
383 | static void gic_all_vpes_irq_cpu_online(struct irq_data *d) |
384 | { | |
385 | struct gic_all_vpes_chip_data *cd; | |
386 | unsigned int intr; | |
387 | ||
388 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
389 | cd = irq_data_get_irq_chip_data(d); | |
390 | ||
6d4d367d | 391 | write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); |
da61fcf9 PB |
392 | if (cd->mask) |
393 | write_gic_vl_smask(BIT(intr)); | |
394 | } | |
395 | ||
e9de688d | 396 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
da61fcf9 PB |
397 | .name = "MIPS GIC Local", |
398 | .irq_mask = gic_mask_local_irq_all_vpes, | |
399 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
400 | .irq_cpu_online = gic_all_vpes_irq_cpu_online, | |
e9de688d AB |
401 | }; |
402 | ||
18743d27 | 403 | static void __gic_irq_dispatch(void) |
39b8d525 | 404 | { |
1b3ed367 RV |
405 | gic_handle_local_int(false); |
406 | gic_handle_shared_int(false); | |
18743d27 | 407 | } |
39b8d525 | 408 | |
bd0b9ac4 | 409 | static void gic_irq_dispatch(struct irq_desc *desc) |
18743d27 | 410 | { |
1b3ed367 RV |
411 | gic_handle_local_int(true); |
412 | gic_handle_shared_int(true); | |
18743d27 AB |
413 | } |
414 | ||
e9de688d | 415 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
7778c4b2 | 416 | irq_hw_number_t hw, unsigned int cpu) |
e9de688d AB |
417 | { |
418 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
d9f82930 | 419 | struct irq_data *data; |
c49581a4 AB |
420 | unsigned long flags; |
421 | ||
d9f82930 PB |
422 | data = irq_get_irq_data(virq); |
423 | ||
c49581a4 | 424 | spin_lock_irqsave(&gic_lock, flags); |
d3e8cf44 | 425 | write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); |
7778c4b2 | 426 | write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); |
d9f82930 | 427 | irq_data_update_effective_affinity(data, cpumask_of(cpu)); |
c49581a4 AB |
428 | spin_unlock_irqrestore(&gic_lock, flags); |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
b87281e7 | 433 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
c98c1822 QY |
434 | const u32 *intspec, unsigned int intsize, |
435 | irq_hw_number_t *out_hwirq, | |
436 | unsigned int *out_type) | |
437 | { | |
438 | if (intsize != 3) | |
439 | return -EINVAL; | |
440 | ||
441 | if (intspec[0] == GIC_SHARED) | |
442 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
443 | else if (intspec[0] == GIC_LOCAL) | |
444 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
445 | else | |
446 | return -EINVAL; | |
447 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
8ada00a6 MR |
452 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
453 | irq_hw_number_t hwirq) | |
c98c1822 | 454 | { |
da61fcf9 | 455 | struct gic_all_vpes_chip_data *cd; |
63b746b1 PB |
456 | unsigned long flags; |
457 | unsigned int intr; | |
da61fcf9 | 458 | int err, cpu; |
63b746b1 | 459 | u32 map; |
c98c1822 | 460 | |
8ada00a6 | 461 | if (hwirq >= GIC_SHARED_HWIRQ_BASE) { |
b87281e7 PB |
462 | /* verify that shared irqs don't conflict with an IPI irq */ |
463 | if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) | |
464 | return -EBUSY; | |
c98c1822 | 465 | |
b87281e7 PB |
466 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
467 | &gic_level_irq_controller, | |
468 | NULL); | |
469 | if (err) | |
470 | return err; | |
471 | ||
18416e45 | 472 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); |
b87281e7 | 473 | return gic_shared_irq_domain_map(d, virq, hwirq, 0); |
c98c1822 QY |
474 | } |
475 | ||
63b746b1 PB |
476 | intr = GIC_HWIRQ_TO_LOCAL(hwirq); |
477 | map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; | |
478 | ||
479 | switch (intr) { | |
b87281e7 | 480 | case GIC_LOCAL_INT_TIMER: |
63b746b1 PB |
481 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
482 | map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin; | |
df561f66 | 483 | fallthrough; |
b87281e7 PB |
484 | case GIC_LOCAL_INT_PERFCTR: |
485 | case GIC_LOCAL_INT_FDC: | |
486 | /* | |
487 | * HACK: These are all really percpu interrupts, but | |
488 | * the rest of the MIPS kernel code does not use the | |
489 | * percpu IRQ API for them. | |
490 | */ | |
da61fcf9 PB |
491 | cd = &gic_all_vpes_chip_data[intr]; |
492 | cd->map = map; | |
b87281e7 PB |
493 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
494 | &gic_all_vpes_local_irq_controller, | |
da61fcf9 | 495 | cd); |
b87281e7 PB |
496 | if (err) |
497 | return err; | |
c98c1822 | 498 | |
b87281e7 PB |
499 | irq_set_handler(virq, handle_percpu_irq); |
500 | break; | |
501 | ||
502 | default: | |
503 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, | |
504 | &gic_local_irq_controller, | |
505 | NULL); | |
506 | if (err) | |
507 | return err; | |
508 | ||
509 | irq_set_handler(virq, handle_percpu_devid_irq); | |
510 | irq_set_percpu_devid(virq); | |
511 | break; | |
512 | } | |
513 | ||
63b746b1 PB |
514 | if (!gic_local_irq_is_routable(intr)) |
515 | return -EPERM; | |
516 | ||
517 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
518 | for_each_online_cpu(cpu) { |
519 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
6d4d367d | 520 | write_gic_vo_map(mips_gic_vx_map_reg(intr), map); |
63b746b1 PB |
521 | } |
522 | spin_unlock_irqrestore(&gic_lock, flags); | |
523 | ||
524 | return 0; | |
c98c1822 QY |
525 | } |
526 | ||
8ada00a6 MR |
527 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
528 | unsigned int nr_irqs, void *arg) | |
529 | { | |
530 | struct irq_fwspec *fwspec = arg; | |
531 | irq_hw_number_t hwirq; | |
532 | ||
533 | if (fwspec->param[0] == GIC_SHARED) | |
534 | hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); | |
535 | else | |
536 | hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); | |
537 | ||
538 | return gic_irq_domain_map(d, virq, hwirq); | |
539 | } | |
540 | ||
b87281e7 PB |
541 | void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, |
542 | unsigned int nr_irqs) | |
2564970a | 543 | { |
2564970a PB |
544 | } |
545 | ||
b87281e7 PB |
546 | static const struct irq_domain_ops gic_irq_domain_ops = { |
547 | .xlate = gic_irq_domain_xlate, | |
548 | .alloc = gic_irq_domain_alloc, | |
549 | .free = gic_irq_domain_free, | |
8ada00a6 | 550 | .map = gic_irq_domain_map, |
2af70a96 QY |
551 | }; |
552 | ||
553 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | |
554 | const u32 *intspec, unsigned int intsize, | |
555 | irq_hw_number_t *out_hwirq, | |
556 | unsigned int *out_type) | |
557 | { | |
558 | /* | |
559 | * There's nothing to translate here. hwirq is dynamically allocated and | |
560 | * the irq type is always edge triggered. | |
561 | * */ | |
562 | *out_hwirq = 0; | |
563 | *out_type = IRQ_TYPE_EDGE_RISING; | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, | |
569 | unsigned int nr_irqs, void *arg) | |
570 | { | |
571 | struct cpumask *ipimask = arg; | |
b87281e7 PB |
572 | irq_hw_number_t hwirq, base_hwirq; |
573 | int cpu, ret, i; | |
2af70a96 | 574 | |
b87281e7 PB |
575 | base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); |
576 | if (base_hwirq == gic_shared_intrs) | |
577 | return -ENOMEM; | |
578 | ||
579 | /* check that we have enough space */ | |
580 | for (i = base_hwirq; i < nr_irqs; i++) { | |
581 | if (!test_bit(i, ipi_available)) | |
582 | return -EBUSY; | |
583 | } | |
584 | bitmap_clear(ipi_available, base_hwirq, nr_irqs); | |
585 | ||
586 | /* map the hwirq for each cpu consecutively */ | |
587 | i = 0; | |
588 | for_each_cpu(cpu, ipimask) { | |
589 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); | |
590 | ||
591 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, | |
592 | &gic_edge_irq_controller, | |
593 | NULL); | |
594 | if (ret) | |
595 | goto error; | |
2af70a96 | 596 | |
b87281e7 | 597 | ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, |
2af70a96 QY |
598 | &gic_edge_irq_controller, |
599 | NULL); | |
600 | if (ret) | |
601 | goto error; | |
602 | ||
603 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); | |
604 | if (ret) | |
605 | goto error; | |
b87281e7 PB |
606 | |
607 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); | |
608 | if (ret) | |
609 | goto error; | |
610 | ||
611 | i++; | |
2af70a96 QY |
612 | } |
613 | ||
614 | return 0; | |
615 | error: | |
b87281e7 | 616 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
2af70a96 QY |
617 | return ret; |
618 | } | |
619 | ||
b0e453ff WY |
620 | static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, |
621 | unsigned int nr_irqs) | |
2af70a96 | 622 | { |
b87281e7 PB |
623 | irq_hw_number_t base_hwirq; |
624 | struct irq_data *data; | |
625 | ||
626 | data = irq_get_irq_data(virq); | |
627 | if (!data) | |
628 | return; | |
629 | ||
630 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); | |
631 | bitmap_set(ipi_available, base_hwirq, nr_irqs); | |
2af70a96 QY |
632 | } |
633 | ||
b0e453ff WY |
634 | static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, |
635 | enum irq_domain_bus_token bus_token) | |
2af70a96 QY |
636 | { |
637 | bool is_ipi; | |
638 | ||
639 | switch (bus_token) { | |
640 | case DOMAIN_BUS_IPI: | |
641 | is_ipi = d->bus_token == bus_token; | |
547aefc4 | 642 | return (!node || to_of_node(d->fwnode) == node) && is_ipi; |
2af70a96 QY |
643 | break; |
644 | default: | |
645 | return 0; | |
646 | } | |
647 | } | |
648 | ||
0b7e815a | 649 | static const struct irq_domain_ops gic_ipi_domain_ops = { |
2af70a96 QY |
650 | .xlate = gic_ipi_domain_xlate, |
651 | .alloc = gic_ipi_domain_alloc, | |
652 | .free = gic_ipi_domain_free, | |
653 | .match = gic_ipi_domain_match, | |
c49581a4 AB |
654 | }; |
655 | ||
da61fcf9 PB |
656 | static int gic_cpu_startup(unsigned int cpu) |
657 | { | |
890f6b55 PB |
658 | /* Enable or disable EIC */ |
659 | change_gic_vl_ctl(GIC_VX_CTL_EIC, | |
660 | cpu_has_veic ? GIC_VX_CTL_EIC : 0); | |
661 | ||
25ac19e1 PB |
662 | /* Clear all local IRQ masks (ie. disable all local interrupts) */ |
663 | write_gic_vl_rmask(~0); | |
664 | ||
da61fcf9 PB |
665 | /* Invoke irq_cpu_online callbacks to enable desired interrupts */ |
666 | irq_cpu_online(); | |
667 | ||
668 | return 0; | |
669 | } | |
fbea7541 PB |
670 | |
671 | static int __init gic_of_init(struct device_node *node, | |
672 | struct device_node *parent) | |
39b8d525 | 673 | { |
25c51dad | 674 | unsigned int cpu_vec, i, gicconfig, v[2], num_ipis; |
b2b2e584 | 675 | unsigned long reserved; |
fbea7541 PB |
676 | phys_addr_t gic_base; |
677 | struct resource res; | |
678 | size_t gic_len; | |
679 | ||
680 | /* Find the first available CPU vector. */ | |
b2b2e584 | 681 | i = 0; |
a08588ea | 682 | reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); |
fbea7541 PB |
683 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", |
684 | i++, &cpu_vec)) | |
685 | reserved |= BIT(cpu_vec); | |
b2b2e584 PB |
686 | |
687 | cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); | |
688 | if (cpu_vec == hweight_long(ST0_IM)) { | |
1f19aee0 | 689 | pr_err("No CPU vectors available\n"); |
fbea7541 PB |
690 | return -ENODEV; |
691 | } | |
692 | ||
693 | if (of_address_to_resource(node, 0, &res)) { | |
694 | /* | |
695 | * Probe the CM for the GIC base address if not specified | |
696 | * in the device-tree. | |
697 | */ | |
698 | if (mips_cm_present()) { | |
699 | gic_base = read_gcr_gic_base() & | |
700 | ~CM_GCR_GIC_BASE_GICEN; | |
701 | gic_len = 0x20000; | |
666740fd MR |
702 | pr_warn("Using inherited base address %pa\n", |
703 | &gic_base); | |
fbea7541 | 704 | } else { |
1f19aee0 | 705 | pr_err("Failed to get memory range\n"); |
fbea7541 PB |
706 | return -ENODEV; |
707 | } | |
708 | } else { | |
709 | gic_base = res.start; | |
710 | gic_len = resource_size(&res); | |
711 | } | |
39b8d525 | 712 | |
fbea7541 PB |
713 | if (mips_cm_present()) { |
714 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); | |
715 | /* Ensure GIC region is enabled before trying to access it */ | |
716 | __sync(); | |
717 | } | |
c0a9f72c | 718 | |
4bdc0d67 | 719 | mips_gic_base = ioremap(gic_base, gic_len); |
39b8d525 | 720 | |
3680746a PB |
721 | gicconfig = read_gic_config(); |
722 | gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; | |
a08588ea | 723 | gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS); |
3680746a | 724 | gic_shared_intrs = (gic_shared_intrs + 1) * 8; |
39b8d525 | 725 | |
18743d27 AB |
726 | if (cpu_has_veic) { |
727 | /* Always use vector 1 in EIC mode */ | |
728 | gic_cpu_pin = 0; | |
1b6af71a | 729 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
730 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
731 | __gic_irq_dispatch); | |
732 | } else { | |
733 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
734 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
735 | gic_irq_dispatch); | |
1b6af71a JH |
736 | /* |
737 | * With the CMP implementation of SMP (deprecated), other CPUs | |
738 | * are started by the bootloader and put into a timer based | |
739 | * waiting poll loop. We must not re-route those CPU's local | |
740 | * timer interrupts as the wait instruction will never finish, | |
741 | * so just handle whatever CPU interrupt it is routed to by | |
742 | * default. | |
743 | * | |
744 | * This workaround should be removed when CMP support is | |
745 | * dropped. | |
746 | */ | |
747 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
748 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
0d0cf58c | 749 | timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP; |
1b6af71a JH |
750 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + |
751 | GIC_CPU_PIN_OFFSET + | |
752 | timer_cpu_pin, | |
753 | gic_irq_dispatch); | |
754 | } else { | |
755 | timer_cpu_pin = gic_cpu_pin; | |
756 | } | |
18743d27 AB |
757 | } |
758 | ||
a7057270 | 759 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
fbea7541 | 760 | gic_shared_intrs, 0, |
c49581a4 | 761 | &gic_irq_domain_ops, NULL); |
fbea7541 | 762 | if (!gic_irq_domain) { |
1f19aee0 | 763 | pr_err("Failed to add IRQ domain"); |
fbea7541 PB |
764 | return -ENXIO; |
765 | } | |
0b271f56 | 766 | |
2af70a96 QY |
767 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
768 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, | |
769 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
770 | node, &gic_ipi_domain_ops, NULL); | |
fbea7541 | 771 | if (!gic_ipi_domain) { |
1f19aee0 | 772 | pr_err("Failed to add IPI domain"); |
fbea7541 PB |
773 | return -ENXIO; |
774 | } | |
2af70a96 | 775 | |
96f0d93a | 776 | irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); |
2af70a96 | 777 | |
16a8083c QY |
778 | if (node && |
779 | !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) { | |
780 | bitmap_set(ipi_resrv, v[0], v[1]); | |
781 | } else { | |
25c51dad PB |
782 | /* |
783 | * Reserve 2 interrupts per possible CPU/VP for use as IPIs, | |
784 | * meeting the requirements of arch/mips SMP. | |
785 | */ | |
786 | num_ipis = 2 * num_possible_cpus(); | |
787 | bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); | |
16a8083c | 788 | } |
2af70a96 | 789 | |
f8dcd9e8 | 790 | bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); |
a7057270 | 791 | |
87888bcb | 792 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
a7057270 | 793 | |
87888bcb PB |
794 | /* Setup defaults */ |
795 | for (i = 0; i < gic_shared_intrs; i++) { | |
796 | change_gic_pol(i, GIC_POL_ACTIVE_HIGH); | |
797 | change_gic_trig(i, GIC_TRIG_LEVEL); | |
90019f8f | 798 | write_gic_rmask(i); |
a7057270 AB |
799 | } |
800 | ||
da61fcf9 PB |
801 | return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, |
802 | "irqchip/mips/gic:starting", | |
803 | gic_cpu_startup, NULL); | |
a7057270 AB |
804 | } |
805 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |