Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
1f19aee0 MR |
9 | |
10 | #define pr_fmt(fmt) "irq-mips-gic: " fmt | |
11 | ||
357a9c4b | 12 | #include <linux/bitfield.h> |
39b8d525 | 13 | #include <linux/bitmap.h> |
fb8f7be1 | 14 | #include <linux/clocksource.h> |
da61fcf9 | 15 | #include <linux/cpuhotplug.h> |
39b8d525 | 16 | #include <linux/init.h> |
18743d27 | 17 | #include <linux/interrupt.h> |
fb8f7be1 | 18 | #include <linux/irq.h> |
41a83e06 | 19 | #include <linux/irqchip.h> |
1982752f | 20 | #include <linux/irqdomain.h> |
a7057270 | 21 | #include <linux/of_address.h> |
aa493737 | 22 | #include <linux/percpu.h> |
18743d27 | 23 | #include <linux/sched.h> |
631330f5 | 24 | #include <linux/smp.h> |
39b8d525 | 25 | |
e83f7e02 | 26 | #include <asm/mips-cps.h> |
98b67c37 SH |
27 | #include <asm/setup.h> |
28 | #include <asm/traps.h> | |
39b8d525 | 29 | |
a7057270 AB |
30 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
31 | ||
b11d4c1f | 32 | #define GIC_MAX_INTRS 256 |
aa493737 | 33 | #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) |
98b67c37 | 34 | |
b11d4c1f PB |
35 | /* Add 2 to convert GIC CPU pin to core interrupt */ |
36 | #define GIC_CPU_PIN_OFFSET 2 | |
37 | ||
38 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ | |
39 | #define GIC_PIN_TO_VEC_OFFSET 1 | |
40 | ||
41 | /* Convert between local/shared IRQ number and GIC HW IRQ number. */ | |
42 | #define GIC_LOCAL_HWIRQ_BASE 0 | |
43 | #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) | |
44 | #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) | |
45 | #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS | |
46 | #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) | |
47 | #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) | |
48 | ||
582e2b4a | 49 | void __iomem *mips_gic_base; |
822350bc | 50 | |
b0e453ff | 51 | static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); |
2af70a96 | 52 | |
95150ae8 | 53 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 54 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 55 | static int gic_shared_intrs; |
3263d085 | 56 | static unsigned int gic_cpu_pin; |
4a6a3ea3 | 57 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
8190cc57 SH |
58 | |
59 | #ifdef CONFIG_GENERIC_IRQ_IPI | |
61dc367e PB |
60 | static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
61 | static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); | |
8190cc57 | 62 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
39b8d525 | 63 | |
da61fcf9 PB |
64 | static struct gic_all_vpes_chip_data { |
65 | u32 map; | |
66 | bool mask; | |
67 | } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; | |
68 | ||
7778c4b2 | 69 | static void gic_clear_pcpu_masks(unsigned int intr) |
8fa4b930 | 70 | { |
7778c4b2 | 71 | unsigned int i; |
835d2b45 | 72 | |
7778c4b2 PB |
73 | /* Clear the interrupt's bit in all pcpu_masks */ |
74 | for_each_possible_cpu(i) | |
75 | clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); | |
835d2b45 PB |
76 | } |
77 | ||
e9de688d AB |
78 | static bool gic_local_irq_is_routable(int intr) |
79 | { | |
80 | u32 vpe_ctl; | |
81 | ||
82 | /* All local interrupts are routable in EIC mode. */ | |
83 | if (cpu_has_veic) | |
84 | return true; | |
85 | ||
0d0cf58c | 86 | vpe_ctl = read_gic_vl_ctl(); |
e9de688d AB |
87 | switch (intr) { |
88 | case GIC_LOCAL_INT_TIMER: | |
0d0cf58c | 89 | return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; |
e9de688d | 90 | case GIC_LOCAL_INT_PERFCTR: |
0d0cf58c | 91 | return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; |
e9de688d | 92 | case GIC_LOCAL_INT_FDC: |
0d0cf58c | 93 | return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; |
e9de688d AB |
94 | case GIC_LOCAL_INT_SWINT0: |
95 | case GIC_LOCAL_INT_SWINT1: | |
0d0cf58c | 96 | return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; |
e9de688d AB |
97 | default: |
98 | return true; | |
99 | } | |
100 | } | |
101 | ||
3263d085 | 102 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
103 | { |
104 | /* Convert irq vector # to hw int # */ | |
105 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
106 | ||
107 | /* Set irq to use shadow set */ | |
0d0cf58c | 108 | write_gic_vl_eic_shadow_set(irq, set); |
98b67c37 SH |
109 | } |
110 | ||
bb11cff3 | 111 | static void gic_send_ipi(struct irq_data *d, unsigned int cpu) |
39b8d525 | 112 | { |
bb11cff3 QY |
113 | irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); |
114 | ||
3680746a | 115 | write_gic_wedge(GIC_WEDGE_RW | hwirq); |
39b8d525 RB |
116 | } |
117 | ||
e9de688d AB |
118 | int gic_get_c0_compare_int(void) |
119 | { | |
120 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
121 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
122 | return irq_create_mapping(gic_irq_domain, | |
123 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
124 | } | |
125 | ||
126 | int gic_get_c0_perfcount_int(void) | |
127 | { | |
128 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 129 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
130 | if (cp0_perfcount_irq < 0) |
131 | return -1; | |
132 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
133 | } | |
134 | return irq_create_mapping(gic_irq_domain, | |
135 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
136 | } | |
137 | ||
6429e2b6 JH |
138 | int gic_get_c0_fdc_int(void) |
139 | { | |
140 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
141 | /* Is the FDC IRQ even present? */ | |
142 | if (cp0_fdc_irq < 0) | |
143 | return -1; | |
144 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
145 | } | |
146 | ||
6429e2b6 JH |
147 | return irq_create_mapping(gic_irq_domain, |
148 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
149 | } | |
150 | ||
1b3ed367 | 151 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 152 | { |
046a6ee2 | 153 | unsigned int intr; |
8f5ee79c | 154 | unsigned long *pcpu_mask; |
8f5ee79c | 155 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
39b8d525 RB |
156 | |
157 | /* Get per-cpu bitmaps */ | |
aa493737 | 158 | pcpu_mask = this_cpu_ptr(pcpu_masks); |
d77d5ac9 | 159 | |
7778c4b2 | 160 | if (mips_cm_is64) |
e98fcb2a PB |
161 | __ioread64_copy(pending, addr_gic_pend(), |
162 | DIV_ROUND_UP(gic_shared_intrs, 64)); | |
7778c4b2 | 163 | else |
e98fcb2a PB |
164 | __ioread32_copy(pending, addr_gic_pend(), |
165 | DIV_ROUND_UP(gic_shared_intrs, 32)); | |
39b8d525 | 166 | |
fbd55241 | 167 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); |
39b8d525 | 168 | |
cae750ba | 169 | for_each_set_bit(intr, pending, gic_shared_intrs) { |
1b3ed367 | 170 | if (chained) |
046a6ee2 MZ |
171 | generic_handle_domain_irq(gic_irq_domain, |
172 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 | 173 | else |
1fee9db9 MZ |
174 | do_domain_IRQ(gic_irq_domain, |
175 | GIC_SHARED_TO_HWIRQ(intr)); | |
d7eb4f2e | 176 | } |
39b8d525 RB |
177 | } |
178 | ||
161d049e | 179 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 180 | { |
7778c4b2 PB |
181 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
182 | ||
90019f8f | 183 | write_gic_rmask(intr); |
7778c4b2 | 184 | gic_clear_pcpu_masks(intr); |
39b8d525 RB |
185 | } |
186 | ||
161d049e | 187 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 188 | { |
7778c4b2 PB |
189 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
190 | unsigned int cpu; | |
191 | ||
90019f8f | 192 | write_gic_smask(intr); |
7778c4b2 PB |
193 | |
194 | gic_clear_pcpu_masks(intr); | |
d9f82930 | 195 | cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); |
7778c4b2 | 196 | set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 RB |
197 | } |
198 | ||
5561c9e4 AB |
199 | static void gic_ack_irq(struct irq_data *d) |
200 | { | |
e9de688d | 201 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 202 | |
3680746a | 203 | write_gic_wedge(irq); |
5561c9e4 AB |
204 | } |
205 | ||
95150ae8 AB |
206 | static int gic_set_type(struct irq_data *d, unsigned int type) |
207 | { | |
5af3e93e | 208 | unsigned int irq, pol, trig, dual; |
95150ae8 | 209 | unsigned long flags; |
5af3e93e PB |
210 | |
211 | irq = GIC_HWIRQ_TO_SHARED(d->hwirq); | |
95150ae8 AB |
212 | |
213 | spin_lock_irqsave(&gic_lock, flags); | |
214 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
215 | case IRQ_TYPE_EDGE_FALLING: | |
5af3e93e PB |
216 | pol = GIC_POL_FALLING_EDGE; |
217 | trig = GIC_TRIG_EDGE; | |
218 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
219 | break; |
220 | case IRQ_TYPE_EDGE_RISING: | |
5af3e93e PB |
221 | pol = GIC_POL_RISING_EDGE; |
222 | trig = GIC_TRIG_EDGE; | |
223 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
224 | break; |
225 | case IRQ_TYPE_EDGE_BOTH: | |
5af3e93e PB |
226 | pol = 0; /* Doesn't matter */ |
227 | trig = GIC_TRIG_EDGE; | |
228 | dual = GIC_DUAL_DUAL; | |
95150ae8 AB |
229 | break; |
230 | case IRQ_TYPE_LEVEL_LOW: | |
5af3e93e PB |
231 | pol = GIC_POL_ACTIVE_LOW; |
232 | trig = GIC_TRIG_LEVEL; | |
233 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
234 | break; |
235 | case IRQ_TYPE_LEVEL_HIGH: | |
236 | default: | |
5af3e93e PB |
237 | pol = GIC_POL_ACTIVE_HIGH; |
238 | trig = GIC_TRIG_LEVEL; | |
239 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
240 | break; |
241 | } | |
242 | ||
5af3e93e PB |
243 | change_gic_pol(irq, pol); |
244 | change_gic_trig(irq, trig); | |
245 | change_gic_dual(irq, dual); | |
246 | ||
247 | if (trig == GIC_TRIG_EDGE) | |
a595fc51 TG |
248 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, |
249 | handle_edge_irq, NULL); | |
250 | else | |
251 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
252 | handle_level_irq, NULL); | |
95150ae8 | 253 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 254 | |
95150ae8 AB |
255 | return 0; |
256 | } | |
257 | ||
258 | #ifdef CONFIG_SMP | |
161d049e TG |
259 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
260 | bool force) | |
39b8d525 | 261 | { |
e9de688d | 262 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
07df8bfe PB |
263 | unsigned long flags; |
264 | unsigned int cpu; | |
39b8d525 | 265 | |
07df8bfe PB |
266 | cpu = cpumask_first_and(cpumask, cpu_online_mask); |
267 | if (cpu >= NR_CPUS) | |
14d160ab | 268 | return -EINVAL; |
39b8d525 RB |
269 | |
270 | /* Assumption : cpumask refers to a single CPU */ | |
271 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 272 | |
c214c035 | 273 | /* Re-route this IRQ */ |
07df8bfe | 274 | write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); |
c214c035 TW |
275 | |
276 | /* Update the pcpu_masks */ | |
7778c4b2 PB |
277 | gic_clear_pcpu_masks(irq); |
278 | if (read_gic_mask(irq)) | |
07df8bfe | 279 | set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 | 280 | |
18416e45 | 281 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
39b8d525 RB |
282 | spin_unlock_irqrestore(&gic_lock, flags); |
283 | ||
7f15a648 | 284 | return IRQ_SET_MASK_OK; |
39b8d525 RB |
285 | } |
286 | #endif | |
287 | ||
4a6a3ea3 AB |
288 | static struct irq_chip gic_level_irq_controller = { |
289 | .name = "MIPS GIC", | |
290 | .irq_mask = gic_mask_irq, | |
291 | .irq_unmask = gic_unmask_irq, | |
292 | .irq_set_type = gic_set_type, | |
293 | #ifdef CONFIG_SMP | |
294 | .irq_set_affinity = gic_set_affinity, | |
295 | #endif | |
296 | }; | |
297 | ||
298 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 299 | .name = "MIPS GIC", |
5561c9e4 | 300 | .irq_ack = gic_ack_irq, |
161d049e | 301 | .irq_mask = gic_mask_irq, |
161d049e | 302 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 303 | .irq_set_type = gic_set_type, |
39b8d525 | 304 | #ifdef CONFIG_SMP |
161d049e | 305 | .irq_set_affinity = gic_set_affinity, |
39b8d525 | 306 | #endif |
bb11cff3 | 307 | .ipi_send_single = gic_send_ipi, |
39b8d525 RB |
308 | }; |
309 | ||
1b3ed367 | 310 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
311 | { |
312 | unsigned long pending, masked; | |
046a6ee2 | 313 | unsigned int intr; |
e9de688d | 314 | |
9da3c645 PB |
315 | pending = read_gic_vl_pend(); |
316 | masked = read_gic_vl_mask(); | |
e9de688d AB |
317 | |
318 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
319 | ||
0f4ed158 | 320 | for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { |
1b3ed367 | 321 | if (chained) |
046a6ee2 MZ |
322 | generic_handle_domain_irq(gic_irq_domain, |
323 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 | 324 | else |
1fee9db9 MZ |
325 | do_domain_IRQ(gic_irq_domain, |
326 | GIC_LOCAL_TO_HWIRQ(intr)); | |
d7eb4f2e | 327 | } |
e9de688d AB |
328 | } |
329 | ||
330 | static void gic_mask_local_irq(struct irq_data *d) | |
331 | { | |
332 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
333 | ||
9da3c645 | 334 | write_gic_vl_rmask(BIT(intr)); |
e9de688d AB |
335 | } |
336 | ||
337 | static void gic_unmask_local_irq(struct irq_data *d) | |
338 | { | |
339 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
340 | ||
9da3c645 | 341 | write_gic_vl_smask(BIT(intr)); |
e9de688d AB |
342 | } |
343 | ||
344 | static struct irq_chip gic_local_irq_controller = { | |
345 | .name = "MIPS GIC Local", | |
346 | .irq_mask = gic_mask_local_irq, | |
347 | .irq_unmask = gic_unmask_local_irq, | |
348 | }; | |
349 | ||
350 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
351 | { | |
da61fcf9 | 352 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 353 | unsigned long flags; |
da61fcf9 PB |
354 | int intr, cpu; |
355 | ||
356 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
357 | cd = irq_data_get_irq_chip_data(d); | |
358 | cd->mask = false; | |
e9de688d AB |
359 | |
360 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
361 | for_each_online_cpu(cpu) { |
362 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 363 | write_gic_vo_rmask(BIT(intr)); |
e9de688d AB |
364 | } |
365 | spin_unlock_irqrestore(&gic_lock, flags); | |
366 | } | |
367 | ||
368 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
369 | { | |
da61fcf9 | 370 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 371 | unsigned long flags; |
da61fcf9 PB |
372 | int intr, cpu; |
373 | ||
374 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
375 | cd = irq_data_get_irq_chip_data(d); | |
376 | cd->mask = true; | |
e9de688d AB |
377 | |
378 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
379 | for_each_online_cpu(cpu) { |
380 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 381 | write_gic_vo_smask(BIT(intr)); |
e9de688d AB |
382 | } |
383 | spin_unlock_irqrestore(&gic_lock, flags); | |
384 | } | |
385 | ||
dd098a0e | 386 | static void gic_all_vpes_irq_cpu_online(void) |
da61fcf9 | 387 | { |
dd098a0e MZ |
388 | static const unsigned int local_intrs[] = { |
389 | GIC_LOCAL_INT_TIMER, | |
390 | GIC_LOCAL_INT_PERFCTR, | |
391 | GIC_LOCAL_INT_FDC, | |
392 | }; | |
393 | unsigned long flags; | |
394 | int i; | |
da61fcf9 | 395 | |
dd098a0e | 396 | spin_lock_irqsave(&gic_lock, flags); |
da61fcf9 | 397 | |
dd098a0e MZ |
398 | for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { |
399 | unsigned int intr = local_intrs[i]; | |
400 | struct gic_all_vpes_chip_data *cd; | |
401 | ||
402 | cd = &gic_all_vpes_chip_data[intr]; | |
403 | write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); | |
404 | if (cd->mask) | |
405 | write_gic_vl_smask(BIT(intr)); | |
406 | } | |
407 | ||
408 | spin_unlock_irqrestore(&gic_lock, flags); | |
da61fcf9 PB |
409 | } |
410 | ||
e9de688d | 411 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
da61fcf9 PB |
412 | .name = "MIPS GIC Local", |
413 | .irq_mask = gic_mask_local_irq_all_vpes, | |
414 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
e9de688d AB |
415 | }; |
416 | ||
18743d27 | 417 | static void __gic_irq_dispatch(void) |
39b8d525 | 418 | { |
1b3ed367 RV |
419 | gic_handle_local_int(false); |
420 | gic_handle_shared_int(false); | |
18743d27 | 421 | } |
39b8d525 | 422 | |
bd0b9ac4 | 423 | static void gic_irq_dispatch(struct irq_desc *desc) |
18743d27 | 424 | { |
1b3ed367 RV |
425 | gic_handle_local_int(true); |
426 | gic_handle_shared_int(true); | |
18743d27 AB |
427 | } |
428 | ||
e9de688d | 429 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
7778c4b2 | 430 | irq_hw_number_t hw, unsigned int cpu) |
e9de688d AB |
431 | { |
432 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
d9f82930 | 433 | struct irq_data *data; |
c49581a4 AB |
434 | unsigned long flags; |
435 | ||
d9f82930 PB |
436 | data = irq_get_irq_data(virq); |
437 | ||
c49581a4 | 438 | spin_lock_irqsave(&gic_lock, flags); |
d3e8cf44 | 439 | write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); |
7778c4b2 | 440 | write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); |
d9f82930 | 441 | irq_data_update_effective_affinity(data, cpumask_of(cpu)); |
c49581a4 AB |
442 | spin_unlock_irqrestore(&gic_lock, flags); |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
b87281e7 | 447 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
c98c1822 QY |
448 | const u32 *intspec, unsigned int intsize, |
449 | irq_hw_number_t *out_hwirq, | |
450 | unsigned int *out_type) | |
451 | { | |
452 | if (intsize != 3) | |
453 | return -EINVAL; | |
454 | ||
455 | if (intspec[0] == GIC_SHARED) | |
456 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
457 | else if (intspec[0] == GIC_LOCAL) | |
458 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
459 | else | |
460 | return -EINVAL; | |
461 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
8ada00a6 MR |
466 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
467 | irq_hw_number_t hwirq) | |
c98c1822 | 468 | { |
da61fcf9 | 469 | struct gic_all_vpes_chip_data *cd; |
63b746b1 PB |
470 | unsigned long flags; |
471 | unsigned int intr; | |
da61fcf9 | 472 | int err, cpu; |
63b746b1 | 473 | u32 map; |
c98c1822 | 474 | |
8ada00a6 | 475 | if (hwirq >= GIC_SHARED_HWIRQ_BASE) { |
8190cc57 | 476 | #ifdef CONFIG_GENERIC_IRQ_IPI |
b87281e7 PB |
477 | /* verify that shared irqs don't conflict with an IPI irq */ |
478 | if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) | |
479 | return -EBUSY; | |
8190cc57 | 480 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
c98c1822 | 481 | |
b87281e7 PB |
482 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
483 | &gic_level_irq_controller, | |
484 | NULL); | |
485 | if (err) | |
486 | return err; | |
487 | ||
18416e45 | 488 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); |
b87281e7 | 489 | return gic_shared_irq_domain_map(d, virq, hwirq, 0); |
c98c1822 QY |
490 | } |
491 | ||
63b746b1 PB |
492 | intr = GIC_HWIRQ_TO_LOCAL(hwirq); |
493 | map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; | |
494 | ||
dd098a0e | 495 | /* |
915649da | 496 | * If adding support for more per-cpu interrupts, keep the |
dd098a0e MZ |
497 | * array in gic_all_vpes_irq_cpu_online() in sync. |
498 | */ | |
63b746b1 | 499 | switch (intr) { |
b87281e7 PB |
500 | case GIC_LOCAL_INT_TIMER: |
501 | case GIC_LOCAL_INT_PERFCTR: | |
502 | case GIC_LOCAL_INT_FDC: | |
503 | /* | |
504 | * HACK: These are all really percpu interrupts, but | |
505 | * the rest of the MIPS kernel code does not use the | |
506 | * percpu IRQ API for them. | |
507 | */ | |
da61fcf9 PB |
508 | cd = &gic_all_vpes_chip_data[intr]; |
509 | cd->map = map; | |
b87281e7 PB |
510 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
511 | &gic_all_vpes_local_irq_controller, | |
da61fcf9 | 512 | cd); |
b87281e7 PB |
513 | if (err) |
514 | return err; | |
c98c1822 | 515 | |
b87281e7 PB |
516 | irq_set_handler(virq, handle_percpu_irq); |
517 | break; | |
518 | ||
519 | default: | |
520 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, | |
521 | &gic_local_irq_controller, | |
522 | NULL); | |
523 | if (err) | |
524 | return err; | |
525 | ||
526 | irq_set_handler(virq, handle_percpu_devid_irq); | |
527 | irq_set_percpu_devid(virq); | |
528 | break; | |
529 | } | |
530 | ||
63b746b1 PB |
531 | if (!gic_local_irq_is_routable(intr)) |
532 | return -EPERM; | |
533 | ||
534 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
535 | for_each_online_cpu(cpu) { |
536 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
6d4d367d | 537 | write_gic_vo_map(mips_gic_vx_map_reg(intr), map); |
63b746b1 PB |
538 | } |
539 | spin_unlock_irqrestore(&gic_lock, flags); | |
540 | ||
541 | return 0; | |
c98c1822 QY |
542 | } |
543 | ||
8ada00a6 MR |
544 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
545 | unsigned int nr_irqs, void *arg) | |
546 | { | |
547 | struct irq_fwspec *fwspec = arg; | |
548 | irq_hw_number_t hwirq; | |
549 | ||
550 | if (fwspec->param[0] == GIC_SHARED) | |
551 | hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); | |
552 | else | |
553 | hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); | |
554 | ||
555 | return gic_irq_domain_map(d, virq, hwirq); | |
556 | } | |
557 | ||
b87281e7 PB |
558 | void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, |
559 | unsigned int nr_irqs) | |
2564970a | 560 | { |
2564970a PB |
561 | } |
562 | ||
b87281e7 PB |
563 | static const struct irq_domain_ops gic_irq_domain_ops = { |
564 | .xlate = gic_irq_domain_xlate, | |
565 | .alloc = gic_irq_domain_alloc, | |
566 | .free = gic_irq_domain_free, | |
8ada00a6 | 567 | .map = gic_irq_domain_map, |
2af70a96 QY |
568 | }; |
569 | ||
8190cc57 SH |
570 | #ifdef CONFIG_GENERIC_IRQ_IPI |
571 | ||
2af70a96 QY |
572 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
573 | const u32 *intspec, unsigned int intsize, | |
574 | irq_hw_number_t *out_hwirq, | |
575 | unsigned int *out_type) | |
576 | { | |
577 | /* | |
578 | * There's nothing to translate here. hwirq is dynamically allocated and | |
579 | * the irq type is always edge triggered. | |
580 | * */ | |
581 | *out_hwirq = 0; | |
582 | *out_type = IRQ_TYPE_EDGE_RISING; | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, | |
588 | unsigned int nr_irqs, void *arg) | |
589 | { | |
590 | struct cpumask *ipimask = arg; | |
b87281e7 PB |
591 | irq_hw_number_t hwirq, base_hwirq; |
592 | int cpu, ret, i; | |
2af70a96 | 593 | |
b87281e7 PB |
594 | base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); |
595 | if (base_hwirq == gic_shared_intrs) | |
596 | return -ENOMEM; | |
597 | ||
598 | /* check that we have enough space */ | |
599 | for (i = base_hwirq; i < nr_irqs; i++) { | |
600 | if (!test_bit(i, ipi_available)) | |
601 | return -EBUSY; | |
602 | } | |
603 | bitmap_clear(ipi_available, base_hwirq, nr_irqs); | |
604 | ||
605 | /* map the hwirq for each cpu consecutively */ | |
606 | i = 0; | |
607 | for_each_cpu(cpu, ipimask) { | |
608 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); | |
609 | ||
610 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, | |
611 | &gic_edge_irq_controller, | |
612 | NULL); | |
613 | if (ret) | |
614 | goto error; | |
2af70a96 | 615 | |
b87281e7 | 616 | ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, |
2af70a96 QY |
617 | &gic_edge_irq_controller, |
618 | NULL); | |
619 | if (ret) | |
620 | goto error; | |
621 | ||
622 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); | |
623 | if (ret) | |
624 | goto error; | |
b87281e7 PB |
625 | |
626 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); | |
627 | if (ret) | |
628 | goto error; | |
629 | ||
630 | i++; | |
2af70a96 QY |
631 | } |
632 | ||
633 | return 0; | |
634 | error: | |
b87281e7 | 635 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
2af70a96 QY |
636 | return ret; |
637 | } | |
638 | ||
b0e453ff WY |
639 | static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, |
640 | unsigned int nr_irqs) | |
2af70a96 | 641 | { |
b87281e7 PB |
642 | irq_hw_number_t base_hwirq; |
643 | struct irq_data *data; | |
644 | ||
645 | data = irq_get_irq_data(virq); | |
646 | if (!data) | |
647 | return; | |
648 | ||
649 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); | |
650 | bitmap_set(ipi_available, base_hwirq, nr_irqs); | |
2af70a96 QY |
651 | } |
652 | ||
b0e453ff WY |
653 | static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, |
654 | enum irq_domain_bus_token bus_token) | |
2af70a96 QY |
655 | { |
656 | bool is_ipi; | |
657 | ||
658 | switch (bus_token) { | |
659 | case DOMAIN_BUS_IPI: | |
660 | is_ipi = d->bus_token == bus_token; | |
547aefc4 | 661 | return (!node || to_of_node(d->fwnode) == node) && is_ipi; |
2af70a96 QY |
662 | break; |
663 | default: | |
664 | return 0; | |
665 | } | |
666 | } | |
667 | ||
0b7e815a | 668 | static const struct irq_domain_ops gic_ipi_domain_ops = { |
2af70a96 QY |
669 | .xlate = gic_ipi_domain_xlate, |
670 | .alloc = gic_ipi_domain_alloc, | |
671 | .free = gic_ipi_domain_free, | |
672 | .match = gic_ipi_domain_match, | |
c49581a4 AB |
673 | }; |
674 | ||
8190cc57 SH |
675 | static int gic_register_ipi_domain(struct device_node *node) |
676 | { | |
677 | struct irq_domain *gic_ipi_domain; | |
678 | unsigned int v[2], num_ipis; | |
679 | ||
680 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, | |
681 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, | |
682 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
683 | node, &gic_ipi_domain_ops, NULL); | |
684 | if (!gic_ipi_domain) { | |
685 | pr_err("Failed to add IPI domain"); | |
686 | return -ENXIO; | |
687 | } | |
688 | ||
689 | irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); | |
690 | ||
691 | if (node && | |
692 | !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) { | |
693 | bitmap_set(ipi_resrv, v[0], v[1]); | |
694 | } else { | |
695 | /* | |
696 | * Reserve 2 interrupts per possible CPU/VP for use as IPIs, | |
697 | * meeting the requirements of arch/mips SMP. | |
698 | */ | |
699 | num_ipis = 2 * num_possible_cpus(); | |
700 | bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); | |
701 | } | |
702 | ||
703 | bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | #else /* !CONFIG_GENERIC_IRQ_IPI */ | |
709 | ||
710 | static inline int gic_register_ipi_domain(struct device_node *node) | |
711 | { | |
712 | return 0; | |
713 | } | |
714 | ||
715 | #endif /* !CONFIG_GENERIC_IRQ_IPI */ | |
716 | ||
da61fcf9 PB |
717 | static int gic_cpu_startup(unsigned int cpu) |
718 | { | |
890f6b55 PB |
719 | /* Enable or disable EIC */ |
720 | change_gic_vl_ctl(GIC_VX_CTL_EIC, | |
721 | cpu_has_veic ? GIC_VX_CTL_EIC : 0); | |
722 | ||
25ac19e1 PB |
723 | /* Clear all local IRQ masks (ie. disable all local interrupts) */ |
724 | write_gic_vl_rmask(~0); | |
725 | ||
dd098a0e MZ |
726 | /* Enable desired interrupts */ |
727 | gic_all_vpes_irq_cpu_online(); | |
da61fcf9 PB |
728 | |
729 | return 0; | |
730 | } | |
fbea7541 PB |
731 | |
732 | static int __init gic_of_init(struct device_node *node, | |
733 | struct device_node *parent) | |
39b8d525 | 734 | { |
8190cc57 | 735 | unsigned int cpu_vec, i, gicconfig; |
b2b2e584 | 736 | unsigned long reserved; |
fbea7541 PB |
737 | phys_addr_t gic_base; |
738 | struct resource res; | |
739 | size_t gic_len; | |
8190cc57 | 740 | int ret; |
fbea7541 PB |
741 | |
742 | /* Find the first available CPU vector. */ | |
b2b2e584 | 743 | i = 0; |
a08588ea | 744 | reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); |
fbea7541 PB |
745 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", |
746 | i++, &cpu_vec)) | |
747 | reserved |= BIT(cpu_vec); | |
b2b2e584 PB |
748 | |
749 | cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); | |
750 | if (cpu_vec == hweight_long(ST0_IM)) { | |
1f19aee0 | 751 | pr_err("No CPU vectors available\n"); |
fbea7541 PB |
752 | return -ENODEV; |
753 | } | |
754 | ||
755 | if (of_address_to_resource(node, 0, &res)) { | |
756 | /* | |
757 | * Probe the CM for the GIC base address if not specified | |
758 | * in the device-tree. | |
759 | */ | |
760 | if (mips_cm_present()) { | |
761 | gic_base = read_gcr_gic_base() & | |
762 | ~CM_GCR_GIC_BASE_GICEN; | |
763 | gic_len = 0x20000; | |
666740fd MR |
764 | pr_warn("Using inherited base address %pa\n", |
765 | &gic_base); | |
fbea7541 | 766 | } else { |
1f19aee0 | 767 | pr_err("Failed to get memory range\n"); |
fbea7541 PB |
768 | return -ENODEV; |
769 | } | |
770 | } else { | |
771 | gic_base = res.start; | |
772 | gic_len = resource_size(&res); | |
773 | } | |
39b8d525 | 774 | |
fbea7541 PB |
775 | if (mips_cm_present()) { |
776 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); | |
777 | /* Ensure GIC region is enabled before trying to access it */ | |
778 | __sync(); | |
779 | } | |
c0a9f72c | 780 | |
4bdc0d67 | 781 | mips_gic_base = ioremap(gic_base, gic_len); |
71349cc8 WD |
782 | if (!mips_gic_base) { |
783 | pr_err("Failed to ioremap gic_base\n"); | |
784 | return -ENOMEM; | |
785 | } | |
39b8d525 | 786 | |
3680746a | 787 | gicconfig = read_gic_config(); |
357a9c4b | 788 | gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig); |
3680746a | 789 | gic_shared_intrs = (gic_shared_intrs + 1) * 8; |
39b8d525 | 790 | |
18743d27 AB |
791 | if (cpu_has_veic) { |
792 | /* Always use vector 1 in EIC mode */ | |
793 | gic_cpu_pin = 0; | |
794 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, | |
795 | __gic_irq_dispatch); | |
796 | } else { | |
797 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
798 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
799 | gic_irq_dispatch); | |
800 | } | |
801 | ||
a7057270 | 802 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
fbea7541 | 803 | gic_shared_intrs, 0, |
c49581a4 | 804 | &gic_irq_domain_ops, NULL); |
fbea7541 | 805 | if (!gic_irq_domain) { |
1f19aee0 | 806 | pr_err("Failed to add IRQ domain"); |
fbea7541 PB |
807 | return -ENXIO; |
808 | } | |
0b271f56 | 809 | |
8190cc57 SH |
810 | ret = gic_register_ipi_domain(node); |
811 | if (ret) | |
812 | return ret; | |
a7057270 | 813 | |
87888bcb | 814 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
a7057270 | 815 | |
87888bcb PB |
816 | /* Setup defaults */ |
817 | for (i = 0; i < gic_shared_intrs; i++) { | |
818 | change_gic_pol(i, GIC_POL_ACTIVE_HIGH); | |
819 | change_gic_trig(i, GIC_TRIG_LEVEL); | |
90019f8f | 820 | write_gic_rmask(i); |
a7057270 AB |
821 | } |
822 | ||
da61fcf9 PB |
823 | return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, |
824 | "irqchip/mips/gic:starting", | |
825 | gic_cpu_startup, NULL); | |
a7057270 AB |
826 | } |
827 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |