Commit | Line | Data |
---|---|---|
2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
41a83e06 | 14 | #include <linux/irqchip.h> |
4060bbe9 | 15 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 16 | #include <linux/of_address.h> |
18743d27 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
39b8d525 | 19 | |
a7057270 | 20 | #include <asm/mips-cm.h> |
98b67c37 SH |
21 | #include <asm/setup.h> |
22 | #include <asm/traps.h> | |
39b8d525 | 23 | |
a7057270 AB |
24 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
25 | ||
ff86714f | 26 | unsigned int gic_present; |
98b67c37 | 27 | |
822350bc | 28 | struct gic_pcpu_mask { |
fbd55241 | 29 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
30 | }; |
31 | ||
5f68fea0 | 32 | static void __iomem *gic_base; |
0b271f56 | 33 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 34 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 35 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 36 | static int gic_shared_intrs; |
e9de688d | 37 | static int gic_vpes; |
3263d085 | 38 | static unsigned int gic_cpu_pin; |
1b6af71a | 39 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 40 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
39b8d525 | 41 | |
18743d27 AB |
42 | static void __gic_irq_dispatch(void); |
43 | ||
5f68fea0 AB |
44 | static inline unsigned int gic_read(unsigned int reg) |
45 | { | |
46 | return __raw_readl(gic_base + reg); | |
47 | } | |
48 | ||
49 | static inline void gic_write(unsigned int reg, unsigned int val) | |
50 | { | |
51 | __raw_writel(val, gic_base + reg); | |
52 | } | |
53 | ||
54 | static inline void gic_update_bits(unsigned int reg, unsigned int mask, | |
55 | unsigned int val) | |
56 | { | |
57 | unsigned int regval; | |
58 | ||
59 | regval = gic_read(reg); | |
60 | regval &= ~mask; | |
61 | regval |= val; | |
62 | gic_write(reg, regval); | |
63 | } | |
64 | ||
65 | static inline void gic_reset_mask(unsigned int intr) | |
66 | { | |
67 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
68 | 1 << GIC_INTR_BIT(intr)); | |
69 | } | |
70 | ||
71 | static inline void gic_set_mask(unsigned int intr) | |
72 | { | |
73 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
74 | 1 << GIC_INTR_BIT(intr)); | |
75 | } | |
76 | ||
77 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
78 | { | |
79 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
80 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
81 | pol << GIC_INTR_BIT(intr)); | |
82 | } | |
83 | ||
84 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
85 | { | |
86 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
87 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
88 | trig << GIC_INTR_BIT(intr)); | |
89 | } | |
90 | ||
91 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
92 | { | |
93 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
94 | 1 << GIC_INTR_BIT(intr), | |
95 | dual << GIC_INTR_BIT(intr)); | |
96 | } | |
97 | ||
98 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
99 | { | |
100 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + | |
101 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
102 | } | |
103 | ||
104 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
105 | { | |
106 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
107 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
108 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
109 | } | |
110 | ||
a331ce63 | 111 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
112 | cycle_t gic_read_count(void) |
113 | { | |
114 | unsigned int hi, hi2, lo; | |
115 | ||
116 | do { | |
5f68fea0 AB |
117 | hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
118 | lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
119 | hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
120 | } while (hi2 != hi); |
121 | ||
122 | return (((cycle_t) hi) << 32) + lo; | |
123 | } | |
0ab2b7d0 | 124 | |
387904ff AB |
125 | unsigned int gic_get_count_width(void) |
126 | { | |
127 | unsigned int bits, config; | |
128 | ||
5f68fea0 | 129 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
130 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
131 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
132 | ||
133 | return bits; | |
134 | } | |
135 | ||
0ab2b7d0 RG |
136 | void gic_write_compare(cycle_t cnt) |
137 | { | |
5f68fea0 | 138 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
0ab2b7d0 | 139 | (int)(cnt >> 32)); |
5f68fea0 | 140 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
0ab2b7d0 RG |
141 | (int)(cnt & 0xffffffff)); |
142 | } | |
143 | ||
414408d0 PB |
144 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
145 | { | |
146 | unsigned long flags; | |
147 | ||
148 | local_irq_save(flags); | |
149 | ||
5f68fea0 AB |
150 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
151 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
414408d0 | 152 | (int)(cnt >> 32)); |
5f68fea0 | 153 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
414408d0 PB |
154 | (int)(cnt & 0xffffffff)); |
155 | ||
156 | local_irq_restore(flags); | |
157 | } | |
158 | ||
0ab2b7d0 RG |
159 | cycle_t gic_read_compare(void) |
160 | { | |
161 | unsigned int hi, lo; | |
162 | ||
5f68fea0 AB |
163 | hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
164 | lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
165 | |
166 | return (((cycle_t) hi) << 32) + lo; | |
167 | } | |
8fa4b930 MC |
168 | |
169 | void gic_start_count(void) | |
170 | { | |
171 | u32 gicconfig; | |
172 | ||
173 | /* Start the counter */ | |
174 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
175 | gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF); | |
176 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
177 | } | |
178 | ||
179 | void gic_stop_count(void) | |
180 | { | |
181 | u32 gicconfig; | |
182 | ||
183 | /* Stop the counter */ | |
184 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
185 | gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF; | |
186 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
187 | } | |
188 | ||
dfa762e1 SH |
189 | #endif |
190 | ||
e9de688d AB |
191 | static bool gic_local_irq_is_routable(int intr) |
192 | { | |
193 | u32 vpe_ctl; | |
194 | ||
195 | /* All local interrupts are routable in EIC mode. */ | |
196 | if (cpu_has_veic) | |
197 | return true; | |
198 | ||
5f68fea0 | 199 | vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
200 | switch (intr) { |
201 | case GIC_LOCAL_INT_TIMER: | |
202 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
203 | case GIC_LOCAL_INT_PERFCTR: | |
204 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
205 | case GIC_LOCAL_INT_FDC: | |
206 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
207 | case GIC_LOCAL_INT_SWINT0: | |
208 | case GIC_LOCAL_INT_SWINT1: | |
209 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
210 | default: | |
211 | return true; | |
212 | } | |
213 | } | |
214 | ||
3263d085 | 215 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
216 | { |
217 | /* Convert irq vector # to hw int # */ | |
218 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
219 | ||
220 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
221 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
222 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
223 | } |
224 | ||
39b8d525 RB |
225 | void gic_send_ipi(unsigned int intr) |
226 | { | |
53a7bc81 | 227 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
228 | } |
229 | ||
e9de688d AB |
230 | int gic_get_c0_compare_int(void) |
231 | { | |
232 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
233 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
234 | return irq_create_mapping(gic_irq_domain, | |
235 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
236 | } | |
237 | ||
238 | int gic_get_c0_perfcount_int(void) | |
239 | { | |
240 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 241 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
242 | if (cp0_perfcount_irq < 0) |
243 | return -1; | |
244 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
245 | } | |
246 | return irq_create_mapping(gic_irq_domain, | |
247 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
248 | } | |
249 | ||
6429e2b6 JH |
250 | int gic_get_c0_fdc_int(void) |
251 | { | |
252 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
253 | /* Is the FDC IRQ even present? */ | |
254 | if (cp0_fdc_irq < 0) | |
255 | return -1; | |
256 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
257 | } | |
258 | ||
259 | /* | |
260 | * Some cores claim the FDC is routable but it doesn't actually seem to | |
261 | * be connected. | |
262 | */ | |
263 | switch (current_cpu_type()) { | |
264 | case CPU_INTERAPTIV: | |
265 | case CPU_PROAPTIV: | |
266 | return -1; | |
267 | } | |
268 | ||
269 | return irq_create_mapping(gic_irq_domain, | |
270 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
271 | } | |
272 | ||
1b3ed367 | 273 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 274 | { |
d7eb4f2e | 275 | unsigned int i, intr, virq; |
8f5ee79c | 276 | unsigned long *pcpu_mask; |
5f68fea0 | 277 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
278 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
279 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
280 | |
281 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
282 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
283 | ||
824f3f7f AB |
284 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
285 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 286 | |
fbd55241 | 287 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
288 | pending[i] = gic_read(pending_reg); |
289 | intrmask[i] = gic_read(intrmask_reg); | |
290 | pending_reg += 0x4; | |
291 | intrmask_reg += 0x4; | |
39b8d525 RB |
292 | } |
293 | ||
fbd55241 AB |
294 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
295 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 296 | |
d7eb4f2e QY |
297 | intr = find_first_bit(pending, gic_shared_intrs); |
298 | while (intr != gic_shared_intrs) { | |
299 | virq = irq_linear_revmap(gic_irq_domain, | |
300 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
301 | if (chained) |
302 | generic_handle_irq(virq); | |
303 | else | |
304 | do_IRQ(virq); | |
d7eb4f2e QY |
305 | |
306 | /* go to next pending bit */ | |
307 | bitmap_clear(pending, intr, 1); | |
308 | intr = find_first_bit(pending, gic_shared_intrs); | |
309 | } | |
39b8d525 RB |
310 | } |
311 | ||
161d049e | 312 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 313 | { |
5f68fea0 | 314 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
315 | } |
316 | ||
161d049e | 317 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 318 | { |
5f68fea0 | 319 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
320 | } |
321 | ||
5561c9e4 AB |
322 | static void gic_ack_irq(struct irq_data *d) |
323 | { | |
e9de688d | 324 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 325 | |
53a7bc81 | 326 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
327 | } |
328 | ||
95150ae8 AB |
329 | static int gic_set_type(struct irq_data *d, unsigned int type) |
330 | { | |
e9de688d | 331 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
332 | unsigned long flags; |
333 | bool is_edge; | |
334 | ||
335 | spin_lock_irqsave(&gic_lock, flags); | |
336 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
337 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
338 | gic_set_polarity(irq, GIC_POL_NEG); |
339 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
340 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
341 | is_edge = true; |
342 | break; | |
343 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
344 | gic_set_polarity(irq, GIC_POL_POS); |
345 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
346 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
347 | is_edge = true; |
348 | break; | |
349 | case IRQ_TYPE_EDGE_BOTH: | |
350 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
351 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
352 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
353 | is_edge = true; |
354 | break; | |
355 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
356 | gic_set_polarity(irq, GIC_POL_NEG); |
357 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
358 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
359 | is_edge = false; |
360 | break; | |
361 | case IRQ_TYPE_LEVEL_HIGH: | |
362 | default: | |
5f68fea0 AB |
363 | gic_set_polarity(irq, GIC_POL_POS); |
364 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
365 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
366 | is_edge = false; |
367 | break; | |
368 | } | |
369 | ||
370 | if (is_edge) { | |
4a6a3ea3 AB |
371 | __irq_set_chip_handler_name_locked(d->irq, |
372 | &gic_edge_irq_controller, | |
373 | handle_edge_irq, NULL); | |
95150ae8 | 374 | } else { |
4a6a3ea3 AB |
375 | __irq_set_chip_handler_name_locked(d->irq, |
376 | &gic_level_irq_controller, | |
377 | handle_level_irq, NULL); | |
95150ae8 AB |
378 | } |
379 | spin_unlock_irqrestore(&gic_lock, flags); | |
39b8d525 | 380 | |
95150ae8 AB |
381 | return 0; |
382 | } | |
383 | ||
384 | #ifdef CONFIG_SMP | |
161d049e TG |
385 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
386 | bool force) | |
39b8d525 | 387 | { |
e9de688d | 388 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
389 | cpumask_t tmp = CPU_MASK_NONE; |
390 | unsigned long flags; | |
391 | int i; | |
392 | ||
0de26520 | 393 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
f9b531fe | 394 | if (cpumask_empty(&tmp)) |
14d160ab | 395 | return -EINVAL; |
39b8d525 RB |
396 | |
397 | /* Assumption : cpumask refers to a single CPU */ | |
398 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 399 | |
c214c035 | 400 | /* Re-route this IRQ */ |
f9b531fe | 401 | gic_map_to_vpe(irq, cpumask_first(&tmp)); |
c214c035 TW |
402 | |
403 | /* Update the pcpu_masks */ | |
404 | for (i = 0; i < NR_CPUS; i++) | |
405 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
f9b531fe | 406 | set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); |
39b8d525 | 407 | |
161d049e | 408 | cpumask_copy(d->affinity, cpumask); |
39b8d525 RB |
409 | spin_unlock_irqrestore(&gic_lock, flags); |
410 | ||
161d049e | 411 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
412 | } |
413 | #endif | |
414 | ||
4a6a3ea3 AB |
415 | static struct irq_chip gic_level_irq_controller = { |
416 | .name = "MIPS GIC", | |
417 | .irq_mask = gic_mask_irq, | |
418 | .irq_unmask = gic_unmask_irq, | |
419 | .irq_set_type = gic_set_type, | |
420 | #ifdef CONFIG_SMP | |
421 | .irq_set_affinity = gic_set_affinity, | |
422 | #endif | |
423 | }; | |
424 | ||
425 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 426 | .name = "MIPS GIC", |
5561c9e4 | 427 | .irq_ack = gic_ack_irq, |
161d049e | 428 | .irq_mask = gic_mask_irq, |
161d049e | 429 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 430 | .irq_set_type = gic_set_type, |
39b8d525 | 431 | #ifdef CONFIG_SMP |
161d049e | 432 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
433 | #endif |
434 | }; | |
435 | ||
1b3ed367 | 436 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
437 | { |
438 | unsigned long pending, masked; | |
d7eb4f2e | 439 | unsigned int intr, virq; |
e9de688d | 440 | |
5f68fea0 AB |
441 | pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
442 | masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
443 | |
444 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
445 | ||
d7eb4f2e QY |
446 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
447 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
448 | virq = irq_linear_revmap(gic_irq_domain, | |
449 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
450 | if (chained) |
451 | generic_handle_irq(virq); | |
452 | else | |
453 | do_IRQ(virq); | |
d7eb4f2e QY |
454 | |
455 | /* go to next pending bit */ | |
456 | bitmap_clear(&pending, intr, 1); | |
457 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
458 | } | |
e9de688d AB |
459 | } |
460 | ||
461 | static void gic_mask_local_irq(struct irq_data *d) | |
462 | { | |
463 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
464 | ||
5f68fea0 | 465 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
466 | } |
467 | ||
468 | static void gic_unmask_local_irq(struct irq_data *d) | |
469 | { | |
470 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
471 | ||
5f68fea0 | 472 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
473 | } |
474 | ||
475 | static struct irq_chip gic_local_irq_controller = { | |
476 | .name = "MIPS GIC Local", | |
477 | .irq_mask = gic_mask_local_irq, | |
478 | .irq_unmask = gic_unmask_local_irq, | |
479 | }; | |
480 | ||
481 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
482 | { | |
483 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
484 | int i; | |
485 | unsigned long flags; | |
486 | ||
487 | spin_lock_irqsave(&gic_lock, flags); | |
488 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
489 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
490 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); | |
e9de688d AB |
491 | } |
492 | spin_unlock_irqrestore(&gic_lock, flags); | |
493 | } | |
494 | ||
495 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
496 | { | |
497 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
498 | int i; | |
499 | unsigned long flags; | |
500 | ||
501 | spin_lock_irqsave(&gic_lock, flags); | |
502 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
503 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
504 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); | |
e9de688d AB |
505 | } |
506 | spin_unlock_irqrestore(&gic_lock, flags); | |
507 | } | |
508 | ||
509 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
510 | .name = "MIPS GIC Local", | |
511 | .irq_mask = gic_mask_local_irq_all_vpes, | |
512 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
513 | }; | |
514 | ||
18743d27 | 515 | static void __gic_irq_dispatch(void) |
39b8d525 | 516 | { |
1b3ed367 RV |
517 | gic_handle_local_int(false); |
518 | gic_handle_shared_int(false); | |
18743d27 | 519 | } |
39b8d525 | 520 | |
18743d27 AB |
521 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
522 | { | |
1b3ed367 RV |
523 | gic_handle_local_int(true); |
524 | gic_handle_shared_int(true); | |
18743d27 AB |
525 | } |
526 | ||
527 | #ifdef CONFIG_MIPS_GIC_IPI | |
528 | static int gic_resched_int_base; | |
529 | static int gic_call_int_base; | |
530 | ||
531 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
532 | { | |
533 | return gic_resched_int_base + cpu; | |
534 | } | |
39b8d525 | 535 | |
18743d27 AB |
536 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
537 | { | |
538 | return gic_call_int_base + cpu; | |
539 | } | |
39b8d525 | 540 | |
18743d27 AB |
541 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
542 | { | |
543 | scheduler_ipi(); | |
544 | ||
545 | return IRQ_HANDLED; | |
546 | } | |
547 | ||
548 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
549 | { | |
550 | smp_call_function_interrupt(); | |
551 | ||
552 | return IRQ_HANDLED; | |
553 | } | |
b0a88ae5 | 554 | |
18743d27 AB |
555 | static struct irqaction irq_resched = { |
556 | .handler = ipi_resched_interrupt, | |
557 | .flags = IRQF_PERCPU, | |
558 | .name = "IPI resched" | |
559 | }; | |
560 | ||
561 | static struct irqaction irq_call = { | |
562 | .handler = ipi_call_interrupt, | |
563 | .flags = IRQF_PERCPU, | |
564 | .name = "IPI call" | |
565 | }; | |
566 | ||
567 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
568 | struct irqaction *action) | |
569 | { | |
e9de688d AB |
570 | int virq = irq_create_mapping(gic_irq_domain, |
571 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
572 | int i; |
573 | ||
5f68fea0 | 574 | gic_map_to_vpe(intr, cpu); |
c49581a4 AB |
575 | for (i = 0; i < NR_CPUS; i++) |
576 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
577 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
578 | ||
18743d27 AB |
579 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
580 | ||
581 | irq_set_handler(virq, handle_percpu_irq); | |
582 | setup_irq(virq, action); | |
39b8d525 RB |
583 | } |
584 | ||
18743d27 | 585 | static __init void gic_ipi_init(void) |
39b8d525 | 586 | { |
18743d27 AB |
587 | int i; |
588 | ||
589 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 590 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
591 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
592 | ||
593 | for (i = 0; i < nr_cpu_ids; i++) { | |
594 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
595 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
596 | } | |
597 | } | |
598 | #else | |
599 | static inline void gic_ipi_init(void) | |
600 | { | |
601 | } | |
602 | #endif | |
603 | ||
e9de688d | 604 | static void __init gic_basic_init(void) |
18743d27 AB |
605 | { |
606 | unsigned int i; | |
98b67c37 SH |
607 | |
608 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
609 | |
610 | /* Setup defaults */ | |
fbd55241 | 611 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
612 | gic_set_polarity(i, GIC_POL_POS); |
613 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
614 | gic_reset_mask(i); | |
39b8d525 RB |
615 | } |
616 | ||
e9de688d AB |
617 | for (i = 0; i < gic_vpes; i++) { |
618 | unsigned int j; | |
619 | ||
5f68fea0 | 620 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
621 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
622 | if (!gic_local_irq_is_routable(j)) | |
623 | continue; | |
5f68fea0 | 624 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
625 | } |
626 | } | |
39b8d525 RB |
627 | } |
628 | ||
e9de688d AB |
629 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
630 | irq_hw_number_t hw) | |
c49581a4 | 631 | { |
e9de688d AB |
632 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
633 | int ret = 0; | |
634 | int i; | |
635 | unsigned long flags; | |
636 | ||
637 | if (!gic_local_irq_is_routable(intr)) | |
638 | return -EPERM; | |
639 | ||
640 | /* | |
641 | * HACK: These are all really percpu interrupts, but the rest | |
642 | * of the MIPS kernel code does not use the percpu IRQ API for | |
643 | * the CP0 timer and performance counter interrupts. | |
644 | */ | |
b720fd8b JH |
645 | switch (intr) { |
646 | case GIC_LOCAL_INT_TIMER: | |
647 | case GIC_LOCAL_INT_PERFCTR: | |
648 | case GIC_LOCAL_INT_FDC: | |
649 | irq_set_chip_and_handler(virq, | |
650 | &gic_all_vpes_local_irq_controller, | |
651 | handle_percpu_irq); | |
652 | break; | |
653 | default: | |
e9de688d AB |
654 | irq_set_chip_and_handler(virq, |
655 | &gic_local_irq_controller, | |
656 | handle_percpu_devid_irq); | |
657 | irq_set_percpu_devid(virq); | |
b720fd8b | 658 | break; |
e9de688d AB |
659 | } |
660 | ||
661 | spin_lock_irqsave(&gic_lock, flags); | |
662 | for (i = 0; i < gic_vpes; i++) { | |
663 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
664 | ||
5f68fea0 | 665 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
666 | |
667 | switch (intr) { | |
668 | case GIC_LOCAL_INT_WD: | |
5f68fea0 | 669 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
670 | break; |
671 | case GIC_LOCAL_INT_COMPARE: | |
5f68fea0 | 672 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); |
e9de688d AB |
673 | break; |
674 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
675 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
676 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
5f68fea0 | 677 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); |
e9de688d AB |
678 | break; |
679 | case GIC_LOCAL_INT_PERFCTR: | |
5f68fea0 | 680 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); |
e9de688d AB |
681 | break; |
682 | case GIC_LOCAL_INT_SWINT0: | |
5f68fea0 | 683 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); |
e9de688d AB |
684 | break; |
685 | case GIC_LOCAL_INT_SWINT1: | |
5f68fea0 | 686 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); |
e9de688d AB |
687 | break; |
688 | case GIC_LOCAL_INT_FDC: | |
5f68fea0 | 689 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
690 | break; |
691 | default: | |
692 | pr_err("Invalid local IRQ %d\n", intr); | |
693 | ret = -EINVAL; | |
694 | break; | |
695 | } | |
696 | } | |
697 | spin_unlock_irqrestore(&gic_lock, flags); | |
698 | ||
699 | return ret; | |
700 | } | |
701 | ||
702 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
703 | irq_hw_number_t hw) | |
704 | { | |
705 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
706 | unsigned long flags; |
707 | ||
4a6a3ea3 AB |
708 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
709 | handle_level_irq); | |
c49581a4 AB |
710 | |
711 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 712 | gic_map_to_pin(intr, gic_cpu_pin); |
c49581a4 | 713 | /* Map to VPE 0 by default */ |
5f68fea0 | 714 | gic_map_to_vpe(intr, 0); |
e9de688d | 715 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
c49581a4 AB |
716 | spin_unlock_irqrestore(&gic_lock, flags); |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
e9de688d AB |
721 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
722 | irq_hw_number_t hw) | |
723 | { | |
724 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
725 | return gic_local_irq_domain_map(d, virq, hw); | |
726 | return gic_shared_irq_domain_map(d, virq, hw); | |
727 | } | |
728 | ||
a7057270 AB |
729 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
730 | const u32 *intspec, unsigned int intsize, | |
731 | irq_hw_number_t *out_hwirq, | |
732 | unsigned int *out_type) | |
733 | { | |
734 | if (intsize != 3) | |
735 | return -EINVAL; | |
736 | ||
737 | if (intspec[0] == GIC_SHARED) | |
738 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
739 | else if (intspec[0] == GIC_LOCAL) | |
740 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
741 | else | |
742 | return -EINVAL; | |
743 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
96009736 | 748 | static const struct irq_domain_ops gic_irq_domain_ops = { |
c49581a4 | 749 | .map = gic_irq_domain_map, |
a7057270 | 750 | .xlate = gic_irq_domain_xlate, |
c49581a4 AB |
751 | }; |
752 | ||
a7057270 AB |
753 | static void __init __gic_init(unsigned long gic_base_addr, |
754 | unsigned long gic_addrspace_size, | |
755 | unsigned int cpu_vec, unsigned int irqbase, | |
756 | struct device_node *node) | |
39b8d525 RB |
757 | { |
758 | unsigned int gicconfig; | |
759 | ||
5f68fea0 | 760 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 761 | |
5f68fea0 | 762 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 763 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 764 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 765 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 766 | |
e9de688d | 767 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 768 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 769 | gic_vpes = gic_vpes + 1; |
39b8d525 | 770 | |
18743d27 AB |
771 | if (cpu_has_veic) { |
772 | /* Always use vector 1 in EIC mode */ | |
773 | gic_cpu_pin = 0; | |
1b6af71a | 774 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
775 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
776 | __gic_irq_dispatch); | |
777 | } else { | |
778 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
779 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
780 | gic_irq_dispatch); | |
1b6af71a JH |
781 | /* |
782 | * With the CMP implementation of SMP (deprecated), other CPUs | |
783 | * are started by the bootloader and put into a timer based | |
784 | * waiting poll loop. We must not re-route those CPU's local | |
785 | * timer interrupts as the wait instruction will never finish, | |
786 | * so just handle whatever CPU interrupt it is routed to by | |
787 | * default. | |
788 | * | |
789 | * This workaround should be removed when CMP support is | |
790 | * dropped. | |
791 | */ | |
792 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
793 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
794 | timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL, | |
795 | GIC_VPE_TIMER_MAP)) & | |
796 | GIC_MAP_MSK; | |
797 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
798 | GIC_CPU_PIN_OFFSET + | |
799 | timer_cpu_pin, | |
800 | gic_irq_dispatch); | |
801 | } else { | |
802 | timer_cpu_pin = gic_cpu_pin; | |
803 | } | |
18743d27 AB |
804 | } |
805 | ||
a7057270 | 806 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 807 | gic_shared_intrs, irqbase, |
c49581a4 AB |
808 | &gic_irq_domain_ops, NULL); |
809 | if (!gic_irq_domain) | |
810 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 811 | |
e9de688d | 812 | gic_basic_init(); |
18743d27 AB |
813 | |
814 | gic_ipi_init(); | |
39b8d525 | 815 | } |
a7057270 AB |
816 | |
817 | void __init gic_init(unsigned long gic_base_addr, | |
818 | unsigned long gic_addrspace_size, | |
819 | unsigned int cpu_vec, unsigned int irqbase) | |
820 | { | |
821 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
822 | } | |
823 | ||
824 | static int __init gic_of_init(struct device_node *node, | |
825 | struct device_node *parent) | |
826 | { | |
827 | struct resource res; | |
828 | unsigned int cpu_vec, i = 0, reserved = 0; | |
829 | phys_addr_t gic_base; | |
830 | size_t gic_len; | |
831 | ||
832 | /* Find the first available CPU vector. */ | |
833 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
834 | i++, &cpu_vec)) | |
835 | reserved |= BIT(cpu_vec); | |
836 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
837 | if (!(reserved & BIT(cpu_vec))) | |
838 | break; | |
839 | } | |
840 | if (cpu_vec == 8) { | |
841 | pr_err("No CPU vectors available for GIC\n"); | |
842 | return -ENODEV; | |
843 | } | |
844 | ||
845 | if (of_address_to_resource(node, 0, &res)) { | |
846 | /* | |
847 | * Probe the CM for the GIC base address if not specified | |
848 | * in the device-tree. | |
849 | */ | |
850 | if (mips_cm_present()) { | |
851 | gic_base = read_gcr_gic_base() & | |
852 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
853 | gic_len = 0x20000; | |
854 | } else { | |
855 | pr_err("Failed to get GIC memory range\n"); | |
856 | return -ENODEV; | |
857 | } | |
858 | } else { | |
859 | gic_base = res.start; | |
860 | gic_len = resource_size(&res); | |
861 | } | |
862 | ||
863 | if (mips_cm_present()) | |
864 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
865 | gic_present = true; | |
866 | ||
867 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |