Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
1f19aee0 MR |
9 | |
10 | #define pr_fmt(fmt) "irq-mips-gic: " fmt | |
11 | ||
39b8d525 | 12 | #include <linux/bitmap.h> |
fb8f7be1 | 13 | #include <linux/clocksource.h> |
da61fcf9 | 14 | #include <linux/cpuhotplug.h> |
39b8d525 | 15 | #include <linux/init.h> |
18743d27 | 16 | #include <linux/interrupt.h> |
fb8f7be1 | 17 | #include <linux/irq.h> |
41a83e06 | 18 | #include <linux/irqchip.h> |
1982752f | 19 | #include <linux/irqdomain.h> |
a7057270 | 20 | #include <linux/of_address.h> |
aa493737 | 21 | #include <linux/percpu.h> |
18743d27 | 22 | #include <linux/sched.h> |
631330f5 | 23 | #include <linux/smp.h> |
39b8d525 | 24 | |
e83f7e02 | 25 | #include <asm/mips-cps.h> |
98b67c37 SH |
26 | #include <asm/setup.h> |
27 | #include <asm/traps.h> | |
39b8d525 | 28 | |
a7057270 AB |
29 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
30 | ||
b11d4c1f | 31 | #define GIC_MAX_INTRS 256 |
aa493737 | 32 | #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) |
98b67c37 | 33 | |
b11d4c1f PB |
34 | /* Add 2 to convert GIC CPU pin to core interrupt */ |
35 | #define GIC_CPU_PIN_OFFSET 2 | |
36 | ||
37 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ | |
38 | #define GIC_PIN_TO_VEC_OFFSET 1 | |
39 | ||
40 | /* Convert between local/shared IRQ number and GIC HW IRQ number. */ | |
41 | #define GIC_LOCAL_HWIRQ_BASE 0 | |
42 | #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) | |
43 | #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) | |
44 | #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS | |
45 | #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) | |
46 | #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) | |
47 | ||
582e2b4a | 48 | void __iomem *mips_gic_base; |
822350bc | 49 | |
b0e453ff | 50 | static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); |
2af70a96 | 51 | |
95150ae8 | 52 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 53 | static struct irq_domain *gic_irq_domain; |
2af70a96 | 54 | static struct irq_domain *gic_ipi_domain; |
fbd55241 | 55 | static int gic_shared_intrs; |
3263d085 | 56 | static unsigned int gic_cpu_pin; |
1b6af71a | 57 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 58 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
61dc367e PB |
59 | static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
60 | static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); | |
39b8d525 | 61 | |
da61fcf9 PB |
62 | static struct gic_all_vpes_chip_data { |
63 | u32 map; | |
64 | bool mask; | |
65 | } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; | |
66 | ||
7778c4b2 | 67 | static void gic_clear_pcpu_masks(unsigned int intr) |
8fa4b930 | 68 | { |
7778c4b2 | 69 | unsigned int i; |
835d2b45 | 70 | |
7778c4b2 PB |
71 | /* Clear the interrupt's bit in all pcpu_masks */ |
72 | for_each_possible_cpu(i) | |
73 | clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); | |
835d2b45 PB |
74 | } |
75 | ||
e9de688d AB |
76 | static bool gic_local_irq_is_routable(int intr) |
77 | { | |
78 | u32 vpe_ctl; | |
79 | ||
80 | /* All local interrupts are routable in EIC mode. */ | |
81 | if (cpu_has_veic) | |
82 | return true; | |
83 | ||
0d0cf58c | 84 | vpe_ctl = read_gic_vl_ctl(); |
e9de688d AB |
85 | switch (intr) { |
86 | case GIC_LOCAL_INT_TIMER: | |
0d0cf58c | 87 | return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; |
e9de688d | 88 | case GIC_LOCAL_INT_PERFCTR: |
0d0cf58c | 89 | return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; |
e9de688d | 90 | case GIC_LOCAL_INT_FDC: |
0d0cf58c | 91 | return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; |
e9de688d AB |
92 | case GIC_LOCAL_INT_SWINT0: |
93 | case GIC_LOCAL_INT_SWINT1: | |
0d0cf58c | 94 | return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; |
e9de688d AB |
95 | default: |
96 | return true; | |
97 | } | |
98 | } | |
99 | ||
3263d085 | 100 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
101 | { |
102 | /* Convert irq vector # to hw int # */ | |
103 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
104 | ||
105 | /* Set irq to use shadow set */ | |
0d0cf58c | 106 | write_gic_vl_eic_shadow_set(irq, set); |
98b67c37 SH |
107 | } |
108 | ||
bb11cff3 | 109 | static void gic_send_ipi(struct irq_data *d, unsigned int cpu) |
39b8d525 | 110 | { |
bb11cff3 QY |
111 | irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); |
112 | ||
3680746a | 113 | write_gic_wedge(GIC_WEDGE_RW | hwirq); |
39b8d525 RB |
114 | } |
115 | ||
e9de688d AB |
116 | int gic_get_c0_compare_int(void) |
117 | { | |
118 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
119 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
120 | return irq_create_mapping(gic_irq_domain, | |
121 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
122 | } | |
123 | ||
124 | int gic_get_c0_perfcount_int(void) | |
125 | { | |
126 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 127 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
128 | if (cp0_perfcount_irq < 0) |
129 | return -1; | |
130 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
131 | } | |
132 | return irq_create_mapping(gic_irq_domain, | |
133 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
134 | } | |
135 | ||
6429e2b6 JH |
136 | int gic_get_c0_fdc_int(void) |
137 | { | |
138 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
139 | /* Is the FDC IRQ even present? */ | |
140 | if (cp0_fdc_irq < 0) | |
141 | return -1; | |
142 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
143 | } | |
144 | ||
6429e2b6 JH |
145 | return irq_create_mapping(gic_irq_domain, |
146 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
147 | } | |
148 | ||
1b3ed367 | 149 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 150 | { |
046a6ee2 | 151 | unsigned int intr; |
8f5ee79c | 152 | unsigned long *pcpu_mask; |
8f5ee79c | 153 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
39b8d525 RB |
154 | |
155 | /* Get per-cpu bitmaps */ | |
aa493737 | 156 | pcpu_mask = this_cpu_ptr(pcpu_masks); |
d77d5ac9 | 157 | |
7778c4b2 | 158 | if (mips_cm_is64) |
e98fcb2a PB |
159 | __ioread64_copy(pending, addr_gic_pend(), |
160 | DIV_ROUND_UP(gic_shared_intrs, 64)); | |
7778c4b2 | 161 | else |
e98fcb2a PB |
162 | __ioread32_copy(pending, addr_gic_pend(), |
163 | DIV_ROUND_UP(gic_shared_intrs, 32)); | |
39b8d525 | 164 | |
fbd55241 | 165 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); |
39b8d525 | 166 | |
cae750ba | 167 | for_each_set_bit(intr, pending, gic_shared_intrs) { |
1b3ed367 | 168 | if (chained) |
046a6ee2 MZ |
169 | generic_handle_domain_irq(gic_irq_domain, |
170 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 | 171 | else |
046a6ee2 MZ |
172 | do_IRQ(irq_find_mapping(gic_irq_domain, |
173 | GIC_SHARED_TO_HWIRQ(intr))); | |
d7eb4f2e | 174 | } |
39b8d525 RB |
175 | } |
176 | ||
161d049e | 177 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 178 | { |
7778c4b2 PB |
179 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
180 | ||
90019f8f | 181 | write_gic_rmask(intr); |
7778c4b2 | 182 | gic_clear_pcpu_masks(intr); |
39b8d525 RB |
183 | } |
184 | ||
161d049e | 185 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 186 | { |
7778c4b2 PB |
187 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
188 | unsigned int cpu; | |
189 | ||
90019f8f | 190 | write_gic_smask(intr); |
7778c4b2 PB |
191 | |
192 | gic_clear_pcpu_masks(intr); | |
d9f82930 | 193 | cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); |
7778c4b2 | 194 | set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 RB |
195 | } |
196 | ||
5561c9e4 AB |
197 | static void gic_ack_irq(struct irq_data *d) |
198 | { | |
e9de688d | 199 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 200 | |
3680746a | 201 | write_gic_wedge(irq); |
5561c9e4 AB |
202 | } |
203 | ||
95150ae8 AB |
204 | static int gic_set_type(struct irq_data *d, unsigned int type) |
205 | { | |
5af3e93e | 206 | unsigned int irq, pol, trig, dual; |
95150ae8 | 207 | unsigned long flags; |
5af3e93e PB |
208 | |
209 | irq = GIC_HWIRQ_TO_SHARED(d->hwirq); | |
95150ae8 AB |
210 | |
211 | spin_lock_irqsave(&gic_lock, flags); | |
212 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
213 | case IRQ_TYPE_EDGE_FALLING: | |
5af3e93e PB |
214 | pol = GIC_POL_FALLING_EDGE; |
215 | trig = GIC_TRIG_EDGE; | |
216 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
217 | break; |
218 | case IRQ_TYPE_EDGE_RISING: | |
5af3e93e PB |
219 | pol = GIC_POL_RISING_EDGE; |
220 | trig = GIC_TRIG_EDGE; | |
221 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
222 | break; |
223 | case IRQ_TYPE_EDGE_BOTH: | |
5af3e93e PB |
224 | pol = 0; /* Doesn't matter */ |
225 | trig = GIC_TRIG_EDGE; | |
226 | dual = GIC_DUAL_DUAL; | |
95150ae8 AB |
227 | break; |
228 | case IRQ_TYPE_LEVEL_LOW: | |
5af3e93e PB |
229 | pol = GIC_POL_ACTIVE_LOW; |
230 | trig = GIC_TRIG_LEVEL; | |
231 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
232 | break; |
233 | case IRQ_TYPE_LEVEL_HIGH: | |
234 | default: | |
5af3e93e PB |
235 | pol = GIC_POL_ACTIVE_HIGH; |
236 | trig = GIC_TRIG_LEVEL; | |
237 | dual = GIC_DUAL_SINGLE; | |
95150ae8 AB |
238 | break; |
239 | } | |
240 | ||
5af3e93e PB |
241 | change_gic_pol(irq, pol); |
242 | change_gic_trig(irq, trig); | |
243 | change_gic_dual(irq, dual); | |
244 | ||
245 | if (trig == GIC_TRIG_EDGE) | |
a595fc51 TG |
246 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, |
247 | handle_edge_irq, NULL); | |
248 | else | |
249 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
250 | handle_level_irq, NULL); | |
95150ae8 | 251 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 252 | |
95150ae8 AB |
253 | return 0; |
254 | } | |
255 | ||
256 | #ifdef CONFIG_SMP | |
161d049e TG |
257 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
258 | bool force) | |
39b8d525 | 259 | { |
e9de688d | 260 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
07df8bfe PB |
261 | unsigned long flags; |
262 | unsigned int cpu; | |
39b8d525 | 263 | |
07df8bfe PB |
264 | cpu = cpumask_first_and(cpumask, cpu_online_mask); |
265 | if (cpu >= NR_CPUS) | |
14d160ab | 266 | return -EINVAL; |
39b8d525 RB |
267 | |
268 | /* Assumption : cpumask refers to a single CPU */ | |
269 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 270 | |
c214c035 | 271 | /* Re-route this IRQ */ |
07df8bfe | 272 | write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); |
c214c035 TW |
273 | |
274 | /* Update the pcpu_masks */ | |
7778c4b2 PB |
275 | gic_clear_pcpu_masks(irq); |
276 | if (read_gic_mask(irq)) | |
07df8bfe | 277 | set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); |
39b8d525 | 278 | |
18416e45 | 279 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
39b8d525 RB |
280 | spin_unlock_irqrestore(&gic_lock, flags); |
281 | ||
7f15a648 | 282 | return IRQ_SET_MASK_OK; |
39b8d525 RB |
283 | } |
284 | #endif | |
285 | ||
4a6a3ea3 AB |
286 | static struct irq_chip gic_level_irq_controller = { |
287 | .name = "MIPS GIC", | |
288 | .irq_mask = gic_mask_irq, | |
289 | .irq_unmask = gic_unmask_irq, | |
290 | .irq_set_type = gic_set_type, | |
291 | #ifdef CONFIG_SMP | |
292 | .irq_set_affinity = gic_set_affinity, | |
293 | #endif | |
294 | }; | |
295 | ||
296 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 297 | .name = "MIPS GIC", |
5561c9e4 | 298 | .irq_ack = gic_ack_irq, |
161d049e | 299 | .irq_mask = gic_mask_irq, |
161d049e | 300 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 301 | .irq_set_type = gic_set_type, |
39b8d525 | 302 | #ifdef CONFIG_SMP |
161d049e | 303 | .irq_set_affinity = gic_set_affinity, |
39b8d525 | 304 | #endif |
bb11cff3 | 305 | .ipi_send_single = gic_send_ipi, |
39b8d525 RB |
306 | }; |
307 | ||
1b3ed367 | 308 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
309 | { |
310 | unsigned long pending, masked; | |
046a6ee2 | 311 | unsigned int intr; |
e9de688d | 312 | |
9da3c645 PB |
313 | pending = read_gic_vl_pend(); |
314 | masked = read_gic_vl_mask(); | |
e9de688d AB |
315 | |
316 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
317 | ||
0f4ed158 | 318 | for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { |
1b3ed367 | 319 | if (chained) |
046a6ee2 MZ |
320 | generic_handle_domain_irq(gic_irq_domain, |
321 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 | 322 | else |
046a6ee2 MZ |
323 | do_IRQ(irq_find_mapping(gic_irq_domain, |
324 | GIC_LOCAL_TO_HWIRQ(intr))); | |
d7eb4f2e | 325 | } |
e9de688d AB |
326 | } |
327 | ||
328 | static void gic_mask_local_irq(struct irq_data *d) | |
329 | { | |
330 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
331 | ||
9da3c645 | 332 | write_gic_vl_rmask(BIT(intr)); |
e9de688d AB |
333 | } |
334 | ||
335 | static void gic_unmask_local_irq(struct irq_data *d) | |
336 | { | |
337 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
338 | ||
9da3c645 | 339 | write_gic_vl_smask(BIT(intr)); |
e9de688d AB |
340 | } |
341 | ||
342 | static struct irq_chip gic_local_irq_controller = { | |
343 | .name = "MIPS GIC Local", | |
344 | .irq_mask = gic_mask_local_irq, | |
345 | .irq_unmask = gic_unmask_local_irq, | |
346 | }; | |
347 | ||
348 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
349 | { | |
da61fcf9 | 350 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 351 | unsigned long flags; |
da61fcf9 PB |
352 | int intr, cpu; |
353 | ||
354 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
355 | cd = irq_data_get_irq_chip_data(d); | |
356 | cd->mask = false; | |
e9de688d AB |
357 | |
358 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
359 | for_each_online_cpu(cpu) { |
360 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 361 | write_gic_vo_rmask(BIT(intr)); |
e9de688d AB |
362 | } |
363 | spin_unlock_irqrestore(&gic_lock, flags); | |
364 | } | |
365 | ||
366 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
367 | { | |
da61fcf9 | 368 | struct gic_all_vpes_chip_data *cd; |
e9de688d | 369 | unsigned long flags; |
da61fcf9 PB |
370 | int intr, cpu; |
371 | ||
372 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
373 | cd = irq_data_get_irq_chip_data(d); | |
374 | cd->mask = true; | |
e9de688d AB |
375 | |
376 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
377 | for_each_online_cpu(cpu) { |
378 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
9da3c645 | 379 | write_gic_vo_smask(BIT(intr)); |
e9de688d AB |
380 | } |
381 | spin_unlock_irqrestore(&gic_lock, flags); | |
382 | } | |
383 | ||
da61fcf9 PB |
384 | static void gic_all_vpes_irq_cpu_online(struct irq_data *d) |
385 | { | |
386 | struct gic_all_vpes_chip_data *cd; | |
387 | unsigned int intr; | |
388 | ||
389 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
390 | cd = irq_data_get_irq_chip_data(d); | |
391 | ||
6d4d367d | 392 | write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); |
da61fcf9 PB |
393 | if (cd->mask) |
394 | write_gic_vl_smask(BIT(intr)); | |
395 | } | |
396 | ||
e9de688d | 397 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
da61fcf9 PB |
398 | .name = "MIPS GIC Local", |
399 | .irq_mask = gic_mask_local_irq_all_vpes, | |
400 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
401 | .irq_cpu_online = gic_all_vpes_irq_cpu_online, | |
e9de688d AB |
402 | }; |
403 | ||
18743d27 | 404 | static void __gic_irq_dispatch(void) |
39b8d525 | 405 | { |
1b3ed367 RV |
406 | gic_handle_local_int(false); |
407 | gic_handle_shared_int(false); | |
18743d27 | 408 | } |
39b8d525 | 409 | |
bd0b9ac4 | 410 | static void gic_irq_dispatch(struct irq_desc *desc) |
18743d27 | 411 | { |
1b3ed367 RV |
412 | gic_handle_local_int(true); |
413 | gic_handle_shared_int(true); | |
18743d27 AB |
414 | } |
415 | ||
e9de688d | 416 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
7778c4b2 | 417 | irq_hw_number_t hw, unsigned int cpu) |
e9de688d AB |
418 | { |
419 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
d9f82930 | 420 | struct irq_data *data; |
c49581a4 AB |
421 | unsigned long flags; |
422 | ||
d9f82930 PB |
423 | data = irq_get_irq_data(virq); |
424 | ||
c49581a4 | 425 | spin_lock_irqsave(&gic_lock, flags); |
d3e8cf44 | 426 | write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); |
7778c4b2 | 427 | write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); |
d9f82930 | 428 | irq_data_update_effective_affinity(data, cpumask_of(cpu)); |
c49581a4 AB |
429 | spin_unlock_irqrestore(&gic_lock, flags); |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
b87281e7 | 434 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
c98c1822 QY |
435 | const u32 *intspec, unsigned int intsize, |
436 | irq_hw_number_t *out_hwirq, | |
437 | unsigned int *out_type) | |
438 | { | |
439 | if (intsize != 3) | |
440 | return -EINVAL; | |
441 | ||
442 | if (intspec[0] == GIC_SHARED) | |
443 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
444 | else if (intspec[0] == GIC_LOCAL) | |
445 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
446 | else | |
447 | return -EINVAL; | |
448 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
8ada00a6 MR |
453 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
454 | irq_hw_number_t hwirq) | |
c98c1822 | 455 | { |
da61fcf9 | 456 | struct gic_all_vpes_chip_data *cd; |
63b746b1 PB |
457 | unsigned long flags; |
458 | unsigned int intr; | |
da61fcf9 | 459 | int err, cpu; |
63b746b1 | 460 | u32 map; |
c98c1822 | 461 | |
8ada00a6 | 462 | if (hwirq >= GIC_SHARED_HWIRQ_BASE) { |
b87281e7 PB |
463 | /* verify that shared irqs don't conflict with an IPI irq */ |
464 | if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) | |
465 | return -EBUSY; | |
c98c1822 | 466 | |
b87281e7 PB |
467 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
468 | &gic_level_irq_controller, | |
469 | NULL); | |
470 | if (err) | |
471 | return err; | |
472 | ||
18416e45 | 473 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); |
b87281e7 | 474 | return gic_shared_irq_domain_map(d, virq, hwirq, 0); |
c98c1822 QY |
475 | } |
476 | ||
63b746b1 PB |
477 | intr = GIC_HWIRQ_TO_LOCAL(hwirq); |
478 | map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; | |
479 | ||
480 | switch (intr) { | |
b87281e7 | 481 | case GIC_LOCAL_INT_TIMER: |
63b746b1 PB |
482 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
483 | map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin; | |
df561f66 | 484 | fallthrough; |
b87281e7 PB |
485 | case GIC_LOCAL_INT_PERFCTR: |
486 | case GIC_LOCAL_INT_FDC: | |
487 | /* | |
488 | * HACK: These are all really percpu interrupts, but | |
489 | * the rest of the MIPS kernel code does not use the | |
490 | * percpu IRQ API for them. | |
491 | */ | |
da61fcf9 PB |
492 | cd = &gic_all_vpes_chip_data[intr]; |
493 | cd->map = map; | |
b87281e7 PB |
494 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
495 | &gic_all_vpes_local_irq_controller, | |
da61fcf9 | 496 | cd); |
b87281e7 PB |
497 | if (err) |
498 | return err; | |
c98c1822 | 499 | |
b87281e7 PB |
500 | irq_set_handler(virq, handle_percpu_irq); |
501 | break; | |
502 | ||
503 | default: | |
504 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, | |
505 | &gic_local_irq_controller, | |
506 | NULL); | |
507 | if (err) | |
508 | return err; | |
509 | ||
510 | irq_set_handler(virq, handle_percpu_devid_irq); | |
511 | irq_set_percpu_devid(virq); | |
512 | break; | |
513 | } | |
514 | ||
63b746b1 PB |
515 | if (!gic_local_irq_is_routable(intr)) |
516 | return -EPERM; | |
517 | ||
518 | spin_lock_irqsave(&gic_lock, flags); | |
da61fcf9 PB |
519 | for_each_online_cpu(cpu) { |
520 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
6d4d367d | 521 | write_gic_vo_map(mips_gic_vx_map_reg(intr), map); |
63b746b1 PB |
522 | } |
523 | spin_unlock_irqrestore(&gic_lock, flags); | |
524 | ||
525 | return 0; | |
c98c1822 QY |
526 | } |
527 | ||
8ada00a6 MR |
528 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
529 | unsigned int nr_irqs, void *arg) | |
530 | { | |
531 | struct irq_fwspec *fwspec = arg; | |
532 | irq_hw_number_t hwirq; | |
533 | ||
534 | if (fwspec->param[0] == GIC_SHARED) | |
535 | hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); | |
536 | else | |
537 | hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); | |
538 | ||
539 | return gic_irq_domain_map(d, virq, hwirq); | |
540 | } | |
541 | ||
b87281e7 PB |
542 | void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, |
543 | unsigned int nr_irqs) | |
2564970a | 544 | { |
2564970a PB |
545 | } |
546 | ||
b87281e7 PB |
547 | static const struct irq_domain_ops gic_irq_domain_ops = { |
548 | .xlate = gic_irq_domain_xlate, | |
549 | .alloc = gic_irq_domain_alloc, | |
550 | .free = gic_irq_domain_free, | |
8ada00a6 | 551 | .map = gic_irq_domain_map, |
2af70a96 QY |
552 | }; |
553 | ||
554 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | |
555 | const u32 *intspec, unsigned int intsize, | |
556 | irq_hw_number_t *out_hwirq, | |
557 | unsigned int *out_type) | |
558 | { | |
559 | /* | |
560 | * There's nothing to translate here. hwirq is dynamically allocated and | |
561 | * the irq type is always edge triggered. | |
562 | * */ | |
563 | *out_hwirq = 0; | |
564 | *out_type = IRQ_TYPE_EDGE_RISING; | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, | |
570 | unsigned int nr_irqs, void *arg) | |
571 | { | |
572 | struct cpumask *ipimask = arg; | |
b87281e7 PB |
573 | irq_hw_number_t hwirq, base_hwirq; |
574 | int cpu, ret, i; | |
2af70a96 | 575 | |
b87281e7 PB |
576 | base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); |
577 | if (base_hwirq == gic_shared_intrs) | |
578 | return -ENOMEM; | |
579 | ||
580 | /* check that we have enough space */ | |
581 | for (i = base_hwirq; i < nr_irqs; i++) { | |
582 | if (!test_bit(i, ipi_available)) | |
583 | return -EBUSY; | |
584 | } | |
585 | bitmap_clear(ipi_available, base_hwirq, nr_irqs); | |
586 | ||
587 | /* map the hwirq for each cpu consecutively */ | |
588 | i = 0; | |
589 | for_each_cpu(cpu, ipimask) { | |
590 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); | |
591 | ||
592 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, | |
593 | &gic_edge_irq_controller, | |
594 | NULL); | |
595 | if (ret) | |
596 | goto error; | |
2af70a96 | 597 | |
b87281e7 | 598 | ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, |
2af70a96 QY |
599 | &gic_edge_irq_controller, |
600 | NULL); | |
601 | if (ret) | |
602 | goto error; | |
603 | ||
604 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); | |
605 | if (ret) | |
606 | goto error; | |
b87281e7 PB |
607 | |
608 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); | |
609 | if (ret) | |
610 | goto error; | |
611 | ||
612 | i++; | |
2af70a96 QY |
613 | } |
614 | ||
615 | return 0; | |
616 | error: | |
b87281e7 | 617 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
2af70a96 QY |
618 | return ret; |
619 | } | |
620 | ||
b0e453ff WY |
621 | static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, |
622 | unsigned int nr_irqs) | |
2af70a96 | 623 | { |
b87281e7 PB |
624 | irq_hw_number_t base_hwirq; |
625 | struct irq_data *data; | |
626 | ||
627 | data = irq_get_irq_data(virq); | |
628 | if (!data) | |
629 | return; | |
630 | ||
631 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); | |
632 | bitmap_set(ipi_available, base_hwirq, nr_irqs); | |
2af70a96 QY |
633 | } |
634 | ||
b0e453ff WY |
635 | static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, |
636 | enum irq_domain_bus_token bus_token) | |
2af70a96 QY |
637 | { |
638 | bool is_ipi; | |
639 | ||
640 | switch (bus_token) { | |
641 | case DOMAIN_BUS_IPI: | |
642 | is_ipi = d->bus_token == bus_token; | |
547aefc4 | 643 | return (!node || to_of_node(d->fwnode) == node) && is_ipi; |
2af70a96 QY |
644 | break; |
645 | default: | |
646 | return 0; | |
647 | } | |
648 | } | |
649 | ||
0b7e815a | 650 | static const struct irq_domain_ops gic_ipi_domain_ops = { |
2af70a96 QY |
651 | .xlate = gic_ipi_domain_xlate, |
652 | .alloc = gic_ipi_domain_alloc, | |
653 | .free = gic_ipi_domain_free, | |
654 | .match = gic_ipi_domain_match, | |
c49581a4 AB |
655 | }; |
656 | ||
da61fcf9 PB |
657 | static int gic_cpu_startup(unsigned int cpu) |
658 | { | |
890f6b55 PB |
659 | /* Enable or disable EIC */ |
660 | change_gic_vl_ctl(GIC_VX_CTL_EIC, | |
661 | cpu_has_veic ? GIC_VX_CTL_EIC : 0); | |
662 | ||
25ac19e1 PB |
663 | /* Clear all local IRQ masks (ie. disable all local interrupts) */ |
664 | write_gic_vl_rmask(~0); | |
665 | ||
da61fcf9 PB |
666 | /* Invoke irq_cpu_online callbacks to enable desired interrupts */ |
667 | irq_cpu_online(); | |
668 | ||
669 | return 0; | |
670 | } | |
fbea7541 PB |
671 | |
672 | static int __init gic_of_init(struct device_node *node, | |
673 | struct device_node *parent) | |
39b8d525 | 674 | { |
25c51dad | 675 | unsigned int cpu_vec, i, gicconfig, v[2], num_ipis; |
b2b2e584 | 676 | unsigned long reserved; |
fbea7541 PB |
677 | phys_addr_t gic_base; |
678 | struct resource res; | |
679 | size_t gic_len; | |
680 | ||
681 | /* Find the first available CPU vector. */ | |
b2b2e584 | 682 | i = 0; |
a08588ea | 683 | reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); |
fbea7541 PB |
684 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", |
685 | i++, &cpu_vec)) | |
686 | reserved |= BIT(cpu_vec); | |
b2b2e584 PB |
687 | |
688 | cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); | |
689 | if (cpu_vec == hweight_long(ST0_IM)) { | |
1f19aee0 | 690 | pr_err("No CPU vectors available\n"); |
fbea7541 PB |
691 | return -ENODEV; |
692 | } | |
693 | ||
694 | if (of_address_to_resource(node, 0, &res)) { | |
695 | /* | |
696 | * Probe the CM for the GIC base address if not specified | |
697 | * in the device-tree. | |
698 | */ | |
699 | if (mips_cm_present()) { | |
700 | gic_base = read_gcr_gic_base() & | |
701 | ~CM_GCR_GIC_BASE_GICEN; | |
702 | gic_len = 0x20000; | |
666740fd MR |
703 | pr_warn("Using inherited base address %pa\n", |
704 | &gic_base); | |
fbea7541 | 705 | } else { |
1f19aee0 | 706 | pr_err("Failed to get memory range\n"); |
fbea7541 PB |
707 | return -ENODEV; |
708 | } | |
709 | } else { | |
710 | gic_base = res.start; | |
711 | gic_len = resource_size(&res); | |
712 | } | |
39b8d525 | 713 | |
fbea7541 PB |
714 | if (mips_cm_present()) { |
715 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); | |
716 | /* Ensure GIC region is enabled before trying to access it */ | |
717 | __sync(); | |
718 | } | |
c0a9f72c | 719 | |
4bdc0d67 | 720 | mips_gic_base = ioremap(gic_base, gic_len); |
39b8d525 | 721 | |
3680746a PB |
722 | gicconfig = read_gic_config(); |
723 | gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; | |
a08588ea | 724 | gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS); |
3680746a | 725 | gic_shared_intrs = (gic_shared_intrs + 1) * 8; |
39b8d525 | 726 | |
18743d27 AB |
727 | if (cpu_has_veic) { |
728 | /* Always use vector 1 in EIC mode */ | |
729 | gic_cpu_pin = 0; | |
1b6af71a | 730 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
731 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
732 | __gic_irq_dispatch); | |
733 | } else { | |
734 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
735 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
736 | gic_irq_dispatch); | |
1b6af71a JH |
737 | /* |
738 | * With the CMP implementation of SMP (deprecated), other CPUs | |
739 | * are started by the bootloader and put into a timer based | |
740 | * waiting poll loop. We must not re-route those CPU's local | |
741 | * timer interrupts as the wait instruction will never finish, | |
742 | * so just handle whatever CPU interrupt it is routed to by | |
743 | * default. | |
744 | * | |
745 | * This workaround should be removed when CMP support is | |
746 | * dropped. | |
747 | */ | |
748 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
749 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
0d0cf58c | 750 | timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP; |
1b6af71a JH |
751 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + |
752 | GIC_CPU_PIN_OFFSET + | |
753 | timer_cpu_pin, | |
754 | gic_irq_dispatch); | |
755 | } else { | |
756 | timer_cpu_pin = gic_cpu_pin; | |
757 | } | |
18743d27 AB |
758 | } |
759 | ||
a7057270 | 760 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
fbea7541 | 761 | gic_shared_intrs, 0, |
c49581a4 | 762 | &gic_irq_domain_ops, NULL); |
fbea7541 | 763 | if (!gic_irq_domain) { |
1f19aee0 | 764 | pr_err("Failed to add IRQ domain"); |
fbea7541 PB |
765 | return -ENXIO; |
766 | } | |
0b271f56 | 767 | |
2af70a96 QY |
768 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
769 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, | |
770 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
771 | node, &gic_ipi_domain_ops, NULL); | |
fbea7541 | 772 | if (!gic_ipi_domain) { |
1f19aee0 | 773 | pr_err("Failed to add IPI domain"); |
fbea7541 PB |
774 | return -ENXIO; |
775 | } | |
2af70a96 | 776 | |
96f0d93a | 777 | irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); |
2af70a96 | 778 | |
16a8083c QY |
779 | if (node && |
780 | !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) { | |
781 | bitmap_set(ipi_resrv, v[0], v[1]); | |
782 | } else { | |
25c51dad PB |
783 | /* |
784 | * Reserve 2 interrupts per possible CPU/VP for use as IPIs, | |
785 | * meeting the requirements of arch/mips SMP. | |
786 | */ | |
787 | num_ipis = 2 * num_possible_cpus(); | |
788 | bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); | |
16a8083c | 789 | } |
2af70a96 | 790 | |
f8dcd9e8 | 791 | bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); |
a7057270 | 792 | |
87888bcb | 793 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
a7057270 | 794 | |
87888bcb PB |
795 | /* Setup defaults */ |
796 | for (i = 0; i < gic_shared_intrs; i++) { | |
797 | change_gic_pol(i, GIC_POL_ACTIVE_HIGH); | |
798 | change_gic_trig(i, GIC_TRIG_LEVEL); | |
90019f8f | 799 | write_gic_rmask(i); |
a7057270 AB |
800 | } |
801 | ||
da61fcf9 PB |
802 | return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, |
803 | "irqchip/mips/gic:starting", | |
804 | gic_cpu_startup, NULL); | |
a7057270 AB |
805 | } |
806 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |