[linux-2.6-block.git] / drivers / irqchip / irq-ixp4xx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * irqchip for the IXP4xx interrupt controller
 * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on arch/arm/mach-ixp4xx/common.c
 * Copyright 2002 (C) Intel Corporation
 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
 * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
 */
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/irq-ixp4xx.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>

#define IXP4XX_ICPR	0x00 /* Interrupt Status */
#define IXP4XX_ICMR	0x04 /* Interrupt Enable */
#define IXP4XX_ICLR	0x08 /* Interrupt IRQ/FIQ Select */
#define IXP4XX_ICIP	0x0C /* IRQ Status */
#define IXP4XX_ICFP	0x10 /* FIQ Status */
#define IXP4XX_ICHR	0x14 /* Interrupt Priority */
#define IXP4XX_ICIH	0x18 /* IRQ Highest Pri Int */
#define IXP4XX_ICFH	0x1C /* FIQ Highest Pri Int */

/* IXP43x and IXP46x-only */
#define	IXP4XX_ICPR2	0x20 /* Interrupt Status 2 */
#define	IXP4XX_ICMR2	0x24 /* Interrupt Enable 2 */
#define	IXP4XX_ICLR2	0x28 /* Interrupt IRQ/FIQ Select 2 */
#define IXP4XX_ICIP2	0x2C /* IRQ Status */
#define IXP4XX_ICFP2	0x30 /* FIQ Status */
#define IXP4XX_ICEEN	0x34 /* Error High Pri Enable */

/**
 * struct ixp4xx_irq - state container for the Faraday IRQ controller
 * @irqbase: IRQ controller memory base in virtual memory
 * @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
 * @irqchip: irqchip for this instance
 * @domain: IRQ domain for this instance
 */
struct ixp4xx_irq {
	void __iomem *irqbase;
	bool is_356;
	struct irq_chip irqchip;
	struct irq_domain *domain;
};

/* Local static state container */
static struct ixp4xx_irq ixirq;

/* GPIO Clocks */
#define IXP4XX_GPIO_CLK_0		14
#define IXP4XX_GPIO_CLK_1		15

static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
{
	/* All are level active high (asserted) here */
	if (type != IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;
	return 0;
}

static void ixp4xx_irq_mask(struct irq_data *d)
{
	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
	u32 val;

	if (ixi->is_356 && d->hwirq >= 32) {
		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
		val &= ~BIT(d->hwirq - 32);
		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
	} else {
		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
		val &= ~BIT(d->hwirq);
		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
	}
}

/*
 * Level triggered interrupts on GPIO lines can only be cleared when the
 * interrupt condition disappears.
 */
static void ixp4xx_irq_unmask(struct irq_data *d)
{
	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
	u32 val;

	if (ixi->is_356 && d->hwirq >= 32) {
		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
		val |= BIT(d->hwirq - 32);
		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
	} else {
		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
		val |= BIT(d->hwirq);
		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
	}
}

asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
{
	struct ixp4xx_irq *ixi = &ixirq;
	unsigned long status;
	int i;

	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
	for_each_set_bit(i, &status, 32)
		handle_domain_irq(ixi->domain, i, regs);

	/*
	 * IXP465/IXP435 has an upper IRQ status register
	 */
	if (ixi->is_356) {
		status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
		for_each_set_bit(i, &status, 32)
			handle_domain_irq(ixi->domain, i + 32, regs);
	}
}

static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
				       struct irq_fwspec *fwspec,
				       unsigned long *hwirq,
				       unsigned int *type)
{
	/* We support standard DT translation */
	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
		*hwirq = fwspec->param[0];
		*type = fwspec->param[1];
		return 0;
	}

	if (is_fwnode_irqchip(fwspec->fwnode)) {
		if (fwspec->param_count != 2)
			return -EINVAL;
		*hwirq = fwspec->param[0];
		*type = fwspec->param[1];
		WARN_ON(*type == IRQ_TYPE_NONE);
		return 0;
	}

	return -EINVAL;
}

static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
				   unsigned int irq, unsigned int nr_irqs,
				   void *data)
{
	struct ixp4xx_irq *ixi = d->host_data;
	irq_hw_number_t hwirq;
	unsigned int type = IRQ_TYPE_NONE;
	struct irq_fwspec *fwspec = data;
	int ret;
	int i;

	ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++) {
		/*
		 * TODO: after converting IXP4xx to only device tree, set
		 * handle_bad_irq as default handler and assume all consumers
		 * call .set_type() as this is provided in the second cell in
		 * the device tree phandle.
		 */
		irq_domain_set_info(d,
				    irq + i,
				    hwirq + i,
				    &ixi->irqchip,
				    ixi,
				    handle_level_irq,
				    NULL, NULL);
		irq_set_probe(irq + i);
	}

	return 0;
}

/*
 * This needs to be a hierarchical irqdomain to work well with the
 * GPIO irqchip (which is lower in the hierarchy)
 */
static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
	.translate = ixp4xx_irq_domain_translate,
	.alloc = ixp4xx_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
};

/**
 * ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
 *
 * This function will go away when we transition to DT probing.
 */
struct irq_domain *ixp4xx_get_irq_domain(void)
{
	struct ixp4xx_irq *ixi = &ixirq;

	return ixi->domain;
}
EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);

/*
 * This is the Linux IRQ to hwirq mapping table. This goes away when
 * we have DT support as all IRQ resources are defined in the device
 * tree. It will register all the IRQs that are not used by the hierarchical
 * GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
 * the GPIO driver using . This is a step-gap solution.
 */
struct ixp4xx_irq_chunk {
	int irq;
	int hwirq;
	int nr_irqs;
};

static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
	{
		.irq = 16,
		.hwirq = 0,
		.nr_irqs = 6,
	},
	{
		.irq = 24,
		.hwirq = 8,
		.nr_irqs = 11,
	},
	{
		.irq = 46,
		.hwirq = 30,
		.nr_irqs = 2,
	},
	/* Only on the 436 variants */
	{
		.irq = 48,
		.hwirq = 32,
		.nr_irqs = 10,
	},
};

/**
 * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
 * @ixi: State container
 * @irqbase: Virtual memory base for the interrupt controller
 * @fwnode: Corresponding fwnode abstraction for this controller
 * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
 */
static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
				   void __iomem *irqbase,
				   struct fwnode_handle *fwnode,
				   bool is_356)
{
	int nr_irqs;

	ixi->irqbase = irqbase;
	ixi->is_356 = is_356;

	/* Route all sources to IRQ instead of FIQ */
	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);

	/* Disable all interrupts */
	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);

	if (is_356) {
		/* Route upper 32 sources to IRQ instead of FIQ */
		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);

		/* Disable upper 32 interrupts */
		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);

		nr_irqs = 64;
	} else {
		nr_irqs = 32;
	}

	ixi->irqchip.name = "IXP4xx";
	ixi->irqchip.irq_mask = ixp4xx_irq_mask;
	ixi->irqchip.irq_unmask	= ixp4xx_irq_unmask;
	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;

	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
					       &ixp4xx_irqdomain_ops,
					       ixi);
	if (!ixi->domain) {
		pr_crit("IXP4XX: can not add primary irqdomain\n");
		return -ENODEV;
	}

	set_handle_irq(ixp4xx_handle_irq);

	return 0;
}

/**
 * ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
 * @irqbase: physical base for the irq controller
 * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
 */
void __init ixp4xx_irq_init(resource_size_t irqbase,
			    bool is_356)
{
	struct ixp4xx_irq *ixi = &ixirq;
	void __iomem *base;
	struct fwnode_handle *fwnode;
	struct irq_fwspec fwspec;
	int nr_chunks;
	int ret;
	int i;

	base = ioremap(irqbase, 0x100);
	if (!base) {
		pr_crit("IXP4XX: could not ioremap interrupt controller\n");
		return;
	}
	fwnode = irq_domain_alloc_fwnode(&irqbase);
	if (!fwnode) {
		pr_crit("IXP4XX: no domain handle\n");
		return;
	}
	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
	if (ret) {
		pr_crit("IXP4XX: failed to set up irqchip\n");
		irq_domain_free_fwnode(fwnode);
	}

	nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
	if (!is_356)
		nr_chunks--;

	/*
	 * After adding OF support, this is no longer needed: irqs
	 * will be allocated for the respective fwnodes.
	 */
	for (i = 0; i < nr_chunks; i++) {
		const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];

		pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
			chunk->irq, chunk->irq + chunk->nr_irqs - 1,
			chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
		fwspec.fwnode = fwnode;
		fwspec.param[0] = chunk->hwirq;
		fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
		fwspec.param_count = 2;
		ret = __irq_domain_alloc_irqs(ixi->domain,
					      chunk->irq,
					      chunk->nr_irqs,
					      NUMA_NO_NODE,
					      &fwspec,
					      false,
					      NULL);
		if (ret < 0) {
			pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
				ret);
			return;
		}
	}
}
EXPORT_SYMBOL_GPL(ixp4xx_irq_init);

#ifdef CONFIG_OF
int __init ixp4xx_of_init_irq(struct device_node *np,
			      struct device_node *parent)
{
	struct ixp4xx_irq *ixi = &ixirq;
	void __iomem *base;
	struct fwnode_handle *fwnode;
	bool is_356;
	int ret;

	base = of_iomap(np, 0);
	if (!base) {
		pr_crit("IXP4XX: could not ioremap interrupt controller\n");
		return -ENODEV;
	}
	fwnode = of_node_to_fwnode(np);

	/* These chip variants have 64 interrupts */
	is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
		of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
		of_device_is_compatible(np, "intel,ixp46x-interrupt");

	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
	if (ret)
		pr_crit("IXP4XX: failed to set up irqchip\n");

	return ret;
}
IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
		ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
		ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
		ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
		ixp4xx_of_init_irq);
#endif
Commit	Line	Data
5b978c10 LW	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* irqchip for the IXP4xx interrupt controller
	4	* Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
	5	*
	6	* Based on arch/arm/mach-ixp4xx/common.c
	7	* Copyright 2002 (C) Intel Corporation
	8	* Copyright 2003-2004 (C) MontaVista, Software, Inc.
	9	* Copyright (C) Deepak Saxena <dsaxena@plexity.net>
	10	*/
	11	#include <linux/bitops.h>
	12	#include <linux/gpio/driver.h>
	13	#include <linux/irq.h>
	14	#include <linux/io.h>
	15	#include <linux/irqchip.h>
	16	#include <linux/irqchip/irq-ixp4xx.h>
	17	#include <linux/irqdomain.h>
f1497f3d LW	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
5b978c10 LW	21	#include <linux/platform_device.h>
	22	#include <linux/cpu.h>
	23
	24	#include <asm/exception.h>
	25	#include <asm/mach/irq.h>
	26
	27	#define IXP4XX_ICPR 0x00 /* Interrupt Status */
	28	#define IXP4XX_ICMR 0x04 /* Interrupt Enable */
	29	#define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
	30	#define IXP4XX_ICIP 0x0C /* IRQ Status */
	31	#define IXP4XX_ICFP 0x10 /* FIQ Status */
	32	#define IXP4XX_ICHR 0x14 /* Interrupt Priority */
	33	#define IXP4XX_ICIH 0x18 /* IRQ Highest Pri Int */
	34	#define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
	35
	36	/* IXP43x and IXP46x-only */
	37	#define IXP4XX_ICPR2 0x20 /* Interrupt Status 2 */
	38	#define IXP4XX_ICMR2 0x24 /* Interrupt Enable 2 */
	39	#define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
	40	#define IXP4XX_ICIP2 0x2C /* IRQ Status */
	41	#define IXP4XX_ICFP2 0x30 /* FIQ Status */
	42	#define IXP4XX_ICEEN 0x34 /* Error High Pri Enable */
	43
	44	/**
	45	* struct ixp4xx_irq - state container for the Faraday IRQ controller
	46	* @irqbase: IRQ controller memory base in virtual memory
	47	* @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
	48	* @irqchip: irqchip for this instance
	49	* @domain: IRQ domain for this instance
	50	*/
	51	struct ixp4xx_irq {
	52	void __iomem *irqbase;
	53	bool is_356;
	54	struct irq_chip irqchip;
	55	struct irq_domain *domain;
	56	};
	57
	58	/* Local static state container */
	59	static struct ixp4xx_irq ixirq;
	60
	61	/* GPIO Clocks */
	62	#define IXP4XX_GPIO_CLK_0 14
	63	#define IXP4XX_GPIO_CLK_1 15
	64
	65	static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
	66	{
	67	/* All are level active high (asserted) here */
	68	if (type != IRQ_TYPE_LEVEL_HIGH)
	69	return -EINVAL;
	70	return 0;
	71	}
	72
	73	static void ixp4xx_irq_mask(struct irq_data *d)
	74	{
	75	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
	76	u32 val;
	77
	78	if (ixi->is_356 && d->hwirq >= 32) {
	79	val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
	80	val &= ~BIT(d->hwirq - 32);
	81	__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
	82	} else {
	83	val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
	84	val &= ~BIT(d->hwirq);
85	__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
86	}
87	}
88
89	/*
90	* Level triggered interrupts on GPIO lines can only be cleared when the
91	* interrupt condition disappears.
92	*/
93	static void ixp4xx_irq_unmask(struct irq_data *d)
94	{
95	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
96	u32 val;
97
98	if (ixi->is_356 && d->hwirq >= 32) {
99	val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
100	val \|= BIT(d->hwirq - 32);
101	__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
102	} else {
103	val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
104	val \|= BIT(d->hwirq);
105	__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
106	}
107	}
108
109	asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
110	{
111	struct ixp4xx_irq *ixi = &ixirq;
112	unsigned long status;
113	int i;
114
115	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
116	for_each_set_bit(i, &status, 32)
117	handle_domain_irq(ixi->domain, i, regs);
118
119	/*
120	* IXP465/IXP435 has an upper IRQ status register
121	*/
122	if (ixi->is_356) {
123	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
124	for_each_set_bit(i, &status, 32)
125	handle_domain_irq(ixi->domain, i + 32, regs);
126	}
127	}
128
129	static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
130	struct irq_fwspec *fwspec,
131	unsigned long *hwirq,
132	unsigned int *type)
133	{
134	/* We support standard DT translation */
135	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
136	*hwirq = fwspec->param[0];
137	*type = fwspec->param[1];
138	return 0;
139	}
140
141	if (is_fwnode_irqchip(fwspec->fwnode)) {
142	if (fwspec->param_count != 2)
143	return -EINVAL;
144	*hwirq = fwspec->param[0];
145	*type = fwspec->param[1];
146	WARN_ON(*type == IRQ_TYPE_NONE);
147	return 0;
148	}
149
150	return -EINVAL;
151	}
152
153	static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
154	unsigned int irq, unsigned int nr_irqs,
155	void *data)
156	{
157	struct ixp4xx_irq *ixi = d->host_data;
158	irq_hw_number_t hwirq;
159	unsigned int type = IRQ_TYPE_NONE;
160	struct irq_fwspec *fwspec = data;
161	int ret;
162	int i;
163
164	ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
165	if (ret)
166	return ret;
167
168	for (i = 0; i < nr_irqs; i++) {
169	/*
170	* TODO: after converting IXP4xx to only device tree, set
171	* handle_bad_irq as default handler and assume all consumers
172	* call .set_type() as this is provided in the second cell in
173	* the device tree phandle.
174	*/
175	irq_domain_set_info(d,
176	irq + i,
177	hwirq + i,
178	&ixi->irqchip,
179	ixi,
180	handle_level_irq,
181	NULL, NULL);
182	irq_set_probe(irq + i);
183	}
184
185	return 0;
186	}
187
188	/*
189	* This needs to be a hierarchical irqdomain to work well with the
190	* GPIO irqchip (which is lower in the hierarchy)
191	*/
192	static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
193	.translate = ixp4xx_irq_domain_translate,
194	.alloc = ixp4xx_irq_domain_alloc,
195	.free = irq_domain_free_irqs_common,
196	};
197
198	/**
199	* ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
200	*
201	* This function will go away when we transition to DT probing.
202	*/
203	struct irq_domain *ixp4xx_get_irq_domain(void)
204	{
205	struct ixp4xx_irq *ixi = &ixirq;
206
207	return ixi->domain;
208	}
209	EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);
210
211	/*
212	* This is the Linux IRQ to hwirq mapping table. This goes away when
213	* we have DT support as all IRQ resources are defined in the device
214	* tree. It will register all the IRQs that are not used by the hierarchical
215	* GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
216	* the GPIO driver using . This is a step-gap solution.
217	*/
218	struct ixp4xx_irq_chunk {
219	int irq;
220	int hwirq;
221	int nr_irqs;
222	};
223
224	static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
225	{
226	.irq = 16,
227	.hwirq = 0,
228	.nr_irqs = 6,
229	},
230	{
231	.irq = 24,
232	.hwirq = 8,
233	.nr_irqs = 11,
234	},
235	{
236	.irq = 46,
237	.hwirq = 30,
238	.nr_irqs = 2,
239	},
240	/* Only on the 436 variants */
241	{
242	.irq = 48,
243	.hwirq = 32,
244	.nr_irqs = 10,
245	},
246	};
247
248	/**
249	* ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
250	* @ixi: State container
251	* @irqbase: Virtual memory base for the interrupt controller
252	* @fwnode: Corresponding fwnode abstraction for this controller
253	* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
254	*/
4ea10150 AB	255	static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
	256	void __iomem *irqbase,
	257	struct fwnode_handle *fwnode,
	258	bool is_356)
5b978c10 LW	259	{
	260	int nr_irqs;
	261
	262	ixi->irqbase = irqbase;
	263	ixi->is_356 = is_356;
	264
	265	/* Route all sources to IRQ instead of FIQ */
	266	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
	267
	268	/* Disable all interrupts */
	269	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
	270
	271	if (is_356) {
	272	/* Route upper 32 sources to IRQ instead of FIQ */
	273	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
	274
	275	/* Disable upper 32 interrupts */
	276	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
	277
	278	nr_irqs = 64;
	279	} else {
	280	nr_irqs = 32;
	281	}
	282
	283	ixi->irqchip.name = "IXP4xx";
	284	ixi->irqchip.irq_mask = ixp4xx_irq_mask;
	285	ixi->irqchip.irq_unmask = ixp4xx_irq_unmask;
	286	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
	287
	288	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
	289	&ixp4xx_irqdomain_ops,
	290	ixi);
	291	if (!ixi->domain) {
	292	pr_crit("IXP4XX: can not add primary irqdomain\n");
	293	return -ENODEV;
	294	}
	295
	296	set_handle_irq(ixp4xx_handle_irq);
	297
	298	return 0;
	299	}
	300
	301	/**
	302	* ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
	303	* @irqbase: physical base for the irq controller
	304	* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
	305	*/
	306	void __init ixp4xx_irq_init(resource_size_t irqbase,
	307	bool is_356)
	308	{
	309	struct ixp4xx_irq *ixi = &ixirq;
	310	void __iomem *base;
	311	struct fwnode_handle *fwnode;
	312	struct irq_fwspec fwspec;
	313	int nr_chunks;
	314	int ret;
	315	int i;
	316
	317	base = ioremap(irqbase, 0x100);
	318	if (!base) {
	319	pr_crit("IXP4XX: could not ioremap interrupt controller\n");
	320	return;
	321	}
9adc54d4	322	fwnode = irq_domain_alloc_fwnode(&irqbase);
5b978c10 LW	323	if (!fwnode) {
	324	pr_crit("IXP4XX: no domain handle\n");
	325	return;
	326	}
	327	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
	328	if (ret) {
	329	pr_crit("IXP4XX: failed to set up irqchip\n");
	330	irq_domain_free_fwnode(fwnode);
	331	}
	332
	333	nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
	334	if (!is_356)
	335	nr_chunks--;
	336
	337	/*
	338	* After adding OF support, this is no longer needed: irqs
	339	* will be allocated for the respective fwnodes.
	340	*/
	341	for (i = 0; i < nr_chunks; i++) {
	342	const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];
	343
	344	pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
	345	chunk->irq, chunk->irq + chunk->nr_irqs - 1,
	346	chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
	347	fwspec.fwnode = fwnode;
	348	fwspec.param[0] = chunk->hwirq;
	349	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
	350	fwspec.param_count = 2;
	351	ret = __irq_domain_alloc_irqs(ixi->domain,
	352	chunk->irq,
	353	chunk->nr_irqs,
	354	NUMA_NO_NODE,
	355	&fwspec,
	356	false,
	357	NULL);
	358	if (ret < 0) {
	359	pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
	360	ret);
	361	return;
	362	}
	363	}
	364	}
	365	EXPORT_SYMBOL_GPL(ixp4xx_irq_init);
f1497f3d LW	366
	367	#ifdef CONFIG_OF
	368	int __init ixp4xx_of_init_irq(struct device_node *np,
	369	struct device_node *parent)
	370	{
	371	struct ixp4xx_irq *ixi = &ixirq;
	372	void __iomem *base;
	373	struct fwnode_handle *fwnode;
	374	bool is_356;
	375	int ret;
	376
	377	base = of_iomap(np, 0);
	378	if (!base) {
	379	pr_crit("IXP4XX: could not ioremap interrupt controller\n");
	380	return -ENODEV;
	381	}
	382	fwnode = of_node_to_fwnode(np);
	383
	384	/* These chip variants have 64 interrupts */
	385	is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") \|\|
	386	of_device_is_compatible(np, "intel,ixp45x-interrupt") \|\|
	387	of_device_is_compatible(np, "intel,ixp46x-interrupt");
	388
	389	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
	390	if (ret)
	391	pr_crit("IXP4XX: failed to set up irqchip\n");
	392
	393	return ret;
	394	}
	395	IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
	396	ixp4xx_of_init_irq);
	397	IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
	398	ixp4xx_of_init_irq);
	399	IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
	400	ixp4xx_of_init_irq);
	401	IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
	402	ixp4xx_of_init_irq);
	403	#endif