Commit | Line | Data |
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a912e80b | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9869848d LPC |
2 | /* |
3 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
4 | * JZ4740 platform IRQ support | |
9869848d LPC |
5 | */ |
6 | ||
7 | #include <linux/errno.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/types.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/ioport.h> | |
41a83e06 | 12 | #include <linux/irqchip.h> |
44e08e70 | 13 | #include <linux/irqchip/ingenic.h> |
3aa94590 | 14 | #include <linux/of_address.h> |
adbdce77 | 15 | #include <linux/of_irq.h> |
9869848d LPC |
16 | #include <linux/timex.h> |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | ||
9869848d | 20 | #include <asm/io.h> |
942e22df BN |
21 | #include <asm/mach-jz4740/irq.h> |
22 | ||
fe778ece PB |
23 | struct ingenic_intc_data { |
24 | void __iomem *base; | |
943d69c6 | 25 | unsigned num_chips; |
fe778ece | 26 | }; |
9869848d LPC |
27 | |
28 | #define JZ_REG_INTC_STATUS 0x00 | |
29 | #define JZ_REG_INTC_MASK 0x04 | |
30 | #define JZ_REG_INTC_SET_MASK 0x08 | |
31 | #define JZ_REG_INTC_CLEAR_MASK 0x0c | |
32 | #define JZ_REG_INTC_PENDING 0x10 | |
943d69c6 | 33 | #define CHIP_SIZE 0x20 |
9869848d | 34 | |
2da01884 | 35 | static irqreturn_t intc_cascade(int irq, void *data) |
9869848d | 36 | { |
fe778ece | 37 | struct ingenic_intc_data *intc = irq_get_handler_data(irq); |
83bc7692 | 38 | uint32_t irq_reg; |
943d69c6 | 39 | unsigned i; |
9869848d | 40 | |
943d69c6 PB |
41 | for (i = 0; i < intc->num_chips; i++) { |
42 | irq_reg = readl(intc->base + (i * CHIP_SIZE) + | |
43 | JZ_REG_INTC_PENDING); | |
44 | if (!irq_reg) | |
45 | continue; | |
9869848d | 46 | |
943d69c6 PB |
47 | generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE); |
48 | } | |
83bc7692 LPC |
49 | |
50 | return IRQ_HANDLED; | |
42b64f38 TG |
51 | } |
52 | ||
2da01884 | 53 | static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) |
9869848d | 54 | { |
83bc7692 | 55 | struct irq_chip_regs *regs = &gc->chip_types->regs; |
9869848d | 56 | |
83bc7692 LPC |
57 | writel(mask, gc->reg_base + regs->enable); |
58 | writel(~mask, gc->reg_base + regs->disable); | |
9869848d LPC |
59 | } |
60 | ||
2da01884 | 61 | void ingenic_intc_irq_suspend(struct irq_data *data) |
9869848d | 62 | { |
83bc7692 | 63 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
2da01884 | 64 | intc_irq_set_mask(gc, gc->wake_active); |
83bc7692 | 65 | } |
9869848d | 66 | |
2da01884 | 67 | void ingenic_intc_irq_resume(struct irq_data *data) |
83bc7692 LPC |
68 | { |
69 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); | |
2da01884 | 70 | intc_irq_set_mask(gc, gc->mask_cache); |
9869848d LPC |
71 | } |
72 | ||
2da01884 PB |
73 | static struct irqaction intc_cascade_action = { |
74 | .handler = intc_cascade, | |
75 | .name = "SoC intc cascade interrupt", | |
9869848d LPC |
76 | }; |
77 | ||
943d69c6 PB |
78 | static int __init ingenic_intc_of_init(struct device_node *node, |
79 | unsigned num_chips) | |
9869848d | 80 | { |
fe778ece | 81 | struct ingenic_intc_data *intc; |
83bc7692 LPC |
82 | struct irq_chip_generic *gc; |
83 | struct irq_chip_type *ct; | |
638c8851 | 84 | struct irq_domain *domain; |
fe778ece | 85 | int parent_irq, err = 0; |
943d69c6 | 86 | unsigned i; |
fe778ece PB |
87 | |
88 | intc = kzalloc(sizeof(*intc), GFP_KERNEL); | |
89 | if (!intc) { | |
90 | err = -ENOMEM; | |
91 | goto out_err; | |
92 | } | |
69ce4b22 PB |
93 | |
94 | parent_irq = irq_of_parse_and_map(node, 0); | |
fe778ece PB |
95 | if (!parent_irq) { |
96 | err = -EINVAL; | |
97 | goto out_free; | |
98 | } | |
83bc7692 | 99 | |
fe778ece PB |
100 | err = irq_set_handler_data(parent_irq, intc); |
101 | if (err) | |
102 | goto out_unmap_irq; | |
103 | ||
943d69c6 | 104 | intc->num_chips = num_chips; |
3aa94590 PB |
105 | intc->base = of_iomap(node, 0); |
106 | if (!intc->base) { | |
107 | err = -ENODEV; | |
108 | goto out_unmap_irq; | |
109 | } | |
9869848d | 110 | |
943d69c6 PB |
111 | for (i = 0; i < num_chips; i++) { |
112 | /* Mask all irqs */ | |
113 | writel(0xffffffff, intc->base + (i * CHIP_SIZE) + | |
114 | JZ_REG_INTC_SET_MASK); | |
115 | ||
116 | gc = irq_alloc_generic_chip("INTC", 1, | |
117 | JZ4740_IRQ_BASE + (i * 32), | |
118 | intc->base + (i * CHIP_SIZE), | |
119 | handle_level_irq); | |
120 | ||
121 | gc->wake_enabled = IRQ_MSK(32); | |
122 | ||
123 | ct = gc->chip_types; | |
124 | ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; | |
125 | ct->regs.disable = JZ_REG_INTC_SET_MASK; | |
126 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
127 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
128 | ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; | |
129 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
2da01884 PB |
130 | ct->chip.irq_suspend = ingenic_intc_irq_suspend; |
131 | ct->chip.irq_resume = ingenic_intc_irq_resume; | |
943d69c6 PB |
132 | |
133 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, | |
134 | IRQ_NOPROBE | IRQ_LEVEL); | |
135 | } | |
9869848d | 136 | |
638c8851 PB |
137 | domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0, |
138 | &irq_domain_simple_ops, NULL); | |
139 | if (!domain) | |
140 | pr_warn("unable to register IRQ domain\n"); | |
141 | ||
2da01884 | 142 | setup_irq(parent_irq, &intc_cascade_action); |
adbdce77 | 143 | return 0; |
fe778ece PB |
144 | |
145 | out_unmap_irq: | |
146 | irq_dispose_mapping(parent_irq); | |
147 | out_free: | |
148 | kfree(intc); | |
149 | out_err: | |
150 | return err; | |
9869848d | 151 | } |
943d69c6 PB |
152 | |
153 | static int __init intc_1chip_of_init(struct device_node *node, | |
154 | struct device_node *parent) | |
155 | { | |
156 | return ingenic_intc_of_init(node, 1); | |
157 | } | |
158 | IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); | |
1047557c | 159 | IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init); |
24ccfa06 PB |
160 | |
161 | static int __init intc_2chip_of_init(struct device_node *node, | |
162 | struct device_node *parent) | |
163 | { | |
164 | return ingenic_intc_of_init(node, 2); | |
165 | } | |
166 | IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); | |
167 | IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); | |
168 | IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); |