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0136afa0 LS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright 2017 NXP | |
4 | * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> | |
5 | */ | |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/irq.h> | |
10 | #include <linux/irqchip/chained_irq.h> | |
11 | #include <linux/irqdomain.h> | |
12 | #include <linux/kernel.h> | |
28528fca | 13 | #include <linux/of_irq.h> |
0136afa0 | 14 | #include <linux/of_platform.h> |
4730d223 | 15 | #include <linux/pm_runtime.h> |
0136afa0 LS |
16 | #include <linux/spinlock.h> |
17 | ||
deb904e4 | 18 | #define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r) |
0136afa0 LS |
19 | #define CHANCTRL 0x0 |
20 | #define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4) | |
21 | #define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4) | |
22 | #define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4) | |
23 | #define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4) | |
24 | #define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8) | |
25 | ||
28528fca AD |
26 | #define CHAN_MAX_OUTPUT_INT 0x8 |
27 | ||
0136afa0 LS |
28 | struct irqsteer_data { |
29 | void __iomem *regs; | |
30 | struct clk *ipg_clk; | |
28528fca AD |
31 | int irq[CHAN_MAX_OUTPUT_INT]; |
32 | int irq_count; | |
0136afa0 | 33 | raw_spinlock_t lock; |
deb904e4 | 34 | int reg_num; |
0136afa0 LS |
35 | int channel; |
36 | struct irq_domain *domain; | |
37 | u32 *saved_reg; | |
38 | }; | |
39 | ||
40 | static int imx_irqsteer_get_reg_index(struct irqsteer_data *data, | |
41 | unsigned long irqnum) | |
42 | { | |
deb904e4 | 43 | return (data->reg_num - irqnum / 32 - 1); |
0136afa0 LS |
44 | } |
45 | ||
46 | static void imx_irqsteer_irq_unmask(struct irq_data *d) | |
47 | { | |
48 | struct irqsteer_data *data = d->chip_data; | |
49 | int idx = imx_irqsteer_get_reg_index(data, d->hwirq); | |
50 | unsigned long flags; | |
51 | u32 val; | |
52 | ||
53 | raw_spin_lock_irqsave(&data->lock, flags); | |
deb904e4 | 54 | val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); |
0136afa0 | 55 | val |= BIT(d->hwirq % 32); |
deb904e4 | 56 | writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); |
0136afa0 LS |
57 | raw_spin_unlock_irqrestore(&data->lock, flags); |
58 | } | |
59 | ||
60 | static void imx_irqsteer_irq_mask(struct irq_data *d) | |
61 | { | |
62 | struct irqsteer_data *data = d->chip_data; | |
63 | int idx = imx_irqsteer_get_reg_index(data, d->hwirq); | |
64 | unsigned long flags; | |
65 | u32 val; | |
66 | ||
67 | raw_spin_lock_irqsave(&data->lock, flags); | |
deb904e4 | 68 | val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); |
0136afa0 | 69 | val &= ~BIT(d->hwirq % 32); |
deb904e4 | 70 | writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); |
0136afa0 LS |
71 | raw_spin_unlock_irqrestore(&data->lock, flags); |
72 | } | |
73 | ||
e9a50f12 | 74 | static const struct irq_chip imx_irqsteer_irq_chip = { |
0136afa0 LS |
75 | .name = "irqsteer", |
76 | .irq_mask = imx_irqsteer_irq_mask, | |
77 | .irq_unmask = imx_irqsteer_irq_unmask, | |
78 | }; | |
79 | ||
80 | static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq, | |
81 | irq_hw_number_t hwirq) | |
82 | { | |
83 | irq_set_status_flags(irq, IRQ_LEVEL); | |
84 | irq_set_chip_data(irq, h->host_data); | |
85 | irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static const struct irq_domain_ops imx_irqsteer_domain_ops = { | |
91 | .map = imx_irqsteer_irq_map, | |
92 | .xlate = irq_domain_xlate_onecell, | |
93 | }; | |
94 | ||
28528fca AD |
95 | static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq) |
96 | { | |
97 | int i; | |
98 | ||
99 | for (i = 0; i < data->irq_count; i++) { | |
100 | if (data->irq[i] == irq) | |
101 | return i * 64; | |
102 | } | |
103 | ||
104 | return -EINVAL; | |
105 | } | |
106 | ||
0136afa0 LS |
107 | static void imx_irqsteer_irq_handler(struct irq_desc *desc) |
108 | { | |
109 | struct irqsteer_data *data = irq_desc_get_handler_data(desc); | |
28528fca AD |
110 | int hwirq; |
111 | int irq, i; | |
0136afa0 LS |
112 | |
113 | chained_irq_enter(irq_desc_get_chip(desc), desc); | |
114 | ||
28528fca AD |
115 | irq = irq_desc_get_irq(desc); |
116 | hwirq = imx_irqsteer_get_hwirq_base(data, irq); | |
117 | if (hwirq < 0) { | |
118 | pr_warn("%s: unable to get hwirq base for irq %d\n", | |
119 | __func__, irq); | |
120 | return; | |
121 | } | |
122 | ||
123 | for (i = 0; i < 2; i++, hwirq += 32) { | |
124 | int idx = imx_irqsteer_get_reg_index(data, hwirq); | |
0136afa0 | 125 | unsigned long irqmap; |
046a6ee2 | 126 | int pos; |
0136afa0 | 127 | |
28528fca AD |
128 | if (hwirq >= data->reg_num * 32) |
129 | break; | |
130 | ||
0136afa0 | 131 | irqmap = readl_relaxed(data->regs + |
deb904e4 | 132 | CHANSTATUS(idx, data->reg_num)); |
0136afa0 | 133 | |
046a6ee2 MZ |
134 | for_each_set_bit(pos, &irqmap, 32) |
135 | generic_handle_domain_irq(data->domain, pos + hwirq); | |
0136afa0 LS |
136 | } |
137 | ||
138 | chained_irq_exit(irq_desc_get_chip(desc), desc); | |
139 | } | |
140 | ||
141 | static int imx_irqsteer_probe(struct platform_device *pdev) | |
142 | { | |
143 | struct device_node *np = pdev->dev.of_node; | |
144 | struct irqsteer_data *data; | |
28528fca AD |
145 | u32 irqs_num; |
146 | int i, ret; | |
0136afa0 LS |
147 | |
148 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
149 | if (!data) | |
150 | return -ENOMEM; | |
151 | ||
358b9d24 | 152 | data->regs = devm_platform_ioremap_resource(pdev, 0); |
0136afa0 LS |
153 | if (IS_ERR(data->regs)) { |
154 | dev_err(&pdev->dev, "failed to initialize reg\n"); | |
155 | return PTR_ERR(data->regs); | |
156 | } | |
157 | ||
0136afa0 | 158 | data->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); |
e0c45b10 AH |
159 | if (IS_ERR(data->ipg_clk)) |
160 | return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk), | |
161 | "failed to get ipg clk\n"); | |
0136afa0 LS |
162 | |
163 | raw_spin_lock_init(&data->lock); | |
164 | ||
7d3a5eb7 AB |
165 | ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num); |
166 | if (ret) | |
167 | return ret; | |
168 | ret = of_property_read_u32(np, "fsl,channel", &data->channel); | |
169 | if (ret) | |
170 | return ret; | |
0136afa0 | 171 | |
28528fca AD |
172 | /* |
173 | * There is one output irq for each group of 64 inputs. | |
174 | * One register bit map can represent 32 input interrupts. | |
175 | */ | |
176 | data->irq_count = DIV_ROUND_UP(irqs_num, 64); | |
177 | data->reg_num = irqs_num / 32; | |
deb904e4 | 178 | |
4730d223 | 179 | if (IS_ENABLED(CONFIG_PM)) { |
0136afa0 | 180 | data->saved_reg = devm_kzalloc(&pdev->dev, |
deb904e4 | 181 | sizeof(u32) * data->reg_num, |
0136afa0 LS |
182 | GFP_KERNEL); |
183 | if (!data->saved_reg) | |
184 | return -ENOMEM; | |
185 | } | |
186 | ||
187 | ret = clk_prepare_enable(data->ipg_clk); | |
188 | if (ret) { | |
189 | dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); | |
190 | return ret; | |
191 | } | |
192 | ||
193 | /* steer all IRQs into configured channel */ | |
194 | writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); | |
195 | ||
deb904e4 | 196 | data->domain = irq_domain_add_linear(np, data->reg_num * 32, |
0136afa0 LS |
197 | &imx_irqsteer_domain_ops, data); |
198 | if (!data->domain) { | |
199 | dev_err(&pdev->dev, "failed to create IRQ domain\n"); | |
28528fca AD |
200 | ret = -ENOMEM; |
201 | goto out; | |
0136afa0 | 202 | } |
4730d223 | 203 | irq_domain_set_pm_device(data->domain, &pdev->dev); |
0136afa0 | 204 | |
28528fca AD |
205 | if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) { |
206 | ret = -EINVAL; | |
207 | goto out; | |
208 | } | |
209 | ||
210 | for (i = 0; i < data->irq_count; i++) { | |
211 | data->irq[i] = irq_of_parse_and_map(np, i); | |
212 | if (!data->irq[i]) { | |
213 | ret = -EINVAL; | |
214 | goto out; | |
215 | } | |
216 | ||
217 | irq_set_chained_handler_and_data(data->irq[i], | |
218 | imx_irqsteer_irq_handler, | |
219 | data); | |
220 | } | |
0136afa0 LS |
221 | |
222 | platform_set_drvdata(pdev, data); | |
223 | ||
4730d223 LS |
224 | pm_runtime_set_active(&pdev->dev); |
225 | pm_runtime_enable(&pdev->dev); | |
226 | ||
0136afa0 | 227 | return 0; |
28528fca AD |
228 | out: |
229 | clk_disable_unprepare(data->ipg_clk); | |
230 | return ret; | |
0136afa0 LS |
231 | } |
232 | ||
233 | static int imx_irqsteer_remove(struct platform_device *pdev) | |
234 | { | |
235 | struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev); | |
28528fca AD |
236 | int i; |
237 | ||
238 | for (i = 0; i < irqsteer_data->irq_count; i++) | |
239 | irq_set_chained_handler_and_data(irqsteer_data->irq[i], | |
240 | NULL, NULL); | |
0136afa0 | 241 | |
0136afa0 LS |
242 | irq_domain_remove(irqsteer_data->domain); |
243 | ||
244 | clk_disable_unprepare(irqsteer_data->ipg_clk); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
4730d223 | 249 | #ifdef CONFIG_PM |
0136afa0 LS |
250 | static void imx_irqsteer_save_regs(struct irqsteer_data *data) |
251 | { | |
252 | int i; | |
253 | ||
deb904e4 | 254 | for (i = 0; i < data->reg_num; i++) |
0136afa0 | 255 | data->saved_reg[i] = readl_relaxed(data->regs + |
deb904e4 | 256 | CHANMASK(i, data->reg_num)); |
0136afa0 LS |
257 | } |
258 | ||
259 | static void imx_irqsteer_restore_regs(struct irqsteer_data *data) | |
260 | { | |
261 | int i; | |
262 | ||
263 | writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); | |
deb904e4 | 264 | for (i = 0; i < data->reg_num; i++) |
0136afa0 | 265 | writel_relaxed(data->saved_reg[i], |
deb904e4 | 266 | data->regs + CHANMASK(i, data->reg_num)); |
0136afa0 LS |
267 | } |
268 | ||
269 | static int imx_irqsteer_suspend(struct device *dev) | |
270 | { | |
271 | struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev); | |
272 | ||
273 | imx_irqsteer_save_regs(irqsteer_data); | |
274 | clk_disable_unprepare(irqsteer_data->ipg_clk); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static int imx_irqsteer_resume(struct device *dev) | |
280 | { | |
281 | struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev); | |
282 | int ret; | |
283 | ||
284 | ret = clk_prepare_enable(irqsteer_data->ipg_clk); | |
285 | if (ret) { | |
286 | dev_err(dev, "failed to enable ipg clk: %d\n", ret); | |
287 | return ret; | |
288 | } | |
289 | imx_irqsteer_restore_regs(irqsteer_data); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | #endif | |
294 | ||
295 | static const struct dev_pm_ops imx_irqsteer_pm_ops = { | |
4730d223 LS |
296 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
297 | pm_runtime_force_resume) | |
298 | SET_RUNTIME_PM_OPS(imx_irqsteer_suspend, | |
299 | imx_irqsteer_resume, NULL) | |
0136afa0 LS |
300 | }; |
301 | ||
302 | static const struct of_device_id imx_irqsteer_dt_ids[] = { | |
303 | { .compatible = "fsl,imx-irqsteer", }, | |
304 | {}, | |
305 | }; | |
306 | ||
307 | static struct platform_driver imx_irqsteer_driver = { | |
308 | .driver = { | |
309 | .name = "imx-irqsteer", | |
310 | .of_match_table = imx_irqsteer_dt_ids, | |
311 | .pm = &imx_irqsteer_pm_ops, | |
312 | }, | |
313 | .probe = imx_irqsteer_probe, | |
314 | .remove = imx_irqsteer_remove, | |
315 | }; | |
316 | builtin_platform_driver(imx_irqsteer_driver); |