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529ea368 TB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Driver for IDT/Renesas 79RC3243x Interrupt Controller. | |
4 | */ | |
5 | ||
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
8 | #include <linux/interrupt.h> | |
9 | #include <linux/irq.h> | |
10 | #include <linux/irqchip.h> | |
11 | #include <linux/irqchip/chained_irq.h> | |
12 | #include <linux/irqdomain.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/of_irq.h> | |
15 | ||
16 | #define IDT_PIC_NR_IRQS 32 | |
17 | ||
18 | #define IDT_PIC_IRQ_PEND 0x00 | |
19 | #define IDT_PIC_IRQ_MASK 0x08 | |
20 | ||
21 | struct idt_pic_data { | |
22 | void __iomem *base; | |
23 | struct irq_domain *irq_domain; | |
24 | struct irq_chip_generic *gc; | |
25 | }; | |
26 | ||
27 | static void idt_irq_dispatch(struct irq_desc *desc) | |
28 | { | |
29 | struct idt_pic_data *idtpic = irq_desc_get_handler_data(desc); | |
30 | struct irq_chip *host_chip = irq_desc_get_chip(desc); | |
046a6ee2 | 31 | u32 pending, hwirq; |
529ea368 TB |
32 | |
33 | chained_irq_enter(host_chip, desc); | |
34 | ||
35 | pending = irq_reg_readl(idtpic->gc, IDT_PIC_IRQ_PEND); | |
36 | pending &= ~idtpic->gc->mask_cache; | |
37 | while (pending) { | |
38 | hwirq = __fls(pending); | |
046a6ee2 | 39 | generic_handle_domain_irq(idtpic->irq_domain, hwirq); |
529ea368 TB |
40 | pending &= ~(1 << hwirq); |
41 | } | |
42 | ||
43 | chained_irq_exit(host_chip, desc); | |
44 | } | |
45 | ||
46 | static int idt_pic_init(struct device_node *of_node, struct device_node *parent) | |
47 | { | |
48 | struct irq_domain *domain; | |
49 | struct idt_pic_data *idtpic; | |
50 | struct irq_chip_generic *gc; | |
51 | struct irq_chip_type *ct; | |
52 | unsigned int parent_irq; | |
53 | int ret = 0; | |
54 | ||
55 | idtpic = kzalloc(sizeof(*idtpic), GFP_KERNEL); | |
56 | if (!idtpic) { | |
57 | ret = -ENOMEM; | |
58 | goto out_err; | |
59 | } | |
60 | ||
61 | parent_irq = irq_of_parse_and_map(of_node, 0); | |
62 | if (!parent_irq) { | |
63 | pr_err("Failed to map parent IRQ!\n"); | |
64 | ret = -EINVAL; | |
65 | goto out_free; | |
66 | } | |
67 | ||
68 | idtpic->base = of_iomap(of_node, 0); | |
69 | if (!idtpic->base) { | |
70 | pr_err("Failed to map base address!\n"); | |
71 | ret = -ENOMEM; | |
72 | goto out_unmap_irq; | |
73 | } | |
74 | ||
75 | domain = irq_domain_add_linear(of_node, IDT_PIC_NR_IRQS, | |
76 | &irq_generic_chip_ops, NULL); | |
77 | if (!domain) { | |
78 | pr_err("Failed to add irqdomain!\n"); | |
79 | ret = -ENOMEM; | |
80 | goto out_iounmap; | |
81 | } | |
82 | idtpic->irq_domain = domain; | |
83 | ||
84 | ret = irq_alloc_domain_generic_chips(domain, 32, 1, "IDTPIC", | |
85 | handle_level_irq, 0, | |
86 | IRQ_NOPROBE | IRQ_LEVEL, 0); | |
87 | if (ret) | |
88 | goto out_domain_remove; | |
89 | ||
90 | gc = irq_get_domain_generic_chip(domain, 0); | |
91 | gc->reg_base = idtpic->base; | |
92 | gc->private = idtpic; | |
93 | ||
94 | ct = gc->chip_types; | |
95 | ct->regs.mask = IDT_PIC_IRQ_MASK; | |
96 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
97 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
98 | idtpic->gc = gc; | |
99 | ||
100 | /* Mask interrupts. */ | |
101 | writel(0xffffffff, idtpic->base + IDT_PIC_IRQ_MASK); | |
102 | gc->mask_cache = 0xffffffff; | |
103 | ||
104 | irq_set_chained_handler_and_data(parent_irq, | |
105 | idt_irq_dispatch, idtpic); | |
106 | ||
107 | return 0; | |
108 | ||
109 | out_domain_remove: | |
110 | irq_domain_remove(domain); | |
111 | out_iounmap: | |
112 | iounmap(idtpic->base); | |
113 | out_unmap_irq: | |
114 | irq_dispose_mapping(parent_irq); | |
115 | out_free: | |
116 | kfree(idtpic); | |
117 | out_err: | |
118 | pr_err("Failed to initialize! (errno = %d)\n", ret); | |
119 | return ret; | |
120 | } | |
121 | ||
122 | IRQCHIP_DECLARE(idt_pic, "idt,32434-pic", idt_pic_init); |