Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
d60fc389 | 44 | #include <linux/irqchip/arm-gic-acpi.h> |
f27ecacc | 45 | |
29e697b1 | 46 | #include <asm/cputype.h> |
f27ecacc | 47 | #include <asm/irq.h> |
562e0027 | 48 | #include <asm/exception.h> |
eb50439b | 49 | #include <asm/smp_plat.h> |
0b996fd3 | 50 | #include <asm/virt.h> |
f27ecacc | 51 | |
d51d0af4 | 52 | #include "irq-gic-common.h" |
f27ecacc | 53 | |
76e52dd0 MZ |
54 | #ifdef CONFIG_ARM64 |
55 | #include <asm/cpufeature.h> | |
56 | ||
57 | static void gic_check_cpu_features(void) | |
58 | { | |
59 | WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), | |
60 | TAINT_CPU_OUT_OF_SPEC, | |
61 | "GICv3 system registers enabled, broken firmware!\n"); | |
62 | } | |
63 | #else | |
64 | #define gic_check_cpu_features() do { } while(0) | |
65 | #endif | |
66 | ||
db0d4db2 MZ |
67 | union gic_base { |
68 | void __iomem *common_base; | |
6859358e | 69 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
70 | }; |
71 | ||
72 | struct gic_chip_data { | |
db0d4db2 MZ |
73 | union gic_base dist_base; |
74 | union gic_base cpu_base; | |
75 | #ifdef CONFIG_CPU_PM | |
76 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
77 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
78 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
79 | u32 __percpu *saved_ppi_enable; | |
80 | u32 __percpu *saved_ppi_conf; | |
81 | #endif | |
75294957 | 82 | struct irq_domain *domain; |
db0d4db2 MZ |
83 | unsigned int gic_irqs; |
84 | #ifdef CONFIG_GIC_NON_BANKED | |
85 | void __iomem *(*get_base)(union gic_base *); | |
86 | #endif | |
87 | }; | |
88 | ||
bd31b859 | 89 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 90 | |
384a2902 NP |
91 | /* |
92 | * The GIC mapping of CPU interfaces does not necessarily match | |
93 | * the logical CPU numbering. Let's use a mapping as returned | |
94 | * by the GIC itself. | |
95 | */ | |
96 | #define NR_GIC_CPU_IF 8 | |
97 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
98 | ||
0b996fd3 MZ |
99 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
100 | ||
b3a1bde4 CM |
101 | #ifndef MAX_GIC_NR |
102 | #define MAX_GIC_NR 1 | |
103 | #endif | |
104 | ||
bef8f9ee | 105 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 106 | |
db0d4db2 MZ |
107 | #ifdef CONFIG_GIC_NON_BANKED |
108 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
109 | { | |
513d1a28 | 110 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
111 | } |
112 | ||
113 | static void __iomem *gic_get_common_base(union gic_base *base) | |
114 | { | |
115 | return base->common_base; | |
116 | } | |
117 | ||
118 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
119 | { | |
120 | return data->get_base(&data->dist_base); | |
121 | } | |
122 | ||
123 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
124 | { | |
125 | return data->get_base(&data->cpu_base); | |
126 | } | |
127 | ||
128 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
129 | void __iomem *(*f)(union gic_base *)) | |
130 | { | |
131 | data->get_base = f; | |
132 | } | |
133 | #else | |
134 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
135 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 136 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
137 | #endif |
138 | ||
7d1f4288 | 139 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 140 | { |
7d1f4288 | 141 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 142 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
143 | } |
144 | ||
7d1f4288 | 145 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 146 | { |
7d1f4288 | 147 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 148 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
149 | } |
150 | ||
7d1f4288 | 151 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 152 | { |
4294f8ba | 153 | return d->hwirq; |
b3a1bde4 CM |
154 | } |
155 | ||
01f779f4 MZ |
156 | static inline bool cascading_gic_irq(struct irq_data *d) |
157 | { | |
158 | void *data = irq_data_get_irq_handler_data(d); | |
159 | ||
160 | /* | |
71466535 TG |
161 | * If handler_data is set, this is a cascading interrupt, and |
162 | * it cannot possibly be forwarded. | |
01f779f4 | 163 | */ |
71466535 | 164 | return data != NULL; |
01f779f4 MZ |
165 | } |
166 | ||
f27ecacc RK |
167 | /* |
168 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 169 | */ |
56717807 MZ |
170 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
171 | { | |
172 | u32 mask = 1 << (gic_irq(d) % 32); | |
173 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
174 | } | |
175 | ||
176 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 177 | { |
4294f8ba | 178 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
179 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
180 | } | |
181 | ||
182 | static void gic_mask_irq(struct irq_data *d) | |
183 | { | |
56717807 | 184 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
185 | } |
186 | ||
0b996fd3 MZ |
187 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
188 | { | |
189 | gic_mask_irq(d); | |
01f779f4 MZ |
190 | /* |
191 | * When masking a forwarded interrupt, make sure it is | |
192 | * deactivated as well. | |
193 | * | |
194 | * This ensures that an interrupt that is getting | |
195 | * disabled/masked will not get "stuck", because there is | |
196 | * noone to deactivate it (guest is being terminated). | |
197 | */ | |
71466535 | 198 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 199 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
200 | } |
201 | ||
7d1f4288 | 202 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 203 | { |
56717807 | 204 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
205 | } |
206 | ||
1a01753e WD |
207 | static void gic_eoi_irq(struct irq_data *d) |
208 | { | |
6ac77e46 | 209 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
210 | } |
211 | ||
0b996fd3 MZ |
212 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
213 | { | |
01f779f4 | 214 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 215 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
216 | return; |
217 | ||
0b996fd3 MZ |
218 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
219 | } | |
220 | ||
56717807 MZ |
221 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
222 | enum irqchip_irq_state which, bool val) | |
223 | { | |
224 | u32 reg; | |
225 | ||
226 | switch (which) { | |
227 | case IRQCHIP_STATE_PENDING: | |
228 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
229 | break; | |
230 | ||
231 | case IRQCHIP_STATE_ACTIVE: | |
232 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
233 | break; | |
234 | ||
235 | case IRQCHIP_STATE_MASKED: | |
236 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
237 | break; | |
238 | ||
239 | default: | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | gic_poke_irq(d, reg); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
248 | enum irqchip_irq_state which, bool *val) | |
249 | { | |
250 | switch (which) { | |
251 | case IRQCHIP_STATE_PENDING: | |
252 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
253 | break; | |
254 | ||
255 | case IRQCHIP_STATE_ACTIVE: | |
256 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
257 | break; | |
258 | ||
259 | case IRQCHIP_STATE_MASKED: | |
260 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
261 | break; | |
262 | ||
263 | default: | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
7d1f4288 | 270 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 271 | { |
7d1f4288 LB |
272 | void __iomem *base = gic_dist_base(d); |
273 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
274 | |
275 | /* Interrupt configuration for SGIs can't be changed */ | |
276 | if (gicirq < 16) | |
277 | return -EINVAL; | |
278 | ||
fb7e7deb LD |
279 | /* SPIs have restrictions on the supported types */ |
280 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
281 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
282 | return -EINVAL; |
283 | ||
1dcc73d7 | 284 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
285 | } |
286 | ||
01f779f4 MZ |
287 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
288 | { | |
289 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
290 | if (cascading_gic_irq(d)) | |
291 | return -EINVAL; | |
292 | ||
71466535 TG |
293 | if (vcpu) |
294 | irqd_set_forwarded_to_vcpu(d); | |
295 | else | |
296 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
297 | return 0; |
298 | } | |
299 | ||
a06f5466 | 300 | #ifdef CONFIG_SMP |
c191789c RK |
301 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
302 | bool force) | |
f27ecacc | 303 | { |
7d1f4288 | 304 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 305 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 306 | u32 val, mask, bit; |
cf613871 | 307 | unsigned long flags; |
f27ecacc | 308 | |
ffde1de6 TG |
309 | if (!force) |
310 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
311 | else | |
312 | cpu = cpumask_first(mask_val); | |
313 | ||
384a2902 | 314 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 315 | return -EINVAL; |
c191789c | 316 | |
cf613871 | 317 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 318 | mask = 0xff << shift; |
384a2902 | 319 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
320 | val = readl_relaxed(reg) & ~mask; |
321 | writel_relaxed(val | bit, reg); | |
cf613871 | 322 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 323 | |
5dfc54e0 | 324 | return IRQ_SET_MASK_OK; |
f27ecacc | 325 | } |
a06f5466 | 326 | #endif |
f27ecacc | 327 | |
8783dd3a | 328 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
329 | { |
330 | u32 irqstat, irqnr; | |
331 | struct gic_chip_data *gic = &gic_data[0]; | |
332 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
333 | ||
334 | do { | |
335 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 336 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 MZ |
337 | |
338 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
0b996fd3 MZ |
339 | if (static_key_true(&supports_deactivate)) |
340 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 341 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
342 | continue; |
343 | } | |
344 | if (irqnr < 16) { | |
345 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
346 | if (static_key_true(&supports_deactivate)) |
347 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 MZ |
348 | #ifdef CONFIG_SMP |
349 | handle_IPI(irqnr, regs); | |
350 | #endif | |
351 | continue; | |
352 | } | |
353 | break; | |
354 | } while (1); | |
355 | } | |
356 | ||
bd0b9ac4 | 357 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 358 | { |
5b29264c JL |
359 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
360 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 361 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
362 | unsigned long status; |
363 | ||
1a01753e | 364 | chained_irq_enter(chip, desc); |
b3a1bde4 | 365 | |
bd31b859 | 366 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 367 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 368 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 369 | |
e5f81539 FK |
370 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
371 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 372 | goto out; |
b3a1bde4 | 373 | |
75294957 GL |
374 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
375 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 376 | handle_bad_irq(desc); |
0f347bb9 RK |
377 | else |
378 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
379 | |
380 | out: | |
1a01753e | 381 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
382 | } |
383 | ||
38c677cb | 384 | static struct irq_chip gic_chip = { |
7d1f4288 | 385 | .name = "GIC", |
7d1f4288 LB |
386 | .irq_mask = gic_mask_irq, |
387 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 388 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 389 | .irq_set_type = gic_set_type, |
f27ecacc | 390 | #ifdef CONFIG_SMP |
c191789c | 391 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 392 | #endif |
56717807 MZ |
393 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
394 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
395 | .flags = IRQCHIP_SET_TYPE_MASKED | |
396 | IRQCHIP_SKIP_SET_WAKE | | |
397 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
398 | }; |
399 | ||
0b996fd3 MZ |
400 | static struct irq_chip gic_eoimode1_chip = { |
401 | .name = "GICv2", | |
402 | .irq_mask = gic_eoimode1_mask_irq, | |
403 | .irq_unmask = gic_unmask_irq, | |
404 | .irq_eoi = gic_eoimode1_eoi_irq, | |
405 | .irq_set_type = gic_set_type, | |
406 | #ifdef CONFIG_SMP | |
407 | .irq_set_affinity = gic_set_affinity, | |
408 | #endif | |
409 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
410 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
01f779f4 | 411 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b996fd3 MZ |
412 | .flags = IRQCHIP_SET_TYPE_MASKED | |
413 | IRQCHIP_SKIP_SET_WAKE | | |
414 | IRQCHIP_MASK_ON_SUSPEND, | |
415 | }; | |
416 | ||
b3a1bde4 CM |
417 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
418 | { | |
419 | if (gic_nr >= MAX_GIC_NR) | |
420 | BUG(); | |
4d83fcf8 TG |
421 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
422 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
423 | } |
424 | ||
2bb31351 RK |
425 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
426 | { | |
427 | void __iomem *base = gic_data_dist_base(gic); | |
428 | u32 mask, i; | |
429 | ||
430 | for (i = mask = 0; i < 32; i += 4) { | |
431 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
432 | mask |= mask >> 16; | |
433 | mask |= mask >> 8; | |
434 | if (mask) | |
435 | break; | |
436 | } | |
437 | ||
6e3aca44 | 438 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
439 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
440 | ||
441 | return mask; | |
442 | } | |
443 | ||
4c2880b3 | 444 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 445 | { |
4c2880b3 | 446 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 447 | u32 bypass = 0; |
0b996fd3 MZ |
448 | u32 mode = 0; |
449 | ||
450 | if (static_key_true(&supports_deactivate)) | |
451 | mode = GIC_CPU_CTRL_EOImodeNS; | |
32289506 FK |
452 | |
453 | /* | |
454 | * Preserve bypass disable bits to be written back later | |
455 | */ | |
456 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
457 | bypass &= GICC_DIS_BYPASS_MASK; | |
458 | ||
0b996fd3 | 459 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
460 | } |
461 | ||
462 | ||
4294f8ba | 463 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 464 | { |
75294957 | 465 | unsigned int i; |
267840f3 | 466 | u32 cpumask; |
4294f8ba | 467 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 468 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 469 | |
e5f81539 | 470 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 471 | |
f27ecacc RK |
472 | /* |
473 | * Set all global interrupts to this CPU only. | |
474 | */ | |
2bb31351 RK |
475 | cpumask = gic_get_cpumask(gic); |
476 | cpumask |= cpumask << 8; | |
477 | cpumask |= cpumask << 16; | |
e6afec9b | 478 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 479 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 480 | |
d51d0af4 | 481 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 482 | |
e5f81539 | 483 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
484 | } |
485 | ||
8c37bb3a | 486 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 487 | { |
db0d4db2 MZ |
488 | void __iomem *dist_base = gic_data_dist_base(gic); |
489 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 490 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
491 | int i; |
492 | ||
384a2902 | 493 | /* |
567e5a01 JH |
494 | * Setting up the CPU map is only relevant for the primary GIC |
495 | * because any nested/secondary GICs do not directly interface | |
496 | * with the CPU(s). | |
384a2902 | 497 | */ |
567e5a01 JH |
498 | if (gic == &gic_data[0]) { |
499 | /* | |
500 | * Get what the GIC says our CPU mask is. | |
501 | */ | |
502 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
503 | cpu_mask = gic_get_cpumask(gic); | |
504 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 505 | |
567e5a01 JH |
506 | /* |
507 | * Clear our mask from the other map entries in case they're | |
508 | * still undefined. | |
509 | */ | |
510 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
511 | if (i != cpu) | |
512 | gic_cpu_map[i] &= ~cpu_mask; | |
513 | } | |
384a2902 | 514 | |
d51d0af4 | 515 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 516 | |
e5f81539 | 517 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 518 | gic_cpu_if_up(gic); |
f27ecacc RK |
519 | } |
520 | ||
4c2880b3 | 521 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 522 | { |
4c2880b3 | 523 | void __iomem *cpu_base; |
32289506 FK |
524 | u32 val = 0; |
525 | ||
4c2880b3 JH |
526 | if (gic_nr >= MAX_GIC_NR) |
527 | return -EINVAL; | |
528 | ||
529 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
530 | val = readl(cpu_base + GIC_CPU_CTRL); |
531 | val &= ~GICC_ENABLE; | |
532 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
533 | |
534 | return 0; | |
10d9eb8a NP |
535 | } |
536 | ||
254056f3 CC |
537 | #ifdef CONFIG_CPU_PM |
538 | /* | |
539 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
540 | * with interrupts disabled but before powering down the GIC. After calling | |
541 | * this function, no interrupts will be delivered by the GIC, and another | |
542 | * platform-specific wakeup source must be enabled. | |
543 | */ | |
544 | static void gic_dist_save(unsigned int gic_nr) | |
545 | { | |
546 | unsigned int gic_irqs; | |
547 | void __iomem *dist_base; | |
548 | int i; | |
549 | ||
550 | if (gic_nr >= MAX_GIC_NR) | |
551 | BUG(); | |
552 | ||
553 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 554 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
555 | |
556 | if (!dist_base) | |
557 | return; | |
558 | ||
559 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
560 | gic_data[gic_nr].saved_spi_conf[i] = | |
561 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
562 | ||
563 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
564 | gic_data[gic_nr].saved_spi_target[i] = | |
565 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
566 | ||
567 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
568 | gic_data[gic_nr].saved_spi_enable[i] = | |
569 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
570 | } | |
571 | ||
572 | /* | |
573 | * Restores the GIC distributor registers during resume or when coming out of | |
574 | * idle. Must be called before enabling interrupts. If a level interrupt | |
575 | * that occured while the GIC was suspended is still present, it will be | |
576 | * handled normally, but any edge interrupts that occured will not be seen by | |
577 | * the GIC and need to be handled by the platform-specific wakeup source. | |
578 | */ | |
579 | static void gic_dist_restore(unsigned int gic_nr) | |
580 | { | |
581 | unsigned int gic_irqs; | |
582 | unsigned int i; | |
583 | void __iomem *dist_base; | |
584 | ||
585 | if (gic_nr >= MAX_GIC_NR) | |
586 | BUG(); | |
587 | ||
588 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 589 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
590 | |
591 | if (!dist_base) | |
592 | return; | |
593 | ||
e5f81539 | 594 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
595 | |
596 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
597 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
598 | dist_base + GIC_DIST_CONFIG + i * 4); | |
599 | ||
600 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 601 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
602 | dist_base + GIC_DIST_PRI + i * 4); |
603 | ||
604 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
605 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
606 | dist_base + GIC_DIST_TARGET + i * 4); | |
607 | ||
608 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
609 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
610 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
611 | ||
e5f81539 | 612 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
613 | } |
614 | ||
615 | static void gic_cpu_save(unsigned int gic_nr) | |
616 | { | |
617 | int i; | |
618 | u32 *ptr; | |
619 | void __iomem *dist_base; | |
620 | void __iomem *cpu_base; | |
621 | ||
622 | if (gic_nr >= MAX_GIC_NR) | |
623 | BUG(); | |
624 | ||
db0d4db2 MZ |
625 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
626 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
627 | |
628 | if (!dist_base || !cpu_base) | |
629 | return; | |
630 | ||
532d0d06 | 631 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
632 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
633 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
634 | ||
532d0d06 | 635 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
636 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
637 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
638 | ||
639 | } | |
640 | ||
641 | static void gic_cpu_restore(unsigned int gic_nr) | |
642 | { | |
643 | int i; | |
644 | u32 *ptr; | |
645 | void __iomem *dist_base; | |
646 | void __iomem *cpu_base; | |
647 | ||
648 | if (gic_nr >= MAX_GIC_NR) | |
649 | BUG(); | |
650 | ||
db0d4db2 MZ |
651 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
652 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
653 | |
654 | if (!dist_base || !cpu_base) | |
655 | return; | |
656 | ||
532d0d06 | 657 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
658 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
659 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
660 | ||
532d0d06 | 661 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
662 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
663 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
664 | ||
665 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
666 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
667 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 668 | |
e5f81539 | 669 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
4c2880b3 | 670 | gic_cpu_if_up(&gic_data[gic_nr]); |
254056f3 CC |
671 | } |
672 | ||
673 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
674 | { | |
675 | int i; | |
676 | ||
677 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
678 | #ifdef CONFIG_GIC_NON_BANKED |
679 | /* Skip over unused GICs */ | |
680 | if (!gic_data[i].get_base) | |
681 | continue; | |
682 | #endif | |
254056f3 CC |
683 | switch (cmd) { |
684 | case CPU_PM_ENTER: | |
685 | gic_cpu_save(i); | |
686 | break; | |
687 | case CPU_PM_ENTER_FAILED: | |
688 | case CPU_PM_EXIT: | |
689 | gic_cpu_restore(i); | |
690 | break; | |
691 | case CPU_CLUSTER_PM_ENTER: | |
692 | gic_dist_save(i); | |
693 | break; | |
694 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
695 | case CPU_CLUSTER_PM_EXIT: | |
696 | gic_dist_restore(i); | |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
701 | return NOTIFY_OK; | |
702 | } | |
703 | ||
704 | static struct notifier_block gic_notifier_block = { | |
705 | .notifier_call = gic_notifier, | |
706 | }; | |
707 | ||
708 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
709 | { | |
710 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
711 | sizeof(u32)); | |
712 | BUG_ON(!gic->saved_ppi_enable); | |
713 | ||
714 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
715 | sizeof(u32)); | |
716 | BUG_ON(!gic->saved_ppi_conf); | |
717 | ||
abdd7b91 MZ |
718 | if (gic == &gic_data[0]) |
719 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
720 | } |
721 | #else | |
722 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
723 | { | |
724 | } | |
725 | #endif | |
726 | ||
b1cffebf | 727 | #ifdef CONFIG_SMP |
6859358e | 728 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
729 | { |
730 | int cpu; | |
1a6b69b6 NP |
731 | unsigned long flags, map = 0; |
732 | ||
733 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
734 | |
735 | /* Convert our logical CPU mask into a physical one. */ | |
736 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 737 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
738 | |
739 | /* | |
740 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 741 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 742 | */ |
8adbf57f | 743 | dmb(ishst); |
b1cffebf RH |
744 | |
745 | /* this always happens on GIC0 */ | |
746 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
747 | |
748 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
749 | } | |
750 | #endif | |
751 | ||
752 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
753 | /* |
754 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
755 | * | |
756 | * cpu_id: the ID for the destination CPU interface | |
757 | * irq: the IPI number to send a SGI for | |
758 | */ | |
759 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
760 | { | |
761 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
762 | cpu_id = 1 << cpu_id; | |
763 | /* this always happens on GIC0 */ | |
764 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
765 | } | |
766 | ||
ed96762e NP |
767 | /* |
768 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
769 | * | |
770 | * @cpu: the logical CPU number to get the GIC ID for. | |
771 | * | |
772 | * Return the CPU interface ID for the given logical CPU number, | |
773 | * or -1 if the CPU number is too large or the interface ID is | |
774 | * unknown (more than one bit set). | |
775 | */ | |
776 | int gic_get_cpu_id(unsigned int cpu) | |
777 | { | |
778 | unsigned int cpu_bit; | |
779 | ||
780 | if (cpu >= NR_GIC_CPU_IF) | |
781 | return -1; | |
782 | cpu_bit = gic_cpu_map[cpu]; | |
783 | if (cpu_bit & (cpu_bit - 1)) | |
784 | return -1; | |
785 | return __ffs(cpu_bit); | |
786 | } | |
787 | ||
1a6b69b6 NP |
788 | /* |
789 | * gic_migrate_target - migrate IRQs to another CPU interface | |
790 | * | |
791 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
792 | * | |
793 | * Migrate all peripheral interrupts with a target matching the current CPU | |
794 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
795 | * is also updated. Targets to other CPU interfaces are unchanged. | |
796 | * This must be called with IRQs locally disabled. | |
797 | */ | |
798 | void gic_migrate_target(unsigned int new_cpu_id) | |
799 | { | |
800 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
801 | void __iomem *dist_base; | |
802 | int i, ror_val, cpu = smp_processor_id(); | |
803 | u32 val, cur_target_mask, active_mask; | |
804 | ||
805 | if (gic_nr >= MAX_GIC_NR) | |
806 | BUG(); | |
807 | ||
808 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
809 | if (!dist_base) | |
810 | return; | |
811 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
812 | ||
813 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
814 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
815 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
816 | ||
817 | raw_spin_lock(&irq_controller_lock); | |
818 | ||
819 | /* Update the target interface for this logical CPU */ | |
820 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
821 | ||
822 | /* | |
823 | * Find all the peripheral interrupts targetting the current | |
824 | * CPU interface and migrate them to the new CPU interface. | |
825 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
826 | */ | |
827 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
828 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
829 | active_mask = val & cur_target_mask; | |
830 | if (active_mask) { | |
831 | val &= ~active_mask; | |
832 | val |= ror32(active_mask, ror_val); | |
833 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
834 | } | |
835 | } | |
836 | ||
837 | raw_spin_unlock(&irq_controller_lock); | |
838 | ||
839 | /* | |
840 | * Now let's migrate and clear any potential SGIs that might be | |
841 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
842 | * is a banked register, we can only forward the SGI using | |
843 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
844 | * doesn't use that information anyway. | |
845 | * | |
846 | * For the same reason we do not adjust SGI source information | |
847 | * for previously sent SGIs by us to other CPUs either. | |
848 | */ | |
849 | for (i = 0; i < 16; i += 4) { | |
850 | int j; | |
851 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
852 | if (!val) | |
853 | continue; | |
854 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
855 | for (j = i; j < i + 4; j++) { | |
856 | if (val & 0xff) | |
857 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
858 | dist_base + GIC_DIST_SOFTINT); | |
859 | val >>= 8; | |
860 | } | |
861 | } | |
b1cffebf | 862 | } |
eeb44658 NP |
863 | |
864 | /* | |
865 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
866 | * | |
867 | * REturn the physical address of the SGI register to be used | |
868 | * by some early assembly code when the kernel is not yet available. | |
869 | */ | |
870 | static unsigned long gic_dist_physaddr; | |
871 | ||
872 | unsigned long gic_get_sgir_physaddr(void) | |
873 | { | |
874 | if (!gic_dist_physaddr) | |
875 | return 0; | |
876 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
877 | } | |
878 | ||
879 | void __init gic_init_physaddr(struct device_node *node) | |
880 | { | |
881 | struct resource res; | |
882 | if (of_address_to_resource(node, 0, &res) == 0) { | |
883 | gic_dist_physaddr = res.start; | |
884 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
885 | } | |
886 | } | |
887 | ||
888 | #else | |
889 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
890 | #endif |
891 | ||
75294957 GL |
892 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
893 | irq_hw_number_t hw) | |
894 | { | |
0b996fd3 MZ |
895 | struct irq_chip *chip = &gic_chip; |
896 | ||
897 | if (static_key_true(&supports_deactivate)) { | |
898 | if (d->host_data == (void *)&gic_data[0]) | |
899 | chip = &gic_eoimode1_chip; | |
900 | } | |
901 | ||
75294957 GL |
902 | if (hw < 32) { |
903 | irq_set_percpu_devid(irq); | |
0b996fd3 | 904 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 905 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 906 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 907 | } else { |
0b996fd3 | 908 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 909 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 910 | irq_set_probe(irq); |
75294957 | 911 | } |
75294957 GL |
912 | return 0; |
913 | } | |
914 | ||
006e983b S |
915 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
916 | { | |
006e983b S |
917 | } |
918 | ||
7bb69bad GL |
919 | static int gic_irq_domain_xlate(struct irq_domain *d, |
920 | struct device_node *controller, | |
921 | const u32 *intspec, unsigned int intsize, | |
922 | unsigned long *out_hwirq, unsigned int *out_type) | |
b3f7ed03 | 923 | { |
006e983b S |
924 | unsigned long ret = 0; |
925 | ||
5d4c9bc7 | 926 | if (irq_domain_get_of_node(d) != controller) |
b3f7ed03 RH |
927 | return -EINVAL; |
928 | if (intsize < 3) | |
929 | return -EINVAL; | |
930 | ||
931 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
932 | *out_hwirq = intspec[1] + 16; | |
933 | ||
934 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
a5561c3e MZ |
935 | if (!intspec[0]) |
936 | *out_hwirq += 16; | |
b3f7ed03 RH |
937 | |
938 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
006e983b S |
939 | |
940 | return ret; | |
b3f7ed03 | 941 | } |
b3f7ed03 | 942 | |
f833f57f MZ |
943 | static int gic_irq_domain_translate(struct irq_domain *d, |
944 | struct irq_fwspec *fwspec, | |
945 | unsigned long *hwirq, | |
946 | unsigned int *type) | |
947 | { | |
948 | if (is_of_node(fwspec->fwnode)) { | |
949 | if (fwspec->param_count < 3) | |
950 | return -EINVAL; | |
951 | ||
952 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
953 | *hwirq = fwspec->param[1] + 16; | |
954 | ||
955 | /* | |
956 | * For SPIs, we need to add 16 more to get the GIC irq | |
957 | * ID number | |
958 | */ | |
959 | if (!fwspec->param[0]) | |
960 | *hwirq += 16; | |
961 | ||
962 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
963 | return 0; | |
964 | } | |
965 | ||
966 | return -EINVAL; | |
967 | } | |
968 | ||
c0114709 | 969 | #ifdef CONFIG_SMP |
8c37bb3a PG |
970 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
971 | void *hcpu) | |
c0114709 | 972 | { |
8b6fd652 | 973 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
974 | gic_cpu_init(&gic_data[0]); |
975 | return NOTIFY_OK; | |
976 | } | |
977 | ||
978 | /* | |
979 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
980 | * priority because the GIC needs to be up before the ARM generic timers. | |
981 | */ | |
8c37bb3a | 982 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
983 | .notifier_call = gic_secondary_init, |
984 | .priority = 100, | |
985 | }; | |
986 | #endif | |
987 | ||
9a1091ef YC |
988 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
989 | unsigned int nr_irqs, void *arg) | |
990 | { | |
991 | int i, ret; | |
992 | irq_hw_number_t hwirq; | |
993 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 994 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 995 | |
f833f57f | 996 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
997 | if (ret) |
998 | return ret; | |
999 | ||
1000 | for (i = 0; i < nr_irqs; i++) | |
1001 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1007 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1008 | .alloc = gic_irq_domain_alloc, |
1009 | .free = irq_domain_free_irqs_top, | |
1010 | }; | |
1011 | ||
6859358e | 1012 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1013 | .map = gic_irq_domain_map, |
006e983b | 1014 | .unmap = gic_irq_domain_unmap, |
7bb69bad | 1015 | .xlate = gic_irq_domain_xlate, |
4294f8ba RH |
1016 | }; |
1017 | ||
4a6ac304 | 1018 | static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, |
db0d4db2 | 1019 | void __iomem *dist_base, void __iomem *cpu_base, |
75294957 | 1020 | u32 percpu_offset, struct device_node *node) |
b580b899 | 1021 | { |
75294957 | 1022 | irq_hw_number_t hwirq_base; |
bef8f9ee | 1023 | struct gic_chip_data *gic; |
384a2902 | 1024 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
1025 | |
1026 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
1027 | ||
76e52dd0 MZ |
1028 | gic_check_cpu_features(); |
1029 | ||
bef8f9ee | 1030 | gic = &gic_data[gic_nr]; |
db0d4db2 MZ |
1031 | #ifdef CONFIG_GIC_NON_BANKED |
1032 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
1033 | unsigned int cpu; | |
1034 | ||
1035 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1036 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1037 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1038 | !gic->cpu_base.percpu_base)) { | |
1039 | free_percpu(gic->dist_base.percpu_base); | |
1040 | free_percpu(gic->cpu_base.percpu_base); | |
1041 | return; | |
1042 | } | |
1043 | ||
1044 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1045 | u32 mpidr = cpu_logical_map(cpu); |
1046 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
1047 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
1048 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
1049 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
1050 | } | |
1051 | ||
1052 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
1053 | } else | |
1054 | #endif | |
1055 | { /* Normal, sane GIC... */ | |
1056 | WARN(percpu_offset, | |
1057 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
1058 | percpu_offset); | |
1059 | gic->dist_base.common_base = dist_base; | |
1060 | gic->cpu_base.common_base = cpu_base; | |
1061 | gic_set_base_accessor(gic, gic_get_common_base); | |
1062 | } | |
bef8f9ee | 1063 | |
4294f8ba RH |
1064 | /* |
1065 | * Find out how many interrupts are supported. | |
1066 | * The GIC only supports up to 1020 interrupt sources. | |
1067 | */ | |
db0d4db2 | 1068 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1069 | gic_irqs = (gic_irqs + 1) * 32; |
1070 | if (gic_irqs > 1020) | |
1071 | gic_irqs = 1020; | |
1072 | gic->gic_irqs = gic_irqs; | |
1073 | ||
9a1091ef | 1074 | if (node) { /* DT case */ |
a5561c3e MZ |
1075 | gic->domain = irq_domain_add_linear(node, gic_irqs, |
1076 | &gic_irq_domain_hierarchy_ops, | |
1077 | gic); | |
9a1091ef YC |
1078 | } else { /* Non-DT case */ |
1079 | /* | |
1080 | * For primary GICs, skip over SGIs. | |
1081 | * For secondary GICs, skip over PPIs, too. | |
1082 | */ | |
1083 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
1084 | hwirq_base = 16; | |
1085 | if (irq_start != -1) | |
1086 | irq_start = (irq_start & ~31) + 16; | |
1087 | } else { | |
1088 | hwirq_base = 32; | |
1089 | } | |
1090 | ||
1091 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1092 | |
006e983b S |
1093 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1094 | numa_node_id()); | |
1095 | if (IS_ERR_VALUE(irq_base)) { | |
1096 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1097 | irq_start); | |
1098 | irq_base = irq_start; | |
1099 | } | |
1100 | ||
1101 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, | |
1102 | hwirq_base, &gic_irq_domain_ops, gic); | |
f37a53cc | 1103 | } |
006e983b | 1104 | |
75294957 GL |
1105 | if (WARN_ON(!gic->domain)) |
1106 | return; | |
bef8f9ee | 1107 | |
08332dff | 1108 | if (gic_nr == 0) { |
567e5a01 JH |
1109 | /* |
1110 | * Initialize the CPU interface map to all CPUs. | |
1111 | * It will be refined as each CPU probes its ID. | |
1112 | * This is only necessary for the primary GIC. | |
1113 | */ | |
1114 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1115 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 1116 | #ifdef CONFIG_SMP |
08332dff MR |
1117 | set_smp_cross_call(gic_raise_softirq); |
1118 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1119 | #endif |
08332dff | 1120 | set_handle_irq(gic_handle_irq); |
0b996fd3 MZ |
1121 | if (static_key_true(&supports_deactivate)) |
1122 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
08332dff | 1123 | } |
cfed7d60 | 1124 | |
4294f8ba | 1125 | gic_dist_init(gic); |
bef8f9ee | 1126 | gic_cpu_init(gic); |
254056f3 | 1127 | gic_pm_init(gic); |
b580b899 RK |
1128 | } |
1129 | ||
4a6ac304 MZ |
1130 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
1131 | void __iomem *dist_base, void __iomem *cpu_base, | |
1132 | u32 percpu_offset, struct device_node *node) | |
1133 | { | |
1134 | /* | |
1135 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1136 | * bother with these... | |
1137 | */ | |
1138 | static_key_slow_dec(&supports_deactivate); | |
1139 | __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, | |
1140 | percpu_offset, node); | |
1141 | } | |
1142 | ||
b3f7ed03 | 1143 | #ifdef CONFIG_OF |
46f101df | 1144 | static int gic_cnt __initdata; |
b3f7ed03 | 1145 | |
12e14066 MZ |
1146 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1147 | { | |
1148 | struct resource cpuif_res; | |
1149 | ||
1150 | of_address_to_resource(node, 1, &cpuif_res); | |
1151 | ||
1152 | if (!is_hyp_mode_available()) | |
1153 | return false; | |
1154 | if (resource_size(&cpuif_res) < SZ_8K) | |
1155 | return false; | |
1156 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1157 | u32 val_low, val_high; | |
1158 | ||
1159 | /* | |
1160 | * Verify that we have the first 4kB of a GIC400 | |
1161 | * aliased over the first 64kB by checking the | |
1162 | * GICC_IIDR register on both ends. | |
1163 | */ | |
1164 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1165 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1166 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1167 | val_low != val_high) | |
1168 | return false; | |
1169 | ||
1170 | /* | |
1171 | * Move the base up by 60kB, so that we have a 8kB | |
1172 | * contiguous region, which allows us to use GICC_DIR | |
1173 | * at its normal offset. Please pass me that bucket. | |
1174 | */ | |
1175 | *base += 0xf000; | |
1176 | cpuif_res.start += 0xf000; | |
1177 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1178 | &cpuif_res.start); | |
1179 | } | |
1180 | ||
1181 | return true; | |
1182 | } | |
1183 | ||
6859358e SB |
1184 | static int __init |
1185 | gic_of_init(struct device_node *node, struct device_node *parent) | |
b3f7ed03 RH |
1186 | { |
1187 | void __iomem *cpu_base; | |
1188 | void __iomem *dist_base; | |
db0d4db2 | 1189 | u32 percpu_offset; |
b3f7ed03 | 1190 | int irq; |
b3f7ed03 RH |
1191 | |
1192 | if (WARN_ON(!node)) | |
1193 | return -ENODEV; | |
1194 | ||
1195 | dist_base = of_iomap(node, 0); | |
1196 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
1197 | ||
1198 | cpu_base = of_iomap(node, 1); | |
1199 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
1200 | ||
0b996fd3 MZ |
1201 | /* |
1202 | * Disable split EOI/Deactivate if either HYP is not available | |
1203 | * or the CPU interface is too small. | |
1204 | */ | |
12e14066 | 1205 | if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) |
0b996fd3 MZ |
1206 | static_key_slow_dec(&supports_deactivate); |
1207 | ||
db0d4db2 MZ |
1208 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1209 | percpu_offset = 0; | |
1210 | ||
4a6ac304 | 1211 | __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
eeb44658 NP |
1212 | if (!gic_cnt) |
1213 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1214 | |
1215 | if (parent) { | |
1216 | irq = irq_of_parse_and_map(node, 0); | |
1217 | gic_cascade_irq(gic_cnt, irq); | |
1218 | } | |
853a33ce SS |
1219 | |
1220 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1221 | gicv2m_of_init(node, gic_data[gic_cnt].domain); | |
1222 | ||
b3f7ed03 RH |
1223 | gic_cnt++; |
1224 | return 0; | |
1225 | } | |
144cb088 | 1226 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1227 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1228 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1229 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1230 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1231 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1232 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1233 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1234 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1235 | |
b3f7ed03 | 1236 | #endif |
d60fc389 TN |
1237 | |
1238 | #ifdef CONFIG_ACPI | |
1239 | static phys_addr_t dist_phy_base, cpu_phy_base __initdata; | |
1240 | ||
1241 | static int __init | |
1242 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1243 | const unsigned long end) | |
1244 | { | |
1245 | struct acpi_madt_generic_interrupt *processor; | |
1246 | phys_addr_t gic_cpu_base; | |
1247 | static int cpu_base_assigned; | |
1248 | ||
1249 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1250 | ||
99e3e3ae | 1251 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1252 | return -EINVAL; |
1253 | ||
1254 | /* | |
1255 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1256 | * All CPU interface addresses have to be the same. | |
1257 | */ | |
1258 | gic_cpu_base = processor->base_address; | |
1259 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1260 | return -EINVAL; | |
1261 | ||
1262 | cpu_phy_base = gic_cpu_base; | |
1263 | cpu_base_assigned = 1; | |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | static int __init | |
1268 | gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, | |
1269 | const unsigned long end) | |
1270 | { | |
1271 | struct acpi_madt_generic_distributor *dist; | |
1272 | ||
1273 | dist = (struct acpi_madt_generic_distributor *)header; | |
1274 | ||
1275 | if (BAD_MADT_ENTRY(dist, end)) | |
1276 | return -EINVAL; | |
1277 | ||
1278 | dist_phy_base = dist->base_address; | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | int __init | |
1283 | gic_v2_acpi_init(struct acpi_table_header *table) | |
1284 | { | |
1285 | void __iomem *cpu_base, *dist_base; | |
1286 | int count; | |
1287 | ||
1288 | /* Collect CPU base addresses */ | |
1289 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1290 | sizeof(struct acpi_table_madt), | |
1291 | gic_acpi_parse_madt_cpu, table, | |
1292 | ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); | |
1293 | if (count <= 0) { | |
1294 | pr_err("No valid GICC entries exist\n"); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
1298 | /* | |
1299 | * Find distributor base address. We expect one distributor entry since | |
1300 | * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. | |
1301 | */ | |
1302 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1303 | sizeof(struct acpi_table_madt), | |
1304 | gic_acpi_parse_madt_distributor, table, | |
1305 | ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); | |
1306 | if (count <= 0) { | |
1307 | pr_err("No valid GICD entries exist\n"); | |
1308 | return -EINVAL; | |
1309 | } else if (count > 1) { | |
1310 | pr_err("More than one GICD entry detected\n"); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | ||
1314 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); | |
1315 | if (!cpu_base) { | |
1316 | pr_err("Unable to map GICC registers\n"); | |
1317 | return -ENOMEM; | |
1318 | } | |
1319 | ||
1320 | dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); | |
1321 | if (!dist_base) { | |
1322 | pr_err("Unable to map GICD registers\n"); | |
1323 | iounmap(cpu_base); | |
1324 | return -ENOMEM; | |
1325 | } | |
1326 | ||
0b996fd3 MZ |
1327 | /* |
1328 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1329 | * guarantees that we'll always have a GICv2, so the CPU | |
1330 | * interface will always be the right size. | |
1331 | */ | |
1332 | if (!is_hyp_mode_available()) | |
1333 | static_key_slow_dec(&supports_deactivate); | |
1334 | ||
d60fc389 TN |
1335 | /* |
1336 | * Initialize zero GIC instance (no multi-GIC support). Also, set GIC | |
1337 | * as default IRQ domain to allow for GSI registration and GSI to IRQ | |
1338 | * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). | |
1339 | */ | |
4a6ac304 | 1340 | __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); |
d60fc389 | 1341 | irq_set_default_host(gic_data[0].domain); |
d8f4f161 LP |
1342 | |
1343 | acpi_irq_model = ACPI_IRQ_MODEL_GIC; | |
d60fc389 TN |
1344 | return 0; |
1345 | } | |
1346 | #endif |