Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
0b996fd3 | 49 | #include <asm/virt.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
76e52dd0 MZ |
53 | #ifdef CONFIG_ARM64 |
54 | #include <asm/cpufeature.h> | |
55 | ||
56 | static void gic_check_cpu_features(void) | |
57 | { | |
58 | WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), | |
59 | TAINT_CPU_OUT_OF_SPEC, | |
60 | "GICv3 system registers enabled, broken firmware!\n"); | |
61 | } | |
62 | #else | |
63 | #define gic_check_cpu_features() do { } while(0) | |
64 | #endif | |
65 | ||
db0d4db2 MZ |
66 | union gic_base { |
67 | void __iomem *common_base; | |
6859358e | 68 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
69 | }; |
70 | ||
71 | struct gic_chip_data { | |
58b89649 | 72 | struct irq_chip chip; |
db0d4db2 MZ |
73 | union gic_base dist_base; |
74 | union gic_base cpu_base; | |
75 | #ifdef CONFIG_CPU_PM | |
76 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
1c7d4dd4 | 77 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
db0d4db2 MZ |
78 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
79 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
80 | u32 __percpu *saved_ppi_enable; | |
1c7d4dd4 | 81 | u32 __percpu *saved_ppi_active; |
db0d4db2 MZ |
82 | u32 __percpu *saved_ppi_conf; |
83 | #endif | |
75294957 | 84 | struct irq_domain *domain; |
db0d4db2 MZ |
85 | unsigned int gic_irqs; |
86 | #ifdef CONFIG_GIC_NON_BANKED | |
87 | void __iomem *(*get_base)(union gic_base *); | |
88 | #endif | |
89 | }; | |
90 | ||
bd31b859 | 91 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 92 | |
384a2902 NP |
93 | /* |
94 | * The GIC mapping of CPU interfaces does not necessarily match | |
95 | * the logical CPU numbering. Let's use a mapping as returned | |
96 | * by the GIC itself. | |
97 | */ | |
98 | #define NR_GIC_CPU_IF 8 | |
99 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
100 | ||
0b996fd3 MZ |
101 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
102 | ||
a27d21e0 | 103 | static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; |
b3a1bde4 | 104 | |
db0d4db2 MZ |
105 | #ifdef CONFIG_GIC_NON_BANKED |
106 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
107 | { | |
513d1a28 | 108 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
109 | } |
110 | ||
111 | static void __iomem *gic_get_common_base(union gic_base *base) | |
112 | { | |
113 | return base->common_base; | |
114 | } | |
115 | ||
116 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
117 | { | |
118 | return data->get_base(&data->dist_base); | |
119 | } | |
120 | ||
121 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
122 | { | |
123 | return data->get_base(&data->cpu_base); | |
124 | } | |
125 | ||
126 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
127 | void __iomem *(*f)(union gic_base *)) | |
128 | { | |
129 | data->get_base = f; | |
130 | } | |
131 | #else | |
132 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
133 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 134 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
135 | #endif |
136 | ||
7d1f4288 | 137 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 138 | { |
7d1f4288 | 139 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 140 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
141 | } |
142 | ||
7d1f4288 | 143 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 144 | { |
7d1f4288 | 145 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 146 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
147 | } |
148 | ||
7d1f4288 | 149 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 150 | { |
4294f8ba | 151 | return d->hwirq; |
b3a1bde4 CM |
152 | } |
153 | ||
01f779f4 MZ |
154 | static inline bool cascading_gic_irq(struct irq_data *d) |
155 | { | |
156 | void *data = irq_data_get_irq_handler_data(d); | |
157 | ||
158 | /* | |
71466535 TG |
159 | * If handler_data is set, this is a cascading interrupt, and |
160 | * it cannot possibly be forwarded. | |
01f779f4 | 161 | */ |
71466535 | 162 | return data != NULL; |
01f779f4 MZ |
163 | } |
164 | ||
f27ecacc RK |
165 | /* |
166 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 167 | */ |
56717807 MZ |
168 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
169 | { | |
170 | u32 mask = 1 << (gic_irq(d) % 32); | |
171 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
172 | } | |
173 | ||
174 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 175 | { |
4294f8ba | 176 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
177 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
178 | } | |
179 | ||
180 | static void gic_mask_irq(struct irq_data *d) | |
181 | { | |
56717807 | 182 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
183 | } |
184 | ||
0b996fd3 MZ |
185 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
186 | { | |
187 | gic_mask_irq(d); | |
01f779f4 MZ |
188 | /* |
189 | * When masking a forwarded interrupt, make sure it is | |
190 | * deactivated as well. | |
191 | * | |
192 | * This ensures that an interrupt that is getting | |
193 | * disabled/masked will not get "stuck", because there is | |
194 | * noone to deactivate it (guest is being terminated). | |
195 | */ | |
71466535 | 196 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 197 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
198 | } |
199 | ||
7d1f4288 | 200 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 201 | { |
56717807 | 202 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
203 | } |
204 | ||
1a01753e WD |
205 | static void gic_eoi_irq(struct irq_data *d) |
206 | { | |
6ac77e46 | 207 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
208 | } |
209 | ||
0b996fd3 MZ |
210 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
211 | { | |
01f779f4 | 212 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 213 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
214 | return; |
215 | ||
0b996fd3 MZ |
216 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
217 | } | |
218 | ||
56717807 MZ |
219 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
220 | enum irqchip_irq_state which, bool val) | |
221 | { | |
222 | u32 reg; | |
223 | ||
224 | switch (which) { | |
225 | case IRQCHIP_STATE_PENDING: | |
226 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
227 | break; | |
228 | ||
229 | case IRQCHIP_STATE_ACTIVE: | |
230 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
231 | break; | |
232 | ||
233 | case IRQCHIP_STATE_MASKED: | |
234 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
235 | break; | |
236 | ||
237 | default: | |
238 | return -EINVAL; | |
239 | } | |
240 | ||
241 | gic_poke_irq(d, reg); | |
242 | return 0; | |
243 | } | |
244 | ||
245 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
246 | enum irqchip_irq_state which, bool *val) | |
247 | { | |
248 | switch (which) { | |
249 | case IRQCHIP_STATE_PENDING: | |
250 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
251 | break; | |
252 | ||
253 | case IRQCHIP_STATE_ACTIVE: | |
254 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
255 | break; | |
256 | ||
257 | case IRQCHIP_STATE_MASKED: | |
258 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
259 | break; | |
260 | ||
261 | default: | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
7d1f4288 | 268 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 269 | { |
7d1f4288 LB |
270 | void __iomem *base = gic_dist_base(d); |
271 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
272 | |
273 | /* Interrupt configuration for SGIs can't be changed */ | |
274 | if (gicirq < 16) | |
275 | return -EINVAL; | |
276 | ||
fb7e7deb LD |
277 | /* SPIs have restrictions on the supported types */ |
278 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
279 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
280 | return -EINVAL; |
281 | ||
1dcc73d7 | 282 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
283 | } |
284 | ||
01f779f4 MZ |
285 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
286 | { | |
287 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
288 | if (cascading_gic_irq(d)) | |
289 | return -EINVAL; | |
290 | ||
71466535 TG |
291 | if (vcpu) |
292 | irqd_set_forwarded_to_vcpu(d); | |
293 | else | |
294 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
295 | return 0; |
296 | } | |
297 | ||
a06f5466 | 298 | #ifdef CONFIG_SMP |
c191789c RK |
299 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
300 | bool force) | |
f27ecacc | 301 | { |
7d1f4288 | 302 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 303 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 304 | u32 val, mask, bit; |
cf613871 | 305 | unsigned long flags; |
f27ecacc | 306 | |
ffde1de6 TG |
307 | if (!force) |
308 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
309 | else | |
310 | cpu = cpumask_first(mask_val); | |
311 | ||
384a2902 | 312 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 313 | return -EINVAL; |
c191789c | 314 | |
cf613871 | 315 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 316 | mask = 0xff << shift; |
384a2902 | 317 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
318 | val = readl_relaxed(reg) & ~mask; |
319 | writel_relaxed(val | bit, reg); | |
cf613871 | 320 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 321 | |
0407dace | 322 | return IRQ_SET_MASK_OK_DONE; |
f27ecacc | 323 | } |
a06f5466 | 324 | #endif |
f27ecacc | 325 | |
8783dd3a | 326 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
327 | { |
328 | u32 irqstat, irqnr; | |
329 | struct gic_chip_data *gic = &gic_data[0]; | |
330 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
331 | ||
332 | do { | |
333 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 334 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 | 335 | |
327ebe1f | 336 | if (likely(irqnr > 15 && irqnr < 1020)) { |
0b996fd3 MZ |
337 | if (static_key_true(&supports_deactivate)) |
338 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 339 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
340 | continue; |
341 | } | |
342 | if (irqnr < 16) { | |
343 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
344 | if (static_key_true(&supports_deactivate)) |
345 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 | 346 | #ifdef CONFIG_SMP |
f86c4fbd WD |
347 | /* |
348 | * Ensure any shared data written by the CPU sending | |
349 | * the IPI is read after we've read the ACK register | |
350 | * on the GIC. | |
351 | * | |
352 | * Pairs with the write barrier in gic_raise_softirq | |
353 | */ | |
354 | smp_rmb(); | |
562e0027 MZ |
355 | handle_IPI(irqnr, regs); |
356 | #endif | |
357 | continue; | |
358 | } | |
359 | break; | |
360 | } while (1); | |
361 | } | |
362 | ||
bd0b9ac4 | 363 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 364 | { |
5b29264c JL |
365 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
366 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 367 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
368 | unsigned long status; |
369 | ||
1a01753e | 370 | chained_irq_enter(chip, desc); |
b3a1bde4 | 371 | |
bd31b859 | 372 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 373 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 374 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 375 | |
e5f81539 FK |
376 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
377 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 378 | goto out; |
b3a1bde4 | 379 | |
75294957 GL |
380 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
381 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 382 | handle_bad_irq(desc); |
0f347bb9 RK |
383 | else |
384 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
385 | |
386 | out: | |
1a01753e | 387 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
388 | } |
389 | ||
38c677cb | 390 | static struct irq_chip gic_chip = { |
7d1f4288 LB |
391 | .irq_mask = gic_mask_irq, |
392 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 393 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 394 | .irq_set_type = gic_set_type, |
56717807 MZ |
395 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
396 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
397 | .flags = IRQCHIP_SET_TYPE_MASKED | |
398 | IRQCHIP_SKIP_SET_WAKE | | |
399 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
400 | }; |
401 | ||
b3a1bde4 CM |
402 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
403 | { | |
a27d21e0 | 404 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
4d83fcf8 TG |
405 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
406 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
407 | } |
408 | ||
2bb31351 RK |
409 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
410 | { | |
411 | void __iomem *base = gic_data_dist_base(gic); | |
412 | u32 mask, i; | |
413 | ||
414 | for (i = mask = 0; i < 32; i += 4) { | |
415 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
416 | mask |= mask >> 16; | |
417 | mask |= mask >> 8; | |
418 | if (mask) | |
419 | break; | |
420 | } | |
421 | ||
6e3aca44 | 422 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
423 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
424 | ||
425 | return mask; | |
426 | } | |
427 | ||
4c2880b3 | 428 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 429 | { |
4c2880b3 | 430 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 431 | u32 bypass = 0; |
0b996fd3 MZ |
432 | u32 mode = 0; |
433 | ||
389a00d3 | 434 | if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) |
0b996fd3 | 435 | mode = GIC_CPU_CTRL_EOImodeNS; |
32289506 FK |
436 | |
437 | /* | |
438 | * Preserve bypass disable bits to be written back later | |
439 | */ | |
440 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
441 | bypass &= GICC_DIS_BYPASS_MASK; | |
442 | ||
0b996fd3 | 443 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
444 | } |
445 | ||
446 | ||
4294f8ba | 447 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 448 | { |
75294957 | 449 | unsigned int i; |
267840f3 | 450 | u32 cpumask; |
4294f8ba | 451 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 452 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 453 | |
e5f81539 | 454 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 455 | |
f27ecacc RK |
456 | /* |
457 | * Set all global interrupts to this CPU only. | |
458 | */ | |
2bb31351 RK |
459 | cpumask = gic_get_cpumask(gic); |
460 | cpumask |= cpumask << 8; | |
461 | cpumask |= cpumask << 16; | |
e6afec9b | 462 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 463 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 464 | |
d51d0af4 | 465 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 466 | |
e5f81539 | 467 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
468 | } |
469 | ||
dc9722cc | 470 | static int gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 471 | { |
db0d4db2 MZ |
472 | void __iomem *dist_base = gic_data_dist_base(gic); |
473 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 474 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
475 | int i; |
476 | ||
384a2902 | 477 | /* |
567e5a01 JH |
478 | * Setting up the CPU map is only relevant for the primary GIC |
479 | * because any nested/secondary GICs do not directly interface | |
480 | * with the CPU(s). | |
384a2902 | 481 | */ |
567e5a01 JH |
482 | if (gic == &gic_data[0]) { |
483 | /* | |
484 | * Get what the GIC says our CPU mask is. | |
485 | */ | |
dc9722cc JH |
486 | if (WARN_ON(cpu >= NR_GIC_CPU_IF)) |
487 | return -EINVAL; | |
488 | ||
567e5a01 JH |
489 | cpu_mask = gic_get_cpumask(gic); |
490 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 491 | |
567e5a01 JH |
492 | /* |
493 | * Clear our mask from the other map entries in case they're | |
494 | * still undefined. | |
495 | */ | |
496 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
497 | if (i != cpu) | |
498 | gic_cpu_map[i] &= ~cpu_mask; | |
499 | } | |
384a2902 | 500 | |
d51d0af4 | 501 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 502 | |
e5f81539 | 503 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 504 | gic_cpu_if_up(gic); |
dc9722cc JH |
505 | |
506 | return 0; | |
f27ecacc RK |
507 | } |
508 | ||
4c2880b3 | 509 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 510 | { |
4c2880b3 | 511 | void __iomem *cpu_base; |
32289506 FK |
512 | u32 val = 0; |
513 | ||
a27d21e0 | 514 | if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) |
4c2880b3 JH |
515 | return -EINVAL; |
516 | ||
517 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
518 | val = readl(cpu_base + GIC_CPU_CTRL); |
519 | val &= ~GICC_ENABLE; | |
520 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
521 | |
522 | return 0; | |
10d9eb8a NP |
523 | } |
524 | ||
254056f3 CC |
525 | #ifdef CONFIG_CPU_PM |
526 | /* | |
527 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
528 | * with interrupts disabled but before powering down the GIC. After calling | |
529 | * this function, no interrupts will be delivered by the GIC, and another | |
530 | * platform-specific wakeup source must be enabled. | |
531 | */ | |
532 | static void gic_dist_save(unsigned int gic_nr) | |
533 | { | |
534 | unsigned int gic_irqs; | |
535 | void __iomem *dist_base; | |
536 | int i; | |
537 | ||
a27d21e0 | 538 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
254056f3 CC |
539 | |
540 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 541 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
542 | |
543 | if (!dist_base) | |
544 | return; | |
545 | ||
546 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
547 | gic_data[gic_nr].saved_spi_conf[i] = | |
548 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
549 | ||
550 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
551 | gic_data[gic_nr].saved_spi_target[i] = | |
552 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
553 | ||
554 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
555 | gic_data[gic_nr].saved_spi_enable[i] = | |
556 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
1c7d4dd4 MZ |
557 | |
558 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
559 | gic_data[gic_nr].saved_spi_active[i] = | |
560 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
254056f3 CC |
561 | } |
562 | ||
563 | /* | |
564 | * Restores the GIC distributor registers during resume or when coming out of | |
565 | * idle. Must be called before enabling interrupts. If a level interrupt | |
566 | * that occured while the GIC was suspended is still present, it will be | |
567 | * handled normally, but any edge interrupts that occured will not be seen by | |
568 | * the GIC and need to be handled by the platform-specific wakeup source. | |
569 | */ | |
570 | static void gic_dist_restore(unsigned int gic_nr) | |
571 | { | |
572 | unsigned int gic_irqs; | |
573 | unsigned int i; | |
574 | void __iomem *dist_base; | |
575 | ||
a27d21e0 | 576 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
254056f3 CC |
577 | |
578 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 579 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
580 | |
581 | if (!dist_base) | |
582 | return; | |
583 | ||
e5f81539 | 584 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
585 | |
586 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
587 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
588 | dist_base + GIC_DIST_CONFIG + i * 4); | |
589 | ||
590 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 591 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
592 | dist_base + GIC_DIST_PRI + i * 4); |
593 | ||
594 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
595 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
596 | dist_base + GIC_DIST_TARGET + i * 4); | |
597 | ||
92eda4ad MZ |
598 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
599 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
600 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 CC |
601 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
602 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
92eda4ad | 603 | } |
254056f3 | 604 | |
1c7d4dd4 MZ |
605 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
606 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
607 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
608 | writel_relaxed(gic_data[gic_nr].saved_spi_active[i], | |
609 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
610 | } | |
611 | ||
e5f81539 | 612 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
613 | } |
614 | ||
615 | static void gic_cpu_save(unsigned int gic_nr) | |
616 | { | |
617 | int i; | |
618 | u32 *ptr; | |
619 | void __iomem *dist_base; | |
620 | void __iomem *cpu_base; | |
621 | ||
a27d21e0 | 622 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
254056f3 | 623 | |
db0d4db2 MZ |
624 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
625 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
626 | |
627 | if (!dist_base || !cpu_base) | |
628 | return; | |
629 | ||
532d0d06 | 630 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
631 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
632 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
633 | ||
1c7d4dd4 MZ |
634 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); |
635 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
636 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
637 | ||
532d0d06 | 638 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
639 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
640 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
641 | ||
642 | } | |
643 | ||
644 | static void gic_cpu_restore(unsigned int gic_nr) | |
645 | { | |
646 | int i; | |
647 | u32 *ptr; | |
648 | void __iomem *dist_base; | |
649 | void __iomem *cpu_base; | |
650 | ||
a27d21e0 | 651 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
254056f3 | 652 | |
db0d4db2 MZ |
653 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
654 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
655 | |
656 | if (!dist_base || !cpu_base) | |
657 | return; | |
658 | ||
532d0d06 | 659 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
92eda4ad MZ |
660 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
661 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
662 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 | 663 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 664 | } |
254056f3 | 665 | |
1c7d4dd4 MZ |
666 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); |
667 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { | |
668 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
669 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
670 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
671 | } | |
672 | ||
532d0d06 | 673 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
674 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
675 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
676 | ||
677 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
678 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
679 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 680 | |
e5f81539 | 681 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
4c2880b3 | 682 | gic_cpu_if_up(&gic_data[gic_nr]); |
254056f3 CC |
683 | } |
684 | ||
685 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
686 | { | |
687 | int i; | |
688 | ||
a27d21e0 | 689 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { |
db0d4db2 MZ |
690 | #ifdef CONFIG_GIC_NON_BANKED |
691 | /* Skip over unused GICs */ | |
692 | if (!gic_data[i].get_base) | |
693 | continue; | |
694 | #endif | |
254056f3 CC |
695 | switch (cmd) { |
696 | case CPU_PM_ENTER: | |
697 | gic_cpu_save(i); | |
698 | break; | |
699 | case CPU_PM_ENTER_FAILED: | |
700 | case CPU_PM_EXIT: | |
701 | gic_cpu_restore(i); | |
702 | break; | |
703 | case CPU_CLUSTER_PM_ENTER: | |
704 | gic_dist_save(i); | |
705 | break; | |
706 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
707 | case CPU_CLUSTER_PM_EXIT: | |
708 | gic_dist_restore(i); | |
709 | break; | |
710 | } | |
711 | } | |
712 | ||
713 | return NOTIFY_OK; | |
714 | } | |
715 | ||
716 | static struct notifier_block gic_notifier_block = { | |
717 | .notifier_call = gic_notifier, | |
718 | }; | |
719 | ||
dc9722cc | 720 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 CC |
721 | { |
722 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
723 | sizeof(u32)); | |
dc9722cc JH |
724 | if (WARN_ON(!gic->saved_ppi_enable)) |
725 | return -ENOMEM; | |
254056f3 | 726 | |
1c7d4dd4 MZ |
727 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
728 | sizeof(u32)); | |
dc9722cc JH |
729 | if (WARN_ON(!gic->saved_ppi_active)) |
730 | goto free_ppi_enable; | |
1c7d4dd4 | 731 | |
254056f3 CC |
732 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
733 | sizeof(u32)); | |
dc9722cc JH |
734 | if (WARN_ON(!gic->saved_ppi_conf)) |
735 | goto free_ppi_active; | |
254056f3 | 736 | |
abdd7b91 MZ |
737 | if (gic == &gic_data[0]) |
738 | cpu_pm_register_notifier(&gic_notifier_block); | |
dc9722cc JH |
739 | |
740 | return 0; | |
741 | ||
742 | free_ppi_active: | |
743 | free_percpu(gic->saved_ppi_active); | |
744 | free_ppi_enable: | |
745 | free_percpu(gic->saved_ppi_enable); | |
746 | ||
747 | return -ENOMEM; | |
254056f3 CC |
748 | } |
749 | #else | |
dc9722cc | 750 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 | 751 | { |
dc9722cc | 752 | return 0; |
254056f3 CC |
753 | } |
754 | #endif | |
755 | ||
b1cffebf | 756 | #ifdef CONFIG_SMP |
6859358e | 757 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
758 | { |
759 | int cpu; | |
1a6b69b6 NP |
760 | unsigned long flags, map = 0; |
761 | ||
762 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
763 | |
764 | /* Convert our logical CPU mask into a physical one. */ | |
765 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 766 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
767 | |
768 | /* | |
769 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 770 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 771 | */ |
8adbf57f | 772 | dmb(ishst); |
b1cffebf RH |
773 | |
774 | /* this always happens on GIC0 */ | |
775 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
776 | |
777 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
778 | } | |
779 | #endif | |
780 | ||
781 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
782 | /* |
783 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
784 | * | |
785 | * cpu_id: the ID for the destination CPU interface | |
786 | * irq: the IPI number to send a SGI for | |
787 | */ | |
788 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
789 | { | |
790 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
791 | cpu_id = 1 << cpu_id; | |
792 | /* this always happens on GIC0 */ | |
793 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
794 | } | |
795 | ||
ed96762e NP |
796 | /* |
797 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
798 | * | |
799 | * @cpu: the logical CPU number to get the GIC ID for. | |
800 | * | |
801 | * Return the CPU interface ID for the given logical CPU number, | |
802 | * or -1 if the CPU number is too large or the interface ID is | |
803 | * unknown (more than one bit set). | |
804 | */ | |
805 | int gic_get_cpu_id(unsigned int cpu) | |
806 | { | |
807 | unsigned int cpu_bit; | |
808 | ||
809 | if (cpu >= NR_GIC_CPU_IF) | |
810 | return -1; | |
811 | cpu_bit = gic_cpu_map[cpu]; | |
812 | if (cpu_bit & (cpu_bit - 1)) | |
813 | return -1; | |
814 | return __ffs(cpu_bit); | |
815 | } | |
816 | ||
1a6b69b6 NP |
817 | /* |
818 | * gic_migrate_target - migrate IRQs to another CPU interface | |
819 | * | |
820 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
821 | * | |
822 | * Migrate all peripheral interrupts with a target matching the current CPU | |
823 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
824 | * is also updated. Targets to other CPU interfaces are unchanged. | |
825 | * This must be called with IRQs locally disabled. | |
826 | */ | |
827 | void gic_migrate_target(unsigned int new_cpu_id) | |
828 | { | |
829 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
830 | void __iomem *dist_base; | |
831 | int i, ror_val, cpu = smp_processor_id(); | |
832 | u32 val, cur_target_mask, active_mask; | |
833 | ||
a27d21e0 | 834 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
1a6b69b6 NP |
835 | |
836 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
837 | if (!dist_base) | |
838 | return; | |
839 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
840 | ||
841 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
842 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
843 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
844 | ||
845 | raw_spin_lock(&irq_controller_lock); | |
846 | ||
847 | /* Update the target interface for this logical CPU */ | |
848 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
849 | ||
850 | /* | |
851 | * Find all the peripheral interrupts targetting the current | |
852 | * CPU interface and migrate them to the new CPU interface. | |
853 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
854 | */ | |
855 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
856 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
857 | active_mask = val & cur_target_mask; | |
858 | if (active_mask) { | |
859 | val &= ~active_mask; | |
860 | val |= ror32(active_mask, ror_val); | |
861 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
862 | } | |
863 | } | |
864 | ||
865 | raw_spin_unlock(&irq_controller_lock); | |
866 | ||
867 | /* | |
868 | * Now let's migrate and clear any potential SGIs that might be | |
869 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
870 | * is a banked register, we can only forward the SGI using | |
871 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
872 | * doesn't use that information anyway. | |
873 | * | |
874 | * For the same reason we do not adjust SGI source information | |
875 | * for previously sent SGIs by us to other CPUs either. | |
876 | */ | |
877 | for (i = 0; i < 16; i += 4) { | |
878 | int j; | |
879 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
880 | if (!val) | |
881 | continue; | |
882 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
883 | for (j = i; j < i + 4; j++) { | |
884 | if (val & 0xff) | |
885 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
886 | dist_base + GIC_DIST_SOFTINT); | |
887 | val >>= 8; | |
888 | } | |
889 | } | |
b1cffebf | 890 | } |
eeb44658 NP |
891 | |
892 | /* | |
893 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
894 | * | |
895 | * REturn the physical address of the SGI register to be used | |
896 | * by some early assembly code when the kernel is not yet available. | |
897 | */ | |
898 | static unsigned long gic_dist_physaddr; | |
899 | ||
900 | unsigned long gic_get_sgir_physaddr(void) | |
901 | { | |
902 | if (!gic_dist_physaddr) | |
903 | return 0; | |
904 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
905 | } | |
906 | ||
907 | void __init gic_init_physaddr(struct device_node *node) | |
908 | { | |
909 | struct resource res; | |
910 | if (of_address_to_resource(node, 0, &res) == 0) { | |
911 | gic_dist_physaddr = res.start; | |
912 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
913 | } | |
914 | } | |
915 | ||
916 | #else | |
917 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
918 | #endif |
919 | ||
75294957 GL |
920 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
921 | irq_hw_number_t hw) | |
922 | { | |
58b89649 | 923 | struct gic_chip_data *gic = d->host_data; |
0b996fd3 | 924 | |
75294957 GL |
925 | if (hw < 32) { |
926 | irq_set_percpu_devid(irq); | |
58b89649 | 927 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 928 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 929 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 930 | } else { |
58b89649 | 931 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 932 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 933 | irq_set_probe(irq); |
75294957 | 934 | } |
75294957 GL |
935 | return 0; |
936 | } | |
937 | ||
006e983b S |
938 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
939 | { | |
006e983b S |
940 | } |
941 | ||
f833f57f MZ |
942 | static int gic_irq_domain_translate(struct irq_domain *d, |
943 | struct irq_fwspec *fwspec, | |
944 | unsigned long *hwirq, | |
945 | unsigned int *type) | |
946 | { | |
947 | if (is_of_node(fwspec->fwnode)) { | |
948 | if (fwspec->param_count < 3) | |
949 | return -EINVAL; | |
950 | ||
951 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
952 | *hwirq = fwspec->param[1] + 16; | |
953 | ||
954 | /* | |
955 | * For SPIs, we need to add 16 more to get the GIC irq | |
956 | * ID number | |
957 | */ | |
958 | if (!fwspec->param[0]) | |
959 | *hwirq += 16; | |
960 | ||
961 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
962 | return 0; | |
963 | } | |
964 | ||
75aba7b0 | 965 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
891ae769 MZ |
966 | if(fwspec->param_count != 2) |
967 | return -EINVAL; | |
968 | ||
969 | *hwirq = fwspec->param[0]; | |
970 | *type = fwspec->param[1]; | |
971 | return 0; | |
972 | } | |
973 | ||
f833f57f MZ |
974 | return -EINVAL; |
975 | } | |
976 | ||
c0114709 | 977 | #ifdef CONFIG_SMP |
8c37bb3a PG |
978 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
979 | void *hcpu) | |
c0114709 | 980 | { |
8b6fd652 | 981 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
982 | gic_cpu_init(&gic_data[0]); |
983 | return NOTIFY_OK; | |
984 | } | |
985 | ||
986 | /* | |
987 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
988 | * priority because the GIC needs to be up before the ARM generic timers. | |
989 | */ | |
8c37bb3a | 990 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
991 | .notifier_call = gic_secondary_init, |
992 | .priority = 100, | |
993 | }; | |
994 | #endif | |
995 | ||
9a1091ef YC |
996 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
997 | unsigned int nr_irqs, void *arg) | |
998 | { | |
999 | int i, ret; | |
1000 | irq_hw_number_t hwirq; | |
1001 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1002 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 1003 | |
f833f57f | 1004 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
1005 | if (ret) |
1006 | return ret; | |
1007 | ||
1008 | for (i = 0; i < nr_irqs; i++) | |
1009 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1015 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1016 | .alloc = gic_irq_domain_alloc, |
1017 | .free = irq_domain_free_irqs_top, | |
1018 | }; | |
1019 | ||
6859358e | 1020 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1021 | .map = gic_irq_domain_map, |
006e983b | 1022 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
1023 | }; |
1024 | ||
dc9722cc | 1025 | static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, |
db0d4db2 | 1026 | void __iomem *dist_base, void __iomem *cpu_base, |
891ae769 | 1027 | u32 percpu_offset, struct fwnode_handle *handle) |
b580b899 | 1028 | { |
75294957 | 1029 | irq_hw_number_t hwirq_base; |
bef8f9ee | 1030 | struct gic_chip_data *gic; |
dc9722cc | 1031 | int gic_irqs, irq_base, i, ret; |
bef8f9ee | 1032 | |
a27d21e0 | 1033 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
bef8f9ee | 1034 | |
76e52dd0 MZ |
1035 | gic_check_cpu_features(); |
1036 | ||
bef8f9ee | 1037 | gic = &gic_data[gic_nr]; |
58b89649 LW |
1038 | |
1039 | /* Initialize irq_chip */ | |
c2baa2f3 JH |
1040 | gic->chip = gic_chip; |
1041 | ||
58b89649 | 1042 | if (static_key_true(&supports_deactivate) && gic_nr == 0) { |
c2baa2f3 JH |
1043 | gic->chip.irq_mask = gic_eoimode1_mask_irq; |
1044 | gic->chip.irq_eoi = gic_eoimode1_eoi_irq; | |
1045 | gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; | |
dc9722cc | 1046 | gic->chip.name = kasprintf(GFP_KERNEL, "GICv2"); |
58b89649 | 1047 | } else { |
58b89649 LW |
1048 | gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr); |
1049 | } | |
1050 | ||
7bf29d3a JH |
1051 | #ifdef CONFIG_SMP |
1052 | if (gic_nr == 0) | |
1053 | gic->chip.irq_set_affinity = gic_set_affinity; | |
1054 | #endif | |
1055 | ||
dc9722cc JH |
1056 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { |
1057 | /* Frankein-GIC without banked registers... */ | |
db0d4db2 MZ |
1058 | unsigned int cpu; |
1059 | ||
1060 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1061 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1062 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1063 | !gic->cpu_base.percpu_base)) { | |
dc9722cc JH |
1064 | ret = -ENOMEM; |
1065 | goto error; | |
db0d4db2 MZ |
1066 | } |
1067 | ||
1068 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1069 | u32 mpidr = cpu_logical_map(cpu); |
1070 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
1071 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
1072 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
1073 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
1074 | } | |
1075 | ||
1076 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
dc9722cc JH |
1077 | } else { |
1078 | /* Normal, sane GIC... */ | |
db0d4db2 MZ |
1079 | WARN(percpu_offset, |
1080 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
1081 | percpu_offset); | |
1082 | gic->dist_base.common_base = dist_base; | |
1083 | gic->cpu_base.common_base = cpu_base; | |
1084 | gic_set_base_accessor(gic, gic_get_common_base); | |
1085 | } | |
bef8f9ee | 1086 | |
4294f8ba RH |
1087 | /* |
1088 | * Find out how many interrupts are supported. | |
1089 | * The GIC only supports up to 1020 interrupt sources. | |
1090 | */ | |
db0d4db2 | 1091 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1092 | gic_irqs = (gic_irqs + 1) * 32; |
1093 | if (gic_irqs > 1020) | |
1094 | gic_irqs = 1020; | |
1095 | gic->gic_irqs = gic_irqs; | |
1096 | ||
891ae769 MZ |
1097 | if (handle) { /* DT/ACPI */ |
1098 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1099 | &gic_irq_domain_hierarchy_ops, | |
1100 | gic); | |
1101 | } else { /* Legacy support */ | |
9a1091ef YC |
1102 | /* |
1103 | * For primary GICs, skip over SGIs. | |
1104 | * For secondary GICs, skip over PPIs, too. | |
1105 | */ | |
1106 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
1107 | hwirq_base = 16; | |
1108 | if (irq_start != -1) | |
1109 | irq_start = (irq_start & ~31) + 16; | |
1110 | } else { | |
1111 | hwirq_base = 32; | |
1112 | } | |
1113 | ||
1114 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1115 | |
006e983b S |
1116 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1117 | numa_node_id()); | |
1118 | if (IS_ERR_VALUE(irq_base)) { | |
1119 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1120 | irq_start); | |
1121 | irq_base = irq_start; | |
1122 | } | |
1123 | ||
891ae769 | 1124 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
006e983b | 1125 | hwirq_base, &gic_irq_domain_ops, gic); |
f37a53cc | 1126 | } |
006e983b | 1127 | |
dc9722cc JH |
1128 | if (WARN_ON(!gic->domain)) { |
1129 | ret = -ENODEV; | |
1130 | goto error; | |
1131 | } | |
bef8f9ee | 1132 | |
08332dff | 1133 | if (gic_nr == 0) { |
567e5a01 JH |
1134 | /* |
1135 | * Initialize the CPU interface map to all CPUs. | |
1136 | * It will be refined as each CPU probes its ID. | |
1137 | * This is only necessary for the primary GIC. | |
1138 | */ | |
1139 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1140 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 1141 | #ifdef CONFIG_SMP |
08332dff MR |
1142 | set_smp_cross_call(gic_raise_softirq); |
1143 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1144 | #endif |
08332dff | 1145 | set_handle_irq(gic_handle_irq); |
0b996fd3 MZ |
1146 | if (static_key_true(&supports_deactivate)) |
1147 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
08332dff | 1148 | } |
cfed7d60 | 1149 | |
4294f8ba | 1150 | gic_dist_init(gic); |
dc9722cc JH |
1151 | ret = gic_cpu_init(gic); |
1152 | if (ret) | |
1153 | goto error; | |
1154 | ||
1155 | ret = gic_pm_init(gic); | |
1156 | if (ret) | |
1157 | goto error; | |
1158 | ||
1159 | return 0; | |
1160 | ||
1161 | error: | |
1162 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { | |
1163 | free_percpu(gic->dist_base.percpu_base); | |
1164 | free_percpu(gic->cpu_base.percpu_base); | |
1165 | } | |
1166 | ||
1167 | kfree(gic->chip.name); | |
1168 | ||
1169 | return ret; | |
b580b899 RK |
1170 | } |
1171 | ||
e81a7cd9 MZ |
1172 | void __init gic_init(unsigned int gic_nr, int irq_start, |
1173 | void __iomem *dist_base, void __iomem *cpu_base) | |
4a6ac304 MZ |
1174 | { |
1175 | /* | |
1176 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1177 | * bother with these... | |
1178 | */ | |
1179 | static_key_slow_dec(&supports_deactivate); | |
e81a7cd9 | 1180 | __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); |
4a6ac304 MZ |
1181 | } |
1182 | ||
b3f7ed03 | 1183 | #ifdef CONFIG_OF |
46f101df | 1184 | static int gic_cnt __initdata; |
b3f7ed03 | 1185 | |
12e14066 MZ |
1186 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1187 | { | |
1188 | struct resource cpuif_res; | |
1189 | ||
1190 | of_address_to_resource(node, 1, &cpuif_res); | |
1191 | ||
1192 | if (!is_hyp_mode_available()) | |
1193 | return false; | |
1194 | if (resource_size(&cpuif_res) < SZ_8K) | |
1195 | return false; | |
1196 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1197 | u32 val_low, val_high; | |
1198 | ||
1199 | /* | |
1200 | * Verify that we have the first 4kB of a GIC400 | |
1201 | * aliased over the first 64kB by checking the | |
1202 | * GICC_IIDR register on both ends. | |
1203 | */ | |
1204 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1205 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1206 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1207 | val_low != val_high) | |
1208 | return false; | |
1209 | ||
1210 | /* | |
1211 | * Move the base up by 60kB, so that we have a 8kB | |
1212 | * contiguous region, which allows us to use GICC_DIR | |
1213 | * at its normal offset. Please pass me that bucket. | |
1214 | */ | |
1215 | *base += 0xf000; | |
1216 | cpuif_res.start += 0xf000; | |
1217 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1218 | &cpuif_res.start); | |
1219 | } | |
1220 | ||
1221 | return true; | |
1222 | } | |
1223 | ||
8673c1d7 | 1224 | int __init |
6859358e | 1225 | gic_of_init(struct device_node *node, struct device_node *parent) |
b3f7ed03 RH |
1226 | { |
1227 | void __iomem *cpu_base; | |
1228 | void __iomem *dist_base; | |
db0d4db2 | 1229 | u32 percpu_offset; |
dc9722cc | 1230 | int irq, ret; |
b3f7ed03 RH |
1231 | |
1232 | if (WARN_ON(!node)) | |
1233 | return -ENODEV; | |
1234 | ||
1235 | dist_base = of_iomap(node, 0); | |
26acfe74 JH |
1236 | if (WARN(!dist_base, "unable to map gic dist registers\n")) |
1237 | return -ENOMEM; | |
b3f7ed03 RH |
1238 | |
1239 | cpu_base = of_iomap(node, 1); | |
26acfe74 JH |
1240 | if (WARN(!cpu_base, "unable to map gic cpu registers\n")) { |
1241 | iounmap(dist_base); | |
1242 | return -ENOMEM; | |
1243 | } | |
b3f7ed03 | 1244 | |
0b996fd3 MZ |
1245 | /* |
1246 | * Disable split EOI/Deactivate if either HYP is not available | |
1247 | * or the CPU interface is too small. | |
1248 | */ | |
12e14066 | 1249 | if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) |
0b996fd3 MZ |
1250 | static_key_slow_dec(&supports_deactivate); |
1251 | ||
db0d4db2 MZ |
1252 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1253 | percpu_offset = 0; | |
1254 | ||
dc9722cc | 1255 | ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, |
891ae769 | 1256 | &node->fwnode); |
dc9722cc JH |
1257 | if (ret) { |
1258 | iounmap(dist_base); | |
1259 | iounmap(cpu_base); | |
1260 | return ret; | |
1261 | } | |
1262 | ||
eeb44658 NP |
1263 | if (!gic_cnt) |
1264 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1265 | |
1266 | if (parent) { | |
1267 | irq = irq_of_parse_and_map(node, 0); | |
1268 | gic_cascade_irq(gic_cnt, irq); | |
1269 | } | |
853a33ce SS |
1270 | |
1271 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
0644b3da | 1272 | gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); |
853a33ce | 1273 | |
b3f7ed03 RH |
1274 | gic_cnt++; |
1275 | return 0; | |
1276 | } | |
144cb088 | 1277 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1278 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1279 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1280 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1281 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1282 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1283 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1284 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1285 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1286 | |
b3f7ed03 | 1287 | #endif |
d60fc389 TN |
1288 | |
1289 | #ifdef CONFIG_ACPI | |
f26527b1 | 1290 | static phys_addr_t cpu_phy_base __initdata; |
d60fc389 TN |
1291 | |
1292 | static int __init | |
1293 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1294 | const unsigned long end) | |
1295 | { | |
1296 | struct acpi_madt_generic_interrupt *processor; | |
1297 | phys_addr_t gic_cpu_base; | |
1298 | static int cpu_base_assigned; | |
1299 | ||
1300 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1301 | ||
99e3e3ae | 1302 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1303 | return -EINVAL; |
1304 | ||
1305 | /* | |
1306 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1307 | * All CPU interface addresses have to be the same. | |
1308 | */ | |
1309 | gic_cpu_base = processor->base_address; | |
1310 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1311 | return -EINVAL; | |
1312 | ||
1313 | cpu_phy_base = gic_cpu_base; | |
1314 | cpu_base_assigned = 1; | |
1315 | return 0; | |
1316 | } | |
1317 | ||
f26527b1 MZ |
1318 | /* The things you have to do to just *count* something... */ |
1319 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, | |
1320 | const unsigned long end) | |
d60fc389 | 1321 | { |
f26527b1 MZ |
1322 | return 0; |
1323 | } | |
d60fc389 | 1324 | |
f26527b1 MZ |
1325 | static bool __init acpi_gic_redist_is_present(void) |
1326 | { | |
1327 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1328 | acpi_dummy_func, 0) > 0; | |
1329 | } | |
d60fc389 | 1330 | |
f26527b1 MZ |
1331 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1332 | struct acpi_probe_entry *ape) | |
1333 | { | |
1334 | struct acpi_madt_generic_distributor *dist; | |
1335 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1336 | |
f26527b1 MZ |
1337 | return (dist->version == ape->driver_data && |
1338 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1339 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1340 | } |
1341 | ||
f26527b1 MZ |
1342 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1343 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
1344 | ||
1345 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1346 | const unsigned long end) | |
d60fc389 | 1347 | { |
f26527b1 | 1348 | struct acpi_madt_generic_distributor *dist; |
d60fc389 | 1349 | void __iomem *cpu_base, *dist_base; |
891ae769 | 1350 | struct fwnode_handle *domain_handle; |
dc9722cc | 1351 | int count, ret; |
d60fc389 TN |
1352 | |
1353 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1354 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1355 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1356 | if (count <= 0) { |
1357 | pr_err("No valid GICC entries exist\n"); | |
1358 | return -EINVAL; | |
1359 | } | |
1360 | ||
d60fc389 TN |
1361 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
1362 | if (!cpu_base) { | |
1363 | pr_err("Unable to map GICC registers\n"); | |
1364 | return -ENOMEM; | |
1365 | } | |
1366 | ||
f26527b1 MZ |
1367 | dist = (struct acpi_madt_generic_distributor *)header; |
1368 | dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE); | |
d60fc389 TN |
1369 | if (!dist_base) { |
1370 | pr_err("Unable to map GICD registers\n"); | |
1371 | iounmap(cpu_base); | |
1372 | return -ENOMEM; | |
1373 | } | |
1374 | ||
0b996fd3 MZ |
1375 | /* |
1376 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1377 | * guarantees that we'll always have a GICv2, so the CPU | |
1378 | * interface will always be the right size. | |
1379 | */ | |
1380 | if (!is_hyp_mode_available()) | |
1381 | static_key_slow_dec(&supports_deactivate); | |
1382 | ||
d60fc389 | 1383 | /* |
891ae769 | 1384 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1385 | */ |
891ae769 MZ |
1386 | domain_handle = irq_domain_alloc_fwnode(dist_base); |
1387 | if (!domain_handle) { | |
1388 | pr_err("Unable to allocate domain handle\n"); | |
1389 | iounmap(cpu_base); | |
1390 | iounmap(dist_base); | |
1391 | return -ENOMEM; | |
1392 | } | |
1393 | ||
dc9722cc JH |
1394 | ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); |
1395 | if (ret) { | |
1396 | pr_err("Failed to initialise GIC\n"); | |
1397 | irq_domain_free_fwnode(domain_handle); | |
1398 | iounmap(cpu_base); | |
1399 | iounmap(dist_base); | |
1400 | return ret; | |
1401 | } | |
d8f4f161 | 1402 | |
891ae769 | 1403 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
0644b3da SS |
1404 | |
1405 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1406 | gicv2m_init(NULL, gic_data[0].domain); | |
1407 | ||
d60fc389 TN |
1408 | return 0; |
1409 | } | |
f26527b1 MZ |
1410 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1411 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1412 | gic_v2_acpi_init); | |
1413 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1414 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1415 | gic_v2_acpi_init); | |
d60fc389 | 1416 | #endif |