Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
de88cbb7 | 41 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 42 | #include <linux/irqchip/arm-gic.h> |
d60fc389 | 43 | #include <linux/irqchip/arm-gic-acpi.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
f27ecacc | 49 | |
d51d0af4 | 50 | #include "irq-gic-common.h" |
81243e44 | 51 | #include "irqchip.h" |
f27ecacc | 52 | |
db0d4db2 MZ |
53 | union gic_base { |
54 | void __iomem *common_base; | |
6859358e | 55 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
56 | }; |
57 | ||
58 | struct gic_chip_data { | |
db0d4db2 MZ |
59 | union gic_base dist_base; |
60 | union gic_base cpu_base; | |
61 | #ifdef CONFIG_CPU_PM | |
62 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
63 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
64 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
65 | u32 __percpu *saved_ppi_enable; | |
66 | u32 __percpu *saved_ppi_conf; | |
67 | #endif | |
75294957 | 68 | struct irq_domain *domain; |
db0d4db2 MZ |
69 | unsigned int gic_irqs; |
70 | #ifdef CONFIG_GIC_NON_BANKED | |
71 | void __iomem *(*get_base)(union gic_base *); | |
72 | #endif | |
73 | }; | |
74 | ||
bd31b859 | 75 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 76 | |
384a2902 NP |
77 | /* |
78 | * The GIC mapping of CPU interfaces does not necessarily match | |
79 | * the logical CPU numbering. Let's use a mapping as returned | |
80 | * by the GIC itself. | |
81 | */ | |
82 | #define NR_GIC_CPU_IF 8 | |
83 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
84 | ||
d7ed36a4 SS |
85 | /* |
86 | * Supported arch specific GIC irq extension. | |
87 | * Default make them NULL. | |
88 | */ | |
89 | struct irq_chip gic_arch_extn = { | |
1a01753e | 90 | .irq_eoi = NULL, |
d7ed36a4 SS |
91 | .irq_mask = NULL, |
92 | .irq_unmask = NULL, | |
93 | .irq_retrigger = NULL, | |
94 | .irq_set_type = NULL, | |
95 | .irq_set_wake = NULL, | |
96 | }; | |
97 | ||
b3a1bde4 CM |
98 | #ifndef MAX_GIC_NR |
99 | #define MAX_GIC_NR 1 | |
100 | #endif | |
101 | ||
bef8f9ee | 102 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 103 | |
db0d4db2 MZ |
104 | #ifdef CONFIG_GIC_NON_BANKED |
105 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
106 | { | |
513d1a28 | 107 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
108 | } |
109 | ||
110 | static void __iomem *gic_get_common_base(union gic_base *base) | |
111 | { | |
112 | return base->common_base; | |
113 | } | |
114 | ||
115 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
116 | { | |
117 | return data->get_base(&data->dist_base); | |
118 | } | |
119 | ||
120 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
121 | { | |
122 | return data->get_base(&data->cpu_base); | |
123 | } | |
124 | ||
125 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
126 | void __iomem *(*f)(union gic_base *)) | |
127 | { | |
128 | data->get_base = f; | |
129 | } | |
130 | #else | |
131 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
132 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 133 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
134 | #endif |
135 | ||
7d1f4288 | 136 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 137 | { |
7d1f4288 | 138 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 139 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
140 | } |
141 | ||
7d1f4288 | 142 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 143 | { |
7d1f4288 | 144 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 145 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
146 | } |
147 | ||
7d1f4288 | 148 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 149 | { |
4294f8ba | 150 | return d->hwirq; |
b3a1bde4 CM |
151 | } |
152 | ||
f27ecacc RK |
153 | /* |
154 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 155 | */ |
7d1f4288 | 156 | static void gic_mask_irq(struct irq_data *d) |
f27ecacc | 157 | { |
4294f8ba | 158 | u32 mask = 1 << (gic_irq(d) % 32); |
cf613871 | 159 | unsigned long flags; |
c4bfa28a | 160 | |
cf613871 | 161 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
6ac77e46 | 162 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
d7ed36a4 SS |
163 | if (gic_arch_extn.irq_mask) |
164 | gic_arch_extn.irq_mask(d); | |
cf613871 | 165 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
f27ecacc RK |
166 | } |
167 | ||
7d1f4288 | 168 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 169 | { |
4294f8ba | 170 | u32 mask = 1 << (gic_irq(d) % 32); |
cf613871 | 171 | unsigned long flags; |
c4bfa28a | 172 | |
cf613871 | 173 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
d7ed36a4 SS |
174 | if (gic_arch_extn.irq_unmask) |
175 | gic_arch_extn.irq_unmask(d); | |
6ac77e46 | 176 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
cf613871 | 177 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
f27ecacc RK |
178 | } |
179 | ||
1a01753e WD |
180 | static void gic_eoi_irq(struct irq_data *d) |
181 | { | |
182 | if (gic_arch_extn.irq_eoi) { | |
bd31b859 | 183 | raw_spin_lock(&irq_controller_lock); |
1a01753e | 184 | gic_arch_extn.irq_eoi(d); |
bd31b859 | 185 | raw_spin_unlock(&irq_controller_lock); |
1a01753e WD |
186 | } |
187 | ||
6ac77e46 | 188 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
189 | } |
190 | ||
7d1f4288 | 191 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 192 | { |
7d1f4288 LB |
193 | void __iomem *base = gic_dist_base(d); |
194 | unsigned int gicirq = gic_irq(d); | |
cf613871 | 195 | unsigned long flags; |
fb7e7deb | 196 | int ret; |
5c0c1f08 RV |
197 | |
198 | /* Interrupt configuration for SGIs can't be changed */ | |
199 | if (gicirq < 16) | |
200 | return -EINVAL; | |
201 | ||
fb7e7deb LD |
202 | /* SPIs have restrictions on the supported types */ |
203 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
204 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
205 | return -EINVAL; |
206 | ||
cf613871 | 207 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
5c0c1f08 | 208 | |
d7ed36a4 SS |
209 | if (gic_arch_extn.irq_set_type) |
210 | gic_arch_extn.irq_set_type(d, type); | |
211 | ||
fb7e7deb | 212 | ret = gic_configure_irq(gicirq, type, base, NULL); |
5c0c1f08 | 213 | |
cf613871 | 214 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
5c0c1f08 | 215 | |
fb7e7deb | 216 | return ret; |
5c0c1f08 RV |
217 | } |
218 | ||
d7ed36a4 SS |
219 | static int gic_retrigger(struct irq_data *d) |
220 | { | |
221 | if (gic_arch_extn.irq_retrigger) | |
222 | return gic_arch_extn.irq_retrigger(d); | |
223 | ||
bad9a43a AD |
224 | /* the genirq layer expects 0 if we can't retrigger in hardware */ |
225 | return 0; | |
d7ed36a4 SS |
226 | } |
227 | ||
a06f5466 | 228 | #ifdef CONFIG_SMP |
c191789c RK |
229 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
230 | bool force) | |
f27ecacc | 231 | { |
7d1f4288 | 232 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 233 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 234 | u32 val, mask, bit; |
cf613871 | 235 | unsigned long flags; |
f27ecacc | 236 | |
ffde1de6 TG |
237 | if (!force) |
238 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
239 | else | |
240 | cpu = cpumask_first(mask_val); | |
241 | ||
384a2902 | 242 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 243 | return -EINVAL; |
c191789c | 244 | |
cf613871 | 245 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 246 | mask = 0xff << shift; |
384a2902 | 247 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
248 | val = readl_relaxed(reg) & ~mask; |
249 | writel_relaxed(val | bit, reg); | |
cf613871 | 250 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 251 | |
5dfc54e0 | 252 | return IRQ_SET_MASK_OK; |
f27ecacc | 253 | } |
a06f5466 | 254 | #endif |
f27ecacc | 255 | |
d7ed36a4 SS |
256 | #ifdef CONFIG_PM |
257 | static int gic_set_wake(struct irq_data *d, unsigned int on) | |
258 | { | |
259 | int ret = -ENXIO; | |
260 | ||
261 | if (gic_arch_extn.irq_set_wake) | |
262 | ret = gic_arch_extn.irq_set_wake(d, on); | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
267 | #else | |
268 | #define gic_set_wake NULL | |
269 | #endif | |
270 | ||
8783dd3a | 271 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
272 | { |
273 | u32 irqstat, irqnr; | |
274 | struct gic_chip_data *gic = &gic_data[0]; | |
275 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
276 | ||
277 | do { | |
278 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 279 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 MZ |
280 | |
281 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
60031b4e | 282 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
283 | continue; |
284 | } | |
285 | if (irqnr < 16) { | |
286 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
287 | #ifdef CONFIG_SMP | |
288 | handle_IPI(irqnr, regs); | |
289 | #endif | |
290 | continue; | |
291 | } | |
292 | break; | |
293 | } while (1); | |
294 | } | |
295 | ||
0f347bb9 | 296 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 | 297 | { |
6845664a TG |
298 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
299 | struct irq_chip *chip = irq_get_chip(irq); | |
0f347bb9 | 300 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
301 | unsigned long status; |
302 | ||
1a01753e | 303 | chained_irq_enter(chip, desc); |
b3a1bde4 | 304 | |
bd31b859 | 305 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 306 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 307 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 308 | |
e5f81539 FK |
309 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
310 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 311 | goto out; |
b3a1bde4 | 312 | |
75294957 GL |
313 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
314 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
aec00956 | 315 | handle_bad_irq(cascade_irq, desc); |
0f347bb9 RK |
316 | else |
317 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
318 | |
319 | out: | |
1a01753e | 320 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
321 | } |
322 | ||
38c677cb | 323 | static struct irq_chip gic_chip = { |
7d1f4288 | 324 | .name = "GIC", |
7d1f4288 LB |
325 | .irq_mask = gic_mask_irq, |
326 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 327 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 328 | .irq_set_type = gic_set_type, |
d7ed36a4 | 329 | .irq_retrigger = gic_retrigger, |
f27ecacc | 330 | #ifdef CONFIG_SMP |
c191789c | 331 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 332 | #endif |
d7ed36a4 | 333 | .irq_set_wake = gic_set_wake, |
f27ecacc RK |
334 | }; |
335 | ||
b3a1bde4 CM |
336 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
337 | { | |
338 | if (gic_nr >= MAX_GIC_NR) | |
339 | BUG(); | |
6845664a | 340 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
b3a1bde4 | 341 | BUG(); |
6845664a | 342 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
b3a1bde4 CM |
343 | } |
344 | ||
2bb31351 RK |
345 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
346 | { | |
347 | void __iomem *base = gic_data_dist_base(gic); | |
348 | u32 mask, i; | |
349 | ||
350 | for (i = mask = 0; i < 32; i += 4) { | |
351 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
352 | mask |= mask >> 16; | |
353 | mask |= mask >> 8; | |
354 | if (mask) | |
355 | break; | |
356 | } | |
357 | ||
358 | if (!mask) | |
359 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); | |
360 | ||
361 | return mask; | |
362 | } | |
363 | ||
32289506 FK |
364 | static void gic_cpu_if_up(void) |
365 | { | |
366 | void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); | |
367 | u32 bypass = 0; | |
368 | ||
369 | /* | |
370 | * Preserve bypass disable bits to be written back later | |
371 | */ | |
372 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
373 | bypass &= GICC_DIS_BYPASS_MASK; | |
374 | ||
375 | writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); | |
376 | } | |
377 | ||
378 | ||
4294f8ba | 379 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 380 | { |
75294957 | 381 | unsigned int i; |
267840f3 | 382 | u32 cpumask; |
4294f8ba | 383 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 384 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 385 | |
e5f81539 | 386 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 387 | |
f27ecacc RK |
388 | /* |
389 | * Set all global interrupts to this CPU only. | |
390 | */ | |
2bb31351 RK |
391 | cpumask = gic_get_cpumask(gic); |
392 | cpumask |= cpumask << 8; | |
393 | cpumask |= cpumask << 16; | |
e6afec9b | 394 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 395 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 396 | |
d51d0af4 | 397 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 398 | |
e5f81539 | 399 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
400 | } |
401 | ||
8c37bb3a | 402 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 403 | { |
db0d4db2 MZ |
404 | void __iomem *dist_base = gic_data_dist_base(gic); |
405 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 406 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
407 | int i; |
408 | ||
384a2902 NP |
409 | /* |
410 | * Get what the GIC says our CPU mask is. | |
411 | */ | |
412 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
2bb31351 | 413 | cpu_mask = gic_get_cpumask(gic); |
384a2902 NP |
414 | gic_cpu_map[cpu] = cpu_mask; |
415 | ||
416 | /* | |
417 | * Clear our mask from the other map entries in case they're | |
418 | * still undefined. | |
419 | */ | |
420 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
421 | if (i != cpu) | |
422 | gic_cpu_map[i] &= ~cpu_mask; | |
423 | ||
d51d0af4 | 424 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 425 | |
e5f81539 | 426 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
32289506 | 427 | gic_cpu_if_up(); |
f27ecacc RK |
428 | } |
429 | ||
10d9eb8a NP |
430 | void gic_cpu_if_down(void) |
431 | { | |
432 | void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); | |
32289506 FK |
433 | u32 val = 0; |
434 | ||
435 | val = readl(cpu_base + GIC_CPU_CTRL); | |
436 | val &= ~GICC_ENABLE; | |
437 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
10d9eb8a NP |
438 | } |
439 | ||
254056f3 CC |
440 | #ifdef CONFIG_CPU_PM |
441 | /* | |
442 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
443 | * with interrupts disabled but before powering down the GIC. After calling | |
444 | * this function, no interrupts will be delivered by the GIC, and another | |
445 | * platform-specific wakeup source must be enabled. | |
446 | */ | |
447 | static void gic_dist_save(unsigned int gic_nr) | |
448 | { | |
449 | unsigned int gic_irqs; | |
450 | void __iomem *dist_base; | |
451 | int i; | |
452 | ||
453 | if (gic_nr >= MAX_GIC_NR) | |
454 | BUG(); | |
455 | ||
456 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 457 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
458 | |
459 | if (!dist_base) | |
460 | return; | |
461 | ||
462 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
463 | gic_data[gic_nr].saved_spi_conf[i] = | |
464 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
465 | ||
466 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
467 | gic_data[gic_nr].saved_spi_target[i] = | |
468 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
469 | ||
470 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
471 | gic_data[gic_nr].saved_spi_enable[i] = | |
472 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
473 | } | |
474 | ||
475 | /* | |
476 | * Restores the GIC distributor registers during resume or when coming out of | |
477 | * idle. Must be called before enabling interrupts. If a level interrupt | |
478 | * that occured while the GIC was suspended is still present, it will be | |
479 | * handled normally, but any edge interrupts that occured will not be seen by | |
480 | * the GIC and need to be handled by the platform-specific wakeup source. | |
481 | */ | |
482 | static void gic_dist_restore(unsigned int gic_nr) | |
483 | { | |
484 | unsigned int gic_irqs; | |
485 | unsigned int i; | |
486 | void __iomem *dist_base; | |
487 | ||
488 | if (gic_nr >= MAX_GIC_NR) | |
489 | BUG(); | |
490 | ||
491 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 492 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
493 | |
494 | if (!dist_base) | |
495 | return; | |
496 | ||
e5f81539 | 497 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
498 | |
499 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
500 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
501 | dist_base + GIC_DIST_CONFIG + i * 4); | |
502 | ||
503 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 504 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
505 | dist_base + GIC_DIST_PRI + i * 4); |
506 | ||
507 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
508 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
509 | dist_base + GIC_DIST_TARGET + i * 4); | |
510 | ||
511 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
512 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
513 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
514 | ||
e5f81539 | 515 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
516 | } |
517 | ||
518 | static void gic_cpu_save(unsigned int gic_nr) | |
519 | { | |
520 | int i; | |
521 | u32 *ptr; | |
522 | void __iomem *dist_base; | |
523 | void __iomem *cpu_base; | |
524 | ||
525 | if (gic_nr >= MAX_GIC_NR) | |
526 | BUG(); | |
527 | ||
db0d4db2 MZ |
528 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
529 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
530 | |
531 | if (!dist_base || !cpu_base) | |
532 | return; | |
533 | ||
532d0d06 | 534 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
535 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
536 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
537 | ||
532d0d06 | 538 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
539 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
540 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
541 | ||
542 | } | |
543 | ||
544 | static void gic_cpu_restore(unsigned int gic_nr) | |
545 | { | |
546 | int i; | |
547 | u32 *ptr; | |
548 | void __iomem *dist_base; | |
549 | void __iomem *cpu_base; | |
550 | ||
551 | if (gic_nr >= MAX_GIC_NR) | |
552 | BUG(); | |
553 | ||
db0d4db2 MZ |
554 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
555 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
556 | |
557 | if (!dist_base || !cpu_base) | |
558 | return; | |
559 | ||
532d0d06 | 560 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
561 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
562 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
563 | ||
532d0d06 | 564 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
565 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
566 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
567 | ||
568 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
569 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
570 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 571 | |
e5f81539 | 572 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
32289506 | 573 | gic_cpu_if_up(); |
254056f3 CC |
574 | } |
575 | ||
576 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
577 | { | |
578 | int i; | |
579 | ||
580 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
581 | #ifdef CONFIG_GIC_NON_BANKED |
582 | /* Skip over unused GICs */ | |
583 | if (!gic_data[i].get_base) | |
584 | continue; | |
585 | #endif | |
254056f3 CC |
586 | switch (cmd) { |
587 | case CPU_PM_ENTER: | |
588 | gic_cpu_save(i); | |
589 | break; | |
590 | case CPU_PM_ENTER_FAILED: | |
591 | case CPU_PM_EXIT: | |
592 | gic_cpu_restore(i); | |
593 | break; | |
594 | case CPU_CLUSTER_PM_ENTER: | |
595 | gic_dist_save(i); | |
596 | break; | |
597 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
598 | case CPU_CLUSTER_PM_EXIT: | |
599 | gic_dist_restore(i); | |
600 | break; | |
601 | } | |
602 | } | |
603 | ||
604 | return NOTIFY_OK; | |
605 | } | |
606 | ||
607 | static struct notifier_block gic_notifier_block = { | |
608 | .notifier_call = gic_notifier, | |
609 | }; | |
610 | ||
611 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
612 | { | |
613 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
614 | sizeof(u32)); | |
615 | BUG_ON(!gic->saved_ppi_enable); | |
616 | ||
617 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
618 | sizeof(u32)); | |
619 | BUG_ON(!gic->saved_ppi_conf); | |
620 | ||
abdd7b91 MZ |
621 | if (gic == &gic_data[0]) |
622 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
623 | } |
624 | #else | |
625 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
626 | { | |
627 | } | |
628 | #endif | |
629 | ||
b1cffebf | 630 | #ifdef CONFIG_SMP |
6859358e | 631 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
632 | { |
633 | int cpu; | |
1a6b69b6 NP |
634 | unsigned long flags, map = 0; |
635 | ||
636 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
637 | |
638 | /* Convert our logical CPU mask into a physical one. */ | |
639 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 640 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
641 | |
642 | /* | |
643 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 644 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 645 | */ |
8adbf57f | 646 | dmb(ishst); |
b1cffebf RH |
647 | |
648 | /* this always happens on GIC0 */ | |
649 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
650 | |
651 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
652 | } | |
653 | #endif | |
654 | ||
655 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
656 | /* |
657 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
658 | * | |
659 | * cpu_id: the ID for the destination CPU interface | |
660 | * irq: the IPI number to send a SGI for | |
661 | */ | |
662 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
663 | { | |
664 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
665 | cpu_id = 1 << cpu_id; | |
666 | /* this always happens on GIC0 */ | |
667 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
668 | } | |
669 | ||
ed96762e NP |
670 | /* |
671 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
672 | * | |
673 | * @cpu: the logical CPU number to get the GIC ID for. | |
674 | * | |
675 | * Return the CPU interface ID for the given logical CPU number, | |
676 | * or -1 if the CPU number is too large or the interface ID is | |
677 | * unknown (more than one bit set). | |
678 | */ | |
679 | int gic_get_cpu_id(unsigned int cpu) | |
680 | { | |
681 | unsigned int cpu_bit; | |
682 | ||
683 | if (cpu >= NR_GIC_CPU_IF) | |
684 | return -1; | |
685 | cpu_bit = gic_cpu_map[cpu]; | |
686 | if (cpu_bit & (cpu_bit - 1)) | |
687 | return -1; | |
688 | return __ffs(cpu_bit); | |
689 | } | |
690 | ||
1a6b69b6 NP |
691 | /* |
692 | * gic_migrate_target - migrate IRQs to another CPU interface | |
693 | * | |
694 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
695 | * | |
696 | * Migrate all peripheral interrupts with a target matching the current CPU | |
697 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
698 | * is also updated. Targets to other CPU interfaces are unchanged. | |
699 | * This must be called with IRQs locally disabled. | |
700 | */ | |
701 | void gic_migrate_target(unsigned int new_cpu_id) | |
702 | { | |
703 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
704 | void __iomem *dist_base; | |
705 | int i, ror_val, cpu = smp_processor_id(); | |
706 | u32 val, cur_target_mask, active_mask; | |
707 | ||
708 | if (gic_nr >= MAX_GIC_NR) | |
709 | BUG(); | |
710 | ||
711 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
712 | if (!dist_base) | |
713 | return; | |
714 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
715 | ||
716 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
717 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
718 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
719 | ||
720 | raw_spin_lock(&irq_controller_lock); | |
721 | ||
722 | /* Update the target interface for this logical CPU */ | |
723 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
724 | ||
725 | /* | |
726 | * Find all the peripheral interrupts targetting the current | |
727 | * CPU interface and migrate them to the new CPU interface. | |
728 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
729 | */ | |
730 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
731 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
732 | active_mask = val & cur_target_mask; | |
733 | if (active_mask) { | |
734 | val &= ~active_mask; | |
735 | val |= ror32(active_mask, ror_val); | |
736 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
737 | } | |
738 | } | |
739 | ||
740 | raw_spin_unlock(&irq_controller_lock); | |
741 | ||
742 | /* | |
743 | * Now let's migrate and clear any potential SGIs that might be | |
744 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
745 | * is a banked register, we can only forward the SGI using | |
746 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
747 | * doesn't use that information anyway. | |
748 | * | |
749 | * For the same reason we do not adjust SGI source information | |
750 | * for previously sent SGIs by us to other CPUs either. | |
751 | */ | |
752 | for (i = 0; i < 16; i += 4) { | |
753 | int j; | |
754 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
755 | if (!val) | |
756 | continue; | |
757 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
758 | for (j = i; j < i + 4; j++) { | |
759 | if (val & 0xff) | |
760 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
761 | dist_base + GIC_DIST_SOFTINT); | |
762 | val >>= 8; | |
763 | } | |
764 | } | |
b1cffebf | 765 | } |
eeb44658 NP |
766 | |
767 | /* | |
768 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
769 | * | |
770 | * REturn the physical address of the SGI register to be used | |
771 | * by some early assembly code when the kernel is not yet available. | |
772 | */ | |
773 | static unsigned long gic_dist_physaddr; | |
774 | ||
775 | unsigned long gic_get_sgir_physaddr(void) | |
776 | { | |
777 | if (!gic_dist_physaddr) | |
778 | return 0; | |
779 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
780 | } | |
781 | ||
782 | void __init gic_init_physaddr(struct device_node *node) | |
783 | { | |
784 | struct resource res; | |
785 | if (of_address_to_resource(node, 0, &res) == 0) { | |
786 | gic_dist_physaddr = res.start; | |
787 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
788 | } | |
789 | } | |
790 | ||
791 | #else | |
792 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
793 | #endif |
794 | ||
75294957 GL |
795 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
796 | irq_hw_number_t hw) | |
797 | { | |
798 | if (hw < 32) { | |
799 | irq_set_percpu_devid(irq); | |
9a1091ef YC |
800 | irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, |
801 | handle_percpu_devid_irq, NULL, NULL); | |
75294957 GL |
802 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
803 | } else { | |
9a1091ef YC |
804 | irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, |
805 | handle_fasteoi_irq, NULL, NULL); | |
75294957 | 806 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
006e983b S |
807 | |
808 | gic_routable_irq_domain_ops->map(d, irq, hw); | |
75294957 | 809 | } |
75294957 GL |
810 | return 0; |
811 | } | |
812 | ||
006e983b S |
813 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
814 | { | |
815 | gic_routable_irq_domain_ops->unmap(d, irq); | |
816 | } | |
817 | ||
7bb69bad GL |
818 | static int gic_irq_domain_xlate(struct irq_domain *d, |
819 | struct device_node *controller, | |
820 | const u32 *intspec, unsigned int intsize, | |
821 | unsigned long *out_hwirq, unsigned int *out_type) | |
b3f7ed03 | 822 | { |
006e983b S |
823 | unsigned long ret = 0; |
824 | ||
b3f7ed03 RH |
825 | if (d->of_node != controller) |
826 | return -EINVAL; | |
827 | if (intsize < 3) | |
828 | return -EINVAL; | |
829 | ||
830 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
831 | *out_hwirq = intspec[1] + 16; | |
832 | ||
833 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
006e983b S |
834 | if (!intspec[0]) { |
835 | ret = gic_routable_irq_domain_ops->xlate(d, controller, | |
836 | intspec, | |
837 | intsize, | |
838 | out_hwirq, | |
839 | out_type); | |
840 | ||
841 | if (IS_ERR_VALUE(ret)) | |
842 | return ret; | |
843 | } | |
b3f7ed03 RH |
844 | |
845 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
006e983b S |
846 | |
847 | return ret; | |
b3f7ed03 | 848 | } |
b3f7ed03 | 849 | |
c0114709 | 850 | #ifdef CONFIG_SMP |
8c37bb3a PG |
851 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
852 | void *hcpu) | |
c0114709 | 853 | { |
8b6fd652 | 854 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
855 | gic_cpu_init(&gic_data[0]); |
856 | return NOTIFY_OK; | |
857 | } | |
858 | ||
859 | /* | |
860 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
861 | * priority because the GIC needs to be up before the ARM generic timers. | |
862 | */ | |
8c37bb3a | 863 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
864 | .notifier_call = gic_secondary_init, |
865 | .priority = 100, | |
866 | }; | |
867 | #endif | |
868 | ||
9a1091ef YC |
869 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
870 | unsigned int nr_irqs, void *arg) | |
871 | { | |
872 | int i, ret; | |
873 | irq_hw_number_t hwirq; | |
874 | unsigned int type = IRQ_TYPE_NONE; | |
875 | struct of_phandle_args *irq_data = arg; | |
876 | ||
877 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, | |
878 | irq_data->args_count, &hwirq, &type); | |
879 | if (ret) | |
880 | return ret; | |
881 | ||
882 | for (i = 0; i < nr_irqs; i++) | |
883 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
889 | .xlate = gic_irq_domain_xlate, | |
890 | .alloc = gic_irq_domain_alloc, | |
891 | .free = irq_domain_free_irqs_top, | |
892 | }; | |
893 | ||
6859358e | 894 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 895 | .map = gic_irq_domain_map, |
006e983b | 896 | .unmap = gic_irq_domain_unmap, |
7bb69bad | 897 | .xlate = gic_irq_domain_xlate, |
4294f8ba RH |
898 | }; |
899 | ||
006e983b S |
900 | /* Default functions for routable irq domain */ |
901 | static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
902 | irq_hw_number_t hw) | |
903 | { | |
904 | return 0; | |
905 | } | |
906 | ||
907 | static void gic_routable_irq_domain_unmap(struct irq_domain *d, | |
908 | unsigned int irq) | |
909 | { | |
910 | } | |
911 | ||
912 | static int gic_routable_irq_domain_xlate(struct irq_domain *d, | |
913 | struct device_node *controller, | |
914 | const u32 *intspec, unsigned int intsize, | |
915 | unsigned long *out_hwirq, | |
916 | unsigned int *out_type) | |
917 | { | |
918 | *out_hwirq += 16; | |
919 | return 0; | |
920 | } | |
921 | ||
f3d147b8 | 922 | static const struct irq_domain_ops gic_default_routable_irq_domain_ops = { |
006e983b S |
923 | .map = gic_routable_irq_domain_map, |
924 | .unmap = gic_routable_irq_domain_unmap, | |
925 | .xlate = gic_routable_irq_domain_xlate, | |
926 | }; | |
927 | ||
928 | const struct irq_domain_ops *gic_routable_irq_domain_ops = | |
929 | &gic_default_routable_irq_domain_ops; | |
930 | ||
db0d4db2 MZ |
931 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
932 | void __iomem *dist_base, void __iomem *cpu_base, | |
75294957 | 933 | u32 percpu_offset, struct device_node *node) |
b580b899 | 934 | { |
75294957 | 935 | irq_hw_number_t hwirq_base; |
bef8f9ee | 936 | struct gic_chip_data *gic; |
384a2902 | 937 | int gic_irqs, irq_base, i; |
006e983b | 938 | int nr_routable_irqs; |
bef8f9ee RK |
939 | |
940 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
941 | ||
942 | gic = &gic_data[gic_nr]; | |
db0d4db2 MZ |
943 | #ifdef CONFIG_GIC_NON_BANKED |
944 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
945 | unsigned int cpu; | |
946 | ||
947 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
948 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
949 | if (WARN_ON(!gic->dist_base.percpu_base || | |
950 | !gic->cpu_base.percpu_base)) { | |
951 | free_percpu(gic->dist_base.percpu_base); | |
952 | free_percpu(gic->cpu_base.percpu_base); | |
953 | return; | |
954 | } | |
955 | ||
956 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
957 | u32 mpidr = cpu_logical_map(cpu); |
958 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
959 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
960 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
961 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
962 | } | |
963 | ||
964 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
965 | } else | |
966 | #endif | |
967 | { /* Normal, sane GIC... */ | |
968 | WARN(percpu_offset, | |
969 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
970 | percpu_offset); | |
971 | gic->dist_base.common_base = dist_base; | |
972 | gic->cpu_base.common_base = cpu_base; | |
973 | gic_set_base_accessor(gic, gic_get_common_base); | |
974 | } | |
bef8f9ee | 975 | |
384a2902 NP |
976 | /* |
977 | * Initialize the CPU interface map to all CPUs. | |
978 | * It will be refined as each CPU probes its ID. | |
979 | */ | |
980 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
981 | gic_cpu_map[i] = 0xff; | |
982 | ||
4294f8ba RH |
983 | /* |
984 | * Find out how many interrupts are supported. | |
985 | * The GIC only supports up to 1020 interrupt sources. | |
986 | */ | |
db0d4db2 | 987 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
988 | gic_irqs = (gic_irqs + 1) * 32; |
989 | if (gic_irqs > 1020) | |
990 | gic_irqs = 1020; | |
991 | gic->gic_irqs = gic_irqs; | |
992 | ||
9a1091ef YC |
993 | if (node) { /* DT case */ |
994 | const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops; | |
995 | ||
996 | if (!of_property_read_u32(node, "arm,routable-irqs", | |
997 | &nr_routable_irqs)) { | |
998 | ops = &gic_irq_domain_ops; | |
999 | gic_irqs = nr_routable_irqs; | |
1000 | } | |
1001 | ||
1002 | gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic); | |
1003 | } else { /* Non-DT case */ | |
1004 | /* | |
1005 | * For primary GICs, skip over SGIs. | |
1006 | * For secondary GICs, skip over PPIs, too. | |
1007 | */ | |
1008 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
1009 | hwirq_base = 16; | |
1010 | if (irq_start != -1) | |
1011 | irq_start = (irq_start & ~31) + 16; | |
1012 | } else { | |
1013 | hwirq_base = 32; | |
1014 | } | |
1015 | ||
1016 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1017 | |
006e983b S |
1018 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1019 | numa_node_id()); | |
1020 | if (IS_ERR_VALUE(irq_base)) { | |
1021 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1022 | irq_start); | |
1023 | irq_base = irq_start; | |
1024 | } | |
1025 | ||
1026 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, | |
1027 | hwirq_base, &gic_irq_domain_ops, gic); | |
f37a53cc | 1028 | } |
006e983b | 1029 | |
75294957 GL |
1030 | if (WARN_ON(!gic->domain)) |
1031 | return; | |
bef8f9ee | 1032 | |
08332dff | 1033 | if (gic_nr == 0) { |
b1cffebf | 1034 | #ifdef CONFIG_SMP |
08332dff MR |
1035 | set_smp_cross_call(gic_raise_softirq); |
1036 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1037 | #endif |
08332dff MR |
1038 | set_handle_irq(gic_handle_irq); |
1039 | } | |
cfed7d60 | 1040 | |
9c12845e | 1041 | gic_chip.flags |= gic_arch_extn.flags; |
4294f8ba | 1042 | gic_dist_init(gic); |
bef8f9ee | 1043 | gic_cpu_init(gic); |
254056f3 | 1044 | gic_pm_init(gic); |
b580b899 RK |
1045 | } |
1046 | ||
b3f7ed03 | 1047 | #ifdef CONFIG_OF |
46f101df | 1048 | static int gic_cnt __initdata; |
b3f7ed03 | 1049 | |
6859358e SB |
1050 | static int __init |
1051 | gic_of_init(struct device_node *node, struct device_node *parent) | |
b3f7ed03 RH |
1052 | { |
1053 | void __iomem *cpu_base; | |
1054 | void __iomem *dist_base; | |
db0d4db2 | 1055 | u32 percpu_offset; |
b3f7ed03 | 1056 | int irq; |
b3f7ed03 RH |
1057 | |
1058 | if (WARN_ON(!node)) | |
1059 | return -ENODEV; | |
1060 | ||
1061 | dist_base = of_iomap(node, 0); | |
1062 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
1063 | ||
1064 | cpu_base = of_iomap(node, 1); | |
1065 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
1066 | ||
db0d4db2 MZ |
1067 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1068 | percpu_offset = 0; | |
1069 | ||
75294957 | 1070 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
eeb44658 NP |
1071 | if (!gic_cnt) |
1072 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1073 | |
1074 | if (parent) { | |
1075 | irq = irq_of_parse_and_map(node, 0); | |
1076 | gic_cascade_irq(gic_cnt, irq); | |
1077 | } | |
853a33ce SS |
1078 | |
1079 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1080 | gicv2m_of_init(node, gic_data[gic_cnt].domain); | |
1081 | ||
b3f7ed03 RH |
1082 | gic_cnt++; |
1083 | return 0; | |
1084 | } | |
144cb088 | 1085 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1086 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1087 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1088 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1089 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1090 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1091 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1092 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
1093 | ||
b3f7ed03 | 1094 | #endif |
d60fc389 TN |
1095 | |
1096 | #ifdef CONFIG_ACPI | |
1097 | static phys_addr_t dist_phy_base, cpu_phy_base __initdata; | |
1098 | ||
1099 | static int __init | |
1100 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1101 | const unsigned long end) | |
1102 | { | |
1103 | struct acpi_madt_generic_interrupt *processor; | |
1104 | phys_addr_t gic_cpu_base; | |
1105 | static int cpu_base_assigned; | |
1106 | ||
1107 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1108 | ||
1109 | if (BAD_MADT_ENTRY(processor, end)) | |
1110 | return -EINVAL; | |
1111 | ||
1112 | /* | |
1113 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1114 | * All CPU interface addresses have to be the same. | |
1115 | */ | |
1116 | gic_cpu_base = processor->base_address; | |
1117 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1118 | return -EINVAL; | |
1119 | ||
1120 | cpu_phy_base = gic_cpu_base; | |
1121 | cpu_base_assigned = 1; | |
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static int __init | |
1126 | gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, | |
1127 | const unsigned long end) | |
1128 | { | |
1129 | struct acpi_madt_generic_distributor *dist; | |
1130 | ||
1131 | dist = (struct acpi_madt_generic_distributor *)header; | |
1132 | ||
1133 | if (BAD_MADT_ENTRY(dist, end)) | |
1134 | return -EINVAL; | |
1135 | ||
1136 | dist_phy_base = dist->base_address; | |
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | int __init | |
1141 | gic_v2_acpi_init(struct acpi_table_header *table) | |
1142 | { | |
1143 | void __iomem *cpu_base, *dist_base; | |
1144 | int count; | |
1145 | ||
1146 | /* Collect CPU base addresses */ | |
1147 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1148 | sizeof(struct acpi_table_madt), | |
1149 | gic_acpi_parse_madt_cpu, table, | |
1150 | ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); | |
1151 | if (count <= 0) { | |
1152 | pr_err("No valid GICC entries exist\n"); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
1156 | /* | |
1157 | * Find distributor base address. We expect one distributor entry since | |
1158 | * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. | |
1159 | */ | |
1160 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1161 | sizeof(struct acpi_table_madt), | |
1162 | gic_acpi_parse_madt_distributor, table, | |
1163 | ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); | |
1164 | if (count <= 0) { | |
1165 | pr_err("No valid GICD entries exist\n"); | |
1166 | return -EINVAL; | |
1167 | } else if (count > 1) { | |
1168 | pr_err("More than one GICD entry detected\n"); | |
1169 | return -EINVAL; | |
1170 | } | |
1171 | ||
1172 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); | |
1173 | if (!cpu_base) { | |
1174 | pr_err("Unable to map GICC registers\n"); | |
1175 | return -ENOMEM; | |
1176 | } | |
1177 | ||
1178 | dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); | |
1179 | if (!dist_base) { | |
1180 | pr_err("Unable to map GICD registers\n"); | |
1181 | iounmap(cpu_base); | |
1182 | return -ENOMEM; | |
1183 | } | |
1184 | ||
1185 | /* | |
1186 | * Initialize zero GIC instance (no multi-GIC support). Also, set GIC | |
1187 | * as default IRQ domain to allow for GSI registration and GSI to IRQ | |
1188 | * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). | |
1189 | */ | |
1190 | gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); | |
1191 | irq_set_default_host(gic_data[0].domain); | |
d8f4f161 LP |
1192 | |
1193 | acpi_irq_model = ACPI_IRQ_MODEL_GIC; | |
d60fc389 TN |
1194 | return 0; |
1195 | } | |
1196 | #endif |