Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
0b996fd3 | 49 | #include <asm/virt.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
76e52dd0 MZ |
53 | #ifdef CONFIG_ARM64 |
54 | #include <asm/cpufeature.h> | |
55 | ||
56 | static void gic_check_cpu_features(void) | |
57 | { | |
25fc11ae | 58 | WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), |
76e52dd0 MZ |
59 | TAINT_CPU_OUT_OF_SPEC, |
60 | "GICv3 system registers enabled, broken firmware!\n"); | |
61 | } | |
62 | #else | |
63 | #define gic_check_cpu_features() do { } while(0) | |
64 | #endif | |
65 | ||
db0d4db2 MZ |
66 | union gic_base { |
67 | void __iomem *common_base; | |
6859358e | 68 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
69 | }; |
70 | ||
71 | struct gic_chip_data { | |
58b89649 | 72 | struct irq_chip chip; |
db0d4db2 MZ |
73 | union gic_base dist_base; |
74 | union gic_base cpu_base; | |
f673b9b5 JH |
75 | void __iomem *raw_dist_base; |
76 | void __iomem *raw_cpu_base; | |
77 | u32 percpu_offset; | |
db0d4db2 MZ |
78 | #ifdef CONFIG_CPU_PM |
79 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
1c7d4dd4 | 80 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
db0d4db2 MZ |
81 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
82 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
83 | u32 __percpu *saved_ppi_enable; | |
1c7d4dd4 | 84 | u32 __percpu *saved_ppi_active; |
db0d4db2 MZ |
85 | u32 __percpu *saved_ppi_conf; |
86 | #endif | |
75294957 | 87 | struct irq_domain *domain; |
db0d4db2 MZ |
88 | unsigned int gic_irqs; |
89 | #ifdef CONFIG_GIC_NON_BANKED | |
90 | void __iomem *(*get_base)(union gic_base *); | |
91 | #endif | |
92 | }; | |
93 | ||
bd31b859 | 94 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 95 | |
384a2902 NP |
96 | /* |
97 | * The GIC mapping of CPU interfaces does not necessarily match | |
98 | * the logical CPU numbering. Let's use a mapping as returned | |
99 | * by the GIC itself. | |
100 | */ | |
101 | #define NR_GIC_CPU_IF 8 | |
102 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
103 | ||
0b996fd3 MZ |
104 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
105 | ||
a27d21e0 | 106 | static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; |
b3a1bde4 | 107 | |
502d6df1 JG |
108 | static struct gic_kvm_info gic_v2_kvm_info; |
109 | ||
db0d4db2 MZ |
110 | #ifdef CONFIG_GIC_NON_BANKED |
111 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
112 | { | |
513d1a28 | 113 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
114 | } |
115 | ||
116 | static void __iomem *gic_get_common_base(union gic_base *base) | |
117 | { | |
118 | return base->common_base; | |
119 | } | |
120 | ||
121 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
122 | { | |
123 | return data->get_base(&data->dist_base); | |
124 | } | |
125 | ||
126 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
127 | { | |
128 | return data->get_base(&data->cpu_base); | |
129 | } | |
130 | ||
131 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
132 | void __iomem *(*f)(union gic_base *)) | |
133 | { | |
134 | data->get_base = f; | |
135 | } | |
136 | #else | |
137 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
138 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 139 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
140 | #endif |
141 | ||
7d1f4288 | 142 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 143 | { |
7d1f4288 | 144 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 145 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
146 | } |
147 | ||
7d1f4288 | 148 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 149 | { |
7d1f4288 | 150 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 151 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
152 | } |
153 | ||
7d1f4288 | 154 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 155 | { |
4294f8ba | 156 | return d->hwirq; |
b3a1bde4 CM |
157 | } |
158 | ||
01f779f4 MZ |
159 | static inline bool cascading_gic_irq(struct irq_data *d) |
160 | { | |
161 | void *data = irq_data_get_irq_handler_data(d); | |
162 | ||
163 | /* | |
71466535 TG |
164 | * If handler_data is set, this is a cascading interrupt, and |
165 | * it cannot possibly be forwarded. | |
01f779f4 | 166 | */ |
71466535 | 167 | return data != NULL; |
01f779f4 MZ |
168 | } |
169 | ||
f27ecacc RK |
170 | /* |
171 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 172 | */ |
56717807 MZ |
173 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
174 | { | |
175 | u32 mask = 1 << (gic_irq(d) % 32); | |
176 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
177 | } | |
178 | ||
179 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 180 | { |
4294f8ba | 181 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
182 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
183 | } | |
184 | ||
185 | static void gic_mask_irq(struct irq_data *d) | |
186 | { | |
56717807 | 187 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
188 | } |
189 | ||
0b996fd3 MZ |
190 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
191 | { | |
192 | gic_mask_irq(d); | |
01f779f4 MZ |
193 | /* |
194 | * When masking a forwarded interrupt, make sure it is | |
195 | * deactivated as well. | |
196 | * | |
197 | * This ensures that an interrupt that is getting | |
198 | * disabled/masked will not get "stuck", because there is | |
199 | * noone to deactivate it (guest is being terminated). | |
200 | */ | |
71466535 | 201 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 202 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
203 | } |
204 | ||
7d1f4288 | 205 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 206 | { |
56717807 | 207 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
208 | } |
209 | ||
1a01753e WD |
210 | static void gic_eoi_irq(struct irq_data *d) |
211 | { | |
6ac77e46 | 212 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
213 | } |
214 | ||
0b996fd3 MZ |
215 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
216 | { | |
01f779f4 | 217 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 218 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
219 | return; |
220 | ||
0b996fd3 MZ |
221 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
222 | } | |
223 | ||
56717807 MZ |
224 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
225 | enum irqchip_irq_state which, bool val) | |
226 | { | |
227 | u32 reg; | |
228 | ||
229 | switch (which) { | |
230 | case IRQCHIP_STATE_PENDING: | |
231 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
232 | break; | |
233 | ||
234 | case IRQCHIP_STATE_ACTIVE: | |
235 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
236 | break; | |
237 | ||
238 | case IRQCHIP_STATE_MASKED: | |
239 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
240 | break; | |
241 | ||
242 | default: | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | gic_poke_irq(d, reg); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
251 | enum irqchip_irq_state which, bool *val) | |
252 | { | |
253 | switch (which) { | |
254 | case IRQCHIP_STATE_PENDING: | |
255 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
256 | break; | |
257 | ||
258 | case IRQCHIP_STATE_ACTIVE: | |
259 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
260 | break; | |
261 | ||
262 | case IRQCHIP_STATE_MASKED: | |
263 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
264 | break; | |
265 | ||
266 | default: | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
7d1f4288 | 273 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 274 | { |
7d1f4288 LB |
275 | void __iomem *base = gic_dist_base(d); |
276 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
277 | |
278 | /* Interrupt configuration for SGIs can't be changed */ | |
279 | if (gicirq < 16) | |
280 | return -EINVAL; | |
281 | ||
fb7e7deb LD |
282 | /* SPIs have restrictions on the supported types */ |
283 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
284 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
285 | return -EINVAL; |
286 | ||
1dcc73d7 | 287 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
288 | } |
289 | ||
01f779f4 MZ |
290 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
291 | { | |
292 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
293 | if (cascading_gic_irq(d)) | |
294 | return -EINVAL; | |
295 | ||
71466535 TG |
296 | if (vcpu) |
297 | irqd_set_forwarded_to_vcpu(d); | |
298 | else | |
299 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
300 | return 0; |
301 | } | |
302 | ||
a06f5466 | 303 | #ifdef CONFIG_SMP |
c191789c RK |
304 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
305 | bool force) | |
f27ecacc | 306 | { |
7d1f4288 | 307 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 308 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 309 | u32 val, mask, bit; |
cf613871 | 310 | unsigned long flags; |
f27ecacc | 311 | |
ffde1de6 TG |
312 | if (!force) |
313 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
314 | else | |
315 | cpu = cpumask_first(mask_val); | |
316 | ||
384a2902 | 317 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 318 | return -EINVAL; |
c191789c | 319 | |
cf613871 | 320 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 321 | mask = 0xff << shift; |
384a2902 | 322 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
323 | val = readl_relaxed(reg) & ~mask; |
324 | writel_relaxed(val | bit, reg); | |
cf613871 | 325 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 326 | |
0407dace | 327 | return IRQ_SET_MASK_OK_DONE; |
f27ecacc | 328 | } |
a06f5466 | 329 | #endif |
f27ecacc | 330 | |
8783dd3a | 331 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
332 | { |
333 | u32 irqstat, irqnr; | |
334 | struct gic_chip_data *gic = &gic_data[0]; | |
335 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
336 | ||
337 | do { | |
338 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 339 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 | 340 | |
327ebe1f | 341 | if (likely(irqnr > 15 && irqnr < 1020)) { |
0b996fd3 MZ |
342 | if (static_key_true(&supports_deactivate)) |
343 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 344 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
345 | continue; |
346 | } | |
347 | if (irqnr < 16) { | |
348 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
349 | if (static_key_true(&supports_deactivate)) |
350 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 | 351 | #ifdef CONFIG_SMP |
f86c4fbd WD |
352 | /* |
353 | * Ensure any shared data written by the CPU sending | |
354 | * the IPI is read after we've read the ACK register | |
355 | * on the GIC. | |
356 | * | |
357 | * Pairs with the write barrier in gic_raise_softirq | |
358 | */ | |
359 | smp_rmb(); | |
562e0027 MZ |
360 | handle_IPI(irqnr, regs); |
361 | #endif | |
362 | continue; | |
363 | } | |
364 | break; | |
365 | } while (1); | |
366 | } | |
367 | ||
bd0b9ac4 | 368 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 369 | { |
5b29264c JL |
370 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
371 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 372 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
373 | unsigned long status; |
374 | ||
1a01753e | 375 | chained_irq_enter(chip, desc); |
b3a1bde4 | 376 | |
bd31b859 | 377 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 378 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 379 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 380 | |
e5f81539 FK |
381 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
382 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 383 | goto out; |
b3a1bde4 | 384 | |
75294957 GL |
385 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
386 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 387 | handle_bad_irq(desc); |
0f347bb9 RK |
388 | else |
389 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
390 | |
391 | out: | |
1a01753e | 392 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
393 | } |
394 | ||
38c677cb | 395 | static struct irq_chip gic_chip = { |
7d1f4288 LB |
396 | .irq_mask = gic_mask_irq, |
397 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 398 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 399 | .irq_set_type = gic_set_type, |
56717807 MZ |
400 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
401 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
402 | .flags = IRQCHIP_SET_TYPE_MASKED | |
403 | IRQCHIP_SKIP_SET_WAKE | | |
404 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
405 | }; |
406 | ||
b3a1bde4 CM |
407 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
408 | { | |
a27d21e0 | 409 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
4d83fcf8 TG |
410 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
411 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
412 | } |
413 | ||
2bb31351 RK |
414 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
415 | { | |
416 | void __iomem *base = gic_data_dist_base(gic); | |
417 | u32 mask, i; | |
418 | ||
419 | for (i = mask = 0; i < 32; i += 4) { | |
420 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
421 | mask |= mask >> 16; | |
422 | mask |= mask >> 8; | |
423 | if (mask) | |
424 | break; | |
425 | } | |
426 | ||
6e3aca44 | 427 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
428 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
429 | ||
430 | return mask; | |
431 | } | |
432 | ||
4c2880b3 | 433 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 434 | { |
4c2880b3 | 435 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 436 | u32 bypass = 0; |
0b996fd3 MZ |
437 | u32 mode = 0; |
438 | ||
389a00d3 | 439 | if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) |
0b996fd3 | 440 | mode = GIC_CPU_CTRL_EOImodeNS; |
32289506 FK |
441 | |
442 | /* | |
443 | * Preserve bypass disable bits to be written back later | |
444 | */ | |
445 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
446 | bypass &= GICC_DIS_BYPASS_MASK; | |
447 | ||
0b996fd3 | 448 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
449 | } |
450 | ||
451 | ||
4294f8ba | 452 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 453 | { |
75294957 | 454 | unsigned int i; |
267840f3 | 455 | u32 cpumask; |
4294f8ba | 456 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 457 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 458 | |
e5f81539 | 459 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 460 | |
f27ecacc RK |
461 | /* |
462 | * Set all global interrupts to this CPU only. | |
463 | */ | |
2bb31351 RK |
464 | cpumask = gic_get_cpumask(gic); |
465 | cpumask |= cpumask << 8; | |
466 | cpumask |= cpumask << 16; | |
e6afec9b | 467 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 468 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 469 | |
d51d0af4 | 470 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 471 | |
e5f81539 | 472 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
473 | } |
474 | ||
dc9722cc | 475 | static int gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 476 | { |
db0d4db2 MZ |
477 | void __iomem *dist_base = gic_data_dist_base(gic); |
478 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 479 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
480 | int i; |
481 | ||
384a2902 | 482 | /* |
567e5a01 JH |
483 | * Setting up the CPU map is only relevant for the primary GIC |
484 | * because any nested/secondary GICs do not directly interface | |
485 | * with the CPU(s). | |
384a2902 | 486 | */ |
567e5a01 JH |
487 | if (gic == &gic_data[0]) { |
488 | /* | |
489 | * Get what the GIC says our CPU mask is. | |
490 | */ | |
dc9722cc JH |
491 | if (WARN_ON(cpu >= NR_GIC_CPU_IF)) |
492 | return -EINVAL; | |
493 | ||
25fc11ae | 494 | gic_check_cpu_features(); |
567e5a01 JH |
495 | cpu_mask = gic_get_cpumask(gic); |
496 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 497 | |
567e5a01 JH |
498 | /* |
499 | * Clear our mask from the other map entries in case they're | |
500 | * still undefined. | |
501 | */ | |
502 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
503 | if (i != cpu) | |
504 | gic_cpu_map[i] &= ~cpu_mask; | |
505 | } | |
384a2902 | 506 | |
d51d0af4 | 507 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 508 | |
e5f81539 | 509 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 510 | gic_cpu_if_up(gic); |
dc9722cc JH |
511 | |
512 | return 0; | |
f27ecacc RK |
513 | } |
514 | ||
4c2880b3 | 515 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 516 | { |
4c2880b3 | 517 | void __iomem *cpu_base; |
32289506 FK |
518 | u32 val = 0; |
519 | ||
a27d21e0 | 520 | if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) |
4c2880b3 JH |
521 | return -EINVAL; |
522 | ||
523 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
524 | val = readl(cpu_base + GIC_CPU_CTRL); |
525 | val &= ~GICC_ENABLE; | |
526 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
527 | |
528 | return 0; | |
10d9eb8a NP |
529 | } |
530 | ||
254056f3 CC |
531 | #ifdef CONFIG_CPU_PM |
532 | /* | |
533 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
534 | * with interrupts disabled but before powering down the GIC. After calling | |
535 | * this function, no interrupts will be delivered by the GIC, and another | |
536 | * platform-specific wakeup source must be enabled. | |
537 | */ | |
6e5b5924 | 538 | static void gic_dist_save(struct gic_chip_data *gic) |
254056f3 CC |
539 | { |
540 | unsigned int gic_irqs; | |
541 | void __iomem *dist_base; | |
542 | int i; | |
543 | ||
6e5b5924 JH |
544 | if (WARN_ON(!gic)) |
545 | return; | |
254056f3 | 546 | |
6e5b5924 JH |
547 | gic_irqs = gic->gic_irqs; |
548 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
549 | |
550 | if (!dist_base) | |
551 | return; | |
552 | ||
553 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 554 | gic->saved_spi_conf[i] = |
254056f3 CC |
555 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
556 | ||
557 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 558 | gic->saved_spi_target[i] = |
254056f3 CC |
559 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
560 | ||
561 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 562 | gic->saved_spi_enable[i] = |
254056f3 | 563 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
1c7d4dd4 MZ |
564 | |
565 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 566 | gic->saved_spi_active[i] = |
1c7d4dd4 | 567 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
254056f3 CC |
568 | } |
569 | ||
570 | /* | |
571 | * Restores the GIC distributor registers during resume or when coming out of | |
572 | * idle. Must be called before enabling interrupts. If a level interrupt | |
573 | * that occured while the GIC was suspended is still present, it will be | |
574 | * handled normally, but any edge interrupts that occured will not be seen by | |
575 | * the GIC and need to be handled by the platform-specific wakeup source. | |
576 | */ | |
6e5b5924 | 577 | static void gic_dist_restore(struct gic_chip_data *gic) |
254056f3 CC |
578 | { |
579 | unsigned int gic_irqs; | |
580 | unsigned int i; | |
581 | void __iomem *dist_base; | |
582 | ||
6e5b5924 JH |
583 | if (WARN_ON(!gic)) |
584 | return; | |
254056f3 | 585 | |
6e5b5924 JH |
586 | gic_irqs = gic->gic_irqs; |
587 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
588 | |
589 | if (!dist_base) | |
590 | return; | |
591 | ||
e5f81539 | 592 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
593 | |
594 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 595 | writel_relaxed(gic->saved_spi_conf[i], |
254056f3 CC |
596 | dist_base + GIC_DIST_CONFIG + i * 4); |
597 | ||
598 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 599 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
600 | dist_base + GIC_DIST_PRI + i * 4); |
601 | ||
602 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 603 | writel_relaxed(gic->saved_spi_target[i], |
254056f3 CC |
604 | dist_base + GIC_DIST_TARGET + i * 4); |
605 | ||
92eda4ad MZ |
606 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
607 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
608 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
6e5b5924 | 609 | writel_relaxed(gic->saved_spi_enable[i], |
254056f3 | 610 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 611 | } |
254056f3 | 612 | |
1c7d4dd4 MZ |
613 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
614 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
615 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
6e5b5924 | 616 | writel_relaxed(gic->saved_spi_active[i], |
1c7d4dd4 MZ |
617 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
618 | } | |
619 | ||
e5f81539 | 620 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
621 | } |
622 | ||
6e5b5924 | 623 | static void gic_cpu_save(struct gic_chip_data *gic) |
254056f3 CC |
624 | { |
625 | int i; | |
626 | u32 *ptr; | |
627 | void __iomem *dist_base; | |
628 | void __iomem *cpu_base; | |
629 | ||
6e5b5924 JH |
630 | if (WARN_ON(!gic)) |
631 | return; | |
254056f3 | 632 | |
6e5b5924 JH |
633 | dist_base = gic_data_dist_base(gic); |
634 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
635 | |
636 | if (!dist_base || !cpu_base) | |
637 | return; | |
638 | ||
6e5b5924 | 639 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
254056f3 CC |
640 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
641 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
642 | ||
6e5b5924 | 643 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
644 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
645 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
646 | ||
6e5b5924 | 647 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
648 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
649 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
650 | ||
651 | } | |
652 | ||
6e5b5924 | 653 | static void gic_cpu_restore(struct gic_chip_data *gic) |
254056f3 CC |
654 | { |
655 | int i; | |
656 | u32 *ptr; | |
657 | void __iomem *dist_base; | |
658 | void __iomem *cpu_base; | |
659 | ||
6e5b5924 JH |
660 | if (WARN_ON(!gic)) |
661 | return; | |
254056f3 | 662 | |
6e5b5924 JH |
663 | dist_base = gic_data_dist_base(gic); |
664 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
665 | |
666 | if (!dist_base || !cpu_base) | |
667 | return; | |
668 | ||
6e5b5924 | 669 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
92eda4ad MZ |
670 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
671 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
672 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 | 673 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 674 | } |
254056f3 | 675 | |
6e5b5924 | 676 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
677 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
678 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
679 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
680 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
681 | } | |
682 | ||
6e5b5924 | 683 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
684 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
685 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
686 | ||
687 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
688 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
689 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 690 | |
e5f81539 | 691 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
6e5b5924 | 692 | gic_cpu_if_up(gic); |
254056f3 CC |
693 | } |
694 | ||
695 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
696 | { | |
697 | int i; | |
698 | ||
a27d21e0 | 699 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { |
db0d4db2 MZ |
700 | #ifdef CONFIG_GIC_NON_BANKED |
701 | /* Skip over unused GICs */ | |
702 | if (!gic_data[i].get_base) | |
703 | continue; | |
704 | #endif | |
254056f3 CC |
705 | switch (cmd) { |
706 | case CPU_PM_ENTER: | |
6e5b5924 | 707 | gic_cpu_save(&gic_data[i]); |
254056f3 CC |
708 | break; |
709 | case CPU_PM_ENTER_FAILED: | |
710 | case CPU_PM_EXIT: | |
6e5b5924 | 711 | gic_cpu_restore(&gic_data[i]); |
254056f3 CC |
712 | break; |
713 | case CPU_CLUSTER_PM_ENTER: | |
6e5b5924 | 714 | gic_dist_save(&gic_data[i]); |
254056f3 CC |
715 | break; |
716 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
717 | case CPU_CLUSTER_PM_EXIT: | |
6e5b5924 | 718 | gic_dist_restore(&gic_data[i]); |
254056f3 CC |
719 | break; |
720 | } | |
721 | } | |
722 | ||
723 | return NOTIFY_OK; | |
724 | } | |
725 | ||
726 | static struct notifier_block gic_notifier_block = { | |
727 | .notifier_call = gic_notifier, | |
728 | }; | |
729 | ||
dc9722cc | 730 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 CC |
731 | { |
732 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
733 | sizeof(u32)); | |
dc9722cc JH |
734 | if (WARN_ON(!gic->saved_ppi_enable)) |
735 | return -ENOMEM; | |
254056f3 | 736 | |
1c7d4dd4 MZ |
737 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
738 | sizeof(u32)); | |
dc9722cc JH |
739 | if (WARN_ON(!gic->saved_ppi_active)) |
740 | goto free_ppi_enable; | |
1c7d4dd4 | 741 | |
254056f3 CC |
742 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
743 | sizeof(u32)); | |
dc9722cc JH |
744 | if (WARN_ON(!gic->saved_ppi_conf)) |
745 | goto free_ppi_active; | |
254056f3 | 746 | |
abdd7b91 MZ |
747 | if (gic == &gic_data[0]) |
748 | cpu_pm_register_notifier(&gic_notifier_block); | |
dc9722cc JH |
749 | |
750 | return 0; | |
751 | ||
752 | free_ppi_active: | |
753 | free_percpu(gic->saved_ppi_active); | |
754 | free_ppi_enable: | |
755 | free_percpu(gic->saved_ppi_enable); | |
756 | ||
757 | return -ENOMEM; | |
254056f3 CC |
758 | } |
759 | #else | |
dc9722cc | 760 | static int __init gic_pm_init(struct gic_chip_data *gic) |
254056f3 | 761 | { |
dc9722cc | 762 | return 0; |
254056f3 CC |
763 | } |
764 | #endif | |
765 | ||
b1cffebf | 766 | #ifdef CONFIG_SMP |
6859358e | 767 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
768 | { |
769 | int cpu; | |
1a6b69b6 NP |
770 | unsigned long flags, map = 0; |
771 | ||
772 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
773 | |
774 | /* Convert our logical CPU mask into a physical one. */ | |
775 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 776 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
777 | |
778 | /* | |
779 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 780 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 781 | */ |
8adbf57f | 782 | dmb(ishst); |
b1cffebf RH |
783 | |
784 | /* this always happens on GIC0 */ | |
785 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
786 | |
787 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
788 | } | |
789 | #endif | |
790 | ||
791 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
792 | /* |
793 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
794 | * | |
795 | * cpu_id: the ID for the destination CPU interface | |
796 | * irq: the IPI number to send a SGI for | |
797 | */ | |
798 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
799 | { | |
800 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
801 | cpu_id = 1 << cpu_id; | |
802 | /* this always happens on GIC0 */ | |
803 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
804 | } | |
805 | ||
ed96762e NP |
806 | /* |
807 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
808 | * | |
809 | * @cpu: the logical CPU number to get the GIC ID for. | |
810 | * | |
811 | * Return the CPU interface ID for the given logical CPU number, | |
812 | * or -1 if the CPU number is too large or the interface ID is | |
813 | * unknown (more than one bit set). | |
814 | */ | |
815 | int gic_get_cpu_id(unsigned int cpu) | |
816 | { | |
817 | unsigned int cpu_bit; | |
818 | ||
819 | if (cpu >= NR_GIC_CPU_IF) | |
820 | return -1; | |
821 | cpu_bit = gic_cpu_map[cpu]; | |
822 | if (cpu_bit & (cpu_bit - 1)) | |
823 | return -1; | |
824 | return __ffs(cpu_bit); | |
825 | } | |
826 | ||
1a6b69b6 NP |
827 | /* |
828 | * gic_migrate_target - migrate IRQs to another CPU interface | |
829 | * | |
830 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
831 | * | |
832 | * Migrate all peripheral interrupts with a target matching the current CPU | |
833 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
834 | * is also updated. Targets to other CPU interfaces are unchanged. | |
835 | * This must be called with IRQs locally disabled. | |
836 | */ | |
837 | void gic_migrate_target(unsigned int new_cpu_id) | |
838 | { | |
839 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
840 | void __iomem *dist_base; | |
841 | int i, ror_val, cpu = smp_processor_id(); | |
842 | u32 val, cur_target_mask, active_mask; | |
843 | ||
a27d21e0 | 844 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
1a6b69b6 NP |
845 | |
846 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
847 | if (!dist_base) | |
848 | return; | |
849 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
850 | ||
851 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
852 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
853 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
854 | ||
855 | raw_spin_lock(&irq_controller_lock); | |
856 | ||
857 | /* Update the target interface for this logical CPU */ | |
858 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
859 | ||
860 | /* | |
861 | * Find all the peripheral interrupts targetting the current | |
862 | * CPU interface and migrate them to the new CPU interface. | |
863 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
864 | */ | |
865 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
866 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
867 | active_mask = val & cur_target_mask; | |
868 | if (active_mask) { | |
869 | val &= ~active_mask; | |
870 | val |= ror32(active_mask, ror_val); | |
871 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
872 | } | |
873 | } | |
874 | ||
875 | raw_spin_unlock(&irq_controller_lock); | |
876 | ||
877 | /* | |
878 | * Now let's migrate and clear any potential SGIs that might be | |
879 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
880 | * is a banked register, we can only forward the SGI using | |
881 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
882 | * doesn't use that information anyway. | |
883 | * | |
884 | * For the same reason we do not adjust SGI source information | |
885 | * for previously sent SGIs by us to other CPUs either. | |
886 | */ | |
887 | for (i = 0; i < 16; i += 4) { | |
888 | int j; | |
889 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
890 | if (!val) | |
891 | continue; | |
892 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
893 | for (j = i; j < i + 4; j++) { | |
894 | if (val & 0xff) | |
895 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
896 | dist_base + GIC_DIST_SOFTINT); | |
897 | val >>= 8; | |
898 | } | |
899 | } | |
b1cffebf | 900 | } |
eeb44658 NP |
901 | |
902 | /* | |
903 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
904 | * | |
905 | * REturn the physical address of the SGI register to be used | |
906 | * by some early assembly code when the kernel is not yet available. | |
907 | */ | |
908 | static unsigned long gic_dist_physaddr; | |
909 | ||
910 | unsigned long gic_get_sgir_physaddr(void) | |
911 | { | |
912 | if (!gic_dist_physaddr) | |
913 | return 0; | |
914 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
915 | } | |
916 | ||
917 | void __init gic_init_physaddr(struct device_node *node) | |
918 | { | |
919 | struct resource res; | |
920 | if (of_address_to_resource(node, 0, &res) == 0) { | |
921 | gic_dist_physaddr = res.start; | |
922 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
923 | } | |
924 | } | |
925 | ||
926 | #else | |
927 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
928 | #endif |
929 | ||
75294957 GL |
930 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
931 | irq_hw_number_t hw) | |
932 | { | |
58b89649 | 933 | struct gic_chip_data *gic = d->host_data; |
0b996fd3 | 934 | |
75294957 GL |
935 | if (hw < 32) { |
936 | irq_set_percpu_devid(irq); | |
58b89649 | 937 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 938 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 939 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 940 | } else { |
58b89649 | 941 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 942 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 943 | irq_set_probe(irq); |
75294957 | 944 | } |
75294957 GL |
945 | return 0; |
946 | } | |
947 | ||
006e983b S |
948 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
949 | { | |
006e983b S |
950 | } |
951 | ||
f833f57f MZ |
952 | static int gic_irq_domain_translate(struct irq_domain *d, |
953 | struct irq_fwspec *fwspec, | |
954 | unsigned long *hwirq, | |
955 | unsigned int *type) | |
956 | { | |
957 | if (is_of_node(fwspec->fwnode)) { | |
958 | if (fwspec->param_count < 3) | |
959 | return -EINVAL; | |
960 | ||
961 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
962 | *hwirq = fwspec->param[1] + 16; | |
963 | ||
964 | /* | |
965 | * For SPIs, we need to add 16 more to get the GIC irq | |
966 | * ID number | |
967 | */ | |
968 | if (!fwspec->param[0]) | |
969 | *hwirq += 16; | |
970 | ||
971 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
972 | return 0; | |
973 | } | |
974 | ||
75aba7b0 | 975 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
891ae769 MZ |
976 | if(fwspec->param_count != 2) |
977 | return -EINVAL; | |
978 | ||
979 | *hwirq = fwspec->param[0]; | |
980 | *type = fwspec->param[1]; | |
981 | return 0; | |
982 | } | |
983 | ||
f833f57f MZ |
984 | return -EINVAL; |
985 | } | |
986 | ||
c0114709 | 987 | #ifdef CONFIG_SMP |
8c37bb3a PG |
988 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
989 | void *hcpu) | |
c0114709 | 990 | { |
8b6fd652 | 991 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
992 | gic_cpu_init(&gic_data[0]); |
993 | return NOTIFY_OK; | |
994 | } | |
995 | ||
996 | /* | |
997 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
998 | * priority because the GIC needs to be up before the ARM generic timers. | |
999 | */ | |
8c37bb3a | 1000 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
1001 | .notifier_call = gic_secondary_init, |
1002 | .priority = 100, | |
1003 | }; | |
1004 | #endif | |
1005 | ||
9a1091ef YC |
1006 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1007 | unsigned int nr_irqs, void *arg) | |
1008 | { | |
1009 | int i, ret; | |
1010 | irq_hw_number_t hwirq; | |
1011 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1012 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 1013 | |
f833f57f | 1014 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
1015 | if (ret) |
1016 | return ret; | |
1017 | ||
1018 | for (i = 0; i < nr_irqs; i++) | |
1019 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1025 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1026 | .alloc = gic_irq_domain_alloc, |
1027 | .free = irq_domain_free_irqs_top, | |
1028 | }; | |
1029 | ||
6859358e | 1030 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1031 | .map = gic_irq_domain_map, |
006e983b | 1032 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
1033 | }; |
1034 | ||
d6ce564c JH |
1035 | static int gic_init_bases(struct gic_chip_data *gic, int irq_start, |
1036 | struct fwnode_handle *handle) | |
b580b899 | 1037 | { |
75294957 | 1038 | irq_hw_number_t hwirq_base; |
d6ce564c | 1039 | int gic_irqs, irq_base, ret; |
58b89649 LW |
1040 | |
1041 | /* Initialize irq_chip */ | |
c2baa2f3 JH |
1042 | gic->chip = gic_chip; |
1043 | ||
f673b9b5 | 1044 | if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { |
c2baa2f3 JH |
1045 | gic->chip.irq_mask = gic_eoimode1_mask_irq; |
1046 | gic->chip.irq_eoi = gic_eoimode1_eoi_irq; | |
1047 | gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; | |
dc9722cc | 1048 | gic->chip.name = kasprintf(GFP_KERNEL, "GICv2"); |
58b89649 | 1049 | } else { |
f673b9b5 JH |
1050 | gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", |
1051 | (int)(gic - &gic_data[0])); | |
58b89649 LW |
1052 | } |
1053 | ||
7bf29d3a | 1054 | #ifdef CONFIG_SMP |
f673b9b5 | 1055 | if (gic == &gic_data[0]) |
7bf29d3a JH |
1056 | gic->chip.irq_set_affinity = gic_set_affinity; |
1057 | #endif | |
1058 | ||
f673b9b5 | 1059 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc | 1060 | /* Frankein-GIC without banked registers... */ |
db0d4db2 MZ |
1061 | unsigned int cpu; |
1062 | ||
1063 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1064 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1065 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1066 | !gic->cpu_base.percpu_base)) { | |
dc9722cc JH |
1067 | ret = -ENOMEM; |
1068 | goto error; | |
db0d4db2 MZ |
1069 | } |
1070 | ||
1071 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1072 | u32 mpidr = cpu_logical_map(cpu); |
1073 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
f673b9b5 JH |
1074 | unsigned long offset = gic->percpu_offset * core_id; |
1075 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = | |
1076 | gic->raw_dist_base + offset; | |
1077 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = | |
1078 | gic->raw_cpu_base + offset; | |
db0d4db2 MZ |
1079 | } |
1080 | ||
1081 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
dc9722cc JH |
1082 | } else { |
1083 | /* Normal, sane GIC... */ | |
f673b9b5 | 1084 | WARN(gic->percpu_offset, |
db0d4db2 | 1085 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
f673b9b5 JH |
1086 | gic->percpu_offset); |
1087 | gic->dist_base.common_base = gic->raw_dist_base; | |
1088 | gic->cpu_base.common_base = gic->raw_cpu_base; | |
db0d4db2 MZ |
1089 | gic_set_base_accessor(gic, gic_get_common_base); |
1090 | } | |
bef8f9ee | 1091 | |
4294f8ba RH |
1092 | /* |
1093 | * Find out how many interrupts are supported. | |
1094 | * The GIC only supports up to 1020 interrupt sources. | |
1095 | */ | |
db0d4db2 | 1096 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1097 | gic_irqs = (gic_irqs + 1) * 32; |
1098 | if (gic_irqs > 1020) | |
1099 | gic_irqs = 1020; | |
1100 | gic->gic_irqs = gic_irqs; | |
1101 | ||
891ae769 MZ |
1102 | if (handle) { /* DT/ACPI */ |
1103 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1104 | &gic_irq_domain_hierarchy_ops, | |
1105 | gic); | |
1106 | } else { /* Legacy support */ | |
9a1091ef YC |
1107 | /* |
1108 | * For primary GICs, skip over SGIs. | |
1109 | * For secondary GICs, skip over PPIs, too. | |
1110 | */ | |
f673b9b5 | 1111 | if (gic == &gic_data[0] && (irq_start & 31) > 0) { |
9a1091ef YC |
1112 | hwirq_base = 16; |
1113 | if (irq_start != -1) | |
1114 | irq_start = (irq_start & ~31) + 16; | |
1115 | } else { | |
1116 | hwirq_base = 32; | |
1117 | } | |
1118 | ||
1119 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1120 | |
006e983b S |
1121 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1122 | numa_node_id()); | |
287980e4 | 1123 | if (irq_base < 0) { |
006e983b S |
1124 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
1125 | irq_start); | |
1126 | irq_base = irq_start; | |
1127 | } | |
1128 | ||
891ae769 | 1129 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
006e983b | 1130 | hwirq_base, &gic_irq_domain_ops, gic); |
f37a53cc | 1131 | } |
006e983b | 1132 | |
dc9722cc JH |
1133 | if (WARN_ON(!gic->domain)) { |
1134 | ret = -ENODEV; | |
1135 | goto error; | |
1136 | } | |
bef8f9ee | 1137 | |
4294f8ba | 1138 | gic_dist_init(gic); |
dc9722cc JH |
1139 | ret = gic_cpu_init(gic); |
1140 | if (ret) | |
1141 | goto error; | |
1142 | ||
1143 | ret = gic_pm_init(gic); | |
1144 | if (ret) | |
1145 | goto error; | |
1146 | ||
1147 | return 0; | |
1148 | ||
1149 | error: | |
f673b9b5 | 1150 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc JH |
1151 | free_percpu(gic->dist_base.percpu_base); |
1152 | free_percpu(gic->cpu_base.percpu_base); | |
1153 | } | |
1154 | ||
1155 | kfree(gic->chip.name); | |
1156 | ||
1157 | return ret; | |
b580b899 RK |
1158 | } |
1159 | ||
d6ce564c JH |
1160 | static int __init __gic_init_bases(struct gic_chip_data *gic, |
1161 | int irq_start, | |
1162 | struct fwnode_handle *handle) | |
1163 | { | |
1164 | int i; | |
1165 | ||
1166 | if (WARN_ON(!gic || gic->domain)) | |
1167 | return -EINVAL; | |
1168 | ||
1169 | if (gic == &gic_data[0]) { | |
1170 | /* | |
1171 | * Initialize the CPU interface map to all CPUs. | |
1172 | * It will be refined as each CPU probes its ID. | |
1173 | * This is only necessary for the primary GIC. | |
1174 | */ | |
1175 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1176 | gic_cpu_map[i] = 0xff; | |
1177 | #ifdef CONFIG_SMP | |
1178 | set_smp_cross_call(gic_raise_softirq); | |
1179 | register_cpu_notifier(&gic_cpu_notifier); | |
1180 | #endif | |
1181 | set_handle_irq(gic_handle_irq); | |
1182 | if (static_key_true(&supports_deactivate)) | |
1183 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
1184 | } | |
1185 | ||
1186 | return gic_init_bases(gic, irq_start, handle); | |
1187 | } | |
1188 | ||
e81a7cd9 MZ |
1189 | void __init gic_init(unsigned int gic_nr, int irq_start, |
1190 | void __iomem *dist_base, void __iomem *cpu_base) | |
4a6ac304 | 1191 | { |
f673b9b5 JH |
1192 | struct gic_chip_data *gic; |
1193 | ||
1194 | if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) | |
1195 | return; | |
1196 | ||
4a6ac304 MZ |
1197 | /* |
1198 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1199 | * bother with these... | |
1200 | */ | |
1201 | static_key_slow_dec(&supports_deactivate); | |
f673b9b5 JH |
1202 | |
1203 | gic = &gic_data[gic_nr]; | |
1204 | gic->raw_dist_base = dist_base; | |
1205 | gic->raw_cpu_base = cpu_base; | |
1206 | ||
1207 | __gic_init_bases(gic, irq_start, NULL); | |
4a6ac304 MZ |
1208 | } |
1209 | ||
d6490461 JH |
1210 | static void gic_teardown(struct gic_chip_data *gic) |
1211 | { | |
1212 | if (WARN_ON(!gic)) | |
1213 | return; | |
1214 | ||
1215 | if (gic->raw_dist_base) | |
1216 | iounmap(gic->raw_dist_base); | |
1217 | if (gic->raw_cpu_base) | |
1218 | iounmap(gic->raw_cpu_base); | |
4a6ac304 MZ |
1219 | } |
1220 | ||
b3f7ed03 | 1221 | #ifdef CONFIG_OF |
46f101df | 1222 | static int gic_cnt __initdata; |
b3f7ed03 | 1223 | |
12e14066 MZ |
1224 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1225 | { | |
1226 | struct resource cpuif_res; | |
1227 | ||
1228 | of_address_to_resource(node, 1, &cpuif_res); | |
1229 | ||
1230 | if (!is_hyp_mode_available()) | |
1231 | return false; | |
1232 | if (resource_size(&cpuif_res) < SZ_8K) | |
1233 | return false; | |
1234 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1235 | u32 val_low, val_high; | |
1236 | ||
1237 | /* | |
1238 | * Verify that we have the first 4kB of a GIC400 | |
1239 | * aliased over the first 64kB by checking the | |
1240 | * GICC_IIDR register on both ends. | |
1241 | */ | |
1242 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1243 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1244 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1245 | val_low != val_high) | |
1246 | return false; | |
1247 | ||
1248 | /* | |
1249 | * Move the base up by 60kB, so that we have a 8kB | |
1250 | * contiguous region, which allows us to use GICC_DIR | |
1251 | * at its normal offset. Please pass me that bucket. | |
1252 | */ | |
1253 | *base += 0xf000; | |
1254 | cpuif_res.start += 0xf000; | |
1255 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1256 | &cpuif_res.start); | |
1257 | } | |
1258 | ||
1259 | return true; | |
1260 | } | |
1261 | ||
7beaa24b | 1262 | static int __init gic_of_setup(struct gic_chip_data *gic, struct device_node *node) |
d6490461 JH |
1263 | { |
1264 | if (!gic || !node) | |
1265 | return -EINVAL; | |
1266 | ||
1267 | gic->raw_dist_base = of_iomap(node, 0); | |
1268 | if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) | |
1269 | goto error; | |
1270 | ||
1271 | gic->raw_cpu_base = of_iomap(node, 1); | |
1272 | if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) | |
1273 | goto error; | |
1274 | ||
1275 | if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) | |
1276 | gic->percpu_offset = 0; | |
1277 | ||
1278 | return 0; | |
1279 | ||
1280 | error: | |
1281 | gic_teardown(gic); | |
1282 | ||
1283 | return -ENOMEM; | |
1284 | } | |
1285 | ||
502d6df1 JG |
1286 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1287 | { | |
1288 | int ret; | |
1289 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; | |
1290 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; | |
1291 | ||
1292 | gic_v2_kvm_info.type = GIC_V2; | |
1293 | ||
1294 | gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1295 | if (!gic_v2_kvm_info.maint_irq) | |
1296 | return; | |
1297 | ||
1298 | ret = of_address_to_resource(node, 2, vctrl_res); | |
1299 | if (ret) | |
1300 | return; | |
1301 | ||
1302 | ret = of_address_to_resource(node, 3, vcpu_res); | |
1303 | if (ret) | |
1304 | return; | |
1305 | ||
1306 | gic_set_kvm_info(&gic_v2_kvm_info); | |
1307 | } | |
1308 | ||
8673c1d7 | 1309 | int __init |
6859358e | 1310 | gic_of_init(struct device_node *node, struct device_node *parent) |
b3f7ed03 | 1311 | { |
f673b9b5 | 1312 | struct gic_chip_data *gic; |
dc9722cc | 1313 | int irq, ret; |
b3f7ed03 RH |
1314 | |
1315 | if (WARN_ON(!node)) | |
1316 | return -ENODEV; | |
1317 | ||
f673b9b5 JH |
1318 | if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) |
1319 | return -EINVAL; | |
1320 | ||
1321 | gic = &gic_data[gic_cnt]; | |
b3f7ed03 | 1322 | |
d6490461 JH |
1323 | ret = gic_of_setup(gic, node); |
1324 | if (ret) | |
1325 | return ret; | |
b3f7ed03 | 1326 | |
0b996fd3 MZ |
1327 | /* |
1328 | * Disable split EOI/Deactivate if either HYP is not available | |
1329 | * or the CPU interface is too small. | |
1330 | */ | |
f673b9b5 | 1331 | if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) |
0b996fd3 MZ |
1332 | static_key_slow_dec(&supports_deactivate); |
1333 | ||
f673b9b5 | 1334 | ret = __gic_init_bases(gic, -1, &node->fwnode); |
dc9722cc | 1335 | if (ret) { |
d6490461 | 1336 | gic_teardown(gic); |
dc9722cc JH |
1337 | return ret; |
1338 | } | |
db0d4db2 | 1339 | |
502d6df1 | 1340 | if (!gic_cnt) { |
eeb44658 | 1341 | gic_init_physaddr(node); |
502d6df1 JG |
1342 | gic_of_setup_kvm_info(node); |
1343 | } | |
b3f7ed03 RH |
1344 | |
1345 | if (parent) { | |
1346 | irq = irq_of_parse_and_map(node, 0); | |
1347 | gic_cascade_irq(gic_cnt, irq); | |
1348 | } | |
853a33ce SS |
1349 | |
1350 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
0644b3da | 1351 | gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); |
853a33ce | 1352 | |
b3f7ed03 RH |
1353 | gic_cnt++; |
1354 | return 0; | |
1355 | } | |
144cb088 | 1356 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1357 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1358 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1359 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1360 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1361 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1362 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1363 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1364 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1365 | |
b3f7ed03 | 1366 | #endif |
d60fc389 TN |
1367 | |
1368 | #ifdef CONFIG_ACPI | |
bafa9193 JG |
1369 | static struct |
1370 | { | |
1371 | phys_addr_t cpu_phys_base; | |
502d6df1 JG |
1372 | u32 maint_irq; |
1373 | int maint_irq_mode; | |
1374 | phys_addr_t vctrl_base; | |
1375 | phys_addr_t vcpu_base; | |
bafa9193 | 1376 | } acpi_data __initdata; |
d60fc389 TN |
1377 | |
1378 | static int __init | |
1379 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1380 | const unsigned long end) | |
1381 | { | |
1382 | struct acpi_madt_generic_interrupt *processor; | |
1383 | phys_addr_t gic_cpu_base; | |
1384 | static int cpu_base_assigned; | |
1385 | ||
1386 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1387 | ||
99e3e3ae | 1388 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1389 | return -EINVAL; |
1390 | ||
1391 | /* | |
1392 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1393 | * All CPU interface addresses have to be the same. | |
1394 | */ | |
1395 | gic_cpu_base = processor->base_address; | |
bafa9193 | 1396 | if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) |
d60fc389 TN |
1397 | return -EINVAL; |
1398 | ||
bafa9193 | 1399 | acpi_data.cpu_phys_base = gic_cpu_base; |
502d6df1 JG |
1400 | acpi_data.maint_irq = processor->vgic_interrupt; |
1401 | acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1402 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1403 | acpi_data.vctrl_base = processor->gich_base_address; | |
1404 | acpi_data.vcpu_base = processor->gicv_base_address; | |
1405 | ||
d60fc389 TN |
1406 | cpu_base_assigned = 1; |
1407 | return 0; | |
1408 | } | |
1409 | ||
f26527b1 MZ |
1410 | /* The things you have to do to just *count* something... */ |
1411 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, | |
1412 | const unsigned long end) | |
d60fc389 | 1413 | { |
f26527b1 MZ |
1414 | return 0; |
1415 | } | |
d60fc389 | 1416 | |
f26527b1 MZ |
1417 | static bool __init acpi_gic_redist_is_present(void) |
1418 | { | |
1419 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1420 | acpi_dummy_func, 0) > 0; | |
1421 | } | |
d60fc389 | 1422 | |
f26527b1 MZ |
1423 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1424 | struct acpi_probe_entry *ape) | |
1425 | { | |
1426 | struct acpi_madt_generic_distributor *dist; | |
1427 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1428 | |
f26527b1 MZ |
1429 | return (dist->version == ape->driver_data && |
1430 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1431 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1432 | } |
1433 | ||
f26527b1 MZ |
1434 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1435 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
502d6df1 JG |
1436 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1437 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1438 | ||
1439 | static void __init gic_acpi_setup_kvm_info(void) | |
1440 | { | |
1441 | int irq; | |
1442 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; | |
1443 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; | |
1444 | ||
1445 | gic_v2_kvm_info.type = GIC_V2; | |
1446 | ||
1447 | if (!acpi_data.vctrl_base) | |
1448 | return; | |
1449 | ||
1450 | vctrl_res->flags = IORESOURCE_MEM; | |
1451 | vctrl_res->start = acpi_data.vctrl_base; | |
1452 | vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; | |
1453 | ||
1454 | if (!acpi_data.vcpu_base) | |
1455 | return; | |
1456 | ||
1457 | vcpu_res->flags = IORESOURCE_MEM; | |
1458 | vcpu_res->start = acpi_data.vcpu_base; | |
1459 | vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1460 | ||
1461 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1462 | acpi_data.maint_irq_mode, | |
1463 | ACPI_ACTIVE_HIGH); | |
1464 | if (irq <= 0) | |
1465 | return; | |
1466 | ||
1467 | gic_v2_kvm_info.maint_irq = irq; | |
1468 | ||
1469 | gic_set_kvm_info(&gic_v2_kvm_info); | |
1470 | } | |
f26527b1 MZ |
1471 | |
1472 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1473 | const unsigned long end) | |
d60fc389 | 1474 | { |
f26527b1 | 1475 | struct acpi_madt_generic_distributor *dist; |
891ae769 | 1476 | struct fwnode_handle *domain_handle; |
f673b9b5 | 1477 | struct gic_chip_data *gic = &gic_data[0]; |
dc9722cc | 1478 | int count, ret; |
d60fc389 TN |
1479 | |
1480 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1481 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1482 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1483 | if (count <= 0) { |
1484 | pr_err("No valid GICC entries exist\n"); | |
1485 | return -EINVAL; | |
1486 | } | |
1487 | ||
7beaa24b | 1488 | gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
f673b9b5 | 1489 | if (!gic->raw_cpu_base) { |
d60fc389 TN |
1490 | pr_err("Unable to map GICC registers\n"); |
1491 | return -ENOMEM; | |
1492 | } | |
1493 | ||
f26527b1 | 1494 | dist = (struct acpi_madt_generic_distributor *)header; |
f673b9b5 JH |
1495 | gic->raw_dist_base = ioremap(dist->base_address, |
1496 | ACPI_GICV2_DIST_MEM_SIZE); | |
1497 | if (!gic->raw_dist_base) { | |
d60fc389 | 1498 | pr_err("Unable to map GICD registers\n"); |
d6490461 | 1499 | gic_teardown(gic); |
d60fc389 TN |
1500 | return -ENOMEM; |
1501 | } | |
1502 | ||
0b996fd3 MZ |
1503 | /* |
1504 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1505 | * guarantees that we'll always have a GICv2, so the CPU | |
1506 | * interface will always be the right size. | |
1507 | */ | |
1508 | if (!is_hyp_mode_available()) | |
1509 | static_key_slow_dec(&supports_deactivate); | |
1510 | ||
d60fc389 | 1511 | /* |
891ae769 | 1512 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1513 | */ |
f673b9b5 | 1514 | domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); |
891ae769 MZ |
1515 | if (!domain_handle) { |
1516 | pr_err("Unable to allocate domain handle\n"); | |
d6490461 | 1517 | gic_teardown(gic); |
891ae769 MZ |
1518 | return -ENOMEM; |
1519 | } | |
1520 | ||
f673b9b5 | 1521 | ret = __gic_init_bases(gic, -1, domain_handle); |
dc9722cc JH |
1522 | if (ret) { |
1523 | pr_err("Failed to initialise GIC\n"); | |
1524 | irq_domain_free_fwnode(domain_handle); | |
d6490461 | 1525 | gic_teardown(gic); |
dc9722cc JH |
1526 | return ret; |
1527 | } | |
d8f4f161 | 1528 | |
891ae769 | 1529 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
0644b3da SS |
1530 | |
1531 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1532 | gicv2m_init(NULL, gic_data[0].domain); | |
1533 | ||
502d6df1 JG |
1534 | gic_acpi_setup_kvm_info(); |
1535 | ||
d60fc389 TN |
1536 | return 0; |
1537 | } | |
f26527b1 MZ |
1538 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1539 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1540 | gic_v2_acpi_init); | |
1541 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1542 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1543 | gic_v2_acpi_init); | |
d60fc389 | 1544 | #endif |