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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f27ecacc | 2 | /* |
f27ecacc RK |
3 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
4 | * | |
f27ecacc RK |
5 | * Interrupt architecture for the GIC: |
6 | * | |
7 | * o There is one Interrupt Distributor, which receives interrupts | |
8 | * from system devices and sends them to the Interrupt Controllers. | |
9 | * | |
10 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
11 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
12 | * associated CPU. The base address of the CPU interface is usually |
13 | * aliased so that the same address points to different chips depending | |
14 | * on the CPU it is accessed from. | |
f27ecacc RK |
15 | * |
16 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
17 | * As such, the enable set/clear, pending set/clear and active bit | |
18 | * registers are banked per-cpu for these sources. | |
19 | */ | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
f37a53cc | 22 | #include <linux/err.h> |
7e1efcf5 | 23 | #include <linux/module.h> |
f27ecacc RK |
24 | #include <linux/list.h> |
25 | #include <linux/smp.h> | |
c0114709 | 26 | #include <linux/cpu.h> |
254056f3 | 27 | #include <linux/cpu_pm.h> |
dcb86e8c | 28 | #include <linux/cpumask.h> |
fced80c7 | 29 | #include <linux/io.h> |
b3f7ed03 RH |
30 | #include <linux/of.h> |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
d60fc389 | 33 | #include <linux/acpi.h> |
4294f8ba | 34 | #include <linux/irqdomain.h> |
292b293c MZ |
35 | #include <linux/interrupt.h> |
36 | #include <linux/percpu.h> | |
37 | #include <linux/slab.h> | |
41a83e06 | 38 | #include <linux/irqchip.h> |
de88cbb7 | 39 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 40 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 41 | |
29e697b1 | 42 | #include <asm/cputype.h> |
f27ecacc | 43 | #include <asm/irq.h> |
562e0027 | 44 | #include <asm/exception.h> |
eb50439b | 45 | #include <asm/smp_plat.h> |
0b996fd3 | 46 | #include <asm/virt.h> |
f27ecacc | 47 | |
d51d0af4 | 48 | #include "irq-gic-common.h" |
f27ecacc | 49 | |
76e52dd0 MZ |
50 | #ifdef CONFIG_ARM64 |
51 | #include <asm/cpufeature.h> | |
52 | ||
53 | static void gic_check_cpu_features(void) | |
54 | { | |
25fc11ae | 55 | WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), |
76e52dd0 MZ |
56 | TAINT_CPU_OUT_OF_SPEC, |
57 | "GICv3 system registers enabled, broken firmware!\n"); | |
58 | } | |
59 | #else | |
60 | #define gic_check_cpu_features() do { } while(0) | |
61 | #endif | |
62 | ||
db0d4db2 MZ |
63 | union gic_base { |
64 | void __iomem *common_base; | |
6859358e | 65 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
66 | }; |
67 | ||
68 | struct gic_chip_data { | |
58b89649 | 69 | struct irq_chip chip; |
db0d4db2 MZ |
70 | union gic_base dist_base; |
71 | union gic_base cpu_base; | |
f673b9b5 JH |
72 | void __iomem *raw_dist_base; |
73 | void __iomem *raw_cpu_base; | |
74 | u32 percpu_offset; | |
9c8edddf | 75 | #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) |
db0d4db2 | 76 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; |
1c7d4dd4 | 77 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
db0d4db2 MZ |
78 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
79 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
80 | u32 __percpu *saved_ppi_enable; | |
1c7d4dd4 | 81 | u32 __percpu *saved_ppi_active; |
db0d4db2 MZ |
82 | u32 __percpu *saved_ppi_conf; |
83 | #endif | |
75294957 | 84 | struct irq_domain *domain; |
db0d4db2 MZ |
85 | unsigned int gic_irqs; |
86 | #ifdef CONFIG_GIC_NON_BANKED | |
87 | void __iomem *(*get_base)(union gic_base *); | |
88 | #endif | |
89 | }; | |
90 | ||
04c8b0f8 MZ |
91 | #ifdef CONFIG_BL_SWITCHER |
92 | ||
93 | static DEFINE_RAW_SPINLOCK(cpu_map_lock); | |
94 | ||
95 | #define gic_lock_irqsave(f) \ | |
96 | raw_spin_lock_irqsave(&cpu_map_lock, (f)) | |
97 | #define gic_unlock_irqrestore(f) \ | |
98 | raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) | |
99 | ||
100 | #define gic_lock() raw_spin_lock(&cpu_map_lock) | |
101 | #define gic_unlock() raw_spin_unlock(&cpu_map_lock) | |
102 | ||
103 | #else | |
104 | ||
105 | #define gic_lock_irqsave(f) do { (void)(f); } while(0) | |
106 | #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) | |
107 | ||
108 | #define gic_lock() do { } while(0) | |
109 | #define gic_unlock() do { } while(0) | |
110 | ||
111 | #endif | |
f27ecacc | 112 | |
384a2902 NP |
113 | /* |
114 | * The GIC mapping of CPU interfaces does not necessarily match | |
115 | * the logical CPU numbering. Let's use a mapping as returned | |
116 | * by the GIC itself. | |
117 | */ | |
118 | #define NR_GIC_CPU_IF 8 | |
119 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
120 | ||
d01d3274 | 121 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
0b996fd3 | 122 | |
a27d21e0 | 123 | static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; |
b3a1bde4 | 124 | |
502d6df1 JG |
125 | static struct gic_kvm_info gic_v2_kvm_info; |
126 | ||
db0d4db2 MZ |
127 | #ifdef CONFIG_GIC_NON_BANKED |
128 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
129 | { | |
513d1a28 | 130 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
131 | } |
132 | ||
133 | static void __iomem *gic_get_common_base(union gic_base *base) | |
134 | { | |
135 | return base->common_base; | |
136 | } | |
137 | ||
138 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
139 | { | |
140 | return data->get_base(&data->dist_base); | |
141 | } | |
142 | ||
143 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
144 | { | |
145 | return data->get_base(&data->cpu_base); | |
146 | } | |
147 | ||
148 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
149 | void __iomem *(*f)(union gic_base *)) | |
150 | { | |
151 | data->get_base = f; | |
152 | } | |
153 | #else | |
154 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
155 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 156 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
157 | #endif |
158 | ||
7d1f4288 | 159 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 160 | { |
7d1f4288 | 161 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 162 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
163 | } |
164 | ||
7d1f4288 | 165 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 166 | { |
7d1f4288 | 167 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 168 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
169 | } |
170 | ||
7d1f4288 | 171 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 172 | { |
4294f8ba | 173 | return d->hwirq; |
b3a1bde4 CM |
174 | } |
175 | ||
01f779f4 MZ |
176 | static inline bool cascading_gic_irq(struct irq_data *d) |
177 | { | |
178 | void *data = irq_data_get_irq_handler_data(d); | |
179 | ||
180 | /* | |
71466535 TG |
181 | * If handler_data is set, this is a cascading interrupt, and |
182 | * it cannot possibly be forwarded. | |
01f779f4 | 183 | */ |
71466535 | 184 | return data != NULL; |
01f779f4 MZ |
185 | } |
186 | ||
f27ecacc RK |
187 | /* |
188 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 189 | */ |
56717807 MZ |
190 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
191 | { | |
192 | u32 mask = 1 << (gic_irq(d) % 32); | |
193 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
194 | } | |
195 | ||
196 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 197 | { |
4294f8ba | 198 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
199 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
200 | } | |
201 | ||
202 | static void gic_mask_irq(struct irq_data *d) | |
203 | { | |
56717807 | 204 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
205 | } |
206 | ||
0b996fd3 MZ |
207 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
208 | { | |
209 | gic_mask_irq(d); | |
01f779f4 MZ |
210 | /* |
211 | * When masking a forwarded interrupt, make sure it is | |
212 | * deactivated as well. | |
213 | * | |
214 | * This ensures that an interrupt that is getting | |
215 | * disabled/masked will not get "stuck", because there is | |
216 | * noone to deactivate it (guest is being terminated). | |
217 | */ | |
71466535 | 218 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 219 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
220 | } |
221 | ||
7d1f4288 | 222 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 223 | { |
56717807 | 224 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
225 | } |
226 | ||
1a01753e WD |
227 | static void gic_eoi_irq(struct irq_data *d) |
228 | { | |
6ac77e46 | 229 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
230 | } |
231 | ||
0b996fd3 MZ |
232 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
233 | { | |
01f779f4 | 234 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 235 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
236 | return; |
237 | ||
0b996fd3 MZ |
238 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
239 | } | |
240 | ||
56717807 MZ |
241 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
242 | enum irqchip_irq_state which, bool val) | |
243 | { | |
244 | u32 reg; | |
245 | ||
246 | switch (which) { | |
247 | case IRQCHIP_STATE_PENDING: | |
248 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
249 | break; | |
250 | ||
251 | case IRQCHIP_STATE_ACTIVE: | |
252 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
253 | break; | |
254 | ||
255 | case IRQCHIP_STATE_MASKED: | |
256 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
257 | break; | |
258 | ||
259 | default: | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
263 | gic_poke_irq(d, reg); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
268 | enum irqchip_irq_state which, bool *val) | |
269 | { | |
270 | switch (which) { | |
271 | case IRQCHIP_STATE_PENDING: | |
272 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
273 | break; | |
274 | ||
275 | case IRQCHIP_STATE_ACTIVE: | |
276 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
277 | break; | |
278 | ||
279 | case IRQCHIP_STATE_MASKED: | |
280 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
281 | break; | |
282 | ||
283 | default: | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
7d1f4288 | 290 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 291 | { |
7d1f4288 LB |
292 | void __iomem *base = gic_dist_base(d); |
293 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
294 | |
295 | /* Interrupt configuration for SGIs can't be changed */ | |
296 | if (gicirq < 16) | |
297 | return -EINVAL; | |
298 | ||
fb7e7deb LD |
299 | /* SPIs have restrictions on the supported types */ |
300 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
301 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
302 | return -EINVAL; |
303 | ||
1dcc73d7 | 304 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
305 | } |
306 | ||
01f779f4 MZ |
307 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
308 | { | |
309 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
310 | if (cascading_gic_irq(d)) | |
311 | return -EINVAL; | |
312 | ||
71466535 TG |
313 | if (vcpu) |
314 | irqd_set_forwarded_to_vcpu(d); | |
315 | else | |
316 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
317 | return 0; |
318 | } | |
319 | ||
a06f5466 | 320 | #ifdef CONFIG_SMP |
c191789c RK |
321 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
322 | bool force) | |
f27ecacc | 323 | { |
7d1f4288 | 324 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 325 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 326 | u32 val, mask, bit; |
cf613871 | 327 | unsigned long flags; |
f27ecacc | 328 | |
ffde1de6 TG |
329 | if (!force) |
330 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
331 | else | |
332 | cpu = cpumask_first(mask_val); | |
333 | ||
384a2902 | 334 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 335 | return -EINVAL; |
c191789c | 336 | |
04c8b0f8 | 337 | gic_lock_irqsave(flags); |
c191789c | 338 | mask = 0xff << shift; |
384a2902 | 339 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
340 | val = readl_relaxed(reg) & ~mask; |
341 | writel_relaxed(val | bit, reg); | |
04c8b0f8 | 342 | gic_unlock_irqrestore(flags); |
d5dedd45 | 343 | |
0c9e4982 MZ |
344 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
345 | ||
0407dace | 346 | return IRQ_SET_MASK_OK_DONE; |
f27ecacc | 347 | } |
a06f5466 | 348 | #endif |
f27ecacc | 349 | |
8783dd3a | 350 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
351 | { |
352 | u32 irqstat, irqnr; | |
353 | struct gic_chip_data *gic = &gic_data[0]; | |
354 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
355 | ||
356 | do { | |
357 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 358 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 | 359 | |
327ebe1f | 360 | if (likely(irqnr > 15 && irqnr < 1020)) { |
d01d3274 | 361 | if (static_branch_likely(&supports_deactivate_key)) |
0b996fd3 | 362 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
39a06b67 | 363 | isb(); |
60031b4e | 364 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
365 | continue; |
366 | } | |
367 | if (irqnr < 16) { | |
368 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
d01d3274 | 369 | if (static_branch_likely(&supports_deactivate_key)) |
0b996fd3 | 370 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); |
562e0027 | 371 | #ifdef CONFIG_SMP |
f86c4fbd WD |
372 | /* |
373 | * Ensure any shared data written by the CPU sending | |
374 | * the IPI is read after we've read the ACK register | |
375 | * on the GIC. | |
376 | * | |
377 | * Pairs with the write barrier in gic_raise_softirq | |
378 | */ | |
379 | smp_rmb(); | |
562e0027 MZ |
380 | handle_IPI(irqnr, regs); |
381 | #endif | |
382 | continue; | |
383 | } | |
384 | break; | |
385 | } while (1); | |
386 | } | |
387 | ||
bd0b9ac4 | 388 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 389 | { |
5b29264c JL |
390 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
391 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 392 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
393 | unsigned long status; |
394 | ||
1a01753e | 395 | chained_irq_enter(chip, desc); |
b3a1bde4 | 396 | |
db0d4db2 | 397 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
b3a1bde4 | 398 | |
e5f81539 FK |
399 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
400 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 401 | goto out; |
b3a1bde4 | 402 | |
75294957 | 403 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
39a06b67 | 404 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) { |
bd0b9ac4 | 405 | handle_bad_irq(desc); |
39a06b67 WD |
406 | } else { |
407 | isb(); | |
0f347bb9 | 408 | generic_handle_irq(cascade_irq); |
39a06b67 | 409 | } |
b3a1bde4 CM |
410 | |
411 | out: | |
1a01753e | 412 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
413 | } |
414 | ||
73c4c37c | 415 | static const struct irq_chip gic_chip = { |
7d1f4288 LB |
416 | .irq_mask = gic_mask_irq, |
417 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 418 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 419 | .irq_set_type = gic_set_type, |
56717807 MZ |
420 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
421 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
422 | .flags = IRQCHIP_SET_TYPE_MASKED | |
423 | IRQCHIP_SKIP_SET_WAKE | | |
424 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
425 | }; |
426 | ||
b3a1bde4 CM |
427 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
428 | { | |
a27d21e0 | 429 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
4d83fcf8 TG |
430 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
431 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
432 | } |
433 | ||
2bb31351 RK |
434 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
435 | { | |
436 | void __iomem *base = gic_data_dist_base(gic); | |
437 | u32 mask, i; | |
438 | ||
439 | for (i = mask = 0; i < 32; i += 4) { | |
440 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
441 | mask |= mask >> 16; | |
442 | mask |= mask >> 8; | |
443 | if (mask) | |
444 | break; | |
445 | } | |
446 | ||
6e3aca44 | 447 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
448 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
449 | ||
450 | return mask; | |
451 | } | |
452 | ||
c5e1035c MZ |
453 | static bool gic_check_gicv2(void __iomem *base) |
454 | { | |
455 | u32 val = readl_relaxed(base + GIC_CPU_IDENT); | |
456 | return (val & 0xff0fff) == 0x02043B; | |
457 | } | |
458 | ||
4c2880b3 | 459 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 460 | { |
4c2880b3 | 461 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 462 | u32 bypass = 0; |
0b996fd3 | 463 | u32 mode = 0; |
c5e1035c | 464 | int i; |
0b996fd3 | 465 | |
d01d3274 | 466 | if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) |
0b996fd3 | 467 | mode = GIC_CPU_CTRL_EOImodeNS; |
32289506 | 468 | |
c5e1035c MZ |
469 | if (gic_check_gicv2(cpu_base)) |
470 | for (i = 0; i < 4; i++) | |
471 | writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); | |
472 | ||
32289506 FK |
473 | /* |
474 | * Preserve bypass disable bits to be written back later | |
475 | */ | |
476 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
477 | bypass &= GICC_DIS_BYPASS_MASK; | |
478 | ||
0b996fd3 | 479 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
480 | } |
481 | ||
482 | ||
cdbb813d | 483 | static void gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 484 | { |
75294957 | 485 | unsigned int i; |
267840f3 | 486 | u32 cpumask; |
4294f8ba | 487 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 488 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 489 | |
e5f81539 | 490 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 491 | |
f27ecacc RK |
492 | /* |
493 | * Set all global interrupts to this CPU only. | |
494 | */ | |
2bb31351 RK |
495 | cpumask = gic_get_cpumask(gic); |
496 | cpumask |= cpumask << 8; | |
497 | cpumask |= cpumask << 16; | |
e6afec9b | 498 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 499 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 500 | |
d51d0af4 | 501 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 502 | |
e5f81539 | 503 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
504 | } |
505 | ||
dc9722cc | 506 | static int gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 507 | { |
db0d4db2 MZ |
508 | void __iomem *dist_base = gic_data_dist_base(gic); |
509 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 510 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
511 | int i; |
512 | ||
384a2902 | 513 | /* |
567e5a01 JH |
514 | * Setting up the CPU map is only relevant for the primary GIC |
515 | * because any nested/secondary GICs do not directly interface | |
516 | * with the CPU(s). | |
384a2902 | 517 | */ |
567e5a01 JH |
518 | if (gic == &gic_data[0]) { |
519 | /* | |
520 | * Get what the GIC says our CPU mask is. | |
521 | */ | |
dc9722cc JH |
522 | if (WARN_ON(cpu >= NR_GIC_CPU_IF)) |
523 | return -EINVAL; | |
524 | ||
25fc11ae | 525 | gic_check_cpu_features(); |
567e5a01 JH |
526 | cpu_mask = gic_get_cpumask(gic); |
527 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 528 | |
567e5a01 JH |
529 | /* |
530 | * Clear our mask from the other map entries in case they're | |
531 | * still undefined. | |
532 | */ | |
533 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
534 | if (i != cpu) | |
535 | gic_cpu_map[i] &= ~cpu_mask; | |
536 | } | |
384a2902 | 537 | |
d51d0af4 | 538 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 539 | |
e5f81539 | 540 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 541 | gic_cpu_if_up(gic); |
dc9722cc JH |
542 | |
543 | return 0; | |
f27ecacc RK |
544 | } |
545 | ||
4c2880b3 | 546 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 547 | { |
4c2880b3 | 548 | void __iomem *cpu_base; |
32289506 FK |
549 | u32 val = 0; |
550 | ||
a27d21e0 | 551 | if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) |
4c2880b3 JH |
552 | return -EINVAL; |
553 | ||
554 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
555 | val = readl(cpu_base + GIC_CPU_CTRL); |
556 | val &= ~GICC_ENABLE; | |
557 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
558 | |
559 | return 0; | |
10d9eb8a NP |
560 | } |
561 | ||
9c8edddf | 562 | #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) |
254056f3 CC |
563 | /* |
564 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
565 | * with interrupts disabled but before powering down the GIC. After calling | |
566 | * this function, no interrupts will be delivered by the GIC, and another | |
567 | * platform-specific wakeup source must be enabled. | |
568 | */ | |
cdbb813d | 569 | void gic_dist_save(struct gic_chip_data *gic) |
254056f3 CC |
570 | { |
571 | unsigned int gic_irqs; | |
572 | void __iomem *dist_base; | |
573 | int i; | |
574 | ||
6e5b5924 JH |
575 | if (WARN_ON(!gic)) |
576 | return; | |
254056f3 | 577 | |
6e5b5924 JH |
578 | gic_irqs = gic->gic_irqs; |
579 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
580 | |
581 | if (!dist_base) | |
582 | return; | |
583 | ||
584 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 585 | gic->saved_spi_conf[i] = |
254056f3 CC |
586 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
587 | ||
588 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 589 | gic->saved_spi_target[i] = |
254056f3 CC |
590 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
591 | ||
592 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 593 | gic->saved_spi_enable[i] = |
254056f3 | 594 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
1c7d4dd4 MZ |
595 | |
596 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
6e5b5924 | 597 | gic->saved_spi_active[i] = |
1c7d4dd4 | 598 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
254056f3 CC |
599 | } |
600 | ||
601 | /* | |
602 | * Restores the GIC distributor registers during resume or when coming out of | |
603 | * idle. Must be called before enabling interrupts. If a level interrupt | |
c5f48c0a IM |
604 | * that occurred while the GIC was suspended is still present, it will be |
605 | * handled normally, but any edge interrupts that occurred will not be seen by | |
254056f3 CC |
606 | * the GIC and need to be handled by the platform-specific wakeup source. |
607 | */ | |
cdbb813d | 608 | void gic_dist_restore(struct gic_chip_data *gic) |
254056f3 CC |
609 | { |
610 | unsigned int gic_irqs; | |
611 | unsigned int i; | |
612 | void __iomem *dist_base; | |
613 | ||
6e5b5924 JH |
614 | if (WARN_ON(!gic)) |
615 | return; | |
254056f3 | 616 | |
6e5b5924 JH |
617 | gic_irqs = gic->gic_irqs; |
618 | dist_base = gic_data_dist_base(gic); | |
254056f3 CC |
619 | |
620 | if (!dist_base) | |
621 | return; | |
622 | ||
e5f81539 | 623 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
624 | |
625 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
6e5b5924 | 626 | writel_relaxed(gic->saved_spi_conf[i], |
254056f3 CC |
627 | dist_base + GIC_DIST_CONFIG + i * 4); |
628 | ||
629 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 630 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
631 | dist_base + GIC_DIST_PRI + i * 4); |
632 | ||
633 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
6e5b5924 | 634 | writel_relaxed(gic->saved_spi_target[i], |
254056f3 CC |
635 | dist_base + GIC_DIST_TARGET + i * 4); |
636 | ||
92eda4ad MZ |
637 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
638 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
639 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
6e5b5924 | 640 | writel_relaxed(gic->saved_spi_enable[i], |
254056f3 | 641 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 642 | } |
254056f3 | 643 | |
1c7d4dd4 MZ |
644 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
645 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
646 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
6e5b5924 | 647 | writel_relaxed(gic->saved_spi_active[i], |
1c7d4dd4 MZ |
648 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
649 | } | |
650 | ||
e5f81539 | 651 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
652 | } |
653 | ||
cdbb813d | 654 | void gic_cpu_save(struct gic_chip_data *gic) |
254056f3 CC |
655 | { |
656 | int i; | |
657 | u32 *ptr; | |
658 | void __iomem *dist_base; | |
659 | void __iomem *cpu_base; | |
660 | ||
6e5b5924 JH |
661 | if (WARN_ON(!gic)) |
662 | return; | |
254056f3 | 663 | |
6e5b5924 JH |
664 | dist_base = gic_data_dist_base(gic); |
665 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
666 | |
667 | if (!dist_base || !cpu_base) | |
668 | return; | |
669 | ||
6e5b5924 | 670 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
254056f3 CC |
671 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
672 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
673 | ||
6e5b5924 | 674 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
675 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
676 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
677 | ||
6e5b5924 | 678 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
679 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
680 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
681 | ||
682 | } | |
683 | ||
cdbb813d | 684 | void gic_cpu_restore(struct gic_chip_data *gic) |
254056f3 CC |
685 | { |
686 | int i; | |
687 | u32 *ptr; | |
688 | void __iomem *dist_base; | |
689 | void __iomem *cpu_base; | |
690 | ||
6e5b5924 JH |
691 | if (WARN_ON(!gic)) |
692 | return; | |
254056f3 | 693 | |
6e5b5924 JH |
694 | dist_base = gic_data_dist_base(gic); |
695 | cpu_base = gic_data_cpu_base(gic); | |
254056f3 CC |
696 | |
697 | if (!dist_base || !cpu_base) | |
698 | return; | |
699 | ||
6e5b5924 | 700 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
92eda4ad MZ |
701 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
702 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
703 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 | 704 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 705 | } |
254056f3 | 706 | |
6e5b5924 | 707 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
1c7d4dd4 MZ |
708 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
709 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
710 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
711 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
712 | } | |
713 | ||
6e5b5924 | 714 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
254056f3 CC |
715 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
716 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
717 | ||
718 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
719 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
720 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 721 | |
e5f81539 | 722 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
6e5b5924 | 723 | gic_cpu_if_up(gic); |
254056f3 CC |
724 | } |
725 | ||
726 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
727 | { | |
728 | int i; | |
729 | ||
a27d21e0 | 730 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { |
db0d4db2 MZ |
731 | #ifdef CONFIG_GIC_NON_BANKED |
732 | /* Skip over unused GICs */ | |
733 | if (!gic_data[i].get_base) | |
734 | continue; | |
735 | #endif | |
254056f3 CC |
736 | switch (cmd) { |
737 | case CPU_PM_ENTER: | |
6e5b5924 | 738 | gic_cpu_save(&gic_data[i]); |
254056f3 CC |
739 | break; |
740 | case CPU_PM_ENTER_FAILED: | |
741 | case CPU_PM_EXIT: | |
6e5b5924 | 742 | gic_cpu_restore(&gic_data[i]); |
254056f3 CC |
743 | break; |
744 | case CPU_CLUSTER_PM_ENTER: | |
6e5b5924 | 745 | gic_dist_save(&gic_data[i]); |
254056f3 CC |
746 | break; |
747 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
748 | case CPU_CLUSTER_PM_EXIT: | |
6e5b5924 | 749 | gic_dist_restore(&gic_data[i]); |
254056f3 CC |
750 | break; |
751 | } | |
752 | } | |
753 | ||
754 | return NOTIFY_OK; | |
755 | } | |
756 | ||
757 | static struct notifier_block gic_notifier_block = { | |
758 | .notifier_call = gic_notifier, | |
759 | }; | |
760 | ||
cdbb813d | 761 | static int gic_pm_init(struct gic_chip_data *gic) |
254056f3 CC |
762 | { |
763 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
764 | sizeof(u32)); | |
dc9722cc JH |
765 | if (WARN_ON(!gic->saved_ppi_enable)) |
766 | return -ENOMEM; | |
254056f3 | 767 | |
1c7d4dd4 MZ |
768 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
769 | sizeof(u32)); | |
dc9722cc JH |
770 | if (WARN_ON(!gic->saved_ppi_active)) |
771 | goto free_ppi_enable; | |
1c7d4dd4 | 772 | |
254056f3 CC |
773 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
774 | sizeof(u32)); | |
dc9722cc JH |
775 | if (WARN_ON(!gic->saved_ppi_conf)) |
776 | goto free_ppi_active; | |
254056f3 | 777 | |
abdd7b91 MZ |
778 | if (gic == &gic_data[0]) |
779 | cpu_pm_register_notifier(&gic_notifier_block); | |
dc9722cc JH |
780 | |
781 | return 0; | |
782 | ||
783 | free_ppi_active: | |
784 | free_percpu(gic->saved_ppi_active); | |
785 | free_ppi_enable: | |
786 | free_percpu(gic->saved_ppi_enable); | |
787 | ||
788 | return -ENOMEM; | |
254056f3 CC |
789 | } |
790 | #else | |
cdbb813d | 791 | static int gic_pm_init(struct gic_chip_data *gic) |
254056f3 | 792 | { |
dc9722cc | 793 | return 0; |
254056f3 CC |
794 | } |
795 | #endif | |
796 | ||
b1cffebf | 797 | #ifdef CONFIG_SMP |
6859358e | 798 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
799 | { |
800 | int cpu; | |
1a6b69b6 NP |
801 | unsigned long flags, map = 0; |
802 | ||
059e2320 MZ |
803 | if (unlikely(nr_cpu_ids == 1)) { |
804 | /* Only one CPU? let's do a self-IPI... */ | |
805 | writel_relaxed(2 << 24 | irq, | |
806 | gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
807 | return; | |
808 | } | |
809 | ||
04c8b0f8 | 810 | gic_lock_irqsave(flags); |
b1cffebf RH |
811 | |
812 | /* Convert our logical CPU mask into a physical one. */ | |
813 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 814 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
815 | |
816 | /* | |
817 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 818 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 819 | */ |
8adbf57f | 820 | dmb(ishst); |
b1cffebf RH |
821 | |
822 | /* this always happens on GIC0 */ | |
823 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 | 824 | |
04c8b0f8 | 825 | gic_unlock_irqrestore(flags); |
1a6b69b6 NP |
826 | } |
827 | #endif | |
828 | ||
829 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
830 | /* |
831 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
832 | * | |
833 | * cpu_id: the ID for the destination CPU interface | |
834 | * irq: the IPI number to send a SGI for | |
835 | */ | |
836 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
837 | { | |
838 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
839 | cpu_id = 1 << cpu_id; | |
840 | /* this always happens on GIC0 */ | |
841 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
842 | } | |
843 | ||
ed96762e NP |
844 | /* |
845 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
846 | * | |
847 | * @cpu: the logical CPU number to get the GIC ID for. | |
848 | * | |
849 | * Return the CPU interface ID for the given logical CPU number, | |
850 | * or -1 if the CPU number is too large or the interface ID is | |
851 | * unknown (more than one bit set). | |
852 | */ | |
853 | int gic_get_cpu_id(unsigned int cpu) | |
854 | { | |
855 | unsigned int cpu_bit; | |
856 | ||
857 | if (cpu >= NR_GIC_CPU_IF) | |
858 | return -1; | |
859 | cpu_bit = gic_cpu_map[cpu]; | |
860 | if (cpu_bit & (cpu_bit - 1)) | |
861 | return -1; | |
862 | return __ffs(cpu_bit); | |
863 | } | |
864 | ||
1a6b69b6 NP |
865 | /* |
866 | * gic_migrate_target - migrate IRQs to another CPU interface | |
867 | * | |
868 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
869 | * | |
870 | * Migrate all peripheral interrupts with a target matching the current CPU | |
871 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
872 | * is also updated. Targets to other CPU interfaces are unchanged. | |
873 | * This must be called with IRQs locally disabled. | |
874 | */ | |
875 | void gic_migrate_target(unsigned int new_cpu_id) | |
876 | { | |
877 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
878 | void __iomem *dist_base; | |
879 | int i, ror_val, cpu = smp_processor_id(); | |
880 | u32 val, cur_target_mask, active_mask; | |
881 | ||
a27d21e0 | 882 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
1a6b69b6 NP |
883 | |
884 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
885 | if (!dist_base) | |
886 | return; | |
887 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
888 | ||
889 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
890 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
891 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
892 | ||
04c8b0f8 | 893 | gic_lock(); |
1a6b69b6 NP |
894 | |
895 | /* Update the target interface for this logical CPU */ | |
896 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
897 | ||
898 | /* | |
c5f48c0a | 899 | * Find all the peripheral interrupts targeting the current |
1a6b69b6 NP |
900 | * CPU interface and migrate them to the new CPU interface. |
901 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
902 | */ | |
903 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
904 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
905 | active_mask = val & cur_target_mask; | |
906 | if (active_mask) { | |
907 | val &= ~active_mask; | |
908 | val |= ror32(active_mask, ror_val); | |
909 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
910 | } | |
911 | } | |
912 | ||
04c8b0f8 | 913 | gic_unlock(); |
1a6b69b6 NP |
914 | |
915 | /* | |
916 | * Now let's migrate and clear any potential SGIs that might be | |
917 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
918 | * is a banked register, we can only forward the SGI using | |
919 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
920 | * doesn't use that information anyway. | |
921 | * | |
922 | * For the same reason we do not adjust SGI source information | |
923 | * for previously sent SGIs by us to other CPUs either. | |
924 | */ | |
925 | for (i = 0; i < 16; i += 4) { | |
926 | int j; | |
927 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
928 | if (!val) | |
929 | continue; | |
930 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
931 | for (j = i; j < i + 4; j++) { | |
932 | if (val & 0xff) | |
933 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
934 | dist_base + GIC_DIST_SOFTINT); | |
935 | val >>= 8; | |
936 | } | |
937 | } | |
b1cffebf | 938 | } |
eeb44658 NP |
939 | |
940 | /* | |
941 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
942 | * | |
943 | * REturn the physical address of the SGI register to be used | |
944 | * by some early assembly code when the kernel is not yet available. | |
945 | */ | |
946 | static unsigned long gic_dist_physaddr; | |
947 | ||
948 | unsigned long gic_get_sgir_physaddr(void) | |
949 | { | |
950 | if (!gic_dist_physaddr) | |
951 | return 0; | |
952 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
953 | } | |
954 | ||
89c59cca | 955 | static void __init gic_init_physaddr(struct device_node *node) |
eeb44658 NP |
956 | { |
957 | struct resource res; | |
958 | if (of_address_to_resource(node, 0, &res) == 0) { | |
959 | gic_dist_physaddr = res.start; | |
960 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
961 | } | |
962 | } | |
963 | ||
964 | #else | |
965 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
966 | #endif |
967 | ||
75294957 GL |
968 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
969 | irq_hw_number_t hw) | |
970 | { | |
58b89649 | 971 | struct gic_chip_data *gic = d->host_data; |
0b996fd3 | 972 | |
75294957 GL |
973 | if (hw < 32) { |
974 | irq_set_percpu_devid(irq); | |
58b89649 | 975 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 976 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 977 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 978 | } else { |
58b89649 | 979 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
9a1091ef | 980 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 981 | irq_set_probe(irq); |
0c9e4982 | 982 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); |
75294957 | 983 | } |
75294957 GL |
984 | return 0; |
985 | } | |
986 | ||
006e983b S |
987 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
988 | { | |
006e983b S |
989 | } |
990 | ||
f833f57f MZ |
991 | static int gic_irq_domain_translate(struct irq_domain *d, |
992 | struct irq_fwspec *fwspec, | |
993 | unsigned long *hwirq, | |
994 | unsigned int *type) | |
995 | { | |
996 | if (is_of_node(fwspec->fwnode)) { | |
997 | if (fwspec->param_count < 3) | |
998 | return -EINVAL; | |
999 | ||
1000 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
1001 | *hwirq = fwspec->param[1] + 16; | |
1002 | ||
1003 | /* | |
1004 | * For SPIs, we need to add 16 more to get the GIC irq | |
1005 | * ID number | |
1006 | */ | |
1007 | if (!fwspec->param[0]) | |
1008 | *hwirq += 16; | |
1009 | ||
1010 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
83a86fbb MZ |
1011 | |
1012 | /* Make it clear that broken DTs are... broken */ | |
1013 | WARN_ON(*type == IRQ_TYPE_NONE); | |
f833f57f MZ |
1014 | return 0; |
1015 | } | |
1016 | ||
75aba7b0 | 1017 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
891ae769 MZ |
1018 | if(fwspec->param_count != 2) |
1019 | return -EINVAL; | |
1020 | ||
1021 | *hwirq = fwspec->param[0]; | |
1022 | *type = fwspec->param[1]; | |
83a86fbb MZ |
1023 | |
1024 | WARN_ON(*type == IRQ_TYPE_NONE); | |
891ae769 MZ |
1025 | return 0; |
1026 | } | |
1027 | ||
f833f57f MZ |
1028 | return -EINVAL; |
1029 | } | |
1030 | ||
93131f7a | 1031 | static int gic_starting_cpu(unsigned int cpu) |
c0114709 | 1032 | { |
93131f7a RC |
1033 | gic_cpu_init(&gic_data[0]); |
1034 | return 0; | |
c0114709 CM |
1035 | } |
1036 | ||
9a1091ef YC |
1037 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1038 | unsigned int nr_irqs, void *arg) | |
1039 | { | |
1040 | int i, ret; | |
1041 | irq_hw_number_t hwirq; | |
1042 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1043 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 1044 | |
f833f57f | 1045 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
1046 | if (ret) |
1047 | return ret; | |
1048 | ||
456c59c3 SP |
1049 | for (i = 0; i < nr_irqs; i++) { |
1050 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1051 | if (ret) | |
1052 | return ret; | |
1053 | } | |
9a1091ef YC |
1054 | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1059 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1060 | .alloc = gic_irq_domain_alloc, |
1061 | .free = irq_domain_free_irqs_top, | |
1062 | }; | |
1063 | ||
6859358e | 1064 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1065 | .map = gic_irq_domain_map, |
006e983b | 1066 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
1067 | }; |
1068 | ||
faea6455 JH |
1069 | static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, |
1070 | const char *name, bool use_eoimode1) | |
b580b899 | 1071 | { |
58b89649 | 1072 | /* Initialize irq_chip */ |
c2baa2f3 | 1073 | gic->chip = gic_chip; |
faea6455 JH |
1074 | gic->chip.name = name; |
1075 | gic->chip.parent_device = dev; | |
c2baa2f3 | 1076 | |
faea6455 | 1077 | if (use_eoimode1) { |
c2baa2f3 JH |
1078 | gic->chip.irq_mask = gic_eoimode1_mask_irq; |
1079 | gic->chip.irq_eoi = gic_eoimode1_eoi_irq; | |
1080 | gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; | |
58b89649 LW |
1081 | } |
1082 | ||
7bf29d3a | 1083 | #ifdef CONFIG_SMP |
f673b9b5 | 1084 | if (gic == &gic_data[0]) |
7bf29d3a JH |
1085 | gic->chip.irq_set_affinity = gic_set_affinity; |
1086 | #endif | |
faea6455 JH |
1087 | } |
1088 | ||
b41fdc4a | 1089 | static int gic_init_bases(struct gic_chip_data *gic, |
faea6455 JH |
1090 | struct fwnode_handle *handle) |
1091 | { | |
b41fdc4a | 1092 | int gic_irqs, ret; |
7bf29d3a | 1093 | |
f673b9b5 | 1094 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc | 1095 | /* Frankein-GIC without banked registers... */ |
db0d4db2 MZ |
1096 | unsigned int cpu; |
1097 | ||
1098 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1099 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1100 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1101 | !gic->cpu_base.percpu_base)) { | |
dc9722cc JH |
1102 | ret = -ENOMEM; |
1103 | goto error; | |
db0d4db2 MZ |
1104 | } |
1105 | ||
1106 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1107 | u32 mpidr = cpu_logical_map(cpu); |
1108 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
f673b9b5 JH |
1109 | unsigned long offset = gic->percpu_offset * core_id; |
1110 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = | |
1111 | gic->raw_dist_base + offset; | |
1112 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = | |
1113 | gic->raw_cpu_base + offset; | |
db0d4db2 MZ |
1114 | } |
1115 | ||
1116 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
dc9722cc JH |
1117 | } else { |
1118 | /* Normal, sane GIC... */ | |
f673b9b5 | 1119 | WARN(gic->percpu_offset, |
db0d4db2 | 1120 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
f673b9b5 JH |
1121 | gic->percpu_offset); |
1122 | gic->dist_base.common_base = gic->raw_dist_base; | |
1123 | gic->cpu_base.common_base = gic->raw_cpu_base; | |
db0d4db2 MZ |
1124 | gic_set_base_accessor(gic, gic_get_common_base); |
1125 | } | |
bef8f9ee | 1126 | |
4294f8ba RH |
1127 | /* |
1128 | * Find out how many interrupts are supported. | |
1129 | * The GIC only supports up to 1020 interrupt sources. | |
1130 | */ | |
db0d4db2 | 1131 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1132 | gic_irqs = (gic_irqs + 1) * 32; |
1133 | if (gic_irqs > 1020) | |
1134 | gic_irqs = 1020; | |
1135 | gic->gic_irqs = gic_irqs; | |
1136 | ||
891ae769 MZ |
1137 | if (handle) { /* DT/ACPI */ |
1138 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1139 | &gic_irq_domain_hierarchy_ops, | |
1140 | gic); | |
1141 | } else { /* Legacy support */ | |
9a1091ef YC |
1142 | /* |
1143 | * For primary GICs, skip over SGIs. | |
b41fdc4a | 1144 | * No secondary GIC support whatsoever. |
9a1091ef | 1145 | */ |
b41fdc4a | 1146 | int irq_base; |
9a1091ef | 1147 | |
b41fdc4a | 1148 | gic_irqs -= 16; /* calculate # of irqs to allocate */ |
006e983b | 1149 | |
b41fdc4a | 1150 | irq_base = irq_alloc_descs(16, 16, gic_irqs, |
006e983b | 1151 | numa_node_id()); |
287980e4 | 1152 | if (irq_base < 0) { |
b41fdc4a MZ |
1153 | WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); |
1154 | irq_base = 16; | |
006e983b S |
1155 | } |
1156 | ||
891ae769 | 1157 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
b41fdc4a | 1158 | 16, &gic_irq_domain_ops, gic); |
f37a53cc | 1159 | } |
006e983b | 1160 | |
dc9722cc JH |
1161 | if (WARN_ON(!gic->domain)) { |
1162 | ret = -ENODEV; | |
1163 | goto error; | |
1164 | } | |
bef8f9ee | 1165 | |
4294f8ba | 1166 | gic_dist_init(gic); |
dc9722cc JH |
1167 | ret = gic_cpu_init(gic); |
1168 | if (ret) | |
1169 | goto error; | |
1170 | ||
1171 | ret = gic_pm_init(gic); | |
1172 | if (ret) | |
1173 | goto error; | |
1174 | ||
1175 | return 0; | |
1176 | ||
1177 | error: | |
f673b9b5 | 1178 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
dc9722cc JH |
1179 | free_percpu(gic->dist_base.percpu_base); |
1180 | free_percpu(gic->cpu_base.percpu_base); | |
1181 | } | |
1182 | ||
dc9722cc | 1183 | return ret; |
b580b899 RK |
1184 | } |
1185 | ||
d6ce564c | 1186 | static int __init __gic_init_bases(struct gic_chip_data *gic, |
d6ce564c JH |
1187 | struct fwnode_handle *handle) |
1188 | { | |
faea6455 JH |
1189 | char *name; |
1190 | int i, ret; | |
d6ce564c JH |
1191 | |
1192 | if (WARN_ON(!gic || gic->domain)) | |
1193 | return -EINVAL; | |
1194 | ||
1195 | if (gic == &gic_data[0]) { | |
1196 | /* | |
1197 | * Initialize the CPU interface map to all CPUs. | |
1198 | * It will be refined as each CPU probes its ID. | |
1199 | * This is only necessary for the primary GIC. | |
1200 | */ | |
1201 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1202 | gic_cpu_map[i] = 0xff; | |
1203 | #ifdef CONFIG_SMP | |
1204 | set_smp_cross_call(gic_raise_softirq); | |
d6ce564c | 1205 | #endif |
93131f7a | 1206 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e | 1207 | "irqchip/arm/gic:starting", |
93131f7a | 1208 | gic_starting_cpu, NULL); |
d6ce564c | 1209 | set_handle_irq(gic_handle_irq); |
d01d3274 | 1210 | if (static_branch_likely(&supports_deactivate_key)) |
d6ce564c JH |
1211 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
1212 | } | |
1213 | ||
d01d3274 | 1214 | if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { |
faea6455 JH |
1215 | name = kasprintf(GFP_KERNEL, "GICv2"); |
1216 | gic_init_chip(gic, NULL, name, true); | |
1217 | } else { | |
1218 | name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); | |
1219 | gic_init_chip(gic, NULL, name, false); | |
1220 | } | |
1221 | ||
b41fdc4a | 1222 | ret = gic_init_bases(gic, handle); |
faea6455 JH |
1223 | if (ret) |
1224 | kfree(name); | |
1225 | ||
1226 | return ret; | |
d6ce564c JH |
1227 | } |
1228 | ||
b41fdc4a | 1229 | void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) |
4a6ac304 | 1230 | { |
f673b9b5 JH |
1231 | struct gic_chip_data *gic; |
1232 | ||
4a6ac304 MZ |
1233 | /* |
1234 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1235 | * bother with these... | |
1236 | */ | |
d01d3274 | 1237 | static_branch_disable(&supports_deactivate_key); |
f673b9b5 | 1238 | |
b41fdc4a | 1239 | gic = &gic_data[0]; |
f673b9b5 JH |
1240 | gic->raw_dist_base = dist_base; |
1241 | gic->raw_cpu_base = cpu_base; | |
1242 | ||
b41fdc4a | 1243 | __gic_init_bases(gic, NULL); |
4a6ac304 MZ |
1244 | } |
1245 | ||
d6490461 JH |
1246 | static void gic_teardown(struct gic_chip_data *gic) |
1247 | { | |
1248 | if (WARN_ON(!gic)) | |
1249 | return; | |
1250 | ||
1251 | if (gic->raw_dist_base) | |
1252 | iounmap(gic->raw_dist_base); | |
1253 | if (gic->raw_cpu_base) | |
1254 | iounmap(gic->raw_cpu_base); | |
4a6ac304 MZ |
1255 | } |
1256 | ||
b3f7ed03 | 1257 | #ifdef CONFIG_OF |
46f101df | 1258 | static int gic_cnt __initdata; |
0962289b MZ |
1259 | static bool gicv2_force_probe; |
1260 | ||
1261 | static int __init gicv2_force_probe_cfg(char *buf) | |
1262 | { | |
1263 | return strtobool(buf, &gicv2_force_probe); | |
1264 | } | |
1265 | early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); | |
1266 | ||
12e14066 MZ |
1267 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1268 | { | |
1269 | struct resource cpuif_res; | |
1270 | ||
1271 | of_address_to_resource(node, 1, &cpuif_res); | |
1272 | ||
1273 | if (!is_hyp_mode_available()) | |
1274 | return false; | |
0962289b MZ |
1275 | if (resource_size(&cpuif_res) < SZ_8K) { |
1276 | void __iomem *alt; | |
1277 | /* | |
1278 | * Check for a stupid firmware that only exposes the | |
1279 | * first page of a GICv2. | |
1280 | */ | |
1281 | if (!gic_check_gicv2(*base)) | |
1282 | return false; | |
1283 | ||
1284 | if (!gicv2_force_probe) { | |
1285 | pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); | |
1286 | return false; | |
1287 | } | |
1288 | ||
1289 | alt = ioremap(cpuif_res.start, SZ_8K); | |
1290 | if (!alt) | |
1291 | return false; | |
1292 | if (!gic_check_gicv2(alt + SZ_4K)) { | |
1293 | /* | |
1294 | * The first page was that of a GICv2, and | |
1295 | * the second was *something*. Let's trust it | |
1296 | * to be a GICv2, and update the mapping. | |
1297 | */ | |
1298 | pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", | |
1299 | &cpuif_res.start); | |
1300 | iounmap(*base); | |
1301 | *base = alt; | |
1302 | return true; | |
1303 | } | |
12e14066 MZ |
1304 | |
1305 | /* | |
0962289b MZ |
1306 | * We detected *two* initial GICv2 pages in a |
1307 | * row. Could be a GICv2 aliased over two 64kB | |
1308 | * pages. Update the resource, map the iospace, and | |
1309 | * pray. | |
1310 | */ | |
1311 | iounmap(alt); | |
1312 | alt = ioremap(cpuif_res.start, SZ_128K); | |
1313 | if (!alt) | |
1314 | return false; | |
1315 | pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", | |
1316 | &cpuif_res.start); | |
1317 | cpuif_res.end = cpuif_res.start + SZ_128K -1; | |
1318 | iounmap(*base); | |
1319 | *base = alt; | |
1320 | } | |
1321 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1322 | /* | |
1323 | * Verify that we have the first 4kB of a GICv2 | |
12e14066 MZ |
1324 | * aliased over the first 64kB by checking the |
1325 | * GICC_IIDR register on both ends. | |
1326 | */ | |
0962289b MZ |
1327 | if (!gic_check_gicv2(*base) || |
1328 | !gic_check_gicv2(*base + 0xf000)) | |
12e14066 MZ |
1329 | return false; |
1330 | ||
1331 | /* | |
1332 | * Move the base up by 60kB, so that we have a 8kB | |
1333 | * contiguous region, which allows us to use GICC_DIR | |
1334 | * at its normal offset. Please pass me that bucket. | |
1335 | */ | |
1336 | *base += 0xf000; | |
1337 | cpuif_res.start += 0xf000; | |
fd5bed48 | 1338 | pr_warn("GIC: Adjusting CPU interface base to %pa\n", |
12e14066 MZ |
1339 | &cpuif_res.start); |
1340 | } | |
1341 | ||
1342 | return true; | |
1343 | } | |
1344 | ||
9c8edddf | 1345 | static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) |
d6490461 JH |
1346 | { |
1347 | if (!gic || !node) | |
1348 | return -EINVAL; | |
1349 | ||
1350 | gic->raw_dist_base = of_iomap(node, 0); | |
1351 | if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) | |
1352 | goto error; | |
1353 | ||
1354 | gic->raw_cpu_base = of_iomap(node, 1); | |
1355 | if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) | |
1356 | goto error; | |
1357 | ||
1358 | if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) | |
1359 | gic->percpu_offset = 0; | |
1360 | ||
1361 | return 0; | |
1362 | ||
1363 | error: | |
1364 | gic_teardown(gic); | |
1365 | ||
1366 | return -ENOMEM; | |
1367 | } | |
1368 | ||
9c8edddf JH |
1369 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) |
1370 | { | |
1371 | int ret; | |
1372 | ||
1373 | if (!dev || !dev->of_node || !gic || !irq) | |
1374 | return -EINVAL; | |
1375 | ||
1376 | *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); | |
1377 | if (!*gic) | |
1378 | return -ENOMEM; | |
1379 | ||
1380 | gic_init_chip(*gic, dev, dev->of_node->name, false); | |
1381 | ||
1382 | ret = gic_of_setup(*gic, dev->of_node); | |
1383 | if (ret) | |
1384 | return ret; | |
1385 | ||
b41fdc4a | 1386 | ret = gic_init_bases(*gic, &dev->of_node->fwnode); |
9c8edddf JH |
1387 | if (ret) { |
1388 | gic_teardown(*gic); | |
1389 | return ret; | |
1390 | } | |
1391 | ||
1392 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
502d6df1 JG |
1397 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1398 | { | |
1399 | int ret; | |
1400 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; | |
1401 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; | |
1402 | ||
1403 | gic_v2_kvm_info.type = GIC_V2; | |
1404 | ||
1405 | gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1406 | if (!gic_v2_kvm_info.maint_irq) | |
1407 | return; | |
1408 | ||
1409 | ret = of_address_to_resource(node, 2, vctrl_res); | |
1410 | if (ret) | |
1411 | return; | |
1412 | ||
1413 | ret = of_address_to_resource(node, 3, vcpu_res); | |
1414 | if (ret) | |
1415 | return; | |
1416 | ||
d01d3274 | 1417 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1418 | gic_set_kvm_info(&gic_v2_kvm_info); |
502d6df1 JG |
1419 | } |
1420 | ||
8673c1d7 | 1421 | int __init |
6859358e | 1422 | gic_of_init(struct device_node *node, struct device_node *parent) |
b3f7ed03 | 1423 | { |
f673b9b5 | 1424 | struct gic_chip_data *gic; |
dc9722cc | 1425 | int irq, ret; |
b3f7ed03 RH |
1426 | |
1427 | if (WARN_ON(!node)) | |
1428 | return -ENODEV; | |
1429 | ||
f673b9b5 JH |
1430 | if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) |
1431 | return -EINVAL; | |
1432 | ||
1433 | gic = &gic_data[gic_cnt]; | |
b3f7ed03 | 1434 | |
d6490461 JH |
1435 | ret = gic_of_setup(gic, node); |
1436 | if (ret) | |
1437 | return ret; | |
b3f7ed03 | 1438 | |
0b996fd3 MZ |
1439 | /* |
1440 | * Disable split EOI/Deactivate if either HYP is not available | |
1441 | * or the CPU interface is too small. | |
1442 | */ | |
f673b9b5 | 1443 | if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) |
d01d3274 | 1444 | static_branch_disable(&supports_deactivate_key); |
0b996fd3 | 1445 | |
b41fdc4a | 1446 | ret = __gic_init_bases(gic, &node->fwnode); |
dc9722cc | 1447 | if (ret) { |
d6490461 | 1448 | gic_teardown(gic); |
dc9722cc JH |
1449 | return ret; |
1450 | } | |
db0d4db2 | 1451 | |
502d6df1 | 1452 | if (!gic_cnt) { |
eeb44658 | 1453 | gic_init_physaddr(node); |
502d6df1 JG |
1454 | gic_of_setup_kvm_info(node); |
1455 | } | |
b3f7ed03 RH |
1456 | |
1457 | if (parent) { | |
1458 | irq = irq_of_parse_and_map(node, 0); | |
1459 | gic_cascade_irq(gic_cnt, irq); | |
1460 | } | |
853a33ce SS |
1461 | |
1462 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
0644b3da | 1463 | gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); |
853a33ce | 1464 | |
b3f7ed03 RH |
1465 | gic_cnt++; |
1466 | return 0; | |
1467 | } | |
144cb088 | 1468 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1469 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1470 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1471 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1472 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1473 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1474 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1475 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1476 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
9c8edddf JH |
1477 | #else |
1478 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) | |
1479 | { | |
1480 | return -ENOTSUPP; | |
1481 | } | |
b3f7ed03 | 1482 | #endif |
d60fc389 TN |
1483 | |
1484 | #ifdef CONFIG_ACPI | |
bafa9193 JG |
1485 | static struct |
1486 | { | |
1487 | phys_addr_t cpu_phys_base; | |
502d6df1 JG |
1488 | u32 maint_irq; |
1489 | int maint_irq_mode; | |
1490 | phys_addr_t vctrl_base; | |
1491 | phys_addr_t vcpu_base; | |
bafa9193 | 1492 | } acpi_data __initdata; |
d60fc389 TN |
1493 | |
1494 | static int __init | |
60574d1e | 1495 | gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, |
d60fc389 TN |
1496 | const unsigned long end) |
1497 | { | |
1498 | struct acpi_madt_generic_interrupt *processor; | |
1499 | phys_addr_t gic_cpu_base; | |
1500 | static int cpu_base_assigned; | |
1501 | ||
1502 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1503 | ||
99e3e3ae | 1504 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1505 | return -EINVAL; |
1506 | ||
1507 | /* | |
1508 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1509 | * All CPU interface addresses have to be the same. | |
1510 | */ | |
1511 | gic_cpu_base = processor->base_address; | |
bafa9193 | 1512 | if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) |
d60fc389 TN |
1513 | return -EINVAL; |
1514 | ||
bafa9193 | 1515 | acpi_data.cpu_phys_base = gic_cpu_base; |
502d6df1 JG |
1516 | acpi_data.maint_irq = processor->vgic_interrupt; |
1517 | acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1518 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1519 | acpi_data.vctrl_base = processor->gich_base_address; | |
1520 | acpi_data.vcpu_base = processor->gicv_base_address; | |
1521 | ||
d60fc389 TN |
1522 | cpu_base_assigned = 1; |
1523 | return 0; | |
1524 | } | |
1525 | ||
f26527b1 | 1526 | /* The things you have to do to just *count* something... */ |
60574d1e | 1527 | static int __init acpi_dummy_func(union acpi_subtable_headers *header, |
f26527b1 | 1528 | const unsigned long end) |
d60fc389 | 1529 | { |
f26527b1 MZ |
1530 | return 0; |
1531 | } | |
d60fc389 | 1532 | |
f26527b1 MZ |
1533 | static bool __init acpi_gic_redist_is_present(void) |
1534 | { | |
1535 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1536 | acpi_dummy_func, 0) > 0; | |
1537 | } | |
d60fc389 | 1538 | |
f26527b1 MZ |
1539 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1540 | struct acpi_probe_entry *ape) | |
1541 | { | |
1542 | struct acpi_madt_generic_distributor *dist; | |
1543 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1544 | |
f26527b1 MZ |
1545 | return (dist->version == ape->driver_data && |
1546 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1547 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1548 | } |
1549 | ||
f26527b1 MZ |
1550 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1551 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
502d6df1 JG |
1552 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1553 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1554 | ||
1555 | static void __init gic_acpi_setup_kvm_info(void) | |
1556 | { | |
1557 | int irq; | |
1558 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; | |
1559 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; | |
1560 | ||
1561 | gic_v2_kvm_info.type = GIC_V2; | |
1562 | ||
1563 | if (!acpi_data.vctrl_base) | |
1564 | return; | |
1565 | ||
1566 | vctrl_res->flags = IORESOURCE_MEM; | |
1567 | vctrl_res->start = acpi_data.vctrl_base; | |
1568 | vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; | |
1569 | ||
1570 | if (!acpi_data.vcpu_base) | |
1571 | return; | |
1572 | ||
1573 | vcpu_res->flags = IORESOURCE_MEM; | |
1574 | vcpu_res->start = acpi_data.vcpu_base; | |
1575 | vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1576 | ||
1577 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1578 | acpi_data.maint_irq_mode, | |
1579 | ACPI_ACTIVE_HIGH); | |
1580 | if (irq <= 0) | |
1581 | return; | |
1582 | ||
1583 | gic_v2_kvm_info.maint_irq = irq; | |
1584 | ||
1585 | gic_set_kvm_info(&gic_v2_kvm_info); | |
1586 | } | |
f26527b1 MZ |
1587 | |
1588 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1589 | const unsigned long end) | |
d60fc389 | 1590 | { |
f26527b1 | 1591 | struct acpi_madt_generic_distributor *dist; |
891ae769 | 1592 | struct fwnode_handle *domain_handle; |
f673b9b5 | 1593 | struct gic_chip_data *gic = &gic_data[0]; |
dc9722cc | 1594 | int count, ret; |
d60fc389 TN |
1595 | |
1596 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1597 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1598 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1599 | if (count <= 0) { |
1600 | pr_err("No valid GICC entries exist\n"); | |
1601 | return -EINVAL; | |
1602 | } | |
1603 | ||
7beaa24b | 1604 | gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
f673b9b5 | 1605 | if (!gic->raw_cpu_base) { |
d60fc389 TN |
1606 | pr_err("Unable to map GICC registers\n"); |
1607 | return -ENOMEM; | |
1608 | } | |
1609 | ||
f26527b1 | 1610 | dist = (struct acpi_madt_generic_distributor *)header; |
f673b9b5 JH |
1611 | gic->raw_dist_base = ioremap(dist->base_address, |
1612 | ACPI_GICV2_DIST_MEM_SIZE); | |
1613 | if (!gic->raw_dist_base) { | |
d60fc389 | 1614 | pr_err("Unable to map GICD registers\n"); |
d6490461 | 1615 | gic_teardown(gic); |
d60fc389 TN |
1616 | return -ENOMEM; |
1617 | } | |
1618 | ||
0b996fd3 MZ |
1619 | /* |
1620 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1621 | * guarantees that we'll always have a GICv2, so the CPU | |
1622 | * interface will always be the right size. | |
1623 | */ | |
1624 | if (!is_hyp_mode_available()) | |
d01d3274 | 1625 | static_branch_disable(&supports_deactivate_key); |
0b996fd3 | 1626 | |
d60fc389 | 1627 | /* |
891ae769 | 1628 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1629 | */ |
188a8471 | 1630 | domain_handle = irq_domain_alloc_fwnode(&dist->base_address); |
891ae769 MZ |
1631 | if (!domain_handle) { |
1632 | pr_err("Unable to allocate domain handle\n"); | |
d6490461 | 1633 | gic_teardown(gic); |
891ae769 MZ |
1634 | return -ENOMEM; |
1635 | } | |
1636 | ||
b41fdc4a | 1637 | ret = __gic_init_bases(gic, domain_handle); |
dc9722cc JH |
1638 | if (ret) { |
1639 | pr_err("Failed to initialise GIC\n"); | |
1640 | irq_domain_free_fwnode(domain_handle); | |
d6490461 | 1641 | gic_teardown(gic); |
dc9722cc JH |
1642 | return ret; |
1643 | } | |
d8f4f161 | 1644 | |
891ae769 | 1645 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
0644b3da SS |
1646 | |
1647 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1648 | gicv2m_init(NULL, gic_data[0].domain); | |
1649 | ||
d01d3274 | 1650 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1651 | gic_acpi_setup_kvm_info(); |
502d6df1 | 1652 | |
d60fc389 TN |
1653 | return 0; |
1654 | } | |
f26527b1 MZ |
1655 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1656 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1657 | gic_v2_acpi_init); | |
1658 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1659 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1660 | gic_v2_acpi_init); | |
d60fc389 | 1661 | #endif |