Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
0b996fd3 | 49 | #include <asm/virt.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
76e52dd0 MZ |
53 | #ifdef CONFIG_ARM64 |
54 | #include <asm/cpufeature.h> | |
55 | ||
56 | static void gic_check_cpu_features(void) | |
57 | { | |
58 | WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), | |
59 | TAINT_CPU_OUT_OF_SPEC, | |
60 | "GICv3 system registers enabled, broken firmware!\n"); | |
61 | } | |
62 | #else | |
63 | #define gic_check_cpu_features() do { } while(0) | |
64 | #endif | |
65 | ||
db0d4db2 MZ |
66 | union gic_base { |
67 | void __iomem *common_base; | |
6859358e | 68 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
69 | }; |
70 | ||
71 | struct gic_chip_data { | |
db0d4db2 MZ |
72 | union gic_base dist_base; |
73 | union gic_base cpu_base; | |
74 | #ifdef CONFIG_CPU_PM | |
75 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
76 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
77 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
78 | u32 __percpu *saved_ppi_enable; | |
79 | u32 __percpu *saved_ppi_conf; | |
80 | #endif | |
75294957 | 81 | struct irq_domain *domain; |
db0d4db2 MZ |
82 | unsigned int gic_irqs; |
83 | #ifdef CONFIG_GIC_NON_BANKED | |
84 | void __iomem *(*get_base)(union gic_base *); | |
85 | #endif | |
86 | }; | |
87 | ||
bd31b859 | 88 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 89 | |
384a2902 NP |
90 | /* |
91 | * The GIC mapping of CPU interfaces does not necessarily match | |
92 | * the logical CPU numbering. Let's use a mapping as returned | |
93 | * by the GIC itself. | |
94 | */ | |
95 | #define NR_GIC_CPU_IF 8 | |
96 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
97 | ||
0b996fd3 MZ |
98 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
99 | ||
b3a1bde4 CM |
100 | #ifndef MAX_GIC_NR |
101 | #define MAX_GIC_NR 1 | |
102 | #endif | |
103 | ||
bef8f9ee | 104 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 105 | |
db0d4db2 MZ |
106 | #ifdef CONFIG_GIC_NON_BANKED |
107 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
108 | { | |
513d1a28 | 109 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
110 | } |
111 | ||
112 | static void __iomem *gic_get_common_base(union gic_base *base) | |
113 | { | |
114 | return base->common_base; | |
115 | } | |
116 | ||
117 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
118 | { | |
119 | return data->get_base(&data->dist_base); | |
120 | } | |
121 | ||
122 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
123 | { | |
124 | return data->get_base(&data->cpu_base); | |
125 | } | |
126 | ||
127 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
128 | void __iomem *(*f)(union gic_base *)) | |
129 | { | |
130 | data->get_base = f; | |
131 | } | |
132 | #else | |
133 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
134 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 135 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
136 | #endif |
137 | ||
7d1f4288 | 138 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 139 | { |
7d1f4288 | 140 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 141 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
142 | } |
143 | ||
7d1f4288 | 144 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 145 | { |
7d1f4288 | 146 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 147 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
148 | } |
149 | ||
7d1f4288 | 150 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 151 | { |
4294f8ba | 152 | return d->hwirq; |
b3a1bde4 CM |
153 | } |
154 | ||
01f779f4 MZ |
155 | static inline bool cascading_gic_irq(struct irq_data *d) |
156 | { | |
157 | void *data = irq_data_get_irq_handler_data(d); | |
158 | ||
159 | /* | |
71466535 TG |
160 | * If handler_data is set, this is a cascading interrupt, and |
161 | * it cannot possibly be forwarded. | |
01f779f4 | 162 | */ |
71466535 | 163 | return data != NULL; |
01f779f4 MZ |
164 | } |
165 | ||
f27ecacc RK |
166 | /* |
167 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 168 | */ |
56717807 MZ |
169 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
170 | { | |
171 | u32 mask = 1 << (gic_irq(d) % 32); | |
172 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
173 | } | |
174 | ||
175 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 176 | { |
4294f8ba | 177 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
178 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
179 | } | |
180 | ||
181 | static void gic_mask_irq(struct irq_data *d) | |
182 | { | |
56717807 | 183 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
184 | } |
185 | ||
0b996fd3 MZ |
186 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
187 | { | |
188 | gic_mask_irq(d); | |
01f779f4 MZ |
189 | /* |
190 | * When masking a forwarded interrupt, make sure it is | |
191 | * deactivated as well. | |
192 | * | |
193 | * This ensures that an interrupt that is getting | |
194 | * disabled/masked will not get "stuck", because there is | |
195 | * noone to deactivate it (guest is being terminated). | |
196 | */ | |
71466535 | 197 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 198 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
199 | } |
200 | ||
7d1f4288 | 201 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 202 | { |
56717807 | 203 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
204 | } |
205 | ||
1a01753e WD |
206 | static void gic_eoi_irq(struct irq_data *d) |
207 | { | |
6ac77e46 | 208 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
209 | } |
210 | ||
0b996fd3 MZ |
211 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
212 | { | |
01f779f4 | 213 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 214 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
215 | return; |
216 | ||
0b996fd3 MZ |
217 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
218 | } | |
219 | ||
56717807 MZ |
220 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
221 | enum irqchip_irq_state which, bool val) | |
222 | { | |
223 | u32 reg; | |
224 | ||
225 | switch (which) { | |
226 | case IRQCHIP_STATE_PENDING: | |
227 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
228 | break; | |
229 | ||
230 | case IRQCHIP_STATE_ACTIVE: | |
231 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
232 | break; | |
233 | ||
234 | case IRQCHIP_STATE_MASKED: | |
235 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
236 | break; | |
237 | ||
238 | default: | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | gic_poke_irq(d, reg); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
247 | enum irqchip_irq_state which, bool *val) | |
248 | { | |
249 | switch (which) { | |
250 | case IRQCHIP_STATE_PENDING: | |
251 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
252 | break; | |
253 | ||
254 | case IRQCHIP_STATE_ACTIVE: | |
255 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
256 | break; | |
257 | ||
258 | case IRQCHIP_STATE_MASKED: | |
259 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
260 | break; | |
261 | ||
262 | default: | |
263 | return -EINVAL; | |
264 | } | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
7d1f4288 | 269 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 270 | { |
7d1f4288 LB |
271 | void __iomem *base = gic_dist_base(d); |
272 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
273 | |
274 | /* Interrupt configuration for SGIs can't be changed */ | |
275 | if (gicirq < 16) | |
276 | return -EINVAL; | |
277 | ||
fb7e7deb LD |
278 | /* SPIs have restrictions on the supported types */ |
279 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
280 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
281 | return -EINVAL; |
282 | ||
1dcc73d7 | 283 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
284 | } |
285 | ||
01f779f4 MZ |
286 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
287 | { | |
288 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
289 | if (cascading_gic_irq(d)) | |
290 | return -EINVAL; | |
291 | ||
71466535 TG |
292 | if (vcpu) |
293 | irqd_set_forwarded_to_vcpu(d); | |
294 | else | |
295 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
296 | return 0; |
297 | } | |
298 | ||
a06f5466 | 299 | #ifdef CONFIG_SMP |
c191789c RK |
300 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
301 | bool force) | |
f27ecacc | 302 | { |
7d1f4288 | 303 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 304 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 305 | u32 val, mask, bit; |
cf613871 | 306 | unsigned long flags; |
f27ecacc | 307 | |
ffde1de6 TG |
308 | if (!force) |
309 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
310 | else | |
311 | cpu = cpumask_first(mask_val); | |
312 | ||
384a2902 | 313 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 314 | return -EINVAL; |
c191789c | 315 | |
cf613871 | 316 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 317 | mask = 0xff << shift; |
384a2902 | 318 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
319 | val = readl_relaxed(reg) & ~mask; |
320 | writel_relaxed(val | bit, reg); | |
cf613871 | 321 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 322 | |
5dfc54e0 | 323 | return IRQ_SET_MASK_OK; |
f27ecacc | 324 | } |
a06f5466 | 325 | #endif |
f27ecacc | 326 | |
8783dd3a | 327 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
328 | { |
329 | u32 irqstat, irqnr; | |
330 | struct gic_chip_data *gic = &gic_data[0]; | |
331 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
332 | ||
333 | do { | |
334 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 335 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 MZ |
336 | |
337 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
0b996fd3 MZ |
338 | if (static_key_true(&supports_deactivate)) |
339 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 340 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
341 | continue; |
342 | } | |
343 | if (irqnr < 16) { | |
344 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
345 | if (static_key_true(&supports_deactivate)) |
346 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 MZ |
347 | #ifdef CONFIG_SMP |
348 | handle_IPI(irqnr, regs); | |
349 | #endif | |
350 | continue; | |
351 | } | |
352 | break; | |
353 | } while (1); | |
354 | } | |
355 | ||
bd0b9ac4 | 356 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 357 | { |
5b29264c JL |
358 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
359 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 360 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
361 | unsigned long status; |
362 | ||
1a01753e | 363 | chained_irq_enter(chip, desc); |
b3a1bde4 | 364 | |
bd31b859 | 365 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 366 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 367 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 368 | |
e5f81539 FK |
369 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
370 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 371 | goto out; |
b3a1bde4 | 372 | |
75294957 GL |
373 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
374 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 375 | handle_bad_irq(desc); |
0f347bb9 RK |
376 | else |
377 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
378 | |
379 | out: | |
1a01753e | 380 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
381 | } |
382 | ||
38c677cb | 383 | static struct irq_chip gic_chip = { |
7d1f4288 | 384 | .name = "GIC", |
7d1f4288 LB |
385 | .irq_mask = gic_mask_irq, |
386 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 387 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 388 | .irq_set_type = gic_set_type, |
f27ecacc | 389 | #ifdef CONFIG_SMP |
c191789c | 390 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 391 | #endif |
56717807 MZ |
392 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
393 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
394 | .flags = IRQCHIP_SET_TYPE_MASKED | |
395 | IRQCHIP_SKIP_SET_WAKE | | |
396 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
397 | }; |
398 | ||
0b996fd3 MZ |
399 | static struct irq_chip gic_eoimode1_chip = { |
400 | .name = "GICv2", | |
401 | .irq_mask = gic_eoimode1_mask_irq, | |
402 | .irq_unmask = gic_unmask_irq, | |
403 | .irq_eoi = gic_eoimode1_eoi_irq, | |
404 | .irq_set_type = gic_set_type, | |
405 | #ifdef CONFIG_SMP | |
406 | .irq_set_affinity = gic_set_affinity, | |
407 | #endif | |
408 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
409 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
01f779f4 | 410 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b996fd3 MZ |
411 | .flags = IRQCHIP_SET_TYPE_MASKED | |
412 | IRQCHIP_SKIP_SET_WAKE | | |
413 | IRQCHIP_MASK_ON_SUSPEND, | |
414 | }; | |
415 | ||
b3a1bde4 CM |
416 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
417 | { | |
418 | if (gic_nr >= MAX_GIC_NR) | |
419 | BUG(); | |
4d83fcf8 TG |
420 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
421 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
422 | } |
423 | ||
2bb31351 RK |
424 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
425 | { | |
426 | void __iomem *base = gic_data_dist_base(gic); | |
427 | u32 mask, i; | |
428 | ||
429 | for (i = mask = 0; i < 32; i += 4) { | |
430 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
431 | mask |= mask >> 16; | |
432 | mask |= mask >> 8; | |
433 | if (mask) | |
434 | break; | |
435 | } | |
436 | ||
6e3aca44 | 437 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
438 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
439 | ||
440 | return mask; | |
441 | } | |
442 | ||
4c2880b3 | 443 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 444 | { |
4c2880b3 | 445 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 446 | u32 bypass = 0; |
0b996fd3 MZ |
447 | u32 mode = 0; |
448 | ||
449 | if (static_key_true(&supports_deactivate)) | |
450 | mode = GIC_CPU_CTRL_EOImodeNS; | |
32289506 FK |
451 | |
452 | /* | |
453 | * Preserve bypass disable bits to be written back later | |
454 | */ | |
455 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
456 | bypass &= GICC_DIS_BYPASS_MASK; | |
457 | ||
0b996fd3 | 458 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
459 | } |
460 | ||
461 | ||
4294f8ba | 462 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 463 | { |
75294957 | 464 | unsigned int i; |
267840f3 | 465 | u32 cpumask; |
4294f8ba | 466 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 467 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 468 | |
e5f81539 | 469 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 470 | |
f27ecacc RK |
471 | /* |
472 | * Set all global interrupts to this CPU only. | |
473 | */ | |
2bb31351 RK |
474 | cpumask = gic_get_cpumask(gic); |
475 | cpumask |= cpumask << 8; | |
476 | cpumask |= cpumask << 16; | |
e6afec9b | 477 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 478 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 479 | |
d51d0af4 | 480 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 481 | |
e5f81539 | 482 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
483 | } |
484 | ||
8c37bb3a | 485 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 486 | { |
db0d4db2 MZ |
487 | void __iomem *dist_base = gic_data_dist_base(gic); |
488 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 489 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
490 | int i; |
491 | ||
384a2902 | 492 | /* |
567e5a01 JH |
493 | * Setting up the CPU map is only relevant for the primary GIC |
494 | * because any nested/secondary GICs do not directly interface | |
495 | * with the CPU(s). | |
384a2902 | 496 | */ |
567e5a01 JH |
497 | if (gic == &gic_data[0]) { |
498 | /* | |
499 | * Get what the GIC says our CPU mask is. | |
500 | */ | |
501 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
502 | cpu_mask = gic_get_cpumask(gic); | |
503 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 504 | |
567e5a01 JH |
505 | /* |
506 | * Clear our mask from the other map entries in case they're | |
507 | * still undefined. | |
508 | */ | |
509 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
510 | if (i != cpu) | |
511 | gic_cpu_map[i] &= ~cpu_mask; | |
512 | } | |
384a2902 | 513 | |
d51d0af4 | 514 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 515 | |
e5f81539 | 516 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 517 | gic_cpu_if_up(gic); |
f27ecacc RK |
518 | } |
519 | ||
4c2880b3 | 520 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 521 | { |
4c2880b3 | 522 | void __iomem *cpu_base; |
32289506 FK |
523 | u32 val = 0; |
524 | ||
4c2880b3 JH |
525 | if (gic_nr >= MAX_GIC_NR) |
526 | return -EINVAL; | |
527 | ||
528 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
529 | val = readl(cpu_base + GIC_CPU_CTRL); |
530 | val &= ~GICC_ENABLE; | |
531 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
532 | |
533 | return 0; | |
10d9eb8a NP |
534 | } |
535 | ||
254056f3 CC |
536 | #ifdef CONFIG_CPU_PM |
537 | /* | |
538 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
539 | * with interrupts disabled but before powering down the GIC. After calling | |
540 | * this function, no interrupts will be delivered by the GIC, and another | |
541 | * platform-specific wakeup source must be enabled. | |
542 | */ | |
543 | static void gic_dist_save(unsigned int gic_nr) | |
544 | { | |
545 | unsigned int gic_irqs; | |
546 | void __iomem *dist_base; | |
547 | int i; | |
548 | ||
549 | if (gic_nr >= MAX_GIC_NR) | |
550 | BUG(); | |
551 | ||
552 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 553 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
554 | |
555 | if (!dist_base) | |
556 | return; | |
557 | ||
558 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
559 | gic_data[gic_nr].saved_spi_conf[i] = | |
560 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
561 | ||
562 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
563 | gic_data[gic_nr].saved_spi_target[i] = | |
564 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
565 | ||
566 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
567 | gic_data[gic_nr].saved_spi_enable[i] = | |
568 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
569 | } | |
570 | ||
571 | /* | |
572 | * Restores the GIC distributor registers during resume or when coming out of | |
573 | * idle. Must be called before enabling interrupts. If a level interrupt | |
574 | * that occured while the GIC was suspended is still present, it will be | |
575 | * handled normally, but any edge interrupts that occured will not be seen by | |
576 | * the GIC and need to be handled by the platform-specific wakeup source. | |
577 | */ | |
578 | static void gic_dist_restore(unsigned int gic_nr) | |
579 | { | |
580 | unsigned int gic_irqs; | |
581 | unsigned int i; | |
582 | void __iomem *dist_base; | |
583 | ||
584 | if (gic_nr >= MAX_GIC_NR) | |
585 | BUG(); | |
586 | ||
587 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 588 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
589 | |
590 | if (!dist_base) | |
591 | return; | |
592 | ||
e5f81539 | 593 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
594 | |
595 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
596 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
597 | dist_base + GIC_DIST_CONFIG + i * 4); | |
598 | ||
599 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 600 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
601 | dist_base + GIC_DIST_PRI + i * 4); |
602 | ||
603 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
604 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
605 | dist_base + GIC_DIST_TARGET + i * 4); | |
606 | ||
607 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
608 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
609 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
610 | ||
e5f81539 | 611 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
612 | } |
613 | ||
614 | static void gic_cpu_save(unsigned int gic_nr) | |
615 | { | |
616 | int i; | |
617 | u32 *ptr; | |
618 | void __iomem *dist_base; | |
619 | void __iomem *cpu_base; | |
620 | ||
621 | if (gic_nr >= MAX_GIC_NR) | |
622 | BUG(); | |
623 | ||
db0d4db2 MZ |
624 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
625 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
626 | |
627 | if (!dist_base || !cpu_base) | |
628 | return; | |
629 | ||
532d0d06 | 630 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
631 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
632 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
633 | ||
532d0d06 | 634 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
635 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
636 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
637 | ||
638 | } | |
639 | ||
640 | static void gic_cpu_restore(unsigned int gic_nr) | |
641 | { | |
642 | int i; | |
643 | u32 *ptr; | |
644 | void __iomem *dist_base; | |
645 | void __iomem *cpu_base; | |
646 | ||
647 | if (gic_nr >= MAX_GIC_NR) | |
648 | BUG(); | |
649 | ||
db0d4db2 MZ |
650 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
651 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
652 | |
653 | if (!dist_base || !cpu_base) | |
654 | return; | |
655 | ||
532d0d06 | 656 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
657 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
658 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
659 | ||
532d0d06 | 660 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
661 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
662 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
663 | ||
664 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
665 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
666 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 667 | |
e5f81539 | 668 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
4c2880b3 | 669 | gic_cpu_if_up(&gic_data[gic_nr]); |
254056f3 CC |
670 | } |
671 | ||
672 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
673 | { | |
674 | int i; | |
675 | ||
676 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
677 | #ifdef CONFIG_GIC_NON_BANKED |
678 | /* Skip over unused GICs */ | |
679 | if (!gic_data[i].get_base) | |
680 | continue; | |
681 | #endif | |
254056f3 CC |
682 | switch (cmd) { |
683 | case CPU_PM_ENTER: | |
684 | gic_cpu_save(i); | |
685 | break; | |
686 | case CPU_PM_ENTER_FAILED: | |
687 | case CPU_PM_EXIT: | |
688 | gic_cpu_restore(i); | |
689 | break; | |
690 | case CPU_CLUSTER_PM_ENTER: | |
691 | gic_dist_save(i); | |
692 | break; | |
693 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
694 | case CPU_CLUSTER_PM_EXIT: | |
695 | gic_dist_restore(i); | |
696 | break; | |
697 | } | |
698 | } | |
699 | ||
700 | return NOTIFY_OK; | |
701 | } | |
702 | ||
703 | static struct notifier_block gic_notifier_block = { | |
704 | .notifier_call = gic_notifier, | |
705 | }; | |
706 | ||
707 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
708 | { | |
709 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
710 | sizeof(u32)); | |
711 | BUG_ON(!gic->saved_ppi_enable); | |
712 | ||
713 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
714 | sizeof(u32)); | |
715 | BUG_ON(!gic->saved_ppi_conf); | |
716 | ||
abdd7b91 MZ |
717 | if (gic == &gic_data[0]) |
718 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
719 | } |
720 | #else | |
721 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
722 | { | |
723 | } | |
724 | #endif | |
725 | ||
b1cffebf | 726 | #ifdef CONFIG_SMP |
6859358e | 727 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
728 | { |
729 | int cpu; | |
1a6b69b6 NP |
730 | unsigned long flags, map = 0; |
731 | ||
732 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
733 | |
734 | /* Convert our logical CPU mask into a physical one. */ | |
735 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 736 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
737 | |
738 | /* | |
739 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 740 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 741 | */ |
8adbf57f | 742 | dmb(ishst); |
b1cffebf RH |
743 | |
744 | /* this always happens on GIC0 */ | |
745 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
746 | |
747 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
748 | } | |
749 | #endif | |
750 | ||
751 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
752 | /* |
753 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
754 | * | |
755 | * cpu_id: the ID for the destination CPU interface | |
756 | * irq: the IPI number to send a SGI for | |
757 | */ | |
758 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
759 | { | |
760 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
761 | cpu_id = 1 << cpu_id; | |
762 | /* this always happens on GIC0 */ | |
763 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
764 | } | |
765 | ||
ed96762e NP |
766 | /* |
767 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
768 | * | |
769 | * @cpu: the logical CPU number to get the GIC ID for. | |
770 | * | |
771 | * Return the CPU interface ID for the given logical CPU number, | |
772 | * or -1 if the CPU number is too large or the interface ID is | |
773 | * unknown (more than one bit set). | |
774 | */ | |
775 | int gic_get_cpu_id(unsigned int cpu) | |
776 | { | |
777 | unsigned int cpu_bit; | |
778 | ||
779 | if (cpu >= NR_GIC_CPU_IF) | |
780 | return -1; | |
781 | cpu_bit = gic_cpu_map[cpu]; | |
782 | if (cpu_bit & (cpu_bit - 1)) | |
783 | return -1; | |
784 | return __ffs(cpu_bit); | |
785 | } | |
786 | ||
1a6b69b6 NP |
787 | /* |
788 | * gic_migrate_target - migrate IRQs to another CPU interface | |
789 | * | |
790 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
791 | * | |
792 | * Migrate all peripheral interrupts with a target matching the current CPU | |
793 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
794 | * is also updated. Targets to other CPU interfaces are unchanged. | |
795 | * This must be called with IRQs locally disabled. | |
796 | */ | |
797 | void gic_migrate_target(unsigned int new_cpu_id) | |
798 | { | |
799 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
800 | void __iomem *dist_base; | |
801 | int i, ror_val, cpu = smp_processor_id(); | |
802 | u32 val, cur_target_mask, active_mask; | |
803 | ||
804 | if (gic_nr >= MAX_GIC_NR) | |
805 | BUG(); | |
806 | ||
807 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
808 | if (!dist_base) | |
809 | return; | |
810 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
811 | ||
812 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
813 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
814 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
815 | ||
816 | raw_spin_lock(&irq_controller_lock); | |
817 | ||
818 | /* Update the target interface for this logical CPU */ | |
819 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
820 | ||
821 | /* | |
822 | * Find all the peripheral interrupts targetting the current | |
823 | * CPU interface and migrate them to the new CPU interface. | |
824 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
825 | */ | |
826 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
827 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
828 | active_mask = val & cur_target_mask; | |
829 | if (active_mask) { | |
830 | val &= ~active_mask; | |
831 | val |= ror32(active_mask, ror_val); | |
832 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
833 | } | |
834 | } | |
835 | ||
836 | raw_spin_unlock(&irq_controller_lock); | |
837 | ||
838 | /* | |
839 | * Now let's migrate and clear any potential SGIs that might be | |
840 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
841 | * is a banked register, we can only forward the SGI using | |
842 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
843 | * doesn't use that information anyway. | |
844 | * | |
845 | * For the same reason we do not adjust SGI source information | |
846 | * for previously sent SGIs by us to other CPUs either. | |
847 | */ | |
848 | for (i = 0; i < 16; i += 4) { | |
849 | int j; | |
850 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
851 | if (!val) | |
852 | continue; | |
853 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
854 | for (j = i; j < i + 4; j++) { | |
855 | if (val & 0xff) | |
856 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
857 | dist_base + GIC_DIST_SOFTINT); | |
858 | val >>= 8; | |
859 | } | |
860 | } | |
b1cffebf | 861 | } |
eeb44658 NP |
862 | |
863 | /* | |
864 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
865 | * | |
866 | * REturn the physical address of the SGI register to be used | |
867 | * by some early assembly code when the kernel is not yet available. | |
868 | */ | |
869 | static unsigned long gic_dist_physaddr; | |
870 | ||
871 | unsigned long gic_get_sgir_physaddr(void) | |
872 | { | |
873 | if (!gic_dist_physaddr) | |
874 | return 0; | |
875 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
876 | } | |
877 | ||
878 | void __init gic_init_physaddr(struct device_node *node) | |
879 | { | |
880 | struct resource res; | |
881 | if (of_address_to_resource(node, 0, &res) == 0) { | |
882 | gic_dist_physaddr = res.start; | |
883 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
884 | } | |
885 | } | |
886 | ||
887 | #else | |
888 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
889 | #endif |
890 | ||
75294957 GL |
891 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
892 | irq_hw_number_t hw) | |
893 | { | |
0b996fd3 MZ |
894 | struct irq_chip *chip = &gic_chip; |
895 | ||
896 | if (static_key_true(&supports_deactivate)) { | |
897 | if (d->host_data == (void *)&gic_data[0]) | |
898 | chip = &gic_eoimode1_chip; | |
899 | } | |
900 | ||
75294957 GL |
901 | if (hw < 32) { |
902 | irq_set_percpu_devid(irq); | |
0b996fd3 | 903 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 904 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 905 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 906 | } else { |
0b996fd3 | 907 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 908 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 909 | irq_set_probe(irq); |
75294957 | 910 | } |
75294957 GL |
911 | return 0; |
912 | } | |
913 | ||
006e983b S |
914 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
915 | { | |
006e983b S |
916 | } |
917 | ||
f833f57f MZ |
918 | static int gic_irq_domain_translate(struct irq_domain *d, |
919 | struct irq_fwspec *fwspec, | |
920 | unsigned long *hwirq, | |
921 | unsigned int *type) | |
922 | { | |
923 | if (is_of_node(fwspec->fwnode)) { | |
924 | if (fwspec->param_count < 3) | |
925 | return -EINVAL; | |
926 | ||
927 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
928 | *hwirq = fwspec->param[1] + 16; | |
929 | ||
930 | /* | |
931 | * For SPIs, we need to add 16 more to get the GIC irq | |
932 | * ID number | |
933 | */ | |
934 | if (!fwspec->param[0]) | |
935 | *hwirq += 16; | |
936 | ||
937 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
938 | return 0; | |
939 | } | |
940 | ||
891ae769 MZ |
941 | if (fwspec->fwnode->type == FWNODE_IRQCHIP) { |
942 | if(fwspec->param_count != 2) | |
943 | return -EINVAL; | |
944 | ||
945 | *hwirq = fwspec->param[0]; | |
946 | *type = fwspec->param[1]; | |
947 | return 0; | |
948 | } | |
949 | ||
f833f57f MZ |
950 | return -EINVAL; |
951 | } | |
952 | ||
c0114709 | 953 | #ifdef CONFIG_SMP |
8c37bb3a PG |
954 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
955 | void *hcpu) | |
c0114709 | 956 | { |
8b6fd652 | 957 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
958 | gic_cpu_init(&gic_data[0]); |
959 | return NOTIFY_OK; | |
960 | } | |
961 | ||
962 | /* | |
963 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
964 | * priority because the GIC needs to be up before the ARM generic timers. | |
965 | */ | |
8c37bb3a | 966 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
967 | .notifier_call = gic_secondary_init, |
968 | .priority = 100, | |
969 | }; | |
970 | #endif | |
971 | ||
9a1091ef YC |
972 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
973 | unsigned int nr_irqs, void *arg) | |
974 | { | |
975 | int i, ret; | |
976 | irq_hw_number_t hwirq; | |
977 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 978 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 979 | |
f833f57f | 980 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
981 | if (ret) |
982 | return ret; | |
983 | ||
984 | for (i = 0; i < nr_irqs; i++) | |
985 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 991 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
992 | .alloc = gic_irq_domain_alloc, |
993 | .free = irq_domain_free_irqs_top, | |
994 | }; | |
995 | ||
6859358e | 996 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 997 | .map = gic_irq_domain_map, |
006e983b | 998 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
999 | }; |
1000 | ||
4a6ac304 | 1001 | static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, |
db0d4db2 | 1002 | void __iomem *dist_base, void __iomem *cpu_base, |
891ae769 | 1003 | u32 percpu_offset, struct fwnode_handle *handle) |
b580b899 | 1004 | { |
75294957 | 1005 | irq_hw_number_t hwirq_base; |
bef8f9ee | 1006 | struct gic_chip_data *gic; |
384a2902 | 1007 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
1008 | |
1009 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
1010 | ||
76e52dd0 MZ |
1011 | gic_check_cpu_features(); |
1012 | ||
bef8f9ee | 1013 | gic = &gic_data[gic_nr]; |
db0d4db2 MZ |
1014 | #ifdef CONFIG_GIC_NON_BANKED |
1015 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
1016 | unsigned int cpu; | |
1017 | ||
1018 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1019 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1020 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1021 | !gic->cpu_base.percpu_base)) { | |
1022 | free_percpu(gic->dist_base.percpu_base); | |
1023 | free_percpu(gic->cpu_base.percpu_base); | |
1024 | return; | |
1025 | } | |
1026 | ||
1027 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1028 | u32 mpidr = cpu_logical_map(cpu); |
1029 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
1030 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
1031 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
1032 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
1033 | } | |
1034 | ||
1035 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
1036 | } else | |
1037 | #endif | |
1038 | { /* Normal, sane GIC... */ | |
1039 | WARN(percpu_offset, | |
1040 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
1041 | percpu_offset); | |
1042 | gic->dist_base.common_base = dist_base; | |
1043 | gic->cpu_base.common_base = cpu_base; | |
1044 | gic_set_base_accessor(gic, gic_get_common_base); | |
1045 | } | |
bef8f9ee | 1046 | |
4294f8ba RH |
1047 | /* |
1048 | * Find out how many interrupts are supported. | |
1049 | * The GIC only supports up to 1020 interrupt sources. | |
1050 | */ | |
db0d4db2 | 1051 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1052 | gic_irqs = (gic_irqs + 1) * 32; |
1053 | if (gic_irqs > 1020) | |
1054 | gic_irqs = 1020; | |
1055 | gic->gic_irqs = gic_irqs; | |
1056 | ||
891ae769 MZ |
1057 | if (handle) { /* DT/ACPI */ |
1058 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1059 | &gic_irq_domain_hierarchy_ops, | |
1060 | gic); | |
1061 | } else { /* Legacy support */ | |
9a1091ef YC |
1062 | /* |
1063 | * For primary GICs, skip over SGIs. | |
1064 | * For secondary GICs, skip over PPIs, too. | |
1065 | */ | |
1066 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
1067 | hwirq_base = 16; | |
1068 | if (irq_start != -1) | |
1069 | irq_start = (irq_start & ~31) + 16; | |
1070 | } else { | |
1071 | hwirq_base = 32; | |
1072 | } | |
1073 | ||
1074 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1075 | |
006e983b S |
1076 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1077 | numa_node_id()); | |
1078 | if (IS_ERR_VALUE(irq_base)) { | |
1079 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1080 | irq_start); | |
1081 | irq_base = irq_start; | |
1082 | } | |
1083 | ||
891ae769 | 1084 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
006e983b | 1085 | hwirq_base, &gic_irq_domain_ops, gic); |
f37a53cc | 1086 | } |
006e983b | 1087 | |
75294957 GL |
1088 | if (WARN_ON(!gic->domain)) |
1089 | return; | |
bef8f9ee | 1090 | |
08332dff | 1091 | if (gic_nr == 0) { |
567e5a01 JH |
1092 | /* |
1093 | * Initialize the CPU interface map to all CPUs. | |
1094 | * It will be refined as each CPU probes its ID. | |
1095 | * This is only necessary for the primary GIC. | |
1096 | */ | |
1097 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1098 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 1099 | #ifdef CONFIG_SMP |
08332dff MR |
1100 | set_smp_cross_call(gic_raise_softirq); |
1101 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1102 | #endif |
08332dff | 1103 | set_handle_irq(gic_handle_irq); |
0b996fd3 MZ |
1104 | if (static_key_true(&supports_deactivate)) |
1105 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
08332dff | 1106 | } |
cfed7d60 | 1107 | |
4294f8ba | 1108 | gic_dist_init(gic); |
bef8f9ee | 1109 | gic_cpu_init(gic); |
254056f3 | 1110 | gic_pm_init(gic); |
b580b899 RK |
1111 | } |
1112 | ||
e81a7cd9 MZ |
1113 | void __init gic_init(unsigned int gic_nr, int irq_start, |
1114 | void __iomem *dist_base, void __iomem *cpu_base) | |
4a6ac304 MZ |
1115 | { |
1116 | /* | |
1117 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1118 | * bother with these... | |
1119 | */ | |
1120 | static_key_slow_dec(&supports_deactivate); | |
e81a7cd9 | 1121 | __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); |
4a6ac304 MZ |
1122 | } |
1123 | ||
b3f7ed03 | 1124 | #ifdef CONFIG_OF |
46f101df | 1125 | static int gic_cnt __initdata; |
b3f7ed03 | 1126 | |
12e14066 MZ |
1127 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1128 | { | |
1129 | struct resource cpuif_res; | |
1130 | ||
1131 | of_address_to_resource(node, 1, &cpuif_res); | |
1132 | ||
1133 | if (!is_hyp_mode_available()) | |
1134 | return false; | |
1135 | if (resource_size(&cpuif_res) < SZ_8K) | |
1136 | return false; | |
1137 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1138 | u32 val_low, val_high; | |
1139 | ||
1140 | /* | |
1141 | * Verify that we have the first 4kB of a GIC400 | |
1142 | * aliased over the first 64kB by checking the | |
1143 | * GICC_IIDR register on both ends. | |
1144 | */ | |
1145 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1146 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1147 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1148 | val_low != val_high) | |
1149 | return false; | |
1150 | ||
1151 | /* | |
1152 | * Move the base up by 60kB, so that we have a 8kB | |
1153 | * contiguous region, which allows us to use GICC_DIR | |
1154 | * at its normal offset. Please pass me that bucket. | |
1155 | */ | |
1156 | *base += 0xf000; | |
1157 | cpuif_res.start += 0xf000; | |
1158 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1159 | &cpuif_res.start); | |
1160 | } | |
1161 | ||
1162 | return true; | |
1163 | } | |
1164 | ||
6859358e SB |
1165 | static int __init |
1166 | gic_of_init(struct device_node *node, struct device_node *parent) | |
b3f7ed03 RH |
1167 | { |
1168 | void __iomem *cpu_base; | |
1169 | void __iomem *dist_base; | |
db0d4db2 | 1170 | u32 percpu_offset; |
b3f7ed03 | 1171 | int irq; |
b3f7ed03 RH |
1172 | |
1173 | if (WARN_ON(!node)) | |
1174 | return -ENODEV; | |
1175 | ||
1176 | dist_base = of_iomap(node, 0); | |
1177 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
1178 | ||
1179 | cpu_base = of_iomap(node, 1); | |
1180 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
1181 | ||
0b996fd3 MZ |
1182 | /* |
1183 | * Disable split EOI/Deactivate if either HYP is not available | |
1184 | * or the CPU interface is too small. | |
1185 | */ | |
12e14066 | 1186 | if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) |
0b996fd3 MZ |
1187 | static_key_slow_dec(&supports_deactivate); |
1188 | ||
db0d4db2 MZ |
1189 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1190 | percpu_offset = 0; | |
1191 | ||
891ae769 MZ |
1192 | __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, |
1193 | &node->fwnode); | |
eeb44658 NP |
1194 | if (!gic_cnt) |
1195 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1196 | |
1197 | if (parent) { | |
1198 | irq = irq_of_parse_and_map(node, 0); | |
1199 | gic_cascade_irq(gic_cnt, irq); | |
1200 | } | |
853a33ce SS |
1201 | |
1202 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1203 | gicv2m_of_init(node, gic_data[gic_cnt].domain); | |
1204 | ||
b3f7ed03 RH |
1205 | gic_cnt++; |
1206 | return 0; | |
1207 | } | |
144cb088 | 1208 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1209 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1210 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1211 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1212 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1213 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1214 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1215 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1216 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1217 | |
b3f7ed03 | 1218 | #endif |
d60fc389 TN |
1219 | |
1220 | #ifdef CONFIG_ACPI | |
f26527b1 | 1221 | static phys_addr_t cpu_phy_base __initdata; |
d60fc389 TN |
1222 | |
1223 | static int __init | |
1224 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1225 | const unsigned long end) | |
1226 | { | |
1227 | struct acpi_madt_generic_interrupt *processor; | |
1228 | phys_addr_t gic_cpu_base; | |
1229 | static int cpu_base_assigned; | |
1230 | ||
1231 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1232 | ||
99e3e3ae | 1233 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1234 | return -EINVAL; |
1235 | ||
1236 | /* | |
1237 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1238 | * All CPU interface addresses have to be the same. | |
1239 | */ | |
1240 | gic_cpu_base = processor->base_address; | |
1241 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1242 | return -EINVAL; | |
1243 | ||
1244 | cpu_phy_base = gic_cpu_base; | |
1245 | cpu_base_assigned = 1; | |
1246 | return 0; | |
1247 | } | |
1248 | ||
f26527b1 MZ |
1249 | /* The things you have to do to just *count* something... */ |
1250 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, | |
1251 | const unsigned long end) | |
d60fc389 | 1252 | { |
f26527b1 MZ |
1253 | return 0; |
1254 | } | |
d60fc389 | 1255 | |
f26527b1 MZ |
1256 | static bool __init acpi_gic_redist_is_present(void) |
1257 | { | |
1258 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1259 | acpi_dummy_func, 0) > 0; | |
1260 | } | |
d60fc389 | 1261 | |
f26527b1 MZ |
1262 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1263 | struct acpi_probe_entry *ape) | |
1264 | { | |
1265 | struct acpi_madt_generic_distributor *dist; | |
1266 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1267 | |
f26527b1 MZ |
1268 | return (dist->version == ape->driver_data && |
1269 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1270 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1271 | } |
1272 | ||
f26527b1 MZ |
1273 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1274 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
1275 | ||
1276 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1277 | const unsigned long end) | |
d60fc389 | 1278 | { |
f26527b1 | 1279 | struct acpi_madt_generic_distributor *dist; |
d60fc389 | 1280 | void __iomem *cpu_base, *dist_base; |
891ae769 | 1281 | struct fwnode_handle *domain_handle; |
d60fc389 TN |
1282 | int count; |
1283 | ||
1284 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1285 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1286 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1287 | if (count <= 0) { |
1288 | pr_err("No valid GICC entries exist\n"); | |
1289 | return -EINVAL; | |
1290 | } | |
1291 | ||
d60fc389 TN |
1292 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
1293 | if (!cpu_base) { | |
1294 | pr_err("Unable to map GICC registers\n"); | |
1295 | return -ENOMEM; | |
1296 | } | |
1297 | ||
f26527b1 MZ |
1298 | dist = (struct acpi_madt_generic_distributor *)header; |
1299 | dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE); | |
d60fc389 TN |
1300 | if (!dist_base) { |
1301 | pr_err("Unable to map GICD registers\n"); | |
1302 | iounmap(cpu_base); | |
1303 | return -ENOMEM; | |
1304 | } | |
1305 | ||
0b996fd3 MZ |
1306 | /* |
1307 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1308 | * guarantees that we'll always have a GICv2, so the CPU | |
1309 | * interface will always be the right size. | |
1310 | */ | |
1311 | if (!is_hyp_mode_available()) | |
1312 | static_key_slow_dec(&supports_deactivate); | |
1313 | ||
d60fc389 | 1314 | /* |
891ae769 | 1315 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1316 | */ |
891ae769 MZ |
1317 | domain_handle = irq_domain_alloc_fwnode(dist_base); |
1318 | if (!domain_handle) { | |
1319 | pr_err("Unable to allocate domain handle\n"); | |
1320 | iounmap(cpu_base); | |
1321 | iounmap(dist_base); | |
1322 | return -ENOMEM; | |
1323 | } | |
1324 | ||
1325 | __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); | |
d8f4f161 | 1326 | |
891ae769 | 1327 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
d60fc389 TN |
1328 | return 0; |
1329 | } | |
f26527b1 MZ |
1330 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1331 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1332 | gic_v2_acpi_init); | |
1333 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1334 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1335 | gic_v2_acpi_init); | |
d60fc389 | 1336 | #endif |