Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
d60fc389 | 44 | #include <linux/irqchip/arm-gic-acpi.h> |
f27ecacc | 45 | |
29e697b1 | 46 | #include <asm/cputype.h> |
f27ecacc | 47 | #include <asm/irq.h> |
562e0027 | 48 | #include <asm/exception.h> |
eb50439b | 49 | #include <asm/smp_plat.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
db0d4db2 MZ |
53 | union gic_base { |
54 | void __iomem *common_base; | |
6859358e | 55 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
56 | }; |
57 | ||
58 | struct gic_chip_data { | |
db0d4db2 MZ |
59 | union gic_base dist_base; |
60 | union gic_base cpu_base; | |
61 | #ifdef CONFIG_CPU_PM | |
62 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
63 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
64 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
65 | u32 __percpu *saved_ppi_enable; | |
66 | u32 __percpu *saved_ppi_conf; | |
67 | #endif | |
75294957 | 68 | struct irq_domain *domain; |
db0d4db2 MZ |
69 | unsigned int gic_irqs; |
70 | #ifdef CONFIG_GIC_NON_BANKED | |
71 | void __iomem *(*get_base)(union gic_base *); | |
72 | #endif | |
73 | }; | |
74 | ||
bd31b859 | 75 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 76 | |
384a2902 NP |
77 | /* |
78 | * The GIC mapping of CPU interfaces does not necessarily match | |
79 | * the logical CPU numbering. Let's use a mapping as returned | |
80 | * by the GIC itself. | |
81 | */ | |
82 | #define NR_GIC_CPU_IF 8 | |
83 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
84 | ||
b3a1bde4 CM |
85 | #ifndef MAX_GIC_NR |
86 | #define MAX_GIC_NR 1 | |
87 | #endif | |
88 | ||
bef8f9ee | 89 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 90 | |
db0d4db2 MZ |
91 | #ifdef CONFIG_GIC_NON_BANKED |
92 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
93 | { | |
513d1a28 | 94 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
95 | } |
96 | ||
97 | static void __iomem *gic_get_common_base(union gic_base *base) | |
98 | { | |
99 | return base->common_base; | |
100 | } | |
101 | ||
102 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
103 | { | |
104 | return data->get_base(&data->dist_base); | |
105 | } | |
106 | ||
107 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
108 | { | |
109 | return data->get_base(&data->cpu_base); | |
110 | } | |
111 | ||
112 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
113 | void __iomem *(*f)(union gic_base *)) | |
114 | { | |
115 | data->get_base = f; | |
116 | } | |
117 | #else | |
118 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
119 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 120 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
121 | #endif |
122 | ||
7d1f4288 | 123 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 124 | { |
7d1f4288 | 125 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 126 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
127 | } |
128 | ||
7d1f4288 | 129 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 130 | { |
7d1f4288 | 131 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 132 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
133 | } |
134 | ||
7d1f4288 | 135 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 136 | { |
4294f8ba | 137 | return d->hwirq; |
b3a1bde4 CM |
138 | } |
139 | ||
f27ecacc RK |
140 | /* |
141 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 142 | */ |
56717807 MZ |
143 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
144 | { | |
145 | u32 mask = 1 << (gic_irq(d) % 32); | |
146 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
147 | } | |
148 | ||
149 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 150 | { |
4294f8ba | 151 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
152 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
153 | } | |
154 | ||
155 | static void gic_mask_irq(struct irq_data *d) | |
156 | { | |
56717807 | 157 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
158 | } |
159 | ||
7d1f4288 | 160 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 161 | { |
56717807 | 162 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
163 | } |
164 | ||
1a01753e WD |
165 | static void gic_eoi_irq(struct irq_data *d) |
166 | { | |
6ac77e46 | 167 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
168 | } |
169 | ||
56717807 MZ |
170 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
171 | enum irqchip_irq_state which, bool val) | |
172 | { | |
173 | u32 reg; | |
174 | ||
175 | switch (which) { | |
176 | case IRQCHIP_STATE_PENDING: | |
177 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
178 | break; | |
179 | ||
180 | case IRQCHIP_STATE_ACTIVE: | |
181 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
182 | break; | |
183 | ||
184 | case IRQCHIP_STATE_MASKED: | |
185 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
186 | break; | |
187 | ||
188 | default: | |
189 | return -EINVAL; | |
190 | } | |
191 | ||
192 | gic_poke_irq(d, reg); | |
193 | return 0; | |
194 | } | |
195 | ||
196 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
197 | enum irqchip_irq_state which, bool *val) | |
198 | { | |
199 | switch (which) { | |
200 | case IRQCHIP_STATE_PENDING: | |
201 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
202 | break; | |
203 | ||
204 | case IRQCHIP_STATE_ACTIVE: | |
205 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
206 | break; | |
207 | ||
208 | case IRQCHIP_STATE_MASKED: | |
209 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
210 | break; | |
211 | ||
212 | default: | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
7d1f4288 | 219 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 220 | { |
7d1f4288 LB |
221 | void __iomem *base = gic_dist_base(d); |
222 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
223 | |
224 | /* Interrupt configuration for SGIs can't be changed */ | |
225 | if (gicirq < 16) | |
226 | return -EINVAL; | |
227 | ||
fb7e7deb LD |
228 | /* SPIs have restrictions on the supported types */ |
229 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
230 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
231 | return -EINVAL; |
232 | ||
1dcc73d7 | 233 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
234 | } |
235 | ||
a06f5466 | 236 | #ifdef CONFIG_SMP |
c191789c RK |
237 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
238 | bool force) | |
f27ecacc | 239 | { |
7d1f4288 | 240 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 241 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 242 | u32 val, mask, bit; |
cf613871 | 243 | unsigned long flags; |
f27ecacc | 244 | |
ffde1de6 TG |
245 | if (!force) |
246 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
247 | else | |
248 | cpu = cpumask_first(mask_val); | |
249 | ||
384a2902 | 250 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 251 | return -EINVAL; |
c191789c | 252 | |
cf613871 | 253 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 254 | mask = 0xff << shift; |
384a2902 | 255 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
256 | val = readl_relaxed(reg) & ~mask; |
257 | writel_relaxed(val | bit, reg); | |
cf613871 | 258 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 259 | |
5dfc54e0 | 260 | return IRQ_SET_MASK_OK; |
f27ecacc | 261 | } |
a06f5466 | 262 | #endif |
f27ecacc | 263 | |
8783dd3a | 264 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
265 | { |
266 | u32 irqstat, irqnr; | |
267 | struct gic_chip_data *gic = &gic_data[0]; | |
268 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
269 | ||
270 | do { | |
271 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 272 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 MZ |
273 | |
274 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
60031b4e | 275 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
276 | continue; |
277 | } | |
278 | if (irqnr < 16) { | |
279 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
280 | #ifdef CONFIG_SMP | |
281 | handle_IPI(irqnr, regs); | |
282 | #endif | |
283 | continue; | |
284 | } | |
285 | break; | |
286 | } while (1); | |
287 | } | |
288 | ||
0f347bb9 | 289 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 | 290 | { |
5b29264c JL |
291 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
292 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 293 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
294 | unsigned long status; |
295 | ||
1a01753e | 296 | chained_irq_enter(chip, desc); |
b3a1bde4 | 297 | |
bd31b859 | 298 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 299 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 300 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 301 | |
e5f81539 FK |
302 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
303 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 304 | goto out; |
b3a1bde4 | 305 | |
75294957 GL |
306 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
307 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
aec00956 | 308 | handle_bad_irq(cascade_irq, desc); |
0f347bb9 RK |
309 | else |
310 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
311 | |
312 | out: | |
1a01753e | 313 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
314 | } |
315 | ||
38c677cb | 316 | static struct irq_chip gic_chip = { |
7d1f4288 | 317 | .name = "GIC", |
7d1f4288 LB |
318 | .irq_mask = gic_mask_irq, |
319 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 320 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 321 | .irq_set_type = gic_set_type, |
f27ecacc | 322 | #ifdef CONFIG_SMP |
c191789c | 323 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 324 | #endif |
56717807 MZ |
325 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
326 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
327 | .flags = IRQCHIP_SET_TYPE_MASKED | |
328 | IRQCHIP_SKIP_SET_WAKE | | |
329 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
330 | }; |
331 | ||
b3a1bde4 CM |
332 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
333 | { | |
334 | if (gic_nr >= MAX_GIC_NR) | |
335 | BUG(); | |
4d83fcf8 TG |
336 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
337 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
338 | } |
339 | ||
2bb31351 RK |
340 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
341 | { | |
342 | void __iomem *base = gic_data_dist_base(gic); | |
343 | u32 mask, i; | |
344 | ||
345 | for (i = mask = 0; i < 32; i += 4) { | |
346 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
347 | mask |= mask >> 16; | |
348 | mask |= mask >> 8; | |
349 | if (mask) | |
350 | break; | |
351 | } | |
352 | ||
6e3aca44 | 353 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
354 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
355 | ||
356 | return mask; | |
357 | } | |
358 | ||
4c2880b3 | 359 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 360 | { |
4c2880b3 | 361 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 FK |
362 | u32 bypass = 0; |
363 | ||
364 | /* | |
365 | * Preserve bypass disable bits to be written back later | |
366 | */ | |
367 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
368 | bypass &= GICC_DIS_BYPASS_MASK; | |
369 | ||
370 | writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); | |
371 | } | |
372 | ||
373 | ||
4294f8ba | 374 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 375 | { |
75294957 | 376 | unsigned int i; |
267840f3 | 377 | u32 cpumask; |
4294f8ba | 378 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 379 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 380 | |
e5f81539 | 381 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 382 | |
f27ecacc RK |
383 | /* |
384 | * Set all global interrupts to this CPU only. | |
385 | */ | |
2bb31351 RK |
386 | cpumask = gic_get_cpumask(gic); |
387 | cpumask |= cpumask << 8; | |
388 | cpumask |= cpumask << 16; | |
e6afec9b | 389 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 390 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 391 | |
d51d0af4 | 392 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 393 | |
e5f81539 | 394 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
395 | } |
396 | ||
8c37bb3a | 397 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 398 | { |
db0d4db2 MZ |
399 | void __iomem *dist_base = gic_data_dist_base(gic); |
400 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 401 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
402 | int i; |
403 | ||
384a2902 | 404 | /* |
567e5a01 JH |
405 | * Setting up the CPU map is only relevant for the primary GIC |
406 | * because any nested/secondary GICs do not directly interface | |
407 | * with the CPU(s). | |
384a2902 | 408 | */ |
567e5a01 JH |
409 | if (gic == &gic_data[0]) { |
410 | /* | |
411 | * Get what the GIC says our CPU mask is. | |
412 | */ | |
413 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
414 | cpu_mask = gic_get_cpumask(gic); | |
415 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 416 | |
567e5a01 JH |
417 | /* |
418 | * Clear our mask from the other map entries in case they're | |
419 | * still undefined. | |
420 | */ | |
421 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
422 | if (i != cpu) | |
423 | gic_cpu_map[i] &= ~cpu_mask; | |
424 | } | |
384a2902 | 425 | |
d51d0af4 | 426 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 427 | |
e5f81539 | 428 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 429 | gic_cpu_if_up(gic); |
f27ecacc RK |
430 | } |
431 | ||
4c2880b3 | 432 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 433 | { |
4c2880b3 | 434 | void __iomem *cpu_base; |
32289506 FK |
435 | u32 val = 0; |
436 | ||
4c2880b3 JH |
437 | if (gic_nr >= MAX_GIC_NR) |
438 | return -EINVAL; | |
439 | ||
440 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
441 | val = readl(cpu_base + GIC_CPU_CTRL); |
442 | val &= ~GICC_ENABLE; | |
443 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
444 | |
445 | return 0; | |
10d9eb8a NP |
446 | } |
447 | ||
254056f3 CC |
448 | #ifdef CONFIG_CPU_PM |
449 | /* | |
450 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
451 | * with interrupts disabled but before powering down the GIC. After calling | |
452 | * this function, no interrupts will be delivered by the GIC, and another | |
453 | * platform-specific wakeup source must be enabled. | |
454 | */ | |
455 | static void gic_dist_save(unsigned int gic_nr) | |
456 | { | |
457 | unsigned int gic_irqs; | |
458 | void __iomem *dist_base; | |
459 | int i; | |
460 | ||
461 | if (gic_nr >= MAX_GIC_NR) | |
462 | BUG(); | |
463 | ||
464 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 465 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
466 | |
467 | if (!dist_base) | |
468 | return; | |
469 | ||
470 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
471 | gic_data[gic_nr].saved_spi_conf[i] = | |
472 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
473 | ||
474 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
475 | gic_data[gic_nr].saved_spi_target[i] = | |
476 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
477 | ||
478 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
479 | gic_data[gic_nr].saved_spi_enable[i] = | |
480 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
481 | } | |
482 | ||
483 | /* | |
484 | * Restores the GIC distributor registers during resume or when coming out of | |
485 | * idle. Must be called before enabling interrupts. If a level interrupt | |
486 | * that occured while the GIC was suspended is still present, it will be | |
487 | * handled normally, but any edge interrupts that occured will not be seen by | |
488 | * the GIC and need to be handled by the platform-specific wakeup source. | |
489 | */ | |
490 | static void gic_dist_restore(unsigned int gic_nr) | |
491 | { | |
492 | unsigned int gic_irqs; | |
493 | unsigned int i; | |
494 | void __iomem *dist_base; | |
495 | ||
496 | if (gic_nr >= MAX_GIC_NR) | |
497 | BUG(); | |
498 | ||
499 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 500 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
501 | |
502 | if (!dist_base) | |
503 | return; | |
504 | ||
e5f81539 | 505 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
506 | |
507 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
508 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
509 | dist_base + GIC_DIST_CONFIG + i * 4); | |
510 | ||
511 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 512 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
513 | dist_base + GIC_DIST_PRI + i * 4); |
514 | ||
515 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
516 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
517 | dist_base + GIC_DIST_TARGET + i * 4); | |
518 | ||
519 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
520 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
521 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
522 | ||
e5f81539 | 523 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
524 | } |
525 | ||
526 | static void gic_cpu_save(unsigned int gic_nr) | |
527 | { | |
528 | int i; | |
529 | u32 *ptr; | |
530 | void __iomem *dist_base; | |
531 | void __iomem *cpu_base; | |
532 | ||
533 | if (gic_nr >= MAX_GIC_NR) | |
534 | BUG(); | |
535 | ||
db0d4db2 MZ |
536 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
537 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
538 | |
539 | if (!dist_base || !cpu_base) | |
540 | return; | |
541 | ||
532d0d06 | 542 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
543 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
544 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
545 | ||
532d0d06 | 546 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
547 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
548 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
549 | ||
550 | } | |
551 | ||
552 | static void gic_cpu_restore(unsigned int gic_nr) | |
553 | { | |
554 | int i; | |
555 | u32 *ptr; | |
556 | void __iomem *dist_base; | |
557 | void __iomem *cpu_base; | |
558 | ||
559 | if (gic_nr >= MAX_GIC_NR) | |
560 | BUG(); | |
561 | ||
db0d4db2 MZ |
562 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
563 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
564 | |
565 | if (!dist_base || !cpu_base) | |
566 | return; | |
567 | ||
532d0d06 | 568 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
569 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
570 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
571 | ||
532d0d06 | 572 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
573 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
574 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
575 | ||
576 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
577 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
578 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 579 | |
e5f81539 | 580 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
4c2880b3 | 581 | gic_cpu_if_up(&gic_data[gic_nr]); |
254056f3 CC |
582 | } |
583 | ||
584 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
585 | { | |
586 | int i; | |
587 | ||
588 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
589 | #ifdef CONFIG_GIC_NON_BANKED |
590 | /* Skip over unused GICs */ | |
591 | if (!gic_data[i].get_base) | |
592 | continue; | |
593 | #endif | |
254056f3 CC |
594 | switch (cmd) { |
595 | case CPU_PM_ENTER: | |
596 | gic_cpu_save(i); | |
597 | break; | |
598 | case CPU_PM_ENTER_FAILED: | |
599 | case CPU_PM_EXIT: | |
600 | gic_cpu_restore(i); | |
601 | break; | |
602 | case CPU_CLUSTER_PM_ENTER: | |
603 | gic_dist_save(i); | |
604 | break; | |
605 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
606 | case CPU_CLUSTER_PM_EXIT: | |
607 | gic_dist_restore(i); | |
608 | break; | |
609 | } | |
610 | } | |
611 | ||
612 | return NOTIFY_OK; | |
613 | } | |
614 | ||
615 | static struct notifier_block gic_notifier_block = { | |
616 | .notifier_call = gic_notifier, | |
617 | }; | |
618 | ||
619 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
620 | { | |
621 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
622 | sizeof(u32)); | |
623 | BUG_ON(!gic->saved_ppi_enable); | |
624 | ||
625 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
626 | sizeof(u32)); | |
627 | BUG_ON(!gic->saved_ppi_conf); | |
628 | ||
abdd7b91 MZ |
629 | if (gic == &gic_data[0]) |
630 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
631 | } |
632 | #else | |
633 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
634 | { | |
635 | } | |
636 | #endif | |
637 | ||
b1cffebf | 638 | #ifdef CONFIG_SMP |
6859358e | 639 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
640 | { |
641 | int cpu; | |
1a6b69b6 NP |
642 | unsigned long flags, map = 0; |
643 | ||
644 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
645 | |
646 | /* Convert our logical CPU mask into a physical one. */ | |
647 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 648 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
649 | |
650 | /* | |
651 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 652 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 653 | */ |
8adbf57f | 654 | dmb(ishst); |
b1cffebf RH |
655 | |
656 | /* this always happens on GIC0 */ | |
657 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
658 | |
659 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
660 | } | |
661 | #endif | |
662 | ||
663 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
664 | /* |
665 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
666 | * | |
667 | * cpu_id: the ID for the destination CPU interface | |
668 | * irq: the IPI number to send a SGI for | |
669 | */ | |
670 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
671 | { | |
672 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
673 | cpu_id = 1 << cpu_id; | |
674 | /* this always happens on GIC0 */ | |
675 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
676 | } | |
677 | ||
ed96762e NP |
678 | /* |
679 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
680 | * | |
681 | * @cpu: the logical CPU number to get the GIC ID for. | |
682 | * | |
683 | * Return the CPU interface ID for the given logical CPU number, | |
684 | * or -1 if the CPU number is too large or the interface ID is | |
685 | * unknown (more than one bit set). | |
686 | */ | |
687 | int gic_get_cpu_id(unsigned int cpu) | |
688 | { | |
689 | unsigned int cpu_bit; | |
690 | ||
691 | if (cpu >= NR_GIC_CPU_IF) | |
692 | return -1; | |
693 | cpu_bit = gic_cpu_map[cpu]; | |
694 | if (cpu_bit & (cpu_bit - 1)) | |
695 | return -1; | |
696 | return __ffs(cpu_bit); | |
697 | } | |
698 | ||
1a6b69b6 NP |
699 | /* |
700 | * gic_migrate_target - migrate IRQs to another CPU interface | |
701 | * | |
702 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
703 | * | |
704 | * Migrate all peripheral interrupts with a target matching the current CPU | |
705 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
706 | * is also updated. Targets to other CPU interfaces are unchanged. | |
707 | * This must be called with IRQs locally disabled. | |
708 | */ | |
709 | void gic_migrate_target(unsigned int new_cpu_id) | |
710 | { | |
711 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
712 | void __iomem *dist_base; | |
713 | int i, ror_val, cpu = smp_processor_id(); | |
714 | u32 val, cur_target_mask, active_mask; | |
715 | ||
716 | if (gic_nr >= MAX_GIC_NR) | |
717 | BUG(); | |
718 | ||
719 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
720 | if (!dist_base) | |
721 | return; | |
722 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
723 | ||
724 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
725 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
726 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
727 | ||
728 | raw_spin_lock(&irq_controller_lock); | |
729 | ||
730 | /* Update the target interface for this logical CPU */ | |
731 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
732 | ||
733 | /* | |
734 | * Find all the peripheral interrupts targetting the current | |
735 | * CPU interface and migrate them to the new CPU interface. | |
736 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
737 | */ | |
738 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
739 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
740 | active_mask = val & cur_target_mask; | |
741 | if (active_mask) { | |
742 | val &= ~active_mask; | |
743 | val |= ror32(active_mask, ror_val); | |
744 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
745 | } | |
746 | } | |
747 | ||
748 | raw_spin_unlock(&irq_controller_lock); | |
749 | ||
750 | /* | |
751 | * Now let's migrate and clear any potential SGIs that might be | |
752 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
753 | * is a banked register, we can only forward the SGI using | |
754 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
755 | * doesn't use that information anyway. | |
756 | * | |
757 | * For the same reason we do not adjust SGI source information | |
758 | * for previously sent SGIs by us to other CPUs either. | |
759 | */ | |
760 | for (i = 0; i < 16; i += 4) { | |
761 | int j; | |
762 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
763 | if (!val) | |
764 | continue; | |
765 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
766 | for (j = i; j < i + 4; j++) { | |
767 | if (val & 0xff) | |
768 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
769 | dist_base + GIC_DIST_SOFTINT); | |
770 | val >>= 8; | |
771 | } | |
772 | } | |
b1cffebf | 773 | } |
eeb44658 NP |
774 | |
775 | /* | |
776 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
777 | * | |
778 | * REturn the physical address of the SGI register to be used | |
779 | * by some early assembly code when the kernel is not yet available. | |
780 | */ | |
781 | static unsigned long gic_dist_physaddr; | |
782 | ||
783 | unsigned long gic_get_sgir_physaddr(void) | |
784 | { | |
785 | if (!gic_dist_physaddr) | |
786 | return 0; | |
787 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
788 | } | |
789 | ||
790 | void __init gic_init_physaddr(struct device_node *node) | |
791 | { | |
792 | struct resource res; | |
793 | if (of_address_to_resource(node, 0, &res) == 0) { | |
794 | gic_dist_physaddr = res.start; | |
795 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
796 | } | |
797 | } | |
798 | ||
799 | #else | |
800 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
801 | #endif |
802 | ||
75294957 GL |
803 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
804 | irq_hw_number_t hw) | |
805 | { | |
806 | if (hw < 32) { | |
807 | irq_set_percpu_devid(irq); | |
9a1091ef YC |
808 | irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, |
809 | handle_percpu_devid_irq, NULL, NULL); | |
75294957 GL |
810 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
811 | } else { | |
9a1091ef YC |
812 | irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, |
813 | handle_fasteoi_irq, NULL, NULL); | |
75294957 GL |
814 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
815 | } | |
75294957 GL |
816 | return 0; |
817 | } | |
818 | ||
006e983b S |
819 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
820 | { | |
006e983b S |
821 | } |
822 | ||
7bb69bad GL |
823 | static int gic_irq_domain_xlate(struct irq_domain *d, |
824 | struct device_node *controller, | |
825 | const u32 *intspec, unsigned int intsize, | |
826 | unsigned long *out_hwirq, unsigned int *out_type) | |
b3f7ed03 | 827 | { |
006e983b S |
828 | unsigned long ret = 0; |
829 | ||
b3f7ed03 RH |
830 | if (d->of_node != controller) |
831 | return -EINVAL; | |
832 | if (intsize < 3) | |
833 | return -EINVAL; | |
834 | ||
835 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
836 | *out_hwirq = intspec[1] + 16; | |
837 | ||
838 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
a5561c3e MZ |
839 | if (!intspec[0]) |
840 | *out_hwirq += 16; | |
b3f7ed03 RH |
841 | |
842 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
006e983b S |
843 | |
844 | return ret; | |
b3f7ed03 | 845 | } |
b3f7ed03 | 846 | |
c0114709 | 847 | #ifdef CONFIG_SMP |
8c37bb3a PG |
848 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
849 | void *hcpu) | |
c0114709 | 850 | { |
8b6fd652 | 851 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
852 | gic_cpu_init(&gic_data[0]); |
853 | return NOTIFY_OK; | |
854 | } | |
855 | ||
856 | /* | |
857 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
858 | * priority because the GIC needs to be up before the ARM generic timers. | |
859 | */ | |
8c37bb3a | 860 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
861 | .notifier_call = gic_secondary_init, |
862 | .priority = 100, | |
863 | }; | |
864 | #endif | |
865 | ||
9a1091ef YC |
866 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
867 | unsigned int nr_irqs, void *arg) | |
868 | { | |
869 | int i, ret; | |
870 | irq_hw_number_t hwirq; | |
871 | unsigned int type = IRQ_TYPE_NONE; | |
872 | struct of_phandle_args *irq_data = arg; | |
873 | ||
874 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, | |
875 | irq_data->args_count, &hwirq, &type); | |
876 | if (ret) | |
877 | return ret; | |
878 | ||
879 | for (i = 0; i < nr_irqs; i++) | |
880 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
886 | .xlate = gic_irq_domain_xlate, | |
887 | .alloc = gic_irq_domain_alloc, | |
888 | .free = irq_domain_free_irqs_top, | |
889 | }; | |
890 | ||
6859358e | 891 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 892 | .map = gic_irq_domain_map, |
006e983b | 893 | .unmap = gic_irq_domain_unmap, |
7bb69bad | 894 | .xlate = gic_irq_domain_xlate, |
4294f8ba RH |
895 | }; |
896 | ||
db0d4db2 MZ |
897 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
898 | void __iomem *dist_base, void __iomem *cpu_base, | |
75294957 | 899 | u32 percpu_offset, struct device_node *node) |
b580b899 | 900 | { |
75294957 | 901 | irq_hw_number_t hwirq_base; |
bef8f9ee | 902 | struct gic_chip_data *gic; |
384a2902 | 903 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
904 | |
905 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
906 | ||
907 | gic = &gic_data[gic_nr]; | |
db0d4db2 MZ |
908 | #ifdef CONFIG_GIC_NON_BANKED |
909 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
910 | unsigned int cpu; | |
911 | ||
912 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
913 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
914 | if (WARN_ON(!gic->dist_base.percpu_base || | |
915 | !gic->cpu_base.percpu_base)) { | |
916 | free_percpu(gic->dist_base.percpu_base); | |
917 | free_percpu(gic->cpu_base.percpu_base); | |
918 | return; | |
919 | } | |
920 | ||
921 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
922 | u32 mpidr = cpu_logical_map(cpu); |
923 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
924 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
925 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
926 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
927 | } | |
928 | ||
929 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
930 | } else | |
931 | #endif | |
932 | { /* Normal, sane GIC... */ | |
933 | WARN(percpu_offset, | |
934 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
935 | percpu_offset); | |
936 | gic->dist_base.common_base = dist_base; | |
937 | gic->cpu_base.common_base = cpu_base; | |
938 | gic_set_base_accessor(gic, gic_get_common_base); | |
939 | } | |
bef8f9ee | 940 | |
4294f8ba RH |
941 | /* |
942 | * Find out how many interrupts are supported. | |
943 | * The GIC only supports up to 1020 interrupt sources. | |
944 | */ | |
db0d4db2 | 945 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
946 | gic_irqs = (gic_irqs + 1) * 32; |
947 | if (gic_irqs > 1020) | |
948 | gic_irqs = 1020; | |
949 | gic->gic_irqs = gic_irqs; | |
950 | ||
9a1091ef | 951 | if (node) { /* DT case */ |
a5561c3e MZ |
952 | gic->domain = irq_domain_add_linear(node, gic_irqs, |
953 | &gic_irq_domain_hierarchy_ops, | |
954 | gic); | |
9a1091ef YC |
955 | } else { /* Non-DT case */ |
956 | /* | |
957 | * For primary GICs, skip over SGIs. | |
958 | * For secondary GICs, skip over PPIs, too. | |
959 | */ | |
960 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
961 | hwirq_base = 16; | |
962 | if (irq_start != -1) | |
963 | irq_start = (irq_start & ~31) + 16; | |
964 | } else { | |
965 | hwirq_base = 32; | |
966 | } | |
967 | ||
968 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 969 | |
006e983b S |
970 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
971 | numa_node_id()); | |
972 | if (IS_ERR_VALUE(irq_base)) { | |
973 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
974 | irq_start); | |
975 | irq_base = irq_start; | |
976 | } | |
977 | ||
978 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, | |
979 | hwirq_base, &gic_irq_domain_ops, gic); | |
f37a53cc | 980 | } |
006e983b | 981 | |
75294957 GL |
982 | if (WARN_ON(!gic->domain)) |
983 | return; | |
bef8f9ee | 984 | |
08332dff | 985 | if (gic_nr == 0) { |
567e5a01 JH |
986 | /* |
987 | * Initialize the CPU interface map to all CPUs. | |
988 | * It will be refined as each CPU probes its ID. | |
989 | * This is only necessary for the primary GIC. | |
990 | */ | |
991 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
992 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 993 | #ifdef CONFIG_SMP |
08332dff MR |
994 | set_smp_cross_call(gic_raise_softirq); |
995 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 996 | #endif |
08332dff MR |
997 | set_handle_irq(gic_handle_irq); |
998 | } | |
cfed7d60 | 999 | |
4294f8ba | 1000 | gic_dist_init(gic); |
bef8f9ee | 1001 | gic_cpu_init(gic); |
254056f3 | 1002 | gic_pm_init(gic); |
b580b899 RK |
1003 | } |
1004 | ||
b3f7ed03 | 1005 | #ifdef CONFIG_OF |
46f101df | 1006 | static int gic_cnt __initdata; |
b3f7ed03 | 1007 | |
6859358e SB |
1008 | static int __init |
1009 | gic_of_init(struct device_node *node, struct device_node *parent) | |
b3f7ed03 RH |
1010 | { |
1011 | void __iomem *cpu_base; | |
1012 | void __iomem *dist_base; | |
db0d4db2 | 1013 | u32 percpu_offset; |
b3f7ed03 | 1014 | int irq; |
b3f7ed03 RH |
1015 | |
1016 | if (WARN_ON(!node)) | |
1017 | return -ENODEV; | |
1018 | ||
1019 | dist_base = of_iomap(node, 0); | |
1020 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
1021 | ||
1022 | cpu_base = of_iomap(node, 1); | |
1023 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
1024 | ||
db0d4db2 MZ |
1025 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1026 | percpu_offset = 0; | |
1027 | ||
75294957 | 1028 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
eeb44658 NP |
1029 | if (!gic_cnt) |
1030 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1031 | |
1032 | if (parent) { | |
1033 | irq = irq_of_parse_and_map(node, 0); | |
1034 | gic_cascade_irq(gic_cnt, irq); | |
1035 | } | |
853a33ce SS |
1036 | |
1037 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1038 | gicv2m_of_init(node, gic_data[gic_cnt].domain); | |
1039 | ||
b3f7ed03 RH |
1040 | gic_cnt++; |
1041 | return 0; | |
1042 | } | |
144cb088 | 1043 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1044 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1045 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1046 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1047 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1048 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1049 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1050 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
1051 | ||
b3f7ed03 | 1052 | #endif |
d60fc389 TN |
1053 | |
1054 | #ifdef CONFIG_ACPI | |
1055 | static phys_addr_t dist_phy_base, cpu_phy_base __initdata; | |
1056 | ||
1057 | static int __init | |
1058 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1059 | const unsigned long end) | |
1060 | { | |
1061 | struct acpi_madt_generic_interrupt *processor; | |
1062 | phys_addr_t gic_cpu_base; | |
1063 | static int cpu_base_assigned; | |
1064 | ||
1065 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1066 | ||
99e3e3ae | 1067 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1068 | return -EINVAL; |
1069 | ||
1070 | /* | |
1071 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1072 | * All CPU interface addresses have to be the same. | |
1073 | */ | |
1074 | gic_cpu_base = processor->base_address; | |
1075 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1076 | return -EINVAL; | |
1077 | ||
1078 | cpu_phy_base = gic_cpu_base; | |
1079 | cpu_base_assigned = 1; | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static int __init | |
1084 | gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, | |
1085 | const unsigned long end) | |
1086 | { | |
1087 | struct acpi_madt_generic_distributor *dist; | |
1088 | ||
1089 | dist = (struct acpi_madt_generic_distributor *)header; | |
1090 | ||
1091 | if (BAD_MADT_ENTRY(dist, end)) | |
1092 | return -EINVAL; | |
1093 | ||
1094 | dist_phy_base = dist->base_address; | |
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | int __init | |
1099 | gic_v2_acpi_init(struct acpi_table_header *table) | |
1100 | { | |
1101 | void __iomem *cpu_base, *dist_base; | |
1102 | int count; | |
1103 | ||
1104 | /* Collect CPU base addresses */ | |
1105 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1106 | sizeof(struct acpi_table_madt), | |
1107 | gic_acpi_parse_madt_cpu, table, | |
1108 | ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); | |
1109 | if (count <= 0) { | |
1110 | pr_err("No valid GICC entries exist\n"); | |
1111 | return -EINVAL; | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Find distributor base address. We expect one distributor entry since | |
1116 | * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. | |
1117 | */ | |
1118 | count = acpi_parse_entries(ACPI_SIG_MADT, | |
1119 | sizeof(struct acpi_table_madt), | |
1120 | gic_acpi_parse_madt_distributor, table, | |
1121 | ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); | |
1122 | if (count <= 0) { | |
1123 | pr_err("No valid GICD entries exist\n"); | |
1124 | return -EINVAL; | |
1125 | } else if (count > 1) { | |
1126 | pr_err("More than one GICD entry detected\n"); | |
1127 | return -EINVAL; | |
1128 | } | |
1129 | ||
1130 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); | |
1131 | if (!cpu_base) { | |
1132 | pr_err("Unable to map GICC registers\n"); | |
1133 | return -ENOMEM; | |
1134 | } | |
1135 | ||
1136 | dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); | |
1137 | if (!dist_base) { | |
1138 | pr_err("Unable to map GICD registers\n"); | |
1139 | iounmap(cpu_base); | |
1140 | return -ENOMEM; | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Initialize zero GIC instance (no multi-GIC support). Also, set GIC | |
1145 | * as default IRQ domain to allow for GSI registration and GSI to IRQ | |
1146 | * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). | |
1147 | */ | |
1148 | gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); | |
1149 | irq_set_default_host(gic_data[0].domain); | |
d8f4f161 LP |
1150 | |
1151 | acpi_irq_model = ACPI_IRQ_MODEL_GIC; | |
d60fc389 TN |
1152 | return 0; |
1153 | } | |
1154 | #endif |