[linux-block.git] / drivers / irqchip / irq-gic-v4.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016,2017 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/msi.h>
#include <linux/sched.h>

#include <linux/irqchip/arm-gic-v4.h>

/*
 * WARNING: The blurb below assumes that you understand the
 * intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
 * translated into GICv4 commands. So it effectively targets at most
 * two individuals. You know who you are.
 *
 * The core GICv4 code is designed to *avoid* exposing too much of the
 * core GIC code (that would in turn leak into the hypervisor code),
 * and instead provide a hypervisor agnostic interface to the HW (of
 * course, the astute reader will quickly realize that hypervisor
 * agnostic actually means KVM-specific - what were you thinking?).
 *
 * In order to achieve a modicum of isolation, we try to hide most of
 * the GICv4 "stuff" behind normal irqchip operations:
 *
 * - Any guest-visible VLPI is backed by a Linux interrupt (and a
 *   physical LPI which gets unmapped when the guest maps the
 *   VLPI). This allows the same DevID/EventID pair to be either
 *   mapped to the LPI (host) or the VLPI (guest). Note that this is
 *   exclusive, and you cannot have both.
 *
 * - Enabling/disabling a VLPI is done by issuing mask/unmask calls.
 *
 * - Guest INT/CLEAR commands are implemented through
 *   irq_set_irqchip_state().
 *
 * - The *bizarre* stuff (mapping/unmapping an interrupt to a VLPI, or
 *   issuing an INV after changing a priority) gets shoved into the
 *   irq_set_vcpu_affinity() method. While this is quite horrible
 *   (let's face it, this is the irqchip version of an ioctl), it
 *   confines the crap to a single location. And map/unmap really is
 *   about setting the affinity of a VLPI to a vcpu, so only INV is
 *   majorly out of place. So there.
 *
 * A number of commands are simply not provided by this interface, as
 * they do not make direct sense. For example, MAPD is purely local to
 * the virtual ITS (because it references a virtual device, and the
 * physical ITS is still very much in charge of the physical
 * device). Same goes for things like MAPC (the physical ITS deals
 * with the actual vPE affinity, and not the braindead concept of
 * collection). SYNC is not provided either, as each and every command
 * is followed by a VSYNC. This could be relaxed in the future, should
 * this be seen as a bottleneck (yes, this means *never*).
 *
 * But handling VLPIs is only one side of the job of the GICv4
 * code. The other (darker) side is to take care of the doorbell
 * interrupts which are delivered when a VLPI targeting a non-running
 * vcpu is being made pending.
 *
 * The choice made here is that each vcpu (VPE in old northern GICv4
 * dialect) gets a single doorbell LPI, no matter how many interrupts
 * are targeting it. This has a nice property, which is that the
 * interrupt becomes a handle for the VPE, and that the hypervisor
 * code can manipulate it through the normal interrupt API:
 *
 * - VMs (or rather the VM abstraction that matters to the GIC)
 *   contain an irq domain where each interrupt maps to a VPE. In
 *   turn, this domain sits on top of the normal LPI allocator, and a
 *   specially crafted irq_chip implementation.
 *
 * - mask/unmask do what is expected on the doorbell interrupt.
 *
 * - irq_set_affinity is used to move a VPE from one redistributor to
 *   another.
 *
 * - irq_set_vcpu_affinity once again gets hijacked for the purpose of
 *   creating a new sub-API, namely scheduling/descheduling a VPE
 *   (which involves programming GICR_V{PROP,PEND}BASER) and
 *   performing INVALL operations.
 */

static struct irq_domain *gic_domain;
static const struct irq_domain_ops *vpe_domain_ops;
static const struct irq_domain_ops *sgi_domain_ops;

static bool has_v4_1(void)
{
	return !!sgi_domain_ops;
}

static int its_alloc_vcpu_sgis(struct its_vpe *vpe, int idx)
{
	char *name;
	int sgi_base;

	if (!has_v4_1())
		return 0;

	name = kasprintf(GFP_KERNEL, "GICv4-sgi-%d", task_pid_nr(current));
	if (!name)
		goto err;

	vpe->fwnode = irq_domain_alloc_named_id_fwnode(name, idx);
	if (!vpe->fwnode)
		goto err;

	kfree(name);
	name = NULL;

	vpe->sgi_domain = irq_domain_create_linear(vpe->fwnode, 16,
						   sgi_domain_ops, vpe);
	if (!vpe->sgi_domain)
		goto err;

	sgi_base = __irq_domain_alloc_irqs(vpe->sgi_domain, -1, 16,
					       NUMA_NO_NODE, vpe,
					       false, NULL);
	if (sgi_base <= 0)
		goto err;

	return 0;

err:
	if (vpe->sgi_domain)
		irq_domain_remove(vpe->sgi_domain);
	if (vpe->fwnode)
		irq_domain_free_fwnode(vpe->fwnode);
	kfree(name);
	return -ENOMEM;
}

int its_alloc_vcpu_irqs(struct its_vm *vm)
{
	int vpe_base_irq, i;

	vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv4-vpe",
						      task_pid_nr(current));
	if (!vm->fwnode)
		goto err;

	vm->domain = irq_domain_create_hierarchy(gic_domain, 0, vm->nr_vpes,
						 vm->fwnode, vpe_domain_ops,
						 vm);
	if (!vm->domain)
		goto err;

	for (i = 0; i < vm->nr_vpes; i++) {
		vm->vpes[i]->its_vm = vm;
		vm->vpes[i]->idai = true;
	}

	vpe_base_irq = __irq_domain_alloc_irqs(vm->domain, -1, vm->nr_vpes,
					       NUMA_NO_NODE, vm,
					       false, NULL);
	if (vpe_base_irq <= 0)
		goto err;

	for (i = 0; i < vm->nr_vpes; i++) {
		int ret;
		vm->vpes[i]->irq = vpe_base_irq + i;
		ret = its_alloc_vcpu_sgis(vm->vpes[i], i);
		if (ret)
			goto err;
	}

	return 0;

err:
	if (vm->domain)
		irq_domain_remove(vm->domain);
	if (vm->fwnode)
		irq_domain_free_fwnode(vm->fwnode);

	return -ENOMEM;
}

static void its_free_sgi_irqs(struct its_vm *vm)
{
	int i;

	if (!has_v4_1())
		return;

	for (i = 0; i < vm->nr_vpes; i++) {
		unsigned int irq = irq_find_mapping(vm->vpes[i]->sgi_domain, 0);

		if (WARN_ON(!irq))
			continue;

		irq_domain_free_irqs(irq, 16);
		irq_domain_remove(vm->vpes[i]->sgi_domain);
		irq_domain_free_fwnode(vm->vpes[i]->fwnode);
	}
}

void its_free_vcpu_irqs(struct its_vm *vm)
{
	its_free_sgi_irqs(vm);
	irq_domain_free_irqs(vm->vpes[0]->irq, vm->nr_vpes);
	irq_domain_remove(vm->domain);
	irq_domain_free_fwnode(vm->fwnode);
}

static int its_send_vpe_cmd(struct its_vpe *vpe, struct its_cmd_info *info)
{
	return irq_set_vcpu_affinity(vpe->irq, info);
}

int its_make_vpe_non_resident(struct its_vpe *vpe, bool db)
{
	struct irq_desc *desc = irq_to_desc(vpe->irq);
	struct its_cmd_info info = { };
	int ret;

	WARN_ON(preemptible());

	info.cmd_type = DESCHEDULE_VPE;
	if (has_v4_1()) {
		/* GICv4.1 can directly deal with doorbells */
		info.req_db = db;
	} else {
		/* Undo the nested disable_irq() calls... */
		while (db && irqd_irq_disabled(&desc->irq_data))
			enable_irq(vpe->irq);
	}

	ret = its_send_vpe_cmd(vpe, &info);
	if (!ret)
		vpe->resident = false;

	return ret;
}

int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en)
{
	struct its_cmd_info info = { };
	int ret;

	WARN_ON(preemptible());

	info.cmd_type = SCHEDULE_VPE;
	if (has_v4_1()) {
		info.g0en = g0en;
		info.g1en = g1en;
	} else {
		/* Disabled the doorbell, as we're about to enter the guest */
		disable_irq_nosync(vpe->irq);
	}

	ret = its_send_vpe_cmd(vpe, &info);
	if (!ret)
		vpe->resident = true;

	return ret;
}

int its_invall_vpe(struct its_vpe *vpe)
{
	struct its_cmd_info info = {
		.cmd_type = INVALL_VPE,
	};

	return its_send_vpe_cmd(vpe, &info);
}

int its_map_vlpi(int irq, struct its_vlpi_map *map)
{
	struct its_cmd_info info = {
		.cmd_type = MAP_VLPI,
		{
			.map      = map,
		},
	};
	int ret;

	/*
	 * The host will never see that interrupt firing again, so it
	 * is vital that we don't do any lazy masking.
	 */
	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);

	ret = irq_set_vcpu_affinity(irq, &info);
	if (ret)
		irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);

	return ret;
}

int its_get_vlpi(int irq, struct its_vlpi_map *map)
{
	struct its_cmd_info info = {
		.cmd_type = GET_VLPI,
		{
			.map      = map,
		},
	};

	return irq_set_vcpu_affinity(irq, &info);
}

int its_unmap_vlpi(int irq)
{
	irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
	return irq_set_vcpu_affinity(irq, NULL);
}

int its_prop_update_vlpi(int irq, u8 config, bool inv)
{
	struct its_cmd_info info = {
		.cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
		{
			.config   = config,
		},
	};

	return irq_set_vcpu_affinity(irq, &info);
}

int its_prop_update_vsgi(int irq, u8 priority, bool group)
{
	struct its_cmd_info info = {
		.cmd_type = PROP_UPDATE_VSGI,
		{
			.priority	= priority,
			.group		= group,
		},
	};

	return irq_set_vcpu_affinity(irq, &info);
}

int its_init_v4(struct irq_domain *domain,
		const struct irq_domain_ops *vpe_ops,
		const struct irq_domain_ops *sgi_ops)
{
	if (domain) {
		pr_info("ITS: Enabling GICv4 support\n");
		gic_domain = domain;
		vpe_domain_ops = vpe_ops;
		sgi_domain_ops = sgi_ops;
		return 0;
	}

	pr_err("ITS: No GICv4 VPE domain allocated\n");
	return -ENODEV;
}
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
7de5c0af MZ	2	/*
	3	* Copyright (C) 2016,2017 ARM Limited, All Rights Reserved.
	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
7de5c0af MZ	5	*/
	6
	7	#include <linux/interrupt.h>
	8	#include <linux/irq.h>
	9	#include <linux/irqdomain.h>
	10	#include <linux/msi.h>
	11	#include <linux/sched.h>
	12
	13	#include <linux/irqchip/arm-gic-v4.h>
	14
7954907b MZ	15	/*
	16	* WARNING: The blurb below assumes that you understand the
	17	* intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
	18	* translated into GICv4 commands. So it effectively targets at most
	19	* two individuals. You know who you are.
	20	*
	21	* The core GICv4 code is designed to avoid exposing too much of the
	22	* core GIC code (that would in turn leak into the hypervisor code),
	23	* and instead provide a hypervisor agnostic interface to the HW (of
	24	* course, the astute reader will quickly realize that hypervisor
	25	* agnostic actually means KVM-specific - what were you thinking?).
	26	*
	27	* In order to achieve a modicum of isolation, we try to hide most of
	28	* the GICv4 "stuff" behind normal irqchip operations:
	29	*
	30	* - Any guest-visible VLPI is backed by a Linux interrupt (and a
	31	* physical LPI which gets unmapped when the guest maps the
	32	* VLPI). This allows the same DevID/EventID pair to be either
	33	* mapped to the LPI (host) or the VLPI (guest). Note that this is
	34	* exclusive, and you cannot have both.
	35	*
	36	* - Enabling/disabling a VLPI is done by issuing mask/unmask calls.
	37	*
	38	* - Guest INT/CLEAR commands are implemented through
	39	* irq_set_irqchip_state().
	40	*
	41	* - The bizarre stuff (mapping/unmapping an interrupt to a VLPI, or
	42	* issuing an INV after changing a priority) gets shoved into the
	43	* irq_set_vcpu_affinity() method. While this is quite horrible
	44	* (let's face it, this is the irqchip version of an ioctl), it
	45	* confines the crap to a single location. And map/unmap really is
	46	* about setting the affinity of a VLPI to a vcpu, so only INV is
	47	* majorly out of place. So there.
	48	*
	49	* A number of commands are simply not provided by this interface, as
	50	* they do not make direct sense. For example, MAPD is purely local to
	51	* the virtual ITS (because it references a virtual device, and the
	52	* physical ITS is still very much in charge of the physical
	53	* device). Same goes for things like MAPC (the physical ITS deals
	54	* with the actual vPE affinity, and not the braindead concept of
	55	* collection). SYNC is not provided either, as each and every command
	56	* is followed by a VSYNC. This could be relaxed in the future, should
	57	* this be seen as a bottleneck (yes, this means never).
	58	*
	59	* But handling VLPIs is only one side of the job of the GICv4
	60	* code. The other (darker) side is to take care of the doorbell
	61	* interrupts which are delivered when a VLPI targeting a non-running
	62	* vcpu is being made pending.
	63	*
	64	* The choice made here is that each vcpu (VPE in old northern GICv4
	65	* dialect) gets a single doorbell LPI, no matter how many interrupts
	66	* are targeting it. This has a nice property, which is that the
	67	* interrupt becomes a handle for the VPE, and that the hypervisor
	68	* code can manipulate it through the normal interrupt API:
	69	*
	70	* - VMs (or rather the VM abstraction that matters to the GIC)
	71	* contain an irq domain where each interrupt maps to a VPE. In
	72	* turn, this domain sits on top of the normal LPI allocator, and a
	73	* specially crafted irq_chip implementation.
	74	*
	75	* - mask/unmask do what is expected on the doorbell interrupt.
	76	*
	77	* - irq_set_affinity is used to move a VPE from one redistributor to
	78	* another.
79	*
80	* - irq_set_vcpu_affinity once again gets hijacked for the purpose of
81	* creating a new sub-API, namely scheduling/descheduling a VPE
82	* (which involves programming GICR_V{PROP,PEND}BASER) and
83	* performing INVALL operations.
84	*/
85
7de5c0af MZ	86	static struct irq_domain *gic_domain;
7de5c0af MZ	87	static const struct irq_domain_ops *vpe_domain_ops;
166cba71	88	static const struct irq_domain_ops *sgi_domain_ops;
7de5c0af	89
ae699ad3 MZ	90	static bool has_v4_1(void)
	91	{
	92	return !!sgi_domain_ops;
	93	}
	94
6d31b6ff MZ	95	static int its_alloc_vcpu_sgis(struct its_vpe *vpe, int idx)
	96	{
	97	char *name;
	98	int sgi_base;
	99
	100	if (!has_v4_1())
	101	return 0;
	102
	103	name = kasprintf(GFP_KERNEL, "GICv4-sgi-%d", task_pid_nr(current));
	104	if (!name)
	105	goto err;
	106
	107	vpe->fwnode = irq_domain_alloc_named_id_fwnode(name, idx);
	108	if (!vpe->fwnode)
	109	goto err;
	110
	111	kfree(name);
	112	name = NULL;
	113
	114	vpe->sgi_domain = irq_domain_create_linear(vpe->fwnode, 16,
	115	sgi_domain_ops, vpe);
	116	if (!vpe->sgi_domain)
	117	goto err;
	118
	119	sgi_base = __irq_domain_alloc_irqs(vpe->sgi_domain, -1, 16,
	120	NUMA_NO_NODE, vpe,
	121	false, NULL);
	122	if (sgi_base <= 0)
	123	goto err;
	124
	125	return 0;
	126
	127	err:
	128	if (vpe->sgi_domain)
	129	irq_domain_remove(vpe->sgi_domain);
	130	if (vpe->fwnode)
	131	irq_domain_free_fwnode(vpe->fwnode);
	132	kfree(name);
	133	return -ENOMEM;
	134	}
	135
7de5c0af MZ	136	int its_alloc_vcpu_irqs(struct its_vm *vm)
	137	{
	138	int vpe_base_irq, i;
	139
	140	vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv4-vpe",
	141	task_pid_nr(current));
	142	if (!vm->fwnode)
	143	goto err;
	144
	145	vm->domain = irq_domain_create_hierarchy(gic_domain, 0, vm->nr_vpes,
	146	vm->fwnode, vpe_domain_ops,
	147	vm);
	148	if (!vm->domain)
	149	goto err;
	150
	151	for (i = 0; i < vm->nr_vpes; i++) {
	152	vm->vpes[i]->its_vm = vm;
	153	vm->vpes[i]->idai = true;
	154	}
	155
	156	vpe_base_irq = __irq_domain_alloc_irqs(vm->domain, -1, vm->nr_vpes,
	157	NUMA_NO_NODE, vm,
	158	false, NULL);
	159	if (vpe_base_irq <= 0)
	160	goto err;
	161
6d31b6ff MZ	162	for (i = 0; i < vm->nr_vpes; i++) {
6d31b6ff MZ	163	int ret;
7de5c0af	164	vm->vpes[i]->irq = vpe_base_irq + i;
6d31b6ff MZ	165	ret = its_alloc_vcpu_sgis(vm->vpes[i], i);
	166	if (ret)
	167	goto err;
	168	}
7de5c0af MZ	169
	170	return 0;
	171
	172	err:
	173	if (vm->domain)
	174	irq_domain_remove(vm->domain);
	175	if (vm->fwnode)
	176	irq_domain_free_fwnode(vm->fwnode);
	177
	178	return -ENOMEM;
	179	}
	180
6d31b6ff MZ	181	static void its_free_sgi_irqs(struct its_vm *vm)
	182	{
	183	int i;
	184
	185	if (!has_v4_1())
	186	return;
	187
	188	for (i = 0; i < vm->nr_vpes; i++) {
	189	unsigned int irq = irq_find_mapping(vm->vpes[i]->sgi_domain, 0);
	190
	191	if (WARN_ON(!irq))
	192	continue;
	193
	194	irq_domain_free_irqs(irq, 16);
	195	irq_domain_remove(vm->vpes[i]->sgi_domain);
	196	irq_domain_free_fwnode(vm->vpes[i]->fwnode);
	197	}
	198	}
	199
7de5c0af MZ	200	void its_free_vcpu_irqs(struct its_vm *vm)
7de5c0af MZ	201	{
6d31b6ff	202	its_free_sgi_irqs(vm);
7de5c0af MZ	203	irq_domain_free_irqs(vm->vpes[0]->irq, vm->nr_vpes);
	204	irq_domain_remove(vm->domain);
	205	irq_domain_free_fwnode(vm->fwnode);
	206	}
eab84318 MZ	207
	208	static int its_send_vpe_cmd(struct its_vpe vpe, struct its_cmd_info info)
	209	{
	210	return irq_set_vcpu_affinity(vpe->irq, info);
	211	}
	212
ae699ad3	213	int its_make_vpe_non_resident(struct its_vpe *vpe, bool db)
eab84318	214	{
ae699ad3 MZ	215	struct irq_desc *desc = irq_to_desc(vpe->irq);
ae699ad3 MZ	216	struct its_cmd_info info = { };
8e01d9a3	217	int ret;
eab84318 MZ	218
	219	WARN_ON(preemptible());
	220
ae699ad3 MZ	221	info.cmd_type = DESCHEDULE_VPE;
	222	if (has_v4_1()) {
	223	/* GICv4.1 can directly deal with doorbells */
	224	info.req_db = db;
	225	} else {
	226	/* Undo the nested disable_irq() calls... */
	227	while (db && irqd_irq_disabled(&desc->irq_data))
	228	enable_irq(vpe->irq);
	229	}
	230
	231	ret = its_send_vpe_cmd(vpe, &info);
	232	if (!ret)
	233	vpe->resident = false;
	234
	235	return ret;
	236	}
	237
	238	int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en)
	239	{
	240	struct its_cmd_info info = { };
	241	int ret;
	242
	243	WARN_ON(preemptible());
	244
	245	info.cmd_type = SCHEDULE_VPE;
	246	if (has_v4_1()) {
	247	info.g0en = g0en;
	248	info.g1en = g1en;
	249	} else {
	250	/* Disabled the doorbell, as we're about to enter the guest */
	251	disable_irq_nosync(vpe->irq);
	252	}
eab84318	253
8e01d9a3 MZ	254	ret = its_send_vpe_cmd(vpe, &info);
8e01d9a3 MZ	255	if (!ret)
ae699ad3	256	vpe->resident = true;
8e01d9a3 MZ	257
8e01d9a3 MZ	258	return ret;
eab84318 MZ	259	}
	260
	261	int its_invall_vpe(struct its_vpe *vpe)
	262	{
	263	struct its_cmd_info info = {
	264	.cmd_type = INVALL_VPE,
	265	};
	266
	267	return its_send_vpe_cmd(vpe, &info);
	268	}
f2eac75d MZ	269
	270	int its_map_vlpi(int irq, struct its_vlpi_map *map)
	271	{
	272	struct its_cmd_info info = {
	273	.cmd_type = MAP_VLPI,
6c09ffd0 AB	274	{
	275	.map = map,
	276	},
f2eac75d	277	};
90dc7122	278	int ret;
f2eac75d MZ	279
	280	/*
	281	* The host will never see that interrupt firing again, so it
	282	* is vital that we don't do any lazy masking.
	283	*/
	284	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
	285
90dc7122 MZ	286	ret = irq_set_vcpu_affinity(irq, &info);
	287	if (ret)
	288	irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
	289
	290	return ret;
f2eac75d MZ	291	}
	292
	293	int its_get_vlpi(int irq, struct its_vlpi_map *map)
	294	{
	295	struct its_cmd_info info = {
	296	.cmd_type = GET_VLPI,
6c09ffd0 AB	297	{
	298	.map = map,
	299	},
f2eac75d MZ	300	};
	301
	302	return irq_set_vcpu_affinity(irq, &info);
	303	}
	304
	305	int its_unmap_vlpi(int irq)
	306	{
	307	irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
	308	return irq_set_vcpu_affinity(irq, NULL);
	309	}
	310
	311	int its_prop_update_vlpi(int irq, u8 config, bool inv)
	312	{
	313	struct its_cmd_info info = {
	314	.cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
6c09ffd0 AB	315	{
	316	.config = config,
	317	},
f2eac75d MZ	318	};
	319
	320	return irq_set_vcpu_affinity(irq, &info);
	321	}
3d63cb53	322
d50676f5 MZ	323	int its_prop_update_vsgi(int irq, u8 priority, bool group)
	324	{
	325	struct its_cmd_info info = {
	326	.cmd_type = PROP_UPDATE_VSGI,
	327	{
	328	.priority = priority,
	329	.group = group,
	330	},
	331	};
	332
	333	return irq_set_vcpu_affinity(irq, &info);
	334	}
	335
166cba71 MZ	336	int its_init_v4(struct irq_domain *domain,
	337	const struct irq_domain_ops *vpe_ops,
	338	const struct irq_domain_ops *sgi_ops)
3d63cb53 MZ	339	{
	340	if (domain) {
	341	pr_info("ITS: Enabling GICv4 support\n");
	342	gic_domain = domain;
166cba71 MZ	343	vpe_domain_ops = vpe_ops;
166cba71 MZ	344	sgi_domain_ops = sgi_ops;
3d63cb53 MZ	345	return 0;
	346	}
	347
	348	pr_err("ITS: No GICv4 VPE domain allocated\n");
	349	return -ENODEV;
	350	}