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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
ffa7d616 | 18 | #include <linux/acpi.h> |
021f6537 | 19 | #include <linux/cpu.h> |
3708d52f | 20 | #include <linux/cpu_pm.h> |
021f6537 MZ |
21 | #include <linux/delay.h> |
22 | #include <linux/interrupt.h> | |
ffa7d616 | 23 | #include <linux/irqdomain.h> |
021f6537 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/percpu.h> | |
28 | #include <linux/slab.h> | |
29 | ||
41a83e06 | 30 | #include <linux/irqchip.h> |
021f6537 MZ |
31 | #include <linux/irqchip/arm-gic-v3.h> |
32 | ||
33 | #include <asm/cputype.h> | |
34 | #include <asm/exception.h> | |
35 | #include <asm/smp_plat.h> | |
0b6a3da9 | 36 | #include <asm/virt.h> |
021f6537 MZ |
37 | |
38 | #include "irq-gic-common.h" | |
021f6537 | 39 | |
f5c1434c MZ |
40 | struct redist_region { |
41 | void __iomem *redist_base; | |
42 | phys_addr_t phys_base; | |
43 | }; | |
44 | ||
021f6537 MZ |
45 | struct gic_chip_data { |
46 | void __iomem *dist_base; | |
f5c1434c MZ |
47 | struct redist_region *redist_regions; |
48 | struct rdists rdists; | |
021f6537 MZ |
49 | struct irq_domain *domain; |
50 | u64 redist_stride; | |
f5c1434c | 51 | u32 nr_redist_regions; |
021f6537 MZ |
52 | unsigned int irq_nr; |
53 | }; | |
54 | ||
55 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 56 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 57 | |
f5c1434c MZ |
58 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
59 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
60 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
61 | ||
62 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
63 | #define DEFAULT_PMR_VALUE 0xf0 | |
64 | ||
65 | static inline unsigned int gic_irq(struct irq_data *d) | |
66 | { | |
67 | return d->hwirq; | |
68 | } | |
69 | ||
70 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
71 | { | |
72 | return gic_irq(d) < 32; | |
73 | } | |
74 | ||
75 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
76 | { | |
77 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
78 | return gic_data_rdist_sgi_base(); | |
79 | ||
80 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
81 | return gic_data.dist_base; | |
82 | ||
021f6537 MZ |
83 | return NULL; |
84 | } | |
85 | ||
86 | static void gic_do_wait_for_rwp(void __iomem *base) | |
87 | { | |
88 | u32 count = 1000000; /* 1s! */ | |
89 | ||
90 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
91 | count--; | |
92 | if (!count) { | |
93 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
94 | return; | |
95 | } | |
96 | cpu_relax(); | |
97 | udelay(1); | |
98 | }; | |
99 | } | |
100 | ||
101 | /* Wait for completion of a distributor change */ | |
102 | static void gic_dist_wait_for_rwp(void) | |
103 | { | |
104 | gic_do_wait_for_rwp(gic_data.dist_base); | |
105 | } | |
106 | ||
107 | /* Wait for completion of a redistributor change */ | |
108 | static void gic_redist_wait_for_rwp(void) | |
109 | { | |
110 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
111 | } | |
112 | ||
7936e914 | 113 | #ifdef CONFIG_ARM64 |
8ac2a170 | 114 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
6d4e11c5 RR |
115 | |
116 | static u64 __maybe_unused gic_read_iar(void) | |
117 | { | |
8ac2a170 | 118 | if (static_branch_unlikely(&is_cavium_thunderx)) |
6d4e11c5 RR |
119 | return gic_read_iar_cavium_thunderx(); |
120 | else | |
121 | return gic_read_iar_common(); | |
122 | } | |
7936e914 | 123 | #endif |
021f6537 | 124 | |
a2c22510 | 125 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
126 | { |
127 | void __iomem *rbase; | |
128 | u32 count = 1000000; /* 1s! */ | |
129 | u32 val; | |
130 | ||
131 | rbase = gic_data_rdist_rd_base(); | |
132 | ||
021f6537 | 133 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
134 | if (enable) |
135 | /* Wake up this CPU redistributor */ | |
136 | val &= ~GICR_WAKER_ProcessorSleep; | |
137 | else | |
138 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
139 | writel_relaxed(val, rbase + GICR_WAKER); |
140 | ||
a2c22510 SH |
141 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
142 | val = readl_relaxed(rbase + GICR_WAKER); | |
143 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
144 | return; /* No PM support in this redistributor */ | |
145 | } | |
146 | ||
147 | while (count--) { | |
148 | val = readl_relaxed(rbase + GICR_WAKER); | |
149 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
150 | break; | |
021f6537 MZ |
151 | cpu_relax(); |
152 | udelay(1); | |
153 | }; | |
a2c22510 SH |
154 | if (!count) |
155 | pr_err_ratelimited("redistributor failed to %s...\n", | |
156 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
157 | } |
158 | ||
159 | /* | |
160 | * Routines to disable, enable, EOI and route interrupts | |
161 | */ | |
b594c6e2 MZ |
162 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
163 | { | |
164 | u32 mask = 1 << (gic_irq(d) % 32); | |
165 | void __iomem *base; | |
166 | ||
167 | if (gic_irq_in_rdist(d)) | |
168 | base = gic_data_rdist_sgi_base(); | |
169 | else | |
170 | base = gic_data.dist_base; | |
171 | ||
172 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
173 | } | |
174 | ||
021f6537 MZ |
175 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
176 | { | |
177 | u32 mask = 1 << (gic_irq(d) % 32); | |
178 | void (*rwp_wait)(void); | |
179 | void __iomem *base; | |
180 | ||
181 | if (gic_irq_in_rdist(d)) { | |
182 | base = gic_data_rdist_sgi_base(); | |
183 | rwp_wait = gic_redist_wait_for_rwp; | |
184 | } else { | |
185 | base = gic_data.dist_base; | |
186 | rwp_wait = gic_dist_wait_for_rwp; | |
187 | } | |
188 | ||
189 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
190 | rwp_wait(); | |
191 | } | |
192 | ||
021f6537 MZ |
193 | static void gic_mask_irq(struct irq_data *d) |
194 | { | |
195 | gic_poke_irq(d, GICD_ICENABLER); | |
196 | } | |
197 | ||
0b6a3da9 MZ |
198 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
199 | { | |
200 | gic_mask_irq(d); | |
530bf353 MZ |
201 | /* |
202 | * When masking a forwarded interrupt, make sure it is | |
203 | * deactivated as well. | |
204 | * | |
205 | * This ensures that an interrupt that is getting | |
206 | * disabled/masked will not get "stuck", because there is | |
207 | * noone to deactivate it (guest is being terminated). | |
208 | */ | |
4df7f54d | 209 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 210 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
211 | } |
212 | ||
021f6537 MZ |
213 | static void gic_unmask_irq(struct irq_data *d) |
214 | { | |
215 | gic_poke_irq(d, GICD_ISENABLER); | |
216 | } | |
217 | ||
b594c6e2 MZ |
218 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
219 | enum irqchip_irq_state which, bool val) | |
220 | { | |
221 | u32 reg; | |
222 | ||
223 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
224 | return -EINVAL; | |
225 | ||
226 | switch (which) { | |
227 | case IRQCHIP_STATE_PENDING: | |
228 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
229 | break; | |
230 | ||
231 | case IRQCHIP_STATE_ACTIVE: | |
232 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
233 | break; | |
234 | ||
235 | case IRQCHIP_STATE_MASKED: | |
236 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
237 | break; | |
238 | ||
239 | default: | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | gic_poke_irq(d, reg); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
248 | enum irqchip_irq_state which, bool *val) | |
249 | { | |
250 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
251 | return -EINVAL; | |
252 | ||
253 | switch (which) { | |
254 | case IRQCHIP_STATE_PENDING: | |
255 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
256 | break; | |
257 | ||
258 | case IRQCHIP_STATE_ACTIVE: | |
259 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
260 | break; | |
261 | ||
262 | case IRQCHIP_STATE_MASKED: | |
263 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
264 | break; | |
265 | ||
266 | default: | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
021f6537 MZ |
273 | static void gic_eoi_irq(struct irq_data *d) |
274 | { | |
275 | gic_write_eoir(gic_irq(d)); | |
276 | } | |
277 | ||
0b6a3da9 MZ |
278 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
279 | { | |
280 | /* | |
530bf353 MZ |
281 | * No need to deactivate an LPI, or an interrupt that |
282 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 283 | */ |
4df7f54d | 284 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
285 | return; |
286 | gic_write_dir(gic_irq(d)); | |
287 | } | |
288 | ||
021f6537 MZ |
289 | static int gic_set_type(struct irq_data *d, unsigned int type) |
290 | { | |
291 | unsigned int irq = gic_irq(d); | |
292 | void (*rwp_wait)(void); | |
293 | void __iomem *base; | |
294 | ||
295 | /* Interrupt configuration for SGIs can't be changed */ | |
296 | if (irq < 16) | |
297 | return -EINVAL; | |
298 | ||
fb7e7deb LD |
299 | /* SPIs have restrictions on the supported types */ |
300 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
301 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
302 | return -EINVAL; |
303 | ||
304 | if (gic_irq_in_rdist(d)) { | |
305 | base = gic_data_rdist_sgi_base(); | |
306 | rwp_wait = gic_redist_wait_for_rwp; | |
307 | } else { | |
308 | base = gic_data.dist_base; | |
309 | rwp_wait = gic_dist_wait_for_rwp; | |
310 | } | |
311 | ||
fb7e7deb | 312 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
313 | } |
314 | ||
530bf353 MZ |
315 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
316 | { | |
4df7f54d TG |
317 | if (vcpu) |
318 | irqd_set_forwarded_to_vcpu(d); | |
319 | else | |
320 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
321 | return 0; |
322 | } | |
323 | ||
f6c86a41 | 324 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
325 | { |
326 | u64 aff; | |
327 | ||
f6c86a41 | 328 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
329 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
330 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
331 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
332 | ||
333 | return aff; | |
334 | } | |
335 | ||
336 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
337 | { | |
f6c86a41 | 338 | u32 irqnr; |
021f6537 MZ |
339 | |
340 | do { | |
341 | irqnr = gic_read_iar(); | |
342 | ||
da33f31d | 343 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 344 | int err; |
0b6a3da9 MZ |
345 | |
346 | if (static_key_true(&supports_deactivate)) | |
347 | gic_write_eoir(irqnr); | |
348 | ||
ebc6de00 MZ |
349 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
350 | if (err) { | |
da33f31d | 351 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
352 | if (static_key_true(&supports_deactivate)) { |
353 | if (irqnr < 8192) | |
354 | gic_write_dir(irqnr); | |
355 | } else { | |
356 | gic_write_eoir(irqnr); | |
357 | } | |
021f6537 | 358 | } |
ebc6de00 | 359 | continue; |
021f6537 MZ |
360 | } |
361 | if (irqnr < 16) { | |
362 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
363 | if (static_key_true(&supports_deactivate)) |
364 | gic_write_dir(irqnr); | |
021f6537 MZ |
365 | #ifdef CONFIG_SMP |
366 | handle_IPI(irqnr, regs); | |
367 | #else | |
368 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
369 | #endif | |
370 | continue; | |
371 | } | |
372 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
373 | } | |
374 | ||
375 | static void __init gic_dist_init(void) | |
376 | { | |
377 | unsigned int i; | |
378 | u64 affinity; | |
379 | void __iomem *base = gic_data.dist_base; | |
380 | ||
381 | /* Disable the distributor */ | |
382 | writel_relaxed(0, base + GICD_CTLR); | |
383 | gic_dist_wait_for_rwp(); | |
384 | ||
385 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
386 | ||
387 | /* Enable distributor with ARE, Group1 */ | |
388 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
389 | base + GICD_CTLR); | |
390 | ||
391 | /* | |
392 | * Set all global interrupts to the boot CPU only. ARE must be | |
393 | * enabled. | |
394 | */ | |
395 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
396 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 397 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
398 | } |
399 | ||
400 | static int gic_populate_rdist(void) | |
401 | { | |
f6c86a41 | 402 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
021f6537 MZ |
403 | u64 typer; |
404 | u32 aff; | |
405 | int i; | |
406 | ||
407 | /* | |
408 | * Convert affinity to a 32bit value that can be matched to | |
409 | * GICR_TYPER bits [63:32]. | |
410 | */ | |
411 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
412 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
413 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
414 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
415 | ||
f5c1434c MZ |
416 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
417 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
418 | u32 reg; |
419 | ||
420 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
421 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
422 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
423 | pr_warn("No redistributor present @%p\n", ptr); | |
424 | break; | |
425 | } | |
426 | ||
427 | do { | |
72c97126 | 428 | typer = gic_read_typer(ptr + GICR_TYPER); |
021f6537 | 429 | if ((typer >> 32) == aff) { |
f5c1434c | 430 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 431 | gic_data_rdist_rd_base() = ptr; |
f5c1434c | 432 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
f6c86a41 JPB |
433 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
434 | smp_processor_id(), mpidr, i, | |
435 | &gic_data_rdist()->phys_base); | |
021f6537 MZ |
436 | return 0; |
437 | } | |
438 | ||
439 | if (gic_data.redist_stride) { | |
440 | ptr += gic_data.redist_stride; | |
441 | } else { | |
442 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
443 | if (typer & GICR_TYPER_VLPIS) | |
444 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
445 | } | |
446 | } while (!(typer & GICR_TYPER_LAST)); | |
447 | } | |
448 | ||
449 | /* We couldn't even deal with ourselves... */ | |
f6c86a41 JPB |
450 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
451 | smp_processor_id(), mpidr); | |
021f6537 MZ |
452 | return -ENODEV; |
453 | } | |
454 | ||
3708d52f SH |
455 | static void gic_cpu_sys_reg_init(void) |
456 | { | |
7cabd008 MZ |
457 | /* |
458 | * Need to check that the SRE bit has actually been set. If | |
459 | * not, it means that SRE is disabled at EL2. We're going to | |
460 | * die painfully, and there is nothing we can do about it. | |
461 | * | |
462 | * Kindly inform the luser. | |
463 | */ | |
464 | if (!gic_enable_sre()) | |
465 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f SH |
466 | |
467 | /* Set priority mask register */ | |
468 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
469 | ||
0b6a3da9 MZ |
470 | if (static_key_true(&supports_deactivate)) { |
471 | /* EOI drops priority only (mode 1) */ | |
472 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
473 | } else { | |
474 | /* EOI deactivates interrupt too (mode 0) */ | |
475 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
476 | } | |
3708d52f SH |
477 | |
478 | /* ... and let's hit the road... */ | |
479 | gic_write_grpen1(1); | |
480 | } | |
481 | ||
da33f31d MZ |
482 | static int gic_dist_supports_lpis(void) |
483 | { | |
484 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
485 | } | |
486 | ||
021f6537 MZ |
487 | static void gic_cpu_init(void) |
488 | { | |
489 | void __iomem *rbase; | |
490 | ||
491 | /* Register ourselves with the rest of the world */ | |
492 | if (gic_populate_rdist()) | |
493 | return; | |
494 | ||
a2c22510 | 495 | gic_enable_redist(true); |
021f6537 MZ |
496 | |
497 | rbase = gic_data_rdist_sgi_base(); | |
498 | ||
499 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
500 | ||
da33f31d MZ |
501 | /* Give LPIs a spin */ |
502 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
503 | its_cpu_init(); | |
504 | ||
3708d52f SH |
505 | /* initialise system registers */ |
506 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
507 | } |
508 | ||
509 | #ifdef CONFIG_SMP | |
510 | static int gic_secondary_init(struct notifier_block *nfb, | |
511 | unsigned long action, void *hcpu) | |
512 | { | |
513 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
514 | gic_cpu_init(); | |
515 | return NOTIFY_OK; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
520 | * priority because the GIC needs to be up before the ARM generic timers. | |
521 | */ | |
522 | static struct notifier_block gic_cpu_notifier = { | |
523 | .notifier_call = gic_secondary_init, | |
524 | .priority = 100, | |
525 | }; | |
526 | ||
527 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
f6c86a41 | 528 | unsigned long cluster_id) |
021f6537 MZ |
529 | { |
530 | int cpu = *base_cpu; | |
f6c86a41 | 531 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
532 | u16 tlist = 0; |
533 | ||
534 | while (cpu < nr_cpu_ids) { | |
535 | /* | |
536 | * If we ever get a cluster of more than 16 CPUs, just | |
537 | * scream and skip that CPU. | |
538 | */ | |
539 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
540 | goto out; | |
541 | ||
542 | tlist |= 1 << (mpidr & 0xf); | |
543 | ||
544 | cpu = cpumask_next(cpu, mask); | |
614be385 | 545 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
546 | goto out; |
547 | ||
548 | mpidr = cpu_logical_map(cpu); | |
549 | ||
550 | if (cluster_id != (mpidr & ~0xffUL)) { | |
551 | cpu--; | |
552 | goto out; | |
553 | } | |
554 | } | |
555 | out: | |
556 | *base_cpu = cpu; | |
557 | return tlist; | |
558 | } | |
559 | ||
7e580278 AP |
560 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
561 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
562 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
563 | ||
021f6537 MZ |
564 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
565 | { | |
566 | u64 val; | |
567 | ||
7e580278 AP |
568 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
569 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
570 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
571 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
572 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
573 | |
574 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
575 | gic_write_sgi1r(val); | |
576 | } | |
577 | ||
578 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
579 | { | |
580 | int cpu; | |
581 | ||
582 | if (WARN_ON(irq >= 16)) | |
583 | return; | |
584 | ||
585 | /* | |
586 | * Ensure that stores to Normal memory are visible to the | |
587 | * other CPUs before issuing the IPI. | |
588 | */ | |
589 | smp_wmb(); | |
590 | ||
f9b531fe | 591 | for_each_cpu(cpu, mask) { |
f6c86a41 | 592 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
021f6537 MZ |
593 | u16 tlist; |
594 | ||
595 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
596 | gic_send_sgi(cluster_id, tlist, irq); | |
597 | } | |
598 | ||
599 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
600 | isb(); | |
601 | } | |
602 | ||
603 | static void gic_smp_init(void) | |
604 | { | |
605 | set_smp_cross_call(gic_raise_softirq); | |
606 | register_cpu_notifier(&gic_cpu_notifier); | |
607 | } | |
608 | ||
609 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
610 | bool force) | |
611 | { | |
612 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
613 | void __iomem *reg; | |
614 | int enabled; | |
615 | u64 val; | |
616 | ||
617 | if (gic_irq_in_rdist(d)) | |
618 | return -EINVAL; | |
619 | ||
620 | /* If interrupt was enabled, disable it first */ | |
621 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
622 | if (enabled) | |
623 | gic_mask_irq(d); | |
624 | ||
625 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
626 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
627 | ||
72c97126 | 628 | gic_write_irouter(val, reg); |
021f6537 MZ |
629 | |
630 | /* | |
631 | * If the interrupt was enabled, enabled it again. Otherwise, | |
632 | * just wait for the distributor to have digested our changes. | |
633 | */ | |
634 | if (enabled) | |
635 | gic_unmask_irq(d); | |
636 | else | |
637 | gic_dist_wait_for_rwp(); | |
638 | ||
639 | return IRQ_SET_MASK_OK; | |
640 | } | |
641 | #else | |
642 | #define gic_set_affinity NULL | |
643 | #define gic_smp_init() do { } while(0) | |
644 | #endif | |
645 | ||
3708d52f SH |
646 | #ifdef CONFIG_CPU_PM |
647 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
648 | unsigned long cmd, void *v) | |
649 | { | |
650 | if (cmd == CPU_PM_EXIT) { | |
651 | gic_enable_redist(true); | |
652 | gic_cpu_sys_reg_init(); | |
653 | } else if (cmd == CPU_PM_ENTER) { | |
654 | gic_write_grpen1(0); | |
655 | gic_enable_redist(false); | |
656 | } | |
657 | return NOTIFY_OK; | |
658 | } | |
659 | ||
660 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
661 | .notifier_call = gic_cpu_pm_notifier, | |
662 | }; | |
663 | ||
664 | static void gic_cpu_pm_init(void) | |
665 | { | |
666 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
667 | } | |
668 | ||
669 | #else | |
670 | static inline void gic_cpu_pm_init(void) { } | |
671 | #endif /* CONFIG_CPU_PM */ | |
672 | ||
021f6537 MZ |
673 | static struct irq_chip gic_chip = { |
674 | .name = "GICv3", | |
675 | .irq_mask = gic_mask_irq, | |
676 | .irq_unmask = gic_unmask_irq, | |
677 | .irq_eoi = gic_eoi_irq, | |
678 | .irq_set_type = gic_set_type, | |
679 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
680 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
681 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 682 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
683 | }; |
684 | ||
0b6a3da9 MZ |
685 | static struct irq_chip gic_eoimode1_chip = { |
686 | .name = "GICv3", | |
687 | .irq_mask = gic_eoimode1_mask_irq, | |
688 | .irq_unmask = gic_unmask_irq, | |
689 | .irq_eoi = gic_eoimode1_eoi_irq, | |
690 | .irq_set_type = gic_set_type, | |
691 | .irq_set_affinity = gic_set_affinity, | |
692 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
693 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 694 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
695 | .flags = IRQCHIP_SET_TYPE_MASKED, |
696 | }; | |
697 | ||
da33f31d MZ |
698 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
699 | ||
021f6537 MZ |
700 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
701 | irq_hw_number_t hw) | |
702 | { | |
0b6a3da9 MZ |
703 | struct irq_chip *chip = &gic_chip; |
704 | ||
705 | if (static_key_true(&supports_deactivate)) | |
706 | chip = &gic_eoimode1_chip; | |
707 | ||
021f6537 MZ |
708 | /* SGIs are private to the core kernel */ |
709 | if (hw < 16) | |
710 | return -EPERM; | |
da33f31d MZ |
711 | /* Nothing here */ |
712 | if (hw >= gic_data.irq_nr && hw < 8192) | |
713 | return -EPERM; | |
714 | /* Off limits */ | |
715 | if (hw >= GIC_ID_NR) | |
716 | return -EPERM; | |
717 | ||
021f6537 MZ |
718 | /* PPIs */ |
719 | if (hw < 32) { | |
720 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 721 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 722 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 723 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
724 | } |
725 | /* SPIs */ | |
726 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 727 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 728 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 729 | irq_set_probe(irq); |
021f6537 | 730 | } |
da33f31d MZ |
731 | /* LPIs */ |
732 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
733 | if (!gic_dist_supports_lpis()) | |
734 | return -EPERM; | |
0b6a3da9 | 735 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 736 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
737 | } |
738 | ||
021f6537 MZ |
739 | return 0; |
740 | } | |
741 | ||
f833f57f MZ |
742 | static int gic_irq_domain_translate(struct irq_domain *d, |
743 | struct irq_fwspec *fwspec, | |
744 | unsigned long *hwirq, | |
745 | unsigned int *type) | |
021f6537 | 746 | { |
f833f57f MZ |
747 | if (is_of_node(fwspec->fwnode)) { |
748 | if (fwspec->param_count < 3) | |
749 | return -EINVAL; | |
021f6537 | 750 | |
db8c70ec MZ |
751 | switch (fwspec->param[0]) { |
752 | case 0: /* SPI */ | |
753 | *hwirq = fwspec->param[1] + 32; | |
754 | break; | |
755 | case 1: /* PPI */ | |
756 | *hwirq = fwspec->param[1] + 16; | |
757 | break; | |
758 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
759 | *hwirq = fwspec->param[1]; | |
760 | break; | |
761 | default: | |
762 | return -EINVAL; | |
763 | } | |
f833f57f MZ |
764 | |
765 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
766 | return 0; | |
021f6537 MZ |
767 | } |
768 | ||
ffa7d616 TN |
769 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
770 | if(fwspec->param_count != 2) | |
771 | return -EINVAL; | |
772 | ||
773 | *hwirq = fwspec->param[0]; | |
774 | *type = fwspec->param[1]; | |
775 | return 0; | |
776 | } | |
777 | ||
f833f57f | 778 | return -EINVAL; |
021f6537 MZ |
779 | } |
780 | ||
443acc4f MZ |
781 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
782 | unsigned int nr_irqs, void *arg) | |
783 | { | |
784 | int i, ret; | |
785 | irq_hw_number_t hwirq; | |
786 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 787 | struct irq_fwspec *fwspec = arg; |
443acc4f | 788 | |
f833f57f | 789 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
790 | if (ret) |
791 | return ret; | |
792 | ||
793 | for (i = 0; i < nr_irqs; i++) | |
794 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
800 | unsigned int nr_irqs) | |
801 | { | |
802 | int i; | |
803 | ||
804 | for (i = 0; i < nr_irqs; i++) { | |
805 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
806 | irq_set_handler(virq + i, NULL); | |
807 | irq_domain_reset_irq_data(d); | |
808 | } | |
809 | } | |
810 | ||
021f6537 | 811 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 812 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
813 | .alloc = gic_irq_domain_alloc, |
814 | .free = gic_irq_domain_free, | |
021f6537 MZ |
815 | }; |
816 | ||
6d4e11c5 RR |
817 | static void gicv3_enable_quirks(void) |
818 | { | |
7936e914 | 819 | #ifdef CONFIG_ARM64 |
6d4e11c5 | 820 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
8ac2a170 | 821 | static_branch_enable(&is_cavium_thunderx); |
7936e914 | 822 | #endif |
6d4e11c5 RR |
823 | } |
824 | ||
db57d746 TN |
825 | static int __init gic_init_bases(void __iomem *dist_base, |
826 | struct redist_region *rdist_regs, | |
827 | u32 nr_redist_regions, | |
828 | u64 redist_stride, | |
829 | struct fwnode_handle *handle) | |
021f6537 | 830 | { |
db57d746 | 831 | struct device_node *node; |
f5c1434c | 832 | u32 typer; |
021f6537 MZ |
833 | int gic_irqs; |
834 | int err; | |
021f6537 | 835 | |
0b6a3da9 MZ |
836 | if (!is_hyp_mode_available()) |
837 | static_key_slow_dec(&supports_deactivate); | |
838 | ||
839 | if (static_key_true(&supports_deactivate)) | |
840 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
841 | ||
021f6537 | 842 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
843 | gic_data.redist_regions = rdist_regs; |
844 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
845 | gic_data.redist_stride = redist_stride; |
846 | ||
6d4e11c5 RR |
847 | gicv3_enable_quirks(); |
848 | ||
021f6537 MZ |
849 | /* |
850 | * Find out how many interrupts are supported. | |
851 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
852 | */ | |
f5c1434c MZ |
853 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
854 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
855 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
856 | if (gic_irqs > 1020) |
857 | gic_irqs = 1020; | |
858 | gic_data.irq_nr = gic_irqs; | |
859 | ||
db57d746 TN |
860 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
861 | &gic_data); | |
f5c1434c | 862 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 863 | |
f5c1434c | 864 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
865 | err = -ENOMEM; |
866 | goto out_free; | |
867 | } | |
868 | ||
869 | set_handle_irq(gic_handle_irq); | |
870 | ||
db57d746 TN |
871 | node = to_of_node(handle); |
872 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && | |
873 | node) /* Temp hack to prevent ITS init for ACPI */ | |
da33f31d MZ |
874 | its_init(node, &gic_data.rdists, gic_data.domain); |
875 | ||
021f6537 MZ |
876 | gic_smp_init(); |
877 | gic_dist_init(); | |
878 | gic_cpu_init(); | |
3708d52f | 879 | gic_cpu_pm_init(); |
021f6537 MZ |
880 | |
881 | return 0; | |
882 | ||
883 | out_free: | |
884 | if (gic_data.domain) | |
885 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 886 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
887 | return err; |
888 | } | |
889 | ||
890 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
891 | { | |
892 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
893 | ||
894 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
895 | return -ENODEV; | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
901 | { | |
902 | void __iomem *dist_base; | |
903 | struct redist_region *rdist_regs; | |
904 | u64 redist_stride; | |
905 | u32 nr_redist_regions; | |
906 | int err, i; | |
907 | ||
908 | dist_base = of_iomap(node, 0); | |
909 | if (!dist_base) { | |
910 | pr_err("%s: unable to map gic dist registers\n", | |
911 | node->full_name); | |
912 | return -ENXIO; | |
913 | } | |
914 | ||
915 | err = gic_validate_dist_version(dist_base); | |
916 | if (err) { | |
917 | pr_err("%s: no distributor detected, giving up\n", | |
918 | node->full_name); | |
919 | goto out_unmap_dist; | |
920 | } | |
921 | ||
922 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
923 | nr_redist_regions = 1; | |
924 | ||
925 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); | |
926 | if (!rdist_regs) { | |
927 | err = -ENOMEM; | |
928 | goto out_unmap_dist; | |
929 | } | |
930 | ||
931 | for (i = 0; i < nr_redist_regions; i++) { | |
932 | struct resource res; | |
933 | int ret; | |
934 | ||
935 | ret = of_address_to_resource(node, 1 + i, &res); | |
936 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
937 | if (ret || !rdist_regs[i].redist_base) { | |
938 | pr_err("%s: couldn't map region %d\n", | |
939 | node->full_name, i); | |
940 | err = -ENODEV; | |
941 | goto out_unmap_rdist; | |
942 | } | |
943 | rdist_regs[i].phys_base = res.start; | |
944 | } | |
945 | ||
946 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
947 | redist_stride = 0; | |
948 | ||
949 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
950 | redist_stride, &node->fwnode); | |
951 | if (!err) | |
952 | return 0; | |
953 | ||
021f6537 | 954 | out_unmap_rdist: |
f5c1434c MZ |
955 | for (i = 0; i < nr_redist_regions; i++) |
956 | if (rdist_regs[i].redist_base) | |
957 | iounmap(rdist_regs[i].redist_base); | |
958 | kfree(rdist_regs); | |
021f6537 MZ |
959 | out_unmap_dist: |
960 | iounmap(dist_base); | |
961 | return err; | |
962 | } | |
963 | ||
964 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
965 | |
966 | #ifdef CONFIG_ACPI | |
967 | static struct redist_region *redist_regs __initdata; | |
968 | static u32 nr_redist_regions __initdata; | |
969 | ||
970 | static int __init | |
971 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
972 | const unsigned long end) | |
973 | { | |
974 | struct acpi_madt_generic_redistributor *redist = | |
975 | (struct acpi_madt_generic_redistributor *)header; | |
976 | void __iomem *redist_base; | |
977 | static int count = 0; | |
978 | ||
979 | redist_base = ioremap(redist->base_address, redist->length); | |
980 | if (!redist_base) { | |
981 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
982 | return -ENOMEM; | |
983 | } | |
984 | ||
985 | redist_regs[count].phys_base = redist->base_address; | |
986 | redist_regs[count].redist_base = redist_base; | |
987 | count++; | |
988 | return 0; | |
989 | } | |
990 | ||
991 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, | |
992 | const unsigned long end) | |
993 | { | |
994 | /* Subtable presence means that redist exists, that's it */ | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, | |
999 | struct acpi_probe_entry *ape) | |
1000 | { | |
1001 | struct acpi_madt_generic_distributor *dist; | |
1002 | int count; | |
1003 | ||
1004 | dist = (struct acpi_madt_generic_distributor *)header; | |
1005 | if (dist->version != ape->driver_data) | |
1006 | return false; | |
1007 | ||
1008 | /* We need to do that exercise anyway, the sooner the better */ | |
1009 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1010 | gic_acpi_match_gicr, 0); | |
1011 | if (count <= 0) | |
1012 | return false; | |
1013 | ||
1014 | nr_redist_regions = count; | |
1015 | return true; | |
1016 | } | |
1017 | ||
1018 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) | |
1019 | ||
1020 | static int __init | |
1021 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1022 | { | |
1023 | struct acpi_madt_generic_distributor *dist; | |
1024 | struct fwnode_handle *domain_handle; | |
1025 | void __iomem *dist_base; | |
1026 | int i, err, count; | |
1027 | ||
1028 | /* Get distributor base address */ | |
1029 | dist = (struct acpi_madt_generic_distributor *)header; | |
1030 | dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); | |
1031 | if (!dist_base) { | |
1032 | pr_err("Unable to map GICD registers\n"); | |
1033 | return -ENOMEM; | |
1034 | } | |
1035 | ||
1036 | err = gic_validate_dist_version(dist_base); | |
1037 | if (err) { | |
1038 | pr_err("No distributor detected at @%p, giving up", dist_base); | |
1039 | goto out_dist_unmap; | |
1040 | } | |
1041 | ||
1042 | redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, | |
1043 | GFP_KERNEL); | |
1044 | if (!redist_regs) { | |
1045 | err = -ENOMEM; | |
1046 | goto out_dist_unmap; | |
1047 | } | |
1048 | ||
1049 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1050 | gic_acpi_parse_madt_redist, 0); | |
1051 | if (count <= 0) { | |
1052 | err = -ENODEV; | |
1053 | goto out_redist_unmap; | |
1054 | } | |
1055 | ||
1056 | domain_handle = irq_domain_alloc_fwnode(dist_base); | |
1057 | if (!domain_handle) { | |
1058 | err = -ENOMEM; | |
1059 | goto out_redist_unmap; | |
1060 | } | |
1061 | ||
1062 | err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, | |
1063 | domain_handle); | |
1064 | if (err) | |
1065 | goto out_fwhandle_free; | |
1066 | ||
1067 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
1068 | return 0; | |
1069 | ||
1070 | out_fwhandle_free: | |
1071 | irq_domain_free_fwnode(domain_handle); | |
1072 | out_redist_unmap: | |
1073 | for (i = 0; i < nr_redist_regions; i++) | |
1074 | if (redist_regs[i].redist_base) | |
1075 | iounmap(redist_regs[i].redist_base); | |
1076 | kfree(redist_regs); | |
1077 | out_dist_unmap: | |
1078 | iounmap(dist_base); | |
1079 | return err; | |
1080 | } | |
1081 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1082 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1083 | gic_acpi_init); | |
1084 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1085 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1086 | gic_acpi_init); | |
1087 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1088 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1089 | gic_acpi_init); | |
1090 | #endif |