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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/cpu.h> | |
3708d52f | 19 | #include <linux/cpu_pm.h> |
021f6537 MZ |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/percpu.h> | |
26 | #include <linux/slab.h> | |
27 | ||
41a83e06 | 28 | #include <linux/irqchip.h> |
021f6537 MZ |
29 | #include <linux/irqchip/arm-gic-v3.h> |
30 | ||
31 | #include <asm/cputype.h> | |
32 | #include <asm/exception.h> | |
33 | #include <asm/smp_plat.h> | |
0b6a3da9 | 34 | #include <asm/virt.h> |
021f6537 MZ |
35 | |
36 | #include "irq-gic-common.h" | |
021f6537 | 37 | |
f5c1434c MZ |
38 | struct redist_region { |
39 | void __iomem *redist_base; | |
40 | phys_addr_t phys_base; | |
41 | }; | |
42 | ||
021f6537 MZ |
43 | struct gic_chip_data { |
44 | void __iomem *dist_base; | |
f5c1434c MZ |
45 | struct redist_region *redist_regions; |
46 | struct rdists rdists; | |
021f6537 MZ |
47 | struct irq_domain *domain; |
48 | u64 redist_stride; | |
f5c1434c | 49 | u32 nr_redist_regions; |
021f6537 MZ |
50 | unsigned int irq_nr; |
51 | }; | |
52 | ||
53 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 54 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 55 | |
f5c1434c MZ |
56 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
57 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
58 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
59 | ||
60 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
61 | #define DEFAULT_PMR_VALUE 0xf0 | |
62 | ||
63 | static inline unsigned int gic_irq(struct irq_data *d) | |
64 | { | |
65 | return d->hwirq; | |
66 | } | |
67 | ||
68 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
69 | { | |
70 | return gic_irq(d) < 32; | |
71 | } | |
72 | ||
73 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
74 | { | |
75 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
76 | return gic_data_rdist_sgi_base(); | |
77 | ||
78 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
79 | return gic_data.dist_base; | |
80 | ||
021f6537 MZ |
81 | return NULL; |
82 | } | |
83 | ||
84 | static void gic_do_wait_for_rwp(void __iomem *base) | |
85 | { | |
86 | u32 count = 1000000; /* 1s! */ | |
87 | ||
88 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
89 | count--; | |
90 | if (!count) { | |
91 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
92 | return; | |
93 | } | |
94 | cpu_relax(); | |
95 | udelay(1); | |
96 | }; | |
97 | } | |
98 | ||
99 | /* Wait for completion of a distributor change */ | |
100 | static void gic_dist_wait_for_rwp(void) | |
101 | { | |
102 | gic_do_wait_for_rwp(gic_data.dist_base); | |
103 | } | |
104 | ||
105 | /* Wait for completion of a redistributor change */ | |
106 | static void gic_redist_wait_for_rwp(void) | |
107 | { | |
108 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
109 | } | |
110 | ||
111 | /* Low level accessors */ | |
6d4e11c5 | 112 | static u64 gic_read_iar_common(void) |
021f6537 MZ |
113 | { |
114 | u64 irqstat; | |
115 | ||
72c58395 | 116 | asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); |
021f6537 MZ |
117 | return irqstat; |
118 | } | |
119 | ||
6d4e11c5 RR |
120 | /* |
121 | * Cavium ThunderX erratum 23154 | |
122 | * | |
123 | * The gicv3 of ThunderX requires a modified version for reading the | |
124 | * IAR status to ensure data synchronization (access to icc_iar1_el1 | |
125 | * is not sync'ed before and after). | |
126 | */ | |
127 | static u64 gic_read_iar_cavium_thunderx(void) | |
128 | { | |
129 | u64 irqstat; | |
130 | ||
131 | asm volatile( | |
132 | "nop;nop;nop;nop\n\t" | |
133 | "nop;nop;nop;nop\n\t" | |
134 | "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t" | |
135 | "nop;nop;nop;nop" | |
136 | : "=r" (irqstat)); | |
137 | mb(); | |
138 | ||
139 | return irqstat; | |
140 | } | |
141 | ||
8ac2a170 | 142 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
6d4e11c5 RR |
143 | |
144 | static u64 __maybe_unused gic_read_iar(void) | |
145 | { | |
8ac2a170 | 146 | if (static_branch_unlikely(&is_cavium_thunderx)) |
6d4e11c5 RR |
147 | return gic_read_iar_cavium_thunderx(); |
148 | else | |
149 | return gic_read_iar_common(); | |
150 | } | |
151 | ||
c44e9d77 | 152 | static void __maybe_unused gic_write_pmr(u64 val) |
021f6537 | 153 | { |
72c58395 | 154 | asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
155 | } |
156 | ||
c44e9d77 | 157 | static void __maybe_unused gic_write_ctlr(u64 val) |
021f6537 | 158 | { |
72c58395 | 159 | asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
160 | isb(); |
161 | } | |
162 | ||
c44e9d77 | 163 | static void __maybe_unused gic_write_grpen1(u64 val) |
021f6537 | 164 | { |
72c58395 | 165 | asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
166 | isb(); |
167 | } | |
168 | ||
c44e9d77 | 169 | static void __maybe_unused gic_write_sgi1r(u64 val) |
021f6537 | 170 | { |
72c58395 | 171 | asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
172 | } |
173 | ||
174 | static void gic_enable_sre(void) | |
175 | { | |
176 | u64 val; | |
177 | ||
72c58395 | 178 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 | 179 | val |= ICC_SRE_EL1_SRE; |
72c58395 | 180 | asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
181 | isb(); |
182 | ||
183 | /* | |
184 | * Need to check that the SRE bit has actually been set. If | |
185 | * not, it means that SRE is disabled at EL2. We're going to | |
186 | * die painfully, and there is nothing we can do about it. | |
187 | * | |
188 | * Kindly inform the luser. | |
189 | */ | |
72c58395 | 190 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 MZ |
191 | if (!(val & ICC_SRE_EL1_SRE)) |
192 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
193 | } | |
194 | ||
a2c22510 | 195 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
196 | { |
197 | void __iomem *rbase; | |
198 | u32 count = 1000000; /* 1s! */ | |
199 | u32 val; | |
200 | ||
201 | rbase = gic_data_rdist_rd_base(); | |
202 | ||
021f6537 | 203 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
204 | if (enable) |
205 | /* Wake up this CPU redistributor */ | |
206 | val &= ~GICR_WAKER_ProcessorSleep; | |
207 | else | |
208 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
209 | writel_relaxed(val, rbase + GICR_WAKER); |
210 | ||
a2c22510 SH |
211 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
212 | val = readl_relaxed(rbase + GICR_WAKER); | |
213 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
214 | return; /* No PM support in this redistributor */ | |
215 | } | |
216 | ||
217 | while (count--) { | |
218 | val = readl_relaxed(rbase + GICR_WAKER); | |
219 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
220 | break; | |
021f6537 MZ |
221 | cpu_relax(); |
222 | udelay(1); | |
223 | }; | |
a2c22510 SH |
224 | if (!count) |
225 | pr_err_ratelimited("redistributor failed to %s...\n", | |
226 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
227 | } |
228 | ||
229 | /* | |
230 | * Routines to disable, enable, EOI and route interrupts | |
231 | */ | |
b594c6e2 MZ |
232 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
233 | { | |
234 | u32 mask = 1 << (gic_irq(d) % 32); | |
235 | void __iomem *base; | |
236 | ||
237 | if (gic_irq_in_rdist(d)) | |
238 | base = gic_data_rdist_sgi_base(); | |
239 | else | |
240 | base = gic_data.dist_base; | |
241 | ||
242 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
243 | } | |
244 | ||
021f6537 MZ |
245 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
246 | { | |
247 | u32 mask = 1 << (gic_irq(d) % 32); | |
248 | void (*rwp_wait)(void); | |
249 | void __iomem *base; | |
250 | ||
251 | if (gic_irq_in_rdist(d)) { | |
252 | base = gic_data_rdist_sgi_base(); | |
253 | rwp_wait = gic_redist_wait_for_rwp; | |
254 | } else { | |
255 | base = gic_data.dist_base; | |
256 | rwp_wait = gic_dist_wait_for_rwp; | |
257 | } | |
258 | ||
259 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
260 | rwp_wait(); | |
261 | } | |
262 | ||
021f6537 MZ |
263 | static void gic_mask_irq(struct irq_data *d) |
264 | { | |
265 | gic_poke_irq(d, GICD_ICENABLER); | |
266 | } | |
267 | ||
0b6a3da9 MZ |
268 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
269 | { | |
270 | gic_mask_irq(d); | |
530bf353 MZ |
271 | /* |
272 | * When masking a forwarded interrupt, make sure it is | |
273 | * deactivated as well. | |
274 | * | |
275 | * This ensures that an interrupt that is getting | |
276 | * disabled/masked will not get "stuck", because there is | |
277 | * noone to deactivate it (guest is being terminated). | |
278 | */ | |
4df7f54d | 279 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 280 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
281 | } |
282 | ||
021f6537 MZ |
283 | static void gic_unmask_irq(struct irq_data *d) |
284 | { | |
285 | gic_poke_irq(d, GICD_ISENABLER); | |
286 | } | |
287 | ||
b594c6e2 MZ |
288 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
289 | enum irqchip_irq_state which, bool val) | |
290 | { | |
291 | u32 reg; | |
292 | ||
293 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
294 | return -EINVAL; | |
295 | ||
296 | switch (which) { | |
297 | case IRQCHIP_STATE_PENDING: | |
298 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
299 | break; | |
300 | ||
301 | case IRQCHIP_STATE_ACTIVE: | |
302 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
303 | break; | |
304 | ||
305 | case IRQCHIP_STATE_MASKED: | |
306 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
307 | break; | |
308 | ||
309 | default: | |
310 | return -EINVAL; | |
311 | } | |
312 | ||
313 | gic_poke_irq(d, reg); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
318 | enum irqchip_irq_state which, bool *val) | |
319 | { | |
320 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
321 | return -EINVAL; | |
322 | ||
323 | switch (which) { | |
324 | case IRQCHIP_STATE_PENDING: | |
325 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
326 | break; | |
327 | ||
328 | case IRQCHIP_STATE_ACTIVE: | |
329 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
330 | break; | |
331 | ||
332 | case IRQCHIP_STATE_MASKED: | |
333 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
334 | break; | |
335 | ||
336 | default: | |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
021f6537 MZ |
343 | static void gic_eoi_irq(struct irq_data *d) |
344 | { | |
345 | gic_write_eoir(gic_irq(d)); | |
346 | } | |
347 | ||
0b6a3da9 MZ |
348 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
349 | { | |
350 | /* | |
530bf353 MZ |
351 | * No need to deactivate an LPI, or an interrupt that |
352 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 353 | */ |
4df7f54d | 354 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
355 | return; |
356 | gic_write_dir(gic_irq(d)); | |
357 | } | |
358 | ||
021f6537 MZ |
359 | static int gic_set_type(struct irq_data *d, unsigned int type) |
360 | { | |
361 | unsigned int irq = gic_irq(d); | |
362 | void (*rwp_wait)(void); | |
363 | void __iomem *base; | |
364 | ||
365 | /* Interrupt configuration for SGIs can't be changed */ | |
366 | if (irq < 16) | |
367 | return -EINVAL; | |
368 | ||
fb7e7deb LD |
369 | /* SPIs have restrictions on the supported types */ |
370 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
371 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
372 | return -EINVAL; |
373 | ||
374 | if (gic_irq_in_rdist(d)) { | |
375 | base = gic_data_rdist_sgi_base(); | |
376 | rwp_wait = gic_redist_wait_for_rwp; | |
377 | } else { | |
378 | base = gic_data.dist_base; | |
379 | rwp_wait = gic_dist_wait_for_rwp; | |
380 | } | |
381 | ||
fb7e7deb | 382 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
383 | } |
384 | ||
530bf353 MZ |
385 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
386 | { | |
4df7f54d TG |
387 | if (vcpu) |
388 | irqd_set_forwarded_to_vcpu(d); | |
389 | else | |
390 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
391 | return 0; |
392 | } | |
393 | ||
021f6537 MZ |
394 | static u64 gic_mpidr_to_affinity(u64 mpidr) |
395 | { | |
396 | u64 aff; | |
397 | ||
398 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | | |
399 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
400 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
401 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
402 | ||
403 | return aff; | |
404 | } | |
405 | ||
406 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
407 | { | |
408 | u64 irqnr; | |
409 | ||
410 | do { | |
411 | irqnr = gic_read_iar(); | |
412 | ||
da33f31d | 413 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 414 | int err; |
0b6a3da9 MZ |
415 | |
416 | if (static_key_true(&supports_deactivate)) | |
417 | gic_write_eoir(irqnr); | |
418 | ||
ebc6de00 MZ |
419 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
420 | if (err) { | |
da33f31d | 421 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
422 | if (static_key_true(&supports_deactivate)) { |
423 | if (irqnr < 8192) | |
424 | gic_write_dir(irqnr); | |
425 | } else { | |
426 | gic_write_eoir(irqnr); | |
427 | } | |
021f6537 | 428 | } |
ebc6de00 | 429 | continue; |
021f6537 MZ |
430 | } |
431 | if (irqnr < 16) { | |
432 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
433 | if (static_key_true(&supports_deactivate)) |
434 | gic_write_dir(irqnr); | |
021f6537 MZ |
435 | #ifdef CONFIG_SMP |
436 | handle_IPI(irqnr, regs); | |
437 | #else | |
438 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
439 | #endif | |
440 | continue; | |
441 | } | |
442 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
443 | } | |
444 | ||
445 | static void __init gic_dist_init(void) | |
446 | { | |
447 | unsigned int i; | |
448 | u64 affinity; | |
449 | void __iomem *base = gic_data.dist_base; | |
450 | ||
451 | /* Disable the distributor */ | |
452 | writel_relaxed(0, base + GICD_CTLR); | |
453 | gic_dist_wait_for_rwp(); | |
454 | ||
455 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
456 | ||
457 | /* Enable distributor with ARE, Group1 */ | |
458 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
459 | base + GICD_CTLR); | |
460 | ||
461 | /* | |
462 | * Set all global interrupts to the boot CPU only. ARE must be | |
463 | * enabled. | |
464 | */ | |
465 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
466 | for (i = 32; i < gic_data.irq_nr; i++) | |
467 | writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); | |
468 | } | |
469 | ||
470 | static int gic_populate_rdist(void) | |
471 | { | |
472 | u64 mpidr = cpu_logical_map(smp_processor_id()); | |
473 | u64 typer; | |
474 | u32 aff; | |
475 | int i; | |
476 | ||
477 | /* | |
478 | * Convert affinity to a 32bit value that can be matched to | |
479 | * GICR_TYPER bits [63:32]. | |
480 | */ | |
481 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
482 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
483 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
484 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
485 | ||
f5c1434c MZ |
486 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
487 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
488 | u32 reg; |
489 | ||
490 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
491 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
492 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
493 | pr_warn("No redistributor present @%p\n", ptr); | |
494 | break; | |
495 | } | |
496 | ||
497 | do { | |
498 | typer = readq_relaxed(ptr + GICR_TYPER); | |
499 | if ((typer >> 32) == aff) { | |
f5c1434c | 500 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 501 | gic_data_rdist_rd_base() = ptr; |
f5c1434c MZ |
502 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
503 | pr_info("CPU%d: found redistributor %llx region %d:%pa\n", | |
021f6537 | 504 | smp_processor_id(), |
f5c1434c MZ |
505 | (unsigned long long)mpidr, |
506 | i, &gic_data_rdist()->phys_base); | |
021f6537 MZ |
507 | return 0; |
508 | } | |
509 | ||
510 | if (gic_data.redist_stride) { | |
511 | ptr += gic_data.redist_stride; | |
512 | } else { | |
513 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
514 | if (typer & GICR_TYPER_VLPIS) | |
515 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
516 | } | |
517 | } while (!(typer & GICR_TYPER_LAST)); | |
518 | } | |
519 | ||
520 | /* We couldn't even deal with ourselves... */ | |
521 | WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", | |
522 | smp_processor_id(), (unsigned long long)mpidr); | |
523 | return -ENODEV; | |
524 | } | |
525 | ||
3708d52f SH |
526 | static void gic_cpu_sys_reg_init(void) |
527 | { | |
528 | /* Enable system registers */ | |
529 | gic_enable_sre(); | |
530 | ||
531 | /* Set priority mask register */ | |
532 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
533 | ||
0b6a3da9 MZ |
534 | if (static_key_true(&supports_deactivate)) { |
535 | /* EOI drops priority only (mode 1) */ | |
536 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
537 | } else { | |
538 | /* EOI deactivates interrupt too (mode 0) */ | |
539 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
540 | } | |
3708d52f SH |
541 | |
542 | /* ... and let's hit the road... */ | |
543 | gic_write_grpen1(1); | |
544 | } | |
545 | ||
da33f31d MZ |
546 | static int gic_dist_supports_lpis(void) |
547 | { | |
548 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
549 | } | |
550 | ||
021f6537 MZ |
551 | static void gic_cpu_init(void) |
552 | { | |
553 | void __iomem *rbase; | |
554 | ||
555 | /* Register ourselves with the rest of the world */ | |
556 | if (gic_populate_rdist()) | |
557 | return; | |
558 | ||
a2c22510 | 559 | gic_enable_redist(true); |
021f6537 MZ |
560 | |
561 | rbase = gic_data_rdist_sgi_base(); | |
562 | ||
563 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
564 | ||
da33f31d MZ |
565 | /* Give LPIs a spin */ |
566 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
567 | its_cpu_init(); | |
568 | ||
3708d52f SH |
569 | /* initialise system registers */ |
570 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
571 | } |
572 | ||
573 | #ifdef CONFIG_SMP | |
574 | static int gic_secondary_init(struct notifier_block *nfb, | |
575 | unsigned long action, void *hcpu) | |
576 | { | |
577 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
578 | gic_cpu_init(); | |
579 | return NOTIFY_OK; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
584 | * priority because the GIC needs to be up before the ARM generic timers. | |
585 | */ | |
586 | static struct notifier_block gic_cpu_notifier = { | |
587 | .notifier_call = gic_secondary_init, | |
588 | .priority = 100, | |
589 | }; | |
590 | ||
591 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
592 | u64 cluster_id) | |
593 | { | |
594 | int cpu = *base_cpu; | |
595 | u64 mpidr = cpu_logical_map(cpu); | |
596 | u16 tlist = 0; | |
597 | ||
598 | while (cpu < nr_cpu_ids) { | |
599 | /* | |
600 | * If we ever get a cluster of more than 16 CPUs, just | |
601 | * scream and skip that CPU. | |
602 | */ | |
603 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
604 | goto out; | |
605 | ||
606 | tlist |= 1 << (mpidr & 0xf); | |
607 | ||
608 | cpu = cpumask_next(cpu, mask); | |
614be385 | 609 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
610 | goto out; |
611 | ||
612 | mpidr = cpu_logical_map(cpu); | |
613 | ||
614 | if (cluster_id != (mpidr & ~0xffUL)) { | |
615 | cpu--; | |
616 | goto out; | |
617 | } | |
618 | } | |
619 | out: | |
620 | *base_cpu = cpu; | |
621 | return tlist; | |
622 | } | |
623 | ||
7e580278 AP |
624 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
625 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
626 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
627 | ||
021f6537 MZ |
628 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
629 | { | |
630 | u64 val; | |
631 | ||
7e580278 AP |
632 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
633 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
634 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
635 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
636 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
637 | |
638 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
639 | gic_write_sgi1r(val); | |
640 | } | |
641 | ||
642 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
643 | { | |
644 | int cpu; | |
645 | ||
646 | if (WARN_ON(irq >= 16)) | |
647 | return; | |
648 | ||
649 | /* | |
650 | * Ensure that stores to Normal memory are visible to the | |
651 | * other CPUs before issuing the IPI. | |
652 | */ | |
653 | smp_wmb(); | |
654 | ||
f9b531fe | 655 | for_each_cpu(cpu, mask) { |
021f6537 MZ |
656 | u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
657 | u16 tlist; | |
658 | ||
659 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
660 | gic_send_sgi(cluster_id, tlist, irq); | |
661 | } | |
662 | ||
663 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
664 | isb(); | |
665 | } | |
666 | ||
667 | static void gic_smp_init(void) | |
668 | { | |
669 | set_smp_cross_call(gic_raise_softirq); | |
670 | register_cpu_notifier(&gic_cpu_notifier); | |
671 | } | |
672 | ||
673 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
674 | bool force) | |
675 | { | |
676 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
677 | void __iomem *reg; | |
678 | int enabled; | |
679 | u64 val; | |
680 | ||
681 | if (gic_irq_in_rdist(d)) | |
682 | return -EINVAL; | |
683 | ||
684 | /* If interrupt was enabled, disable it first */ | |
685 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
686 | if (enabled) | |
687 | gic_mask_irq(d); | |
688 | ||
689 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
690 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
691 | ||
692 | writeq_relaxed(val, reg); | |
693 | ||
694 | /* | |
695 | * If the interrupt was enabled, enabled it again. Otherwise, | |
696 | * just wait for the distributor to have digested our changes. | |
697 | */ | |
698 | if (enabled) | |
699 | gic_unmask_irq(d); | |
700 | else | |
701 | gic_dist_wait_for_rwp(); | |
702 | ||
703 | return IRQ_SET_MASK_OK; | |
704 | } | |
705 | #else | |
706 | #define gic_set_affinity NULL | |
707 | #define gic_smp_init() do { } while(0) | |
708 | #endif | |
709 | ||
3708d52f SH |
710 | #ifdef CONFIG_CPU_PM |
711 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
712 | unsigned long cmd, void *v) | |
713 | { | |
714 | if (cmd == CPU_PM_EXIT) { | |
715 | gic_enable_redist(true); | |
716 | gic_cpu_sys_reg_init(); | |
717 | } else if (cmd == CPU_PM_ENTER) { | |
718 | gic_write_grpen1(0); | |
719 | gic_enable_redist(false); | |
720 | } | |
721 | return NOTIFY_OK; | |
722 | } | |
723 | ||
724 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
725 | .notifier_call = gic_cpu_pm_notifier, | |
726 | }; | |
727 | ||
728 | static void gic_cpu_pm_init(void) | |
729 | { | |
730 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
731 | } | |
732 | ||
733 | #else | |
734 | static inline void gic_cpu_pm_init(void) { } | |
735 | #endif /* CONFIG_CPU_PM */ | |
736 | ||
021f6537 MZ |
737 | static struct irq_chip gic_chip = { |
738 | .name = "GICv3", | |
739 | .irq_mask = gic_mask_irq, | |
740 | .irq_unmask = gic_unmask_irq, | |
741 | .irq_eoi = gic_eoi_irq, | |
742 | .irq_set_type = gic_set_type, | |
743 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
744 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
745 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 746 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
747 | }; |
748 | ||
0b6a3da9 MZ |
749 | static struct irq_chip gic_eoimode1_chip = { |
750 | .name = "GICv3", | |
751 | .irq_mask = gic_eoimode1_mask_irq, | |
752 | .irq_unmask = gic_unmask_irq, | |
753 | .irq_eoi = gic_eoimode1_eoi_irq, | |
754 | .irq_set_type = gic_set_type, | |
755 | .irq_set_affinity = gic_set_affinity, | |
756 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
757 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 758 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
759 | .flags = IRQCHIP_SET_TYPE_MASKED, |
760 | }; | |
761 | ||
da33f31d MZ |
762 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
763 | ||
021f6537 MZ |
764 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
765 | irq_hw_number_t hw) | |
766 | { | |
0b6a3da9 MZ |
767 | struct irq_chip *chip = &gic_chip; |
768 | ||
769 | if (static_key_true(&supports_deactivate)) | |
770 | chip = &gic_eoimode1_chip; | |
771 | ||
021f6537 MZ |
772 | /* SGIs are private to the core kernel */ |
773 | if (hw < 16) | |
774 | return -EPERM; | |
da33f31d MZ |
775 | /* Nothing here */ |
776 | if (hw >= gic_data.irq_nr && hw < 8192) | |
777 | return -EPERM; | |
778 | /* Off limits */ | |
779 | if (hw >= GIC_ID_NR) | |
780 | return -EPERM; | |
781 | ||
021f6537 MZ |
782 | /* PPIs */ |
783 | if (hw < 32) { | |
784 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 785 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 786 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 787 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
788 | } |
789 | /* SPIs */ | |
790 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 791 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 792 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 793 | irq_set_probe(irq); |
021f6537 | 794 | } |
da33f31d MZ |
795 | /* LPIs */ |
796 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
797 | if (!gic_dist_supports_lpis()) | |
798 | return -EPERM; | |
0b6a3da9 | 799 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 800 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
801 | } |
802 | ||
021f6537 MZ |
803 | return 0; |
804 | } | |
805 | ||
806 | static int gic_irq_domain_xlate(struct irq_domain *d, | |
807 | struct device_node *controller, | |
808 | const u32 *intspec, unsigned int intsize, | |
809 | unsigned long *out_hwirq, unsigned int *out_type) | |
810 | { | |
811 | if (d->of_node != controller) | |
812 | return -EINVAL; | |
813 | if (intsize < 3) | |
814 | return -EINVAL; | |
815 | ||
816 | switch(intspec[0]) { | |
817 | case 0: /* SPI */ | |
818 | *out_hwirq = intspec[1] + 32; | |
819 | break; | |
820 | case 1: /* PPI */ | |
821 | *out_hwirq = intspec[1] + 16; | |
822 | break; | |
da33f31d MZ |
823 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
824 | *out_hwirq = intspec[1]; | |
825 | break; | |
021f6537 MZ |
826 | default: |
827 | return -EINVAL; | |
828 | } | |
829 | ||
830 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
831 | return 0; | |
832 | } | |
833 | ||
443acc4f MZ |
834 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
835 | unsigned int nr_irqs, void *arg) | |
836 | { | |
837 | int i, ret; | |
838 | irq_hw_number_t hwirq; | |
839 | unsigned int type = IRQ_TYPE_NONE; | |
840 | struct of_phandle_args *irq_data = arg; | |
841 | ||
842 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, | |
843 | irq_data->args_count, &hwirq, &type); | |
844 | if (ret) | |
845 | return ret; | |
846 | ||
847 | for (i = 0; i < nr_irqs; i++) | |
848 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
854 | unsigned int nr_irqs) | |
855 | { | |
856 | int i; | |
857 | ||
858 | for (i = 0; i < nr_irqs; i++) { | |
859 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
860 | irq_set_handler(virq + i, NULL); | |
861 | irq_domain_reset_irq_data(d); | |
862 | } | |
863 | } | |
864 | ||
021f6537 | 865 | static const struct irq_domain_ops gic_irq_domain_ops = { |
021f6537 | 866 | .xlate = gic_irq_domain_xlate, |
443acc4f MZ |
867 | .alloc = gic_irq_domain_alloc, |
868 | .free = gic_irq_domain_free, | |
021f6537 MZ |
869 | }; |
870 | ||
6d4e11c5 RR |
871 | static void gicv3_enable_quirks(void) |
872 | { | |
873 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) | |
8ac2a170 | 874 | static_branch_enable(&is_cavium_thunderx); |
6d4e11c5 RR |
875 | } |
876 | ||
021f6537 MZ |
877 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
878 | { | |
879 | void __iomem *dist_base; | |
f5c1434c | 880 | struct redist_region *rdist_regs; |
021f6537 | 881 | u64 redist_stride; |
f5c1434c MZ |
882 | u32 nr_redist_regions; |
883 | u32 typer; | |
021f6537 MZ |
884 | u32 reg; |
885 | int gic_irqs; | |
886 | int err; | |
887 | int i; | |
888 | ||
889 | dist_base = of_iomap(node, 0); | |
890 | if (!dist_base) { | |
891 | pr_err("%s: unable to map gic dist registers\n", | |
892 | node->full_name); | |
893 | return -ENXIO; | |
894 | } | |
895 | ||
896 | reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
897 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { | |
898 | pr_err("%s: no distributor detected, giving up\n", | |
899 | node->full_name); | |
900 | err = -ENODEV; | |
901 | goto out_unmap_dist; | |
902 | } | |
903 | ||
f5c1434c MZ |
904 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) |
905 | nr_redist_regions = 1; | |
021f6537 | 906 | |
f5c1434c MZ |
907 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); |
908 | if (!rdist_regs) { | |
021f6537 MZ |
909 | err = -ENOMEM; |
910 | goto out_unmap_dist; | |
911 | } | |
912 | ||
f5c1434c MZ |
913 | for (i = 0; i < nr_redist_regions; i++) { |
914 | struct resource res; | |
915 | int ret; | |
916 | ||
917 | ret = of_address_to_resource(node, 1 + i, &res); | |
918 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
919 | if (ret || !rdist_regs[i].redist_base) { | |
021f6537 MZ |
920 | pr_err("%s: couldn't map region %d\n", |
921 | node->full_name, i); | |
922 | err = -ENODEV; | |
923 | goto out_unmap_rdist; | |
924 | } | |
f5c1434c | 925 | rdist_regs[i].phys_base = res.start; |
021f6537 MZ |
926 | } |
927 | ||
928 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
929 | redist_stride = 0; | |
930 | ||
0b6a3da9 MZ |
931 | if (!is_hyp_mode_available()) |
932 | static_key_slow_dec(&supports_deactivate); | |
933 | ||
934 | if (static_key_true(&supports_deactivate)) | |
935 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
936 | ||
021f6537 | 937 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
938 | gic_data.redist_regions = rdist_regs; |
939 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
940 | gic_data.redist_stride = redist_stride; |
941 | ||
6d4e11c5 RR |
942 | gicv3_enable_quirks(); |
943 | ||
021f6537 MZ |
944 | /* |
945 | * Find out how many interrupts are supported. | |
946 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
947 | */ | |
f5c1434c MZ |
948 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
949 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
950 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
951 | if (gic_irqs > 1020) |
952 | gic_irqs = 1020; | |
953 | gic_data.irq_nr = gic_irqs; | |
954 | ||
955 | gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, | |
956 | &gic_data); | |
f5c1434c | 957 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 958 | |
f5c1434c | 959 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
960 | err = -ENOMEM; |
961 | goto out_free; | |
962 | } | |
963 | ||
964 | set_handle_irq(gic_handle_irq); | |
965 | ||
da33f31d MZ |
966 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
967 | its_init(node, &gic_data.rdists, gic_data.domain); | |
968 | ||
021f6537 MZ |
969 | gic_smp_init(); |
970 | gic_dist_init(); | |
971 | gic_cpu_init(); | |
3708d52f | 972 | gic_cpu_pm_init(); |
021f6537 MZ |
973 | |
974 | return 0; | |
975 | ||
976 | out_free: | |
977 | if (gic_data.domain) | |
978 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 979 | free_percpu(gic_data.rdists.rdist); |
021f6537 | 980 | out_unmap_rdist: |
f5c1434c MZ |
981 | for (i = 0; i < nr_redist_regions; i++) |
982 | if (rdist_regs[i].redist_base) | |
983 | iounmap(rdist_regs[i].redist_base); | |
984 | kfree(rdist_regs); | |
021f6537 MZ |
985 | out_unmap_dist: |
986 | iounmap(dist_base); | |
987 | return err; | |
988 | } | |
989 | ||
990 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |