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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
021f6537 | 2 | /* |
0edc23ea | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
021f6537 MZ |
5 | */ |
6 | ||
68628bb8 JG |
7 | #define pr_fmt(fmt) "GICv3: " fmt |
8 | ||
ffa7d616 | 9 | #include <linux/acpi.h> |
021f6537 | 10 | #include <linux/cpu.h> |
3708d52f | 11 | #include <linux/cpu_pm.h> |
021f6537 MZ |
12 | #include <linux/delay.h> |
13 | #include <linux/interrupt.h> | |
ffa7d616 | 14 | #include <linux/irqdomain.h> |
5e279739 | 15 | #include <linux/kstrtox.h> |
021f6537 MZ |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/percpu.h> | |
101b35f7 | 20 | #include <linux/refcount.h> |
021f6537 MZ |
21 | #include <linux/slab.h> |
22 | ||
41a83e06 | 23 | #include <linux/irqchip.h> |
1839e576 | 24 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 26 | #include <linux/irqchip/irq-partition-percpu.h> |
35727af2 SD |
27 | #include <linux/bitfield.h> |
28 | #include <linux/bits.h> | |
29 | #include <linux/arm-smccc.h> | |
021f6537 MZ |
30 | |
31 | #include <asm/cputype.h> | |
32 | #include <asm/exception.h> | |
33 | #include <asm/smp_plat.h> | |
0b6a3da9 | 34 | #include <asm/virt.h> |
021f6537 MZ |
35 | |
36 | #include "irq-gic-common.h" | |
021f6537 | 37 | |
f32c9266 JT |
38 | #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) |
39 | ||
9c8114c2 | 40 | #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) |
d01fd161 | 41 | #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) |
44bd78dd | 42 | #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) |
b4d81fab | 43 | #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) |
9c8114c2 | 44 | |
64b499d8 MZ |
45 | #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) |
46 | ||
f5c1434c MZ |
47 | struct redist_region { |
48 | void __iomem *redist_base; | |
49 | phys_addr_t phys_base; | |
b70fb7af | 50 | bool single_redist; |
f5c1434c MZ |
51 | }; |
52 | ||
021f6537 | 53 | struct gic_chip_data { |
e3825ba1 | 54 | struct fwnode_handle *fwnode; |
35727af2 | 55 | phys_addr_t dist_phys_base; |
021f6537 | 56 | void __iomem *dist_base; |
f5c1434c MZ |
57 | struct redist_region *redist_regions; |
58 | struct rdists rdists; | |
021f6537 MZ |
59 | struct irq_domain *domain; |
60 | u64 redist_stride; | |
f5c1434c | 61 | u32 nr_redist_regions; |
9c8114c2 | 62 | u64 flags; |
eda0d04a | 63 | bool has_rss; |
1a60e1e6 | 64 | unsigned int ppi_nr; |
52085d3f | 65 | struct partition_desc **ppi_descs; |
021f6537 MZ |
66 | }; |
67 | ||
35727af2 SD |
68 | #define T241_CHIPS_MAX 4 |
69 | static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly; | |
70 | static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum); | |
71 | ||
6fe5c68e LP |
72 | static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum); |
73 | ||
021f6537 | 74 | static struct gic_chip_data gic_data __read_mostly; |
d01d3274 | 75 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
021f6537 | 76 | |
211bddd2 | 77 | #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) |
c107d613 | 78 | #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) |
211bddd2 MZ |
79 | #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) |
80 | ||
a02026bf DA |
81 | /* |
82 | * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs | |
83 | * are potentially stolen by the secure side. Some code, especially code dealing | |
84 | * with hwirq IDs, is simplified by accounting for all 16. | |
85 | */ | |
86 | #define SGI_NR 16 | |
87 | ||
d98d0a99 JT |
88 | /* |
89 | * The behaviours of RPR and PMR registers differ depending on the value of | |
90 | * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the | |
91 | * distributor and redistributors depends on whether security is enabled in the | |
92 | * GIC. | |
93 | * | |
94 | * When security is enabled, non-secure priority values from the (re)distributor | |
95 | * are presented to the GIC CPUIF as follow: | |
96 | * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; | |
97 | * | |
d4034114 | 98 | * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure |
d98d0a99 | 99 | * EL1 are subject to a similar operation thus matching the priorities presented |
33678059 | 100 | * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, |
d4034114 | 101 | * these values are unchanged by the GIC. |
d98d0a99 JT |
102 | * |
103 | * see GICv3/GICv4 Architecture Specification (IHI0069D): | |
104 | * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt | |
105 | * priorities. | |
106 | * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 | |
107 | * interrupt. | |
d98d0a99 JT |
108 | */ |
109 | static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); | |
110 | ||
33678059 AE |
111 | DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); |
112 | EXPORT_SYMBOL(gic_nonsecure_priorities); | |
113 | ||
8d474dea CYT |
114 | /* |
115 | * When the Non-secure world has access to group 0 interrupts (as a | |
116 | * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will | |
117 | * return the Distributor's view of the interrupt priority. | |
118 | * | |
119 | * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority | |
120 | * written by software is moved to the Non-secure range by the Distributor. | |
121 | * | |
122 | * If both are true (which is when gic_nonsecure_priorities gets enabled), | |
123 | * we need to shift down the priority programmed by software to match it | |
124 | * against the value returned by ICC_RPR_EL1. | |
125 | */ | |
126 | #define GICD_INT_RPR_PRI(priority) \ | |
127 | ({ \ | |
128 | u32 __priority = (priority); \ | |
129 | if (static_branch_unlikely(&gic_nonsecure_priorities)) \ | |
130 | __priority = 0x80 | (__priority >> 1); \ | |
131 | \ | |
132 | __priority; \ | |
133 | }) | |
134 | ||
a02026bf DA |
135 | /* rdist_nmi_refs[n] == number of cpus having the rdist interrupt n set as NMI */ |
136 | static refcount_t *rdist_nmi_refs; | |
101b35f7 | 137 | |
0e5cb777 | 138 | static struct gic_kvm_info gic_v3_kvm_info __initdata; |
eda0d04a | 139 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 140 | |
eda0d04a | 141 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
142 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
143 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
144 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
145 | ||
146 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
147 | #define DEFAULT_PMR_VALUE 0xf0 | |
148 | ||
e91b036e | 149 | enum gic_intid_range { |
70a29c32 | 150 | SGI_RANGE, |
e91b036e MZ |
151 | PPI_RANGE, |
152 | SPI_RANGE, | |
5f51f803 | 153 | EPPI_RANGE, |
211bddd2 | 154 | ESPI_RANGE, |
e91b036e MZ |
155 | LPI_RANGE, |
156 | __INVALID_RANGE__ | |
157 | }; | |
158 | ||
159 | static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) | |
160 | { | |
161 | switch (hwirq) { | |
70a29c32 MZ |
162 | case 0 ... 15: |
163 | return SGI_RANGE; | |
e91b036e MZ |
164 | case 16 ... 31: |
165 | return PPI_RANGE; | |
166 | case 32 ... 1019: | |
167 | return SPI_RANGE; | |
5f51f803 MZ |
168 | case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): |
169 | return EPPI_RANGE; | |
211bddd2 MZ |
170 | case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): |
171 | return ESPI_RANGE; | |
e91b036e MZ |
172 | case 8192 ... GENMASK(23, 0): |
173 | return LPI_RANGE; | |
174 | default: | |
175 | return __INVALID_RANGE__; | |
176 | } | |
177 | } | |
178 | ||
179 | static enum gic_intid_range get_intid_range(struct irq_data *d) | |
180 | { | |
181 | return __get_intid_range(d->hwirq); | |
182 | } | |
183 | ||
021f6537 MZ |
184 | static inline unsigned int gic_irq(struct irq_data *d) |
185 | { | |
186 | return d->hwirq; | |
187 | } | |
188 | ||
70a29c32 | 189 | static inline bool gic_irq_in_rdist(struct irq_data *d) |
021f6537 | 190 | { |
70a29c32 MZ |
191 | switch (get_intid_range(d)) { |
192 | case SGI_RANGE: | |
193 | case PPI_RANGE: | |
194 | case EPPI_RANGE: | |
195 | return true; | |
196 | default: | |
197 | return false; | |
198 | } | |
021f6537 MZ |
199 | } |
200 | ||
35727af2 SD |
201 | static inline void __iomem *gic_dist_base_alias(struct irq_data *d) |
202 | { | |
203 | if (static_branch_unlikely(&gic_nvidia_t241_erratum)) { | |
204 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
205 | u32 chip; | |
206 | ||
207 | /* | |
208 | * For the erratum T241-FABRIC-4, read accesses to GICD_In{E} | |
209 | * registers are directed to the chip that owns the SPI. The | |
210 | * the alias region can also be used for writes to the | |
211 | * GICD_In{E} except GICD_ICENABLERn. Each chip has support | |
212 | * for 320 {E}SPIs. Mappings for all 4 chips: | |
213 | * Chip0 = 32-351 | |
214 | * Chip1 = 352-671 | |
215 | * Chip2 = 672-991 | |
216 | * Chip3 = 4096-4415 | |
217 | */ | |
218 | switch (__get_intid_range(hwirq)) { | |
219 | case SPI_RANGE: | |
220 | chip = (hwirq - 32) / 320; | |
221 | break; | |
222 | case ESPI_RANGE: | |
223 | chip = 3; | |
224 | break; | |
225 | default: | |
226 | unreachable(); | |
227 | } | |
228 | return t241_dist_base_alias[chip]; | |
229 | } | |
230 | ||
231 | return gic_data.dist_base; | |
232 | } | |
233 | ||
021f6537 MZ |
234 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
235 | { | |
e91b036e | 236 | switch (get_intid_range(d)) { |
70a29c32 | 237 | case SGI_RANGE: |
e91b036e | 238 | case PPI_RANGE: |
5f51f803 | 239 | case EPPI_RANGE: |
e91b036e | 240 | /* SGI+PPI -> SGI_base for this CPU */ |
021f6537 MZ |
241 | return gic_data_rdist_sgi_base(); |
242 | ||
e91b036e | 243 | case SPI_RANGE: |
211bddd2 | 244 | case ESPI_RANGE: |
e91b036e | 245 | /* SPI -> dist_base */ |
021f6537 MZ |
246 | return gic_data.dist_base; |
247 | ||
e91b036e MZ |
248 | default: |
249 | return NULL; | |
250 | } | |
021f6537 MZ |
251 | } |
252 | ||
0df66645 | 253 | static void gic_do_wait_for_rwp(void __iomem *base, u32 bit) |
021f6537 MZ |
254 | { |
255 | u32 count = 1000000; /* 1s! */ | |
256 | ||
0df66645 | 257 | while (readl_relaxed(base + GICD_CTLR) & bit) { |
021f6537 MZ |
258 | count--; |
259 | if (!count) { | |
260 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
261 | return; | |
262 | } | |
263 | cpu_relax(); | |
264 | udelay(1); | |
2c542426 | 265 | } |
021f6537 MZ |
266 | } |
267 | ||
268 | /* Wait for completion of a distributor change */ | |
269 | static void gic_dist_wait_for_rwp(void) | |
270 | { | |
0df66645 | 271 | gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP); |
021f6537 MZ |
272 | } |
273 | ||
274 | /* Wait for completion of a redistributor change */ | |
275 | static void gic_redist_wait_for_rwp(void) | |
276 | { | |
0df66645 | 277 | gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP); |
021f6537 MZ |
278 | } |
279 | ||
7936e914 | 280 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
281 | |
282 | static u64 __maybe_unused gic_read_iar(void) | |
283 | { | |
a4023f68 | 284 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
285 | return gic_read_iar_cavium_thunderx(); |
286 | else | |
287 | return gic_read_iar_common(); | |
288 | } | |
7936e914 | 289 | #endif |
021f6537 | 290 | |
a2c22510 | 291 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
292 | { |
293 | void __iomem *rbase; | |
294 | u32 count = 1000000; /* 1s! */ | |
295 | u32 val; | |
296 | ||
9c8114c2 SK |
297 | if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) |
298 | return; | |
299 | ||
021f6537 MZ |
300 | rbase = gic_data_rdist_rd_base(); |
301 | ||
021f6537 | 302 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
303 | if (enable) |
304 | /* Wake up this CPU redistributor */ | |
305 | val &= ~GICR_WAKER_ProcessorSleep; | |
306 | else | |
307 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
308 | writel_relaxed(val, rbase + GICR_WAKER); |
309 | ||
a2c22510 SH |
310 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
311 | val = readl_relaxed(rbase + GICR_WAKER); | |
312 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
313 | return; /* No PM support in this redistributor */ | |
314 | } | |
315 | ||
d102eb5c | 316 | while (--count) { |
a2c22510 | 317 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 318 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 319 | break; |
021f6537 MZ |
320 | cpu_relax(); |
321 | udelay(1); | |
2c542426 | 322 | } |
a2c22510 SH |
323 | if (!count) |
324 | pr_err_ratelimited("redistributor failed to %s...\n", | |
325 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
326 | } |
327 | ||
328 | /* | |
329 | * Routines to disable, enable, EOI and route interrupts | |
330 | */ | |
e91b036e MZ |
331 | static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) |
332 | { | |
333 | switch (get_intid_range(d)) { | |
70a29c32 | 334 | case SGI_RANGE: |
e91b036e MZ |
335 | case PPI_RANGE: |
336 | case SPI_RANGE: | |
337 | *index = d->hwirq; | |
338 | return offset; | |
5f51f803 MZ |
339 | case EPPI_RANGE: |
340 | /* | |
341 | * Contrary to the ESPI range, the EPPI range is contiguous | |
342 | * to the PPI range in the registers, so let's adjust the | |
343 | * displacement accordingly. Consistency is overrated. | |
344 | */ | |
345 | *index = d->hwirq - EPPI_BASE_INTID + 32; | |
346 | return offset; | |
211bddd2 MZ |
347 | case ESPI_RANGE: |
348 | *index = d->hwirq - ESPI_BASE_INTID; | |
349 | switch (offset) { | |
350 | case GICD_ISENABLER: | |
351 | return GICD_ISENABLERnE; | |
352 | case GICD_ICENABLER: | |
353 | return GICD_ICENABLERnE; | |
354 | case GICD_ISPENDR: | |
355 | return GICD_ISPENDRnE; | |
356 | case GICD_ICPENDR: | |
357 | return GICD_ICPENDRnE; | |
358 | case GICD_ISACTIVER: | |
359 | return GICD_ISACTIVERnE; | |
360 | case GICD_ICACTIVER: | |
361 | return GICD_ICACTIVERnE; | |
362 | case GICD_IPRIORITYR: | |
363 | return GICD_IPRIORITYRnE; | |
364 | case GICD_ICFGR: | |
365 | return GICD_ICFGRnE; | |
366 | case GICD_IROUTER: | |
367 | return GICD_IROUTERnE; | |
368 | default: | |
369 | break; | |
370 | } | |
371 | break; | |
e91b036e MZ |
372 | default: |
373 | break; | |
374 | } | |
375 | ||
376 | WARN_ON(1); | |
377 | *index = d->hwirq; | |
378 | return offset; | |
379 | } | |
380 | ||
b594c6e2 MZ |
381 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
382 | { | |
b594c6e2 | 383 | void __iomem *base; |
e91b036e MZ |
384 | u32 index, mask; |
385 | ||
386 | offset = convert_offset_index(d, offset, &index); | |
387 | mask = 1 << (index % 32); | |
b594c6e2 MZ |
388 | |
389 | if (gic_irq_in_rdist(d)) | |
390 | base = gic_data_rdist_sgi_base(); | |
391 | else | |
35727af2 | 392 | base = gic_dist_base_alias(d); |
b594c6e2 | 393 | |
e91b036e | 394 | return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); |
b594c6e2 MZ |
395 | } |
396 | ||
021f6537 MZ |
397 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
398 | { | |
021f6537 | 399 | void __iomem *base; |
e91b036e MZ |
400 | u32 index, mask; |
401 | ||
402 | offset = convert_offset_index(d, offset, &index); | |
403 | mask = 1 << (index % 32); | |
021f6537 | 404 | |
63f13483 | 405 | if (gic_irq_in_rdist(d)) |
021f6537 | 406 | base = gic_data_rdist_sgi_base(); |
63f13483 | 407 | else |
021f6537 | 408 | base = gic_data.dist_base; |
021f6537 | 409 | |
e91b036e | 410 | writel_relaxed(mask, base + offset + (index / 32) * 4); |
021f6537 MZ |
411 | } |
412 | ||
021f6537 MZ |
413 | static void gic_mask_irq(struct irq_data *d) |
414 | { | |
415 | gic_poke_irq(d, GICD_ICENABLER); | |
63f13483 MZ |
416 | if (gic_irq_in_rdist(d)) |
417 | gic_redist_wait_for_rwp(); | |
418 | else | |
419 | gic_dist_wait_for_rwp(); | |
021f6537 MZ |
420 | } |
421 | ||
0b6a3da9 MZ |
422 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
423 | { | |
424 | gic_mask_irq(d); | |
530bf353 MZ |
425 | /* |
426 | * When masking a forwarded interrupt, make sure it is | |
427 | * deactivated as well. | |
428 | * | |
429 | * This ensures that an interrupt that is getting | |
430 | * disabled/masked will not get "stuck", because there is | |
431 | * noone to deactivate it (guest is being terminated). | |
432 | */ | |
4df7f54d | 433 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 434 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
435 | } |
436 | ||
021f6537 MZ |
437 | static void gic_unmask_irq(struct irq_data *d) |
438 | { | |
439 | gic_poke_irq(d, GICD_ISENABLER); | |
440 | } | |
441 | ||
d98d0a99 JT |
442 | static inline bool gic_supports_nmi(void) |
443 | { | |
444 | return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && | |
445 | static_branch_likely(&supports_pseudo_nmis); | |
446 | } | |
447 | ||
b594c6e2 MZ |
448 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
449 | enum irqchip_irq_state which, bool val) | |
450 | { | |
451 | u32 reg; | |
452 | ||
64b499d8 | 453 | if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ |
b594c6e2 MZ |
454 | return -EINVAL; |
455 | ||
456 | switch (which) { | |
457 | case IRQCHIP_STATE_PENDING: | |
458 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
459 | break; | |
460 | ||
461 | case IRQCHIP_STATE_ACTIVE: | |
462 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
463 | break; | |
464 | ||
465 | case IRQCHIP_STATE_MASKED: | |
63f13483 MZ |
466 | if (val) { |
467 | gic_mask_irq(d); | |
468 | return 0; | |
469 | } | |
470 | reg = GICD_ISENABLER; | |
b594c6e2 MZ |
471 | break; |
472 | ||
473 | default: | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
477 | gic_poke_irq(d, reg); | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
482 | enum irqchip_irq_state which, bool *val) | |
483 | { | |
211bddd2 | 484 | if (d->hwirq >= 8192) /* PPI/SPI only */ |
b594c6e2 MZ |
485 | return -EINVAL; |
486 | ||
487 | switch (which) { | |
488 | case IRQCHIP_STATE_PENDING: | |
489 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
490 | break; | |
491 | ||
492 | case IRQCHIP_STATE_ACTIVE: | |
493 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
494 | break; | |
495 | ||
496 | case IRQCHIP_STATE_MASKED: | |
497 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
498 | break; | |
499 | ||
500 | default: | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
101b35f7 JT |
507 | static void gic_irq_set_prio(struct irq_data *d, u8 prio) |
508 | { | |
509 | void __iomem *base = gic_dist_base(d); | |
e91b036e | 510 | u32 offset, index; |
101b35f7 | 511 | |
e91b036e MZ |
512 | offset = convert_offset_index(d, GICD_IPRIORITYR, &index); |
513 | ||
514 | writeb_relaxed(prio, base + offset + index); | |
101b35f7 JT |
515 | } |
516 | ||
bfa80ee9 | 517 | static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) |
81a43273 | 518 | { |
bfa80ee9 | 519 | switch (__get_intid_range(hwirq)) { |
81a43273 | 520 | case PPI_RANGE: |
bfa80ee9 | 521 | return hwirq - 16; |
5f51f803 | 522 | case EPPI_RANGE: |
bfa80ee9 | 523 | return hwirq - EPPI_BASE_INTID + 16; |
81a43273 MZ |
524 | default: |
525 | unreachable(); | |
526 | } | |
527 | } | |
528 | ||
a02026bf DA |
529 | static u32 __gic_get_rdist_index(irq_hw_number_t hwirq) |
530 | { | |
531 | switch (__get_intid_range(hwirq)) { | |
532 | case SGI_RANGE: | |
533 | case PPI_RANGE: | |
534 | return hwirq; | |
535 | case EPPI_RANGE: | |
536 | return hwirq - EPPI_BASE_INTID + 32; | |
537 | default: | |
538 | unreachable(); | |
539 | } | |
540 | } | |
541 | ||
542 | static u32 gic_get_rdist_index(struct irq_data *d) | |
bfa80ee9 | 543 | { |
a02026bf | 544 | return __gic_get_rdist_index(d->hwirq); |
bfa80ee9 JM |
545 | } |
546 | ||
101b35f7 JT |
547 | static int gic_irq_nmi_setup(struct irq_data *d) |
548 | { | |
549 | struct irq_desc *desc = irq_to_desc(d->irq); | |
550 | ||
551 | if (!gic_supports_nmi()) | |
552 | return -EINVAL; | |
553 | ||
554 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
555 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
559 | /* | |
560 | * A secondary irq_chip should be in charge of LPI request, | |
561 | * it should not be possible to get there | |
562 | */ | |
563 | if (WARN_ON(gic_irq(d) >= 8192)) | |
564 | return -EINVAL; | |
565 | ||
566 | /* desc lock should already be held */ | |
81a43273 | 567 | if (gic_irq_in_rdist(d)) { |
a02026bf | 568 | u32 idx = gic_get_rdist_index(d); |
81a43273 | 569 | |
a02026bf DA |
570 | /* |
571 | * Setting up a percpu interrupt as NMI, only switch handler | |
572 | * for first NMI | |
573 | */ | |
574 | if (!refcount_inc_not_zero(&rdist_nmi_refs[idx])) { | |
575 | refcount_set(&rdist_nmi_refs[idx], 1); | |
101b35f7 JT |
576 | desc->handle_irq = handle_percpu_devid_fasteoi_nmi; |
577 | } | |
578 | } else { | |
579 | desc->handle_irq = handle_fasteoi_nmi; | |
580 | } | |
581 | ||
582 | gic_irq_set_prio(d, GICD_INT_NMI_PRI); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static void gic_irq_nmi_teardown(struct irq_data *d) | |
588 | { | |
589 | struct irq_desc *desc = irq_to_desc(d->irq); | |
590 | ||
591 | if (WARN_ON(!gic_supports_nmi())) | |
592 | return; | |
593 | ||
594 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
595 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
596 | return; | |
597 | } | |
598 | ||
599 | /* | |
600 | * A secondary irq_chip should be in charge of LPI request, | |
601 | * it should not be possible to get there | |
602 | */ | |
603 | if (WARN_ON(gic_irq(d) >= 8192)) | |
604 | return; | |
605 | ||
606 | /* desc lock should already be held */ | |
81a43273 | 607 | if (gic_irq_in_rdist(d)) { |
a02026bf | 608 | u32 idx = gic_get_rdist_index(d); |
81a43273 | 609 | |
101b35f7 | 610 | /* Tearing down NMI, only switch handler for last NMI */ |
a02026bf | 611 | if (refcount_dec_and_test(&rdist_nmi_refs[idx])) |
101b35f7 JT |
612 | desc->handle_irq = handle_percpu_devid_irq; |
613 | } else { | |
614 | desc->handle_irq = handle_fasteoi_irq; | |
615 | } | |
616 | ||
617 | gic_irq_set_prio(d, GICD_INT_DEF_PRI); | |
618 | } | |
619 | ||
6fe5c68e LP |
620 | static bool gic_arm64_erratum_2941627_needed(struct irq_data *d) |
621 | { | |
622 | enum gic_intid_range range; | |
623 | ||
624 | if (!static_branch_unlikely(&gic_arm64_2941627_erratum)) | |
625 | return false; | |
626 | ||
627 | range = get_intid_range(d); | |
628 | ||
629 | /* | |
630 | * The workaround is needed if the IRQ is an SPI and | |
631 | * the target cpu is different from the one we are | |
632 | * executing on. | |
633 | */ | |
634 | return (range == SPI_RANGE || range == ESPI_RANGE) && | |
635 | !cpumask_test_cpu(raw_smp_processor_id(), | |
636 | irq_data_get_effective_affinity_mask(d)); | |
637 | } | |
638 | ||
021f6537 MZ |
639 | static void gic_eoi_irq(struct irq_data *d) |
640 | { | |
6efb5092 MR |
641 | write_gicreg(gic_irq(d), ICC_EOIR1_EL1); |
642 | isb(); | |
6fe5c68e LP |
643 | |
644 | if (gic_arm64_erratum_2941627_needed(d)) { | |
645 | /* | |
646 | * Make sure the GIC stream deactivate packet | |
647 | * issued by ICC_EOIR1_EL1 has completed before | |
648 | * deactivating through GICD_IACTIVER. | |
649 | */ | |
650 | dsb(sy); | |
651 | gic_poke_irq(d, GICD_ICACTIVER); | |
652 | } | |
021f6537 MZ |
653 | } |
654 | ||
0b6a3da9 MZ |
655 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
656 | { | |
657 | /* | |
530bf353 MZ |
658 | * No need to deactivate an LPI, or an interrupt that |
659 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 660 | */ |
4df7f54d | 661 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 | 662 | return; |
6fe5c68e LP |
663 | |
664 | if (!gic_arm64_erratum_2941627_needed(d)) | |
665 | gic_write_dir(gic_irq(d)); | |
666 | else | |
667 | gic_poke_irq(d, GICD_ICACTIVER); | |
0b6a3da9 MZ |
668 | } |
669 | ||
021f6537 MZ |
670 | static int gic_set_type(struct irq_data *d, unsigned int type) |
671 | { | |
5f51f803 | 672 | enum gic_intid_range range; |
021f6537 | 673 | unsigned int irq = gic_irq(d); |
021f6537 | 674 | void __iomem *base; |
e91b036e | 675 | u32 offset, index; |
13d22e2e | 676 | int ret; |
021f6537 | 677 | |
5f51f803 MZ |
678 | range = get_intid_range(d); |
679 | ||
64b499d8 MZ |
680 | /* Interrupt configuration for SGIs can't be changed */ |
681 | if (range == SGI_RANGE) | |
682 | return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; | |
683 | ||
fb7e7deb | 684 | /* SPIs have restrictions on the supported types */ |
5f51f803 MZ |
685 | if ((range == SPI_RANGE || range == ESPI_RANGE) && |
686 | type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
687 | return -EINVAL; |
688 | ||
63f13483 | 689 | if (gic_irq_in_rdist(d)) |
021f6537 | 690 | base = gic_data_rdist_sgi_base(); |
63f13483 | 691 | else |
35727af2 | 692 | base = gic_dist_base_alias(d); |
021f6537 | 693 | |
e91b036e | 694 | offset = convert_offset_index(d, GICD_ICFGR, &index); |
13d22e2e | 695 | |
63f13483 | 696 | ret = gic_configure_irq(index, type, base + offset, NULL); |
5f51f803 | 697 | if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { |
13d22e2e | 698 | /* Misconfigured PPIs are usually not fatal */ |
5f51f803 | 699 | pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); |
13d22e2e MZ |
700 | ret = 0; |
701 | } | |
702 | ||
703 | return ret; | |
021f6537 MZ |
704 | } |
705 | ||
530bf353 MZ |
706 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
707 | { | |
64b499d8 MZ |
708 | if (get_intid_range(d) == SGI_RANGE) |
709 | return -EINVAL; | |
710 | ||
4df7f54d TG |
711 | if (vcpu) |
712 | irqd_set_forwarded_to_vcpu(d); | |
713 | else | |
714 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
715 | return 0; |
716 | } | |
717 | ||
3c65cbb7 | 718 | static u64 gic_cpu_to_affinity(int cpu) |
021f6537 | 719 | { |
3c65cbb7 | 720 | u64 mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
721 | u64 aff; |
722 | ||
b4d81fab | 723 | /* ASR8601 needs to have its affinities shifted down... */ |
724 | if (unlikely(gic_data.flags & FLAGS_WORKAROUND_ASR_ERRATUM_8601001)) | |
725 | mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) | | |
726 | (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8)); | |
727 | ||
f6c86a41 | 728 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
729 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
730 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
731 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
732 | ||
733 | return aff; | |
734 | } | |
735 | ||
f32c9266 JT |
736 | static void gic_deactivate_unhandled(u32 irqnr) |
737 | { | |
738 | if (static_branch_likely(&supports_deactivate_key)) { | |
739 | if (irqnr < 8192) | |
740 | gic_write_dir(irqnr); | |
741 | } else { | |
6efb5092 MR |
742 | write_gicreg(irqnr, ICC_EOIR1_EL1); |
743 | isb(); | |
f32c9266 JT |
744 | } |
745 | } | |
746 | ||
6efb5092 MR |
747 | /* |
748 | * Follow a read of the IAR with any HW maintenance that needs to happen prior | |
749 | * to invoking the relevant IRQ handler. We must do two things: | |
750 | * | |
751 | * (1) Ensure instruction ordering between a read of IAR and subsequent | |
752 | * instructions in the IRQ handler using an ISB. | |
753 | * | |
754 | * It is possible for the IAR to report an IRQ which was signalled *after* | |
755 | * the CPU took an IRQ exception as multiple interrupts can race to be | |
756 | * recognized by the GIC, earlier interrupts could be withdrawn, and/or | |
757 | * later interrupts could be prioritized by the GIC. | |
758 | * | |
759 | * For devices which are tightly coupled to the CPU, such as PMUs, a | |
760 | * context synchronization event is necessary to ensure that system | |
761 | * register state is not stale, as these may have been indirectly written | |
762 | * *after* exception entry. | |
763 | * | |
764 | * (2) Deactivate the interrupt when EOI mode 1 is in use. | |
765 | */ | |
766 | static inline void gic_complete_ack(u32 irqnr) | |
f32c9266 | 767 | { |
f32c9266 | 768 | if (static_branch_likely(&supports_deactivate_key)) |
6efb5092 | 769 | write_gicreg(irqnr, ICC_EOIR1_EL1); |
17ce302f | 770 | |
6efb5092 | 771 | isb(); |
f32c9266 JT |
772 | } |
773 | ||
614ab80c | 774 | static bool gic_rpr_is_nmi_prio(void) |
382e6e17 | 775 | { |
614ab80c MR |
776 | if (!gic_supports_nmi()) |
777 | return false; | |
f32c9266 | 778 | |
614ab80c MR |
779 | return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI)); |
780 | } | |
382e6e17 | 781 | |
614ab80c MR |
782 | static bool gic_irqnr_is_special(u32 irqnr) |
783 | { | |
784 | return irqnr >= 1020 && irqnr <= 1023; | |
785 | } | |
382e6e17 | 786 | |
614ab80c MR |
787 | static void __gic_handle_irq(u32 irqnr, struct pt_regs *regs) |
788 | { | |
789 | if (gic_irqnr_is_special(irqnr)) | |
790 | return; | |
382e6e17 | 791 | |
6efb5092 | 792 | gic_complete_ack(irqnr); |
382e6e17 | 793 | |
614ab80c MR |
794 | if (generic_handle_domain_irq(gic_data.domain, irqnr)) { |
795 | WARN_ONCE(true, "Unexpected interrupt (irqnr %u)\n", irqnr); | |
f32c9266 | 796 | gic_deactivate_unhandled(irqnr); |
382e6e17 | 797 | } |
f32c9266 JT |
798 | } |
799 | ||
614ab80c | 800 | static void __gic_handle_nmi(u32 irqnr, struct pt_regs *regs) |
382e6e17 | 801 | { |
614ab80c MR |
802 | if (gic_irqnr_is_special(irqnr)) |
803 | return; | |
382e6e17 | 804 | |
614ab80c | 805 | gic_complete_ack(irqnr); |
382e6e17 | 806 | |
614ab80c MR |
807 | if (generic_handle_domain_nmi(gic_data.domain, irqnr)) { |
808 | WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr); | |
809 | gic_deactivate_unhandled(irqnr); | |
382e6e17 | 810 | } |
382e6e17 MZ |
811 | } |
812 | ||
614ab80c MR |
813 | /* |
814 | * An exception has been taken from a context with IRQs enabled, and this could | |
815 | * be an IRQ or an NMI. | |
816 | * | |
817 | * The entry code called us with DAIF.IF set to keep NMIs masked. We must clear | |
818 | * DAIF.IF (and update ICC_PMR_EL1 to mask regular IRQs) prior to returning, | |
819 | * after handling any NMI but before handling any IRQ. | |
820 | * | |
821 | * The entry code has performed IRQ entry, and if an NMI is detected we must | |
822 | * perform NMI entry/exit around invoking the handler. | |
823 | */ | |
824 | static void __gic_handle_irq_from_irqson(struct pt_regs *regs) | |
021f6537 | 825 | { |
614ab80c | 826 | bool is_nmi; |
f6c86a41 | 827 | u32 irqnr; |
021f6537 | 828 | |
614ab80c | 829 | irqnr = gic_read_iar(); |
021f6537 | 830 | |
614ab80c | 831 | is_nmi = gic_rpr_is_nmi_prio(); |
a97709f5 | 832 | |
614ab80c MR |
833 | if (is_nmi) { |
834 | nmi_enter(); | |
835 | __gic_handle_nmi(irqnr, regs); | |
836 | nmi_exit(); | |
f32c9266 JT |
837 | } |
838 | ||
3f1f3234 JT |
839 | if (gic_prio_masking_enabled()) { |
840 | gic_pmr_mask_irqs(); | |
841 | gic_arch_enable_irqs(); | |
842 | } | |
843 | ||
614ab80c MR |
844 | if (!is_nmi) |
845 | __gic_handle_irq(irqnr, regs); | |
846 | } | |
64b499d8 | 847 | |
614ab80c MR |
848 | /* |
849 | * An exception has been taken from a context with IRQs disabled, which can only | |
850 | * be an NMI. | |
851 | * | |
852 | * The entry code called us with DAIF.IF set to keep NMIs masked. We must leave | |
853 | * DAIF.IF (and ICC_PMR_EL1) unchanged. | |
854 | * | |
855 | * The entry code has performed NMI entry. | |
856 | */ | |
857 | static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs) | |
858 | { | |
859 | u64 pmr; | |
860 | u32 irqnr; | |
861 | ||
862 | /* | |
863 | * We were in a context with IRQs disabled. However, the | |
864 | * entry code has set PMR to a value that allows any | |
865 | * interrupt to be acknowledged, and not just NMIs. This can | |
866 | * lead to surprising effects if the NMI has been retired in | |
867 | * the meantime, and that there is an IRQ pending. The IRQ | |
868 | * would then be taken in NMI context, something that nobody | |
869 | * wants to debug twice. | |
870 | * | |
871 | * Until we sort this, drop PMR again to a level that will | |
872 | * actually only allow NMIs before reading IAR, and then | |
873 | * restore it to what it was. | |
874 | */ | |
875 | pmr = gic_read_pmr(); | |
876 | gic_pmr_mask_irqs(); | |
877 | isb(); | |
878 | irqnr = gic_read_iar(); | |
879 | gic_write_pmr(pmr); | |
880 | ||
881 | __gic_handle_nmi(irqnr, regs); | |
882 | } | |
883 | ||
884 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
885 | { | |
886 | if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs))) | |
887 | __gic_handle_irq_from_irqsoff(regs); | |
888 | else | |
889 | __gic_handle_irq_from_irqson(regs); | |
021f6537 MZ |
890 | } |
891 | ||
b5cf6073 JT |
892 | static u32 gic_get_pribits(void) |
893 | { | |
894 | u32 pribits; | |
895 | ||
896 | pribits = gic_read_ctlr(); | |
897 | pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
898 | pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
899 | pribits++; | |
900 | ||
901 | return pribits; | |
902 | } | |
903 | ||
904 | static bool gic_has_group0(void) | |
905 | { | |
906 | u32 val; | |
e7932188 JT |
907 | u32 old_pmr; |
908 | ||
909 | old_pmr = gic_read_pmr(); | |
b5cf6073 JT |
910 | |
911 | /* | |
912 | * Let's find out if Group0 is under control of EL3 or not by | |
913 | * setting the highest possible, non-zero priority in PMR. | |
914 | * | |
915 | * If SCR_EL3.FIQ is set, the priority gets shifted down in | |
916 | * order for the CPU interface to set bit 7, and keep the | |
917 | * actual priority in the non-secure range. In the process, it | |
918 | * looses the least significant bit and the actual priority | |
919 | * becomes 0x80. Reading it back returns 0, indicating that | |
920 | * we're don't have access to Group0. | |
921 | */ | |
922 | gic_write_pmr(BIT(8 - gic_get_pribits())); | |
923 | val = gic_read_pmr(); | |
924 | ||
e7932188 JT |
925 | gic_write_pmr(old_pmr); |
926 | ||
b5cf6073 JT |
927 | return val != 0; |
928 | } | |
929 | ||
021f6537 MZ |
930 | static void __init gic_dist_init(void) |
931 | { | |
932 | unsigned int i; | |
933 | u64 affinity; | |
934 | void __iomem *base = gic_data.dist_base; | |
0b04758b | 935 | u32 val; |
021f6537 MZ |
936 | |
937 | /* Disable the distributor */ | |
938 | writel_relaxed(0, base + GICD_CTLR); | |
939 | gic_dist_wait_for_rwp(); | |
940 | ||
7c9b9730 MZ |
941 | /* |
942 | * Configure SPIs as non-secure Group-1. This will only matter | |
943 | * if the GIC only has a single security state. This will not | |
944 | * do the right thing if the kernel is running in secure mode, | |
945 | * but that's not the intended use case anyway. | |
946 | */ | |
211bddd2 | 947 | for (i = 32; i < GIC_LINE_NR; i += 32) |
7c9b9730 MZ |
948 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); |
949 | ||
211bddd2 MZ |
950 | /* Extended SPI range, not handled by the GICv2/GICv3 common code */ |
951 | for (i = 0; i < GIC_ESPI_NR; i += 32) { | |
952 | writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); | |
953 | writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); | |
954 | } | |
955 | ||
956 | for (i = 0; i < GIC_ESPI_NR; i += 32) | |
957 | writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); | |
958 | ||
959 | for (i = 0; i < GIC_ESPI_NR; i += 16) | |
960 | writel_relaxed(0, base + GICD_ICFGRnE + i / 4); | |
961 | ||
962 | for (i = 0; i < GIC_ESPI_NR; i += 4) | |
963 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); | |
964 | ||
63f13483 MZ |
965 | /* Now do the common stuff */ |
966 | gic_dist_config(base, GIC_LINE_NR, NULL); | |
021f6537 | 967 | |
0b04758b MZ |
968 | val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; |
969 | if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { | |
970 | pr_info("Enabling SGIs without active state\n"); | |
971 | val |= GICD_CTLR_nASSGIreq; | |
972 | } | |
973 | ||
63f13483 | 974 | /* Enable distributor with ARE, Group1, and wait for it to drain */ |
0b04758b | 975 | writel_relaxed(val, base + GICD_CTLR); |
63f13483 | 976 | gic_dist_wait_for_rwp(); |
021f6537 MZ |
977 | |
978 | /* | |
979 | * Set all global interrupts to the boot CPU only. ARE must be | |
980 | * enabled. | |
981 | */ | |
3c65cbb7 | 982 | affinity = gic_cpu_to_affinity(smp_processor_id()); |
211bddd2 | 983 | for (i = 32; i < GIC_LINE_NR; i++) |
72c97126 | 984 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
211bddd2 MZ |
985 | |
986 | for (i = 0; i < GIC_ESPI_NR; i++) | |
987 | gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); | |
021f6537 MZ |
988 | } |
989 | ||
0d94ded2 | 990 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 991 | { |
0d94ded2 | 992 | int ret = -ENODEV; |
021f6537 MZ |
993 | int i; |
994 | ||
f5c1434c MZ |
995 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
996 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 997 | u64 typer; |
021f6537 MZ |
998 | u32 reg; |
999 | ||
1000 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1001 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
1002 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
1003 | pr_warn("No redistributor present @%p\n", ptr); | |
1004 | break; | |
1005 | } | |
1006 | ||
1007 | do { | |
72c97126 | 1008 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
1009 | ret = fn(gic_data.redist_regions + i, ptr); |
1010 | if (!ret) | |
021f6537 | 1011 | return 0; |
021f6537 | 1012 | |
b70fb7af TN |
1013 | if (gic_data.redist_regions[i].single_redist) |
1014 | break; | |
1015 | ||
021f6537 MZ |
1016 | if (gic_data.redist_stride) { |
1017 | ptr += gic_data.redist_stride; | |
1018 | } else { | |
1019 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
1020 | if (typer & GICR_TYPER_VLPIS) | |
1021 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
1022 | } | |
1023 | } while (!(typer & GICR_TYPER_LAST)); | |
1024 | } | |
1025 | ||
0d94ded2 MZ |
1026 | return ret ? -ENODEV : 0; |
1027 | } | |
1028 | ||
1029 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
1030 | { | |
3c65cbb7 | 1031 | unsigned long mpidr; |
0d94ded2 MZ |
1032 | u64 typer; |
1033 | u32 aff; | |
1034 | ||
1035 | /* | |
1036 | * Convert affinity to a 32bit value that can be matched to | |
1037 | * GICR_TYPER bits [63:32]. | |
1038 | */ | |
3c65cbb7 MZ |
1039 | mpidr = gic_cpu_to_affinity(smp_processor_id()); |
1040 | ||
0d94ded2 MZ |
1041 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | |
1042 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
1043 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
1044 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
1045 | ||
1046 | typer = gic_read_typer(ptr + GICR_TYPER); | |
1047 | if ((typer >> 32) == aff) { | |
1048 | u64 offset = ptr - region->redist_base; | |
9058a4e9 | 1049 | raw_spin_lock_init(&gic_data_rdist()->rd_lock); |
0d94ded2 MZ |
1050 | gic_data_rdist_rd_base() = ptr; |
1051 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
1052 | ||
1053 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
1054 | smp_processor_id(), mpidr, | |
1055 | (int)(region - gic_data.redist_regions), | |
1056 | &gic_data_rdist()->phys_base); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | /* Try next one */ | |
1061 | return 1; | |
1062 | } | |
1063 | ||
1064 | static int gic_populate_rdist(void) | |
1065 | { | |
1066 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
1067 | return 0; | |
1068 | ||
021f6537 | 1069 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 1070 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
1071 | smp_processor_id(), |
1072 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
1073 | return -ENODEV; |
1074 | } | |
1075 | ||
1a60e1e6 MZ |
1076 | static int __gic_update_rdist_properties(struct redist_region *region, |
1077 | void __iomem *ptr) | |
0edc23ea MZ |
1078 | { |
1079 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
a837ed36 | 1080 | u32 ctlr = readl_relaxed(ptr + GICR_CTLR); |
b25319d2 | 1081 | |
4d968297 | 1082 | /* Boot-time cleanup */ |
79a7f77b MZ |
1083 | if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { |
1084 | u64 val; | |
1085 | ||
1086 | /* Deactivate any present vPE */ | |
1087 | val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER); | |
1088 | if (val & GICR_VPENDBASER_Valid) | |
1089 | gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast, | |
1090 | ptr + SZ_128K + GICR_VPENDBASER); | |
1091 | ||
1092 | /* Mark the VPE table as invalid */ | |
1093 | val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER); | |
1094 | val &= ~GICR_VPROPBASER_4_1_VALID; | |
1095 | gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER); | |
1096 | } | |
1097 | ||
0edc23ea | 1098 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); |
b25319d2 | 1099 | |
a837ed36 MZ |
1100 | /* |
1101 | * TYPER.RVPEID implies some form of DirectLPI, no matter what the | |
1102 | * doc says... :-/ And CTLR.IR implies another subset of DirectLPI | |
1103 | * that the ITS driver can make use of for LPIs (and not VLPIs). | |
1104 | * | |
1105 | * These are 3 different ways to express the same thing, depending | |
1106 | * on the revision of the architecture and its relaxations over | |
1107 | * time. Just group them under the 'direct_lpi' banner. | |
1108 | */ | |
b25319d2 MZ |
1109 | gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); |
1110 | gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | | |
a837ed36 | 1111 | !!(ctlr & GICR_CTLR_IR) | |
b25319d2 | 1112 | gic_data.rdists.has_rvpeid); |
96806229 | 1113 | gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); |
b25319d2 MZ |
1114 | |
1115 | /* Detect non-sensical configurations */ | |
1116 | if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { | |
1117 | gic_data.rdists.has_direct_lpi = false; | |
1118 | gic_data.rdists.has_vlpis = false; | |
1119 | gic_data.rdists.has_rvpeid = false; | |
1120 | } | |
1121 | ||
5f51f803 | 1122 | gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); |
0edc23ea MZ |
1123 | |
1124 | return 1; | |
1125 | } | |
1126 | ||
1a60e1e6 | 1127 | static void gic_update_rdist_properties(void) |
0edc23ea | 1128 | { |
1a60e1e6 MZ |
1129 | gic_data.ppi_nr = UINT_MAX; |
1130 | gic_iterate_rdists(__gic_update_rdist_properties); | |
1131 | if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) | |
1132 | gic_data.ppi_nr = 0; | |
a837ed36 MZ |
1133 | pr_info("GICv3 features: %d PPIs%s%s\n", |
1134 | gic_data.ppi_nr, | |
1135 | gic_data.has_rss ? ", RSS" : "", | |
1136 | gic_data.rdists.has_direct_lpi ? ", DirectLPI" : ""); | |
1137 | ||
96806229 MZ |
1138 | if (gic_data.rdists.has_vlpis) |
1139 | pr_info("GICv4 features: %s%s%s\n", | |
1140 | gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", | |
1141 | gic_data.rdists.has_rvpeid ? "RVPEID " : "", | |
1142 | gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); | |
0edc23ea MZ |
1143 | } |
1144 | ||
d98d0a99 JT |
1145 | /* Check whether it's single security state view */ |
1146 | static inline bool gic_dist_security_disabled(void) | |
1147 | { | |
1148 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
1149 | } | |
1150 | ||
3708d52f SH |
1151 | static void gic_cpu_sys_reg_init(void) |
1152 | { | |
eda0d04a | 1153 | int i, cpu = smp_processor_id(); |
3c65cbb7 | 1154 | u64 mpidr = gic_cpu_to_affinity(cpu); |
eda0d04a | 1155 | u64 need_rss = MPIDR_RS(mpidr); |
33625282 | 1156 | bool group0; |
b5cf6073 | 1157 | u32 pribits; |
eda0d04a | 1158 | |
7cabd008 MZ |
1159 | /* |
1160 | * Need to check that the SRE bit has actually been set. If | |
1161 | * not, it means that SRE is disabled at EL2. We're going to | |
1162 | * die painfully, and there is nothing we can do about it. | |
1163 | * | |
1164 | * Kindly inform the luser. | |
1165 | */ | |
1166 | if (!gic_enable_sre()) | |
1167 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f | 1168 | |
b5cf6073 | 1169 | pribits = gic_get_pribits(); |
33625282 | 1170 | |
b5cf6073 | 1171 | group0 = gic_has_group0(); |
33625282 | 1172 | |
3708d52f | 1173 | /* Set priority mask register */ |
d98d0a99 | 1174 | if (!gic_prio_masking_enabled()) { |
e7932188 | 1175 | write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); |
33678059 | 1176 | } else if (gic_supports_nmi()) { |
d98d0a99 JT |
1177 | /* |
1178 | * Mismatch configuration with boot CPU, the system is likely | |
1179 | * to die as interrupt masking will not work properly on all | |
1180 | * CPUs | |
33678059 AE |
1181 | * |
1182 | * The boot CPU calls this function before enabling NMI support, | |
1183 | * and as a result we'll never see this warning in the boot path | |
1184 | * for that CPU. | |
d98d0a99 | 1185 | */ |
33678059 AE |
1186 | if (static_branch_unlikely(&gic_nonsecure_priorities)) |
1187 | WARN_ON(!group0 || gic_dist_security_disabled()); | |
1188 | else | |
1189 | WARN_ON(group0 && !gic_dist_security_disabled()); | |
d98d0a99 | 1190 | } |
3708d52f | 1191 | |
91ef8442 DT |
1192 | /* |
1193 | * Some firmwares hand over to the kernel with the BPR changed from | |
1194 | * its reset value (and with a value large enough to prevent | |
1195 | * any pre-emptive interrupts from working at all). Writing a zero | |
1196 | * to BPR restores is reset value. | |
1197 | */ | |
1198 | gic_write_bpr1(0); | |
1199 | ||
d01d3274 | 1200 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
1201 | /* EOI drops priority only (mode 1) */ |
1202 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
1203 | } else { | |
1204 | /* EOI deactivates interrupt too (mode 0) */ | |
1205 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
1206 | } | |
3708d52f | 1207 | |
33625282 MZ |
1208 | /* Always whack Group0 before Group1 */ |
1209 | if (group0) { | |
1210 | switch(pribits) { | |
1211 | case 8: | |
1212 | case 7: | |
1213 | write_gicreg(0, ICC_AP0R3_EL1); | |
1214 | write_gicreg(0, ICC_AP0R2_EL1); | |
df561f66 | 1215 | fallthrough; |
33625282 MZ |
1216 | case 6: |
1217 | write_gicreg(0, ICC_AP0R1_EL1); | |
df561f66 | 1218 | fallthrough; |
33625282 MZ |
1219 | case 5: |
1220 | case 4: | |
1221 | write_gicreg(0, ICC_AP0R0_EL1); | |
1222 | } | |
1223 | ||
1224 | isb(); | |
1225 | } | |
d6062a6d | 1226 | |
33625282 | 1227 | switch(pribits) { |
d6062a6d MZ |
1228 | case 8: |
1229 | case 7: | |
d6062a6d | 1230 | write_gicreg(0, ICC_AP1R3_EL1); |
d6062a6d | 1231 | write_gicreg(0, ICC_AP1R2_EL1); |
df561f66 | 1232 | fallthrough; |
d6062a6d | 1233 | case 6: |
d6062a6d | 1234 | write_gicreg(0, ICC_AP1R1_EL1); |
df561f66 | 1235 | fallthrough; |
d6062a6d MZ |
1236 | case 5: |
1237 | case 4: | |
d6062a6d MZ |
1238 | write_gicreg(0, ICC_AP1R0_EL1); |
1239 | } | |
1240 | ||
1241 | isb(); | |
1242 | ||
3708d52f SH |
1243 | /* ... and let's hit the road... */ |
1244 | gic_write_grpen1(1); | |
eda0d04a SD |
1245 | |
1246 | /* Keep the RSS capability status in per_cpu variable */ | |
1247 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
1248 | ||
1249 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
1250 | for_each_online_cpu(i) { | |
1251 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
1252 | ||
3c65cbb7 | 1253 | need_rss |= MPIDR_RS(gic_cpu_to_affinity(i)); |
eda0d04a SD |
1254 | if (need_rss && (!have_rss)) |
1255 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
1256 | cpu, (unsigned long)mpidr, | |
3c65cbb7 | 1257 | i, (unsigned long)gic_cpu_to_affinity(i)); |
eda0d04a SD |
1258 | } |
1259 | ||
1260 | /** | |
1261 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
1262 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
1263 | * UNPREDICTABLE choice of : | |
1264 | * - The write is ignored. | |
1265 | * - The RS field is treated as 0. | |
1266 | */ | |
1267 | if (need_rss && (!gic_data.has_rss)) | |
1268 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
1269 | } |
1270 | ||
f736d65d MZ |
1271 | static bool gicv3_nolpi; |
1272 | ||
1273 | static int __init gicv3_nolpi_cfg(char *buf) | |
1274 | { | |
5e279739 | 1275 | return kstrtobool(buf, &gicv3_nolpi); |
f736d65d MZ |
1276 | } |
1277 | early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); | |
1278 | ||
da33f31d MZ |
1279 | static int gic_dist_supports_lpis(void) |
1280 | { | |
d38a71c5 MZ |
1281 | return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && |
1282 | !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && | |
1283 | !gicv3_nolpi); | |
da33f31d MZ |
1284 | } |
1285 | ||
021f6537 MZ |
1286 | static void gic_cpu_init(void) |
1287 | { | |
1288 | void __iomem *rbase; | |
1a60e1e6 | 1289 | int i; |
021f6537 MZ |
1290 | |
1291 | /* Register ourselves with the rest of the world */ | |
1292 | if (gic_populate_rdist()) | |
1293 | return; | |
1294 | ||
a2c22510 | 1295 | gic_enable_redist(true); |
021f6537 | 1296 | |
ad5a78d3 MZ |
1297 | WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && |
1298 | !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), | |
1299 | "Distributor has extended ranges, but CPU%d doesn't\n", | |
1300 | smp_processor_id()); | |
1301 | ||
021f6537 MZ |
1302 | rbase = gic_data_rdist_sgi_base(); |
1303 | ||
7c9b9730 | 1304 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
a02026bf | 1305 | for (i = 0; i < gic_data.ppi_nr + SGI_NR; i += 32) |
1a60e1e6 | 1306 | writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); |
7c9b9730 | 1307 | |
a02026bf | 1308 | gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); |
021f6537 | 1309 | |
3708d52f SH |
1310 | /* initialise system registers */ |
1311 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
1312 | } |
1313 | ||
1314 | #ifdef CONFIG_SMP | |
6670a6d8 | 1315 | |
eda0d04a SD |
1316 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
1317 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
1318 | ||
6670a6d8 | 1319 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 1320 | { |
6670a6d8 | 1321 | gic_cpu_init(); |
d38a71c5 MZ |
1322 | |
1323 | if (gic_dist_supports_lpis()) | |
1324 | its_cpu_init(); | |
1325 | ||
6670a6d8 | 1326 | return 0; |
021f6537 MZ |
1327 | } |
1328 | ||
021f6537 | 1329 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 1330 | unsigned long cluster_id) |
021f6537 | 1331 | { |
727653d6 | 1332 | int next_cpu, cpu = *base_cpu; |
3c65cbb7 | 1333 | unsigned long mpidr; |
021f6537 MZ |
1334 | u16 tlist = 0; |
1335 | ||
3c65cbb7 MZ |
1336 | mpidr = gic_cpu_to_affinity(cpu); |
1337 | ||
021f6537 | 1338 | while (cpu < nr_cpu_ids) { |
021f6537 MZ |
1339 | tlist |= 1 << (mpidr & 0xf); |
1340 | ||
727653d6 JM |
1341 | next_cpu = cpumask_next(cpu, mask); |
1342 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 1343 | goto out; |
727653d6 | 1344 | cpu = next_cpu; |
021f6537 | 1345 | |
3c65cbb7 | 1346 | mpidr = gic_cpu_to_affinity(cpu); |
021f6537 | 1347 | |
eda0d04a | 1348 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
1349 | cpu--; |
1350 | goto out; | |
1351 | } | |
1352 | } | |
1353 | out: | |
1354 | *base_cpu = cpu; | |
1355 | return tlist; | |
1356 | } | |
1357 | ||
7e580278 AP |
1358 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
1359 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
1360 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
1361 | ||
021f6537 MZ |
1362 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
1363 | { | |
1364 | u64 val; | |
1365 | ||
7e580278 AP |
1366 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
1367 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
1368 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
1369 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 1370 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 1371 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 1372 | |
b6dd4d83 | 1373 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
1374 | gic_write_sgi1r(val); |
1375 | } | |
1376 | ||
64b499d8 | 1377 | static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) |
021f6537 MZ |
1378 | { |
1379 | int cpu; | |
1380 | ||
64b499d8 | 1381 | if (WARN_ON(d->hwirq >= 16)) |
021f6537 MZ |
1382 | return; |
1383 | ||
1384 | /* | |
1385 | * Ensure that stores to Normal memory are visible to the | |
1386 | * other CPUs before issuing the IPI. | |
1387 | */ | |
80e4e1f4 | 1388 | dsb(ishst); |
021f6537 | 1389 | |
f9b531fe | 1390 | for_each_cpu(cpu, mask) { |
3c65cbb7 | 1391 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu)); |
021f6537 MZ |
1392 | u16 tlist; |
1393 | ||
1394 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
64b499d8 | 1395 | gic_send_sgi(cluster_id, tlist, d->hwirq); |
021f6537 MZ |
1396 | } |
1397 | ||
1398 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
1399 | isb(); | |
1400 | } | |
1401 | ||
8a94c1ab | 1402 | static void __init gic_smp_init(void) |
021f6537 | 1403 | { |
64b499d8 MZ |
1404 | struct irq_fwspec sgi_fwspec = { |
1405 | .fwnode = gic_data.fwnode, | |
1406 | .param_count = 1, | |
1407 | }; | |
1408 | int base_sgi; | |
1409 | ||
6896bcd1 | 1410 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
1411 | "irqchip/arm/gicv3:starting", |
1412 | gic_starting_cpu, NULL); | |
64b499d8 MZ |
1413 | |
1414 | /* Register all 8 non-secure SGIs */ | |
0e2213fe | 1415 | base_sgi = irq_domain_alloc_irqs(gic_data.domain, 8, NUMA_NO_NODE, &sgi_fwspec); |
64b499d8 MZ |
1416 | if (WARN_ON(base_sgi <= 0)) |
1417 | return; | |
1418 | ||
1419 | set_smp_ipi_range(base_sgi, 8); | |
021f6537 MZ |
1420 | } |
1421 | ||
1422 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
1423 | bool force) | |
1424 | { | |
65a30f8b | 1425 | unsigned int cpu; |
e91b036e | 1426 | u32 offset, index; |
021f6537 MZ |
1427 | void __iomem *reg; |
1428 | int enabled; | |
1429 | u64 val; | |
1430 | ||
65a30f8b SP |
1431 | if (force) |
1432 | cpu = cpumask_first(mask_val); | |
1433 | else | |
1434 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
1435 | ||
866d7c1b SP |
1436 | if (cpu >= nr_cpu_ids) |
1437 | return -EINVAL; | |
1438 | ||
021f6537 MZ |
1439 | if (gic_irq_in_rdist(d)) |
1440 | return -EINVAL; | |
1441 | ||
1442 | /* If interrupt was enabled, disable it first */ | |
1443 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
1444 | if (enabled) | |
1445 | gic_mask_irq(d); | |
1446 | ||
e91b036e MZ |
1447 | offset = convert_offset_index(d, GICD_IROUTER, &index); |
1448 | reg = gic_dist_base(d) + offset + (index * 8); | |
3c65cbb7 | 1449 | val = gic_cpu_to_affinity(cpu); |
021f6537 | 1450 | |
72c97126 | 1451 | gic_write_irouter(val, reg); |
021f6537 MZ |
1452 | |
1453 | /* | |
1454 | * If the interrupt was enabled, enabled it again. Otherwise, | |
1455 | * just wait for the distributor to have digested our changes. | |
1456 | */ | |
1457 | if (enabled) | |
1458 | gic_unmask_irq(d); | |
021f6537 | 1459 | |
956ae91a MZ |
1460 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
1461 | ||
0fc6fa29 | 1462 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
1463 | } |
1464 | #else | |
1465 | #define gic_set_affinity NULL | |
64b499d8 | 1466 | #define gic_ipi_send_mask NULL |
021f6537 MZ |
1467 | #define gic_smp_init() do { } while(0) |
1468 | #endif | |
1469 | ||
17f644e9 VS |
1470 | static int gic_retrigger(struct irq_data *data) |
1471 | { | |
1472 | return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); | |
1473 | } | |
1474 | ||
3708d52f SH |
1475 | #ifdef CONFIG_CPU_PM |
1476 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
1477 | unsigned long cmd, void *v) | |
1478 | { | |
1479 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
1480 | if (gic_dist_security_disabled()) |
1481 | gic_enable_redist(true); | |
3708d52f | 1482 | gic_cpu_sys_reg_init(); |
ccd9432a | 1483 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
1484 | gic_write_grpen1(0); |
1485 | gic_enable_redist(false); | |
1486 | } | |
1487 | return NOTIFY_OK; | |
1488 | } | |
1489 | ||
1490 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
1491 | .notifier_call = gic_cpu_pm_notifier, | |
1492 | }; | |
1493 | ||
1494 | static void gic_cpu_pm_init(void) | |
1495 | { | |
1496 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
1497 | } | |
1498 | ||
1499 | #else | |
1500 | static inline void gic_cpu_pm_init(void) { } | |
1501 | #endif /* CONFIG_CPU_PM */ | |
1502 | ||
021f6537 MZ |
1503 | static struct irq_chip gic_chip = { |
1504 | .name = "GICv3", | |
1505 | .irq_mask = gic_mask_irq, | |
1506 | .irq_unmask = gic_unmask_irq, | |
1507 | .irq_eoi = gic_eoi_irq, | |
1508 | .irq_set_type = gic_set_type, | |
1509 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1510 | .irq_retrigger = gic_retrigger, |
b594c6e2 MZ |
1511 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1512 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
101b35f7 JT |
1513 | .irq_nmi_setup = gic_irq_nmi_setup, |
1514 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1515 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1516 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1517 | IRQCHIP_SKIP_SET_WAKE | | |
1518 | IRQCHIP_MASK_ON_SUSPEND, | |
021f6537 MZ |
1519 | }; |
1520 | ||
0b6a3da9 MZ |
1521 | static struct irq_chip gic_eoimode1_chip = { |
1522 | .name = "GICv3", | |
1523 | .irq_mask = gic_eoimode1_mask_irq, | |
1524 | .irq_unmask = gic_unmask_irq, | |
1525 | .irq_eoi = gic_eoimode1_eoi_irq, | |
1526 | .irq_set_type = gic_set_type, | |
1527 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1528 | .irq_retrigger = gic_retrigger, |
0b6a3da9 MZ |
1529 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1530 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 1531 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
101b35f7 JT |
1532 | .irq_nmi_setup = gic_irq_nmi_setup, |
1533 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1534 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1535 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1536 | IRQCHIP_SKIP_SET_WAKE | | |
1537 | IRQCHIP_MASK_ON_SUSPEND, | |
0b6a3da9 MZ |
1538 | }; |
1539 | ||
021f6537 MZ |
1540 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
1541 | irq_hw_number_t hw) | |
1542 | { | |
0b6a3da9 | 1543 | struct irq_chip *chip = &gic_chip; |
1b57d91b | 1544 | struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); |
0b6a3da9 | 1545 | |
d01d3274 | 1546 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1547 | chip = &gic_eoimode1_chip; |
1548 | ||
e91b036e | 1549 | switch (__get_intid_range(hw)) { |
70a29c32 | 1550 | case SGI_RANGE: |
e91b036e | 1551 | case PPI_RANGE: |
5f51f803 | 1552 | case EPPI_RANGE: |
021f6537 | 1553 | irq_set_percpu_devid(irq); |
0b6a3da9 | 1554 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1555 | handle_percpu_devid_irq, NULL, NULL); |
e91b036e MZ |
1556 | break; |
1557 | ||
1558 | case SPI_RANGE: | |
211bddd2 | 1559 | case ESPI_RANGE: |
0b6a3da9 | 1560 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1561 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 1562 | irq_set_probe(irq); |
1b57d91b | 1563 | irqd_set_single_target(irqd); |
e91b036e MZ |
1564 | break; |
1565 | ||
1566 | case LPI_RANGE: | |
da33f31d MZ |
1567 | if (!gic_dist_supports_lpis()) |
1568 | return -EPERM; | |
0b6a3da9 | 1569 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 1570 | handle_fasteoi_irq, NULL, NULL); |
e91b036e MZ |
1571 | break; |
1572 | ||
1573 | default: | |
1574 | return -EPERM; | |
da33f31d MZ |
1575 | } |
1576 | ||
1b57d91b VS |
1577 | /* Prevents SW retriggers which mess up the ACK/EOI ordering */ |
1578 | irqd_set_handle_enforce_irqctx(irqd); | |
021f6537 MZ |
1579 | return 0; |
1580 | } | |
1581 | ||
f833f57f MZ |
1582 | static int gic_irq_domain_translate(struct irq_domain *d, |
1583 | struct irq_fwspec *fwspec, | |
1584 | unsigned long *hwirq, | |
1585 | unsigned int *type) | |
021f6537 | 1586 | { |
64b499d8 MZ |
1587 | if (fwspec->param_count == 1 && fwspec->param[0] < 16) { |
1588 | *hwirq = fwspec->param[0]; | |
1589 | *type = IRQ_TYPE_EDGE_RISING; | |
1590 | return 0; | |
1591 | } | |
1592 | ||
f833f57f MZ |
1593 | if (is_of_node(fwspec->fwnode)) { |
1594 | if (fwspec->param_count < 3) | |
1595 | return -EINVAL; | |
021f6537 | 1596 | |
db8c70ec MZ |
1597 | switch (fwspec->param[0]) { |
1598 | case 0: /* SPI */ | |
1599 | *hwirq = fwspec->param[1] + 32; | |
1600 | break; | |
1601 | case 1: /* PPI */ | |
1602 | *hwirq = fwspec->param[1] + 16; | |
1603 | break; | |
211bddd2 MZ |
1604 | case 2: /* ESPI */ |
1605 | *hwirq = fwspec->param[1] + ESPI_BASE_INTID; | |
1606 | break; | |
5f51f803 MZ |
1607 | case 3: /* EPPI */ |
1608 | *hwirq = fwspec->param[1] + EPPI_BASE_INTID; | |
1609 | break; | |
db8c70ec MZ |
1610 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
1611 | *hwirq = fwspec->param[1]; | |
1612 | break; | |
5f51f803 MZ |
1613 | case GIC_IRQ_TYPE_PARTITION: |
1614 | *hwirq = fwspec->param[1]; | |
1615 | if (fwspec->param[1] >= 16) | |
1616 | *hwirq += EPPI_BASE_INTID - 16; | |
1617 | else | |
1618 | *hwirq += 16; | |
1619 | break; | |
db8c70ec MZ |
1620 | default: |
1621 | return -EINVAL; | |
1622 | } | |
f833f57f MZ |
1623 | |
1624 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
6ef6386e | 1625 | |
65da7d19 MZ |
1626 | /* |
1627 | * Make it clear that broken DTs are... broken. | |
a359f757 | 1628 | * Partitioned PPIs are an unfortunate exception. |
65da7d19 MZ |
1629 | */ |
1630 | WARN_ON(*type == IRQ_TYPE_NONE && | |
1631 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | |
f833f57f | 1632 | return 0; |
021f6537 MZ |
1633 | } |
1634 | ||
ffa7d616 TN |
1635 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
1636 | if(fwspec->param_count != 2) | |
1637 | return -EINVAL; | |
1638 | ||
544808f7 AP |
1639 | if (fwspec->param[0] < 16) { |
1640 | pr_err(FW_BUG "Illegal GSI%d translation request\n", | |
1641 | fwspec->param[0]); | |
1642 | return -EINVAL; | |
1643 | } | |
1644 | ||
ffa7d616 TN |
1645 | *hwirq = fwspec->param[0]; |
1646 | *type = fwspec->param[1]; | |
6ef6386e MZ |
1647 | |
1648 | WARN_ON(*type == IRQ_TYPE_NONE); | |
ffa7d616 TN |
1649 | return 0; |
1650 | } | |
1651 | ||
f833f57f | 1652 | return -EINVAL; |
021f6537 MZ |
1653 | } |
1654 | ||
443acc4f MZ |
1655 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1656 | unsigned int nr_irqs, void *arg) | |
1657 | { | |
1658 | int i, ret; | |
1659 | irq_hw_number_t hwirq; | |
1660 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1661 | struct irq_fwspec *fwspec = arg; |
443acc4f | 1662 | |
f833f57f | 1663 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
1664 | if (ret) |
1665 | return ret; | |
1666 | ||
63c16c6e SP |
1667 | for (i = 0; i < nr_irqs; i++) { |
1668 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1669 | if (ret) | |
1670 | return ret; | |
1671 | } | |
443acc4f MZ |
1672 | |
1673 | return 0; | |
1674 | } | |
1675 | ||
1676 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
1677 | unsigned int nr_irqs) | |
1678 | { | |
1679 | int i; | |
1680 | ||
1681 | for (i = 0; i < nr_irqs; i++) { | |
1682 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
1683 | irq_set_handler(virq + i, NULL); | |
1684 | irq_domain_reset_irq_data(d); | |
1685 | } | |
1686 | } | |
1687 | ||
d753f849 JM |
1688 | static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, |
1689 | irq_hw_number_t hwirq) | |
1690 | { | |
1691 | enum gic_intid_range range; | |
1692 | ||
1693 | if (!gic_data.ppi_descs) | |
1694 | return false; | |
1695 | ||
1696 | if (!is_of_node(fwspec->fwnode)) | |
1697 | return false; | |
1698 | ||
1699 | if (fwspec->param_count < 4 || !fwspec->param[3]) | |
1700 | return false; | |
1701 | ||
1702 | range = __get_intid_range(hwirq); | |
1703 | if (range != PPI_RANGE && range != EPPI_RANGE) | |
1704 | return false; | |
1705 | ||
1706 | return true; | |
1707 | } | |
1708 | ||
e3825ba1 MZ |
1709 | static int gic_irq_domain_select(struct irq_domain *d, |
1710 | struct irq_fwspec *fwspec, | |
1711 | enum irq_domain_bus_token bus_token) | |
1712 | { | |
d753f849 JM |
1713 | unsigned int type, ret, ppi_idx; |
1714 | irq_hw_number_t hwirq; | |
1715 | ||
e3825ba1 MZ |
1716 | /* Not for us */ |
1717 | if (fwspec->fwnode != d->fwnode) | |
1718 | return 0; | |
1719 | ||
1720 | /* If this is not DT, then we have a single domain */ | |
1721 | if (!is_of_node(fwspec->fwnode)) | |
1722 | return 1; | |
1723 | ||
d753f849 JM |
1724 | ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type); |
1725 | if (WARN_ON_ONCE(ret)) | |
1726 | return 0; | |
1727 | ||
1728 | if (!fwspec_is_partitioned_ppi(fwspec, hwirq)) | |
1729 | return d == gic_data.domain; | |
1730 | ||
e3825ba1 MZ |
1731 | /* |
1732 | * If this is a PPI and we have a 4th (non-null) parameter, | |
1733 | * then we need to match the partition domain. | |
1734 | */ | |
d753f849 JM |
1735 | ppi_idx = __gic_get_ppi_index(hwirq); |
1736 | return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]); | |
e3825ba1 MZ |
1737 | } |
1738 | ||
021f6537 | 1739 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 1740 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
1741 | .alloc = gic_irq_domain_alloc, |
1742 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
1743 | .select = gic_irq_domain_select, |
1744 | }; | |
1745 | ||
1746 | static int partition_domain_translate(struct irq_domain *d, | |
1747 | struct irq_fwspec *fwspec, | |
1748 | unsigned long *hwirq, | |
1749 | unsigned int *type) | |
1750 | { | |
d753f849 | 1751 | unsigned long ppi_intid; |
e3825ba1 | 1752 | struct device_node *np; |
d753f849 | 1753 | unsigned int ppi_idx; |
e3825ba1 MZ |
1754 | int ret; |
1755 | ||
52085d3f MZ |
1756 | if (!gic_data.ppi_descs) |
1757 | return -ENOMEM; | |
1758 | ||
e3825ba1 MZ |
1759 | np = of_find_node_by_phandle(fwspec->param[3]); |
1760 | if (WARN_ON(!np)) | |
1761 | return -EINVAL; | |
1762 | ||
d753f849 JM |
1763 | ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type); |
1764 | if (WARN_ON_ONCE(ret)) | |
1765 | return 0; | |
1766 | ||
1767 | ppi_idx = __gic_get_ppi_index(ppi_intid); | |
1768 | ret = partition_translate_id(gic_data.ppi_descs[ppi_idx], | |
e3825ba1 MZ |
1769 | of_node_to_fwnode(np)); |
1770 | if (ret < 0) | |
1771 | return ret; | |
1772 | ||
1773 | *hwirq = ret; | |
1774 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | static const struct irq_domain_ops partition_domain_ops = { | |
1780 | .translate = partition_domain_translate, | |
1781 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1782 | }; |
1783 | ||
9c8114c2 SK |
1784 | static bool gic_enable_quirk_msm8996(void *data) |
1785 | { | |
1786 | struct gic_chip_data *d = data; | |
1787 | ||
1788 | d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; | |
1789 | ||
1790 | return true; | |
1791 | } | |
1792 | ||
44bd78dd DA |
1793 | static bool gic_enable_quirk_mtk_gicr(void *data) |
1794 | { | |
1795 | struct gic_chip_data *d = data; | |
1796 | ||
1797 | d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; | |
1798 | ||
1799 | return true; | |
1800 | } | |
1801 | ||
d01fd161 MZ |
1802 | static bool gic_enable_quirk_cavium_38539(void *data) |
1803 | { | |
1804 | struct gic_chip_data *d = data; | |
1805 | ||
1806 | d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; | |
1807 | ||
1808 | return true; | |
1809 | } | |
1810 | ||
7f2481b3 MZ |
1811 | static bool gic_enable_quirk_hip06_07(void *data) |
1812 | { | |
1813 | struct gic_chip_data *d = data; | |
1814 | ||
1815 | /* | |
1816 | * HIP06 GICD_IIDR clashes with GIC-600 product number (despite | |
1817 | * not being an actual ARM implementation). The saving grace is | |
1818 | * that GIC-600 doesn't have ESPI, so nothing to do in that case. | |
1819 | * HIP07 doesn't even have a proper IIDR, and still pretends to | |
1820 | * have ESPI. In both cases, put them right. | |
1821 | */ | |
1822 | if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { | |
1823 | /* Zero both ESPI and the RES0 field next to it... */ | |
1824 | d->rdists.gicd_typer &= ~GENMASK(9, 8); | |
1825 | return true; | |
1826 | } | |
1827 | ||
1828 | return false; | |
1829 | } | |
1830 | ||
35727af2 SD |
1831 | #define T241_CHIPN_MASK GENMASK_ULL(45, 44) |
1832 | #define T241_CHIP_GICDA_OFFSET 0x1580000 | |
1833 | #define SMCCC_SOC_ID_T241 0x036b0241 | |
1834 | ||
1835 | static bool gic_enable_quirk_nvidia_t241(void *data) | |
1836 | { | |
1837 | s32 soc_id = arm_smccc_get_soc_id_version(); | |
1838 | unsigned long chip_bmask = 0; | |
1839 | phys_addr_t phys; | |
1840 | u32 i; | |
1841 | ||
1842 | /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */ | |
1843 | if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241)) | |
1844 | return false; | |
1845 | ||
1846 | /* Find the chips based on GICR regions PHYS addr */ | |
1847 | for (i = 0; i < gic_data.nr_redist_regions; i++) { | |
1848 | chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK, | |
1849 | (u64)gic_data.redist_regions[i].phys_base)); | |
1850 | } | |
1851 | ||
1852 | if (hweight32(chip_bmask) < 3) | |
1853 | return false; | |
1854 | ||
1855 | /* Setup GICD alias regions */ | |
1856 | for (i = 0; i < ARRAY_SIZE(t241_dist_base_alias); i++) { | |
1857 | if (chip_bmask & BIT(i)) { | |
1858 | phys = gic_data.dist_phys_base + T241_CHIP_GICDA_OFFSET; | |
1859 | phys |= FIELD_PREP(T241_CHIPN_MASK, i); | |
1860 | t241_dist_base_alias[i] = ioremap(phys, SZ_64K); | |
1861 | WARN_ON_ONCE(!t241_dist_base_alias[i]); | |
1862 | } | |
1863 | } | |
1864 | static_branch_enable(&gic_nvidia_t241_erratum); | |
1865 | return true; | |
1866 | } | |
1867 | ||
b4d81fab | 1868 | static bool gic_enable_quirk_asr8601(void *data) |
1869 | { | |
1870 | struct gic_chip_data *d = data; | |
1871 | ||
1872 | d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001; | |
1873 | ||
1874 | return true; | |
1875 | } | |
1876 | ||
6fe5c68e LP |
1877 | static bool gic_enable_quirk_arm64_2941627(void *data) |
1878 | { | |
1879 | static_branch_enable(&gic_arm64_2941627_erratum); | |
1880 | return true; | |
1881 | } | |
1882 | ||
7f2481b3 MZ |
1883 | static const struct gic_quirk gic_quirks[] = { |
1884 | { | |
1885 | .desc = "GICv3: Qualcomm MSM8996 broken firmware", | |
1886 | .compatible = "qcom,msm8996-gic-v3", | |
1887 | .init = gic_enable_quirk_msm8996, | |
1888 | }, | |
b4d81fab | 1889 | { |
1890 | .desc = "GICv3: ASR erratum 8601001", | |
1891 | .compatible = "asr,asr8601-gic-v3", | |
1892 | .init = gic_enable_quirk_asr8601, | |
1893 | }, | |
44bd78dd DA |
1894 | { |
1895 | .desc = "GICv3: Mediatek Chromebook GICR save problem", | |
1896 | .property = "mediatek,broken-save-restore-fw", | |
1897 | .init = gic_enable_quirk_mtk_gicr, | |
1898 | }, | |
7f2481b3 MZ |
1899 | { |
1900 | .desc = "GICv3: HIP06 erratum 161010803", | |
1901 | .iidr = 0x0204043b, | |
1902 | .mask = 0xffffffff, | |
1903 | .init = gic_enable_quirk_hip06_07, | |
1904 | }, | |
1905 | { | |
1906 | .desc = "GICv3: HIP07 erratum 161010803", | |
1907 | .iidr = 0x00000000, | |
1908 | .mask = 0xffffffff, | |
1909 | .init = gic_enable_quirk_hip06_07, | |
1910 | }, | |
d01fd161 MZ |
1911 | { |
1912 | /* | |
1913 | * Reserved register accesses generate a Synchronous | |
1914 | * External Abort. This erratum applies to: | |
1915 | * - ThunderX: CN88xx | |
1916 | * - OCTEON TX: CN83xx, CN81xx | |
1917 | * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* | |
1918 | */ | |
1919 | .desc = "GICv3: Cavium erratum 38539", | |
1920 | .iidr = 0xa000034c, | |
1921 | .mask = 0xe8f00fff, | |
1922 | .init = gic_enable_quirk_cavium_38539, | |
1923 | }, | |
35727af2 SD |
1924 | { |
1925 | .desc = "GICv3: NVIDIA erratum T241-FABRIC-4", | |
1926 | .iidr = 0x0402043b, | |
1927 | .mask = 0xffffffff, | |
1928 | .init = gic_enable_quirk_nvidia_t241, | |
1929 | }, | |
6fe5c68e LP |
1930 | { |
1931 | /* | |
1932 | * GIC-700: 2941627 workaround - IP variant [0,1] | |
1933 | * | |
1934 | */ | |
1935 | .desc = "GICv3: ARM64 erratum 2941627", | |
1936 | .iidr = 0x0400043b, | |
1937 | .mask = 0xff0e0fff, | |
1938 | .init = gic_enable_quirk_arm64_2941627, | |
1939 | }, | |
1940 | { | |
1941 | /* | |
1942 | * GIC-700: 2941627 workaround - IP variant [2] | |
1943 | */ | |
1944 | .desc = "GICv3: ARM64 erratum 2941627", | |
1945 | .iidr = 0x0402043b, | |
1946 | .mask = 0xff0f0fff, | |
1947 | .init = gic_enable_quirk_arm64_2941627, | |
1948 | }, | |
7f2481b3 MZ |
1949 | { |
1950 | } | |
1951 | }; | |
1952 | ||
d98d0a99 JT |
1953 | static void gic_enable_nmi_support(void) |
1954 | { | |
101b35f7 JT |
1955 | int i; |
1956 | ||
81a43273 MZ |
1957 | if (!gic_prio_masking_enabled()) |
1958 | return; | |
1959 | ||
44bd78dd DA |
1960 | if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) { |
1961 | pr_warn("Skipping NMI enable due to firmware issues\n"); | |
1962 | return; | |
1963 | } | |
1964 | ||
a02026bf DA |
1965 | rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR, |
1966 | sizeof(*rdist_nmi_refs), GFP_KERNEL); | |
1967 | if (!rdist_nmi_refs) | |
81a43273 MZ |
1968 | return; |
1969 | ||
a02026bf DA |
1970 | for (i = 0; i < gic_data.ppi_nr + SGI_NR; i++) |
1971 | refcount_set(&rdist_nmi_refs[i], 0); | |
101b35f7 | 1972 | |
4e594ad1 | 1973 | pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", |
8bf0a804 | 1974 | gic_has_relaxed_pmr_sync() ? "relaxed" : "forced"); |
f2266504 | 1975 | |
33678059 AE |
1976 | /* |
1977 | * How priority values are used by the GIC depends on two things: | |
1978 | * the security state of the GIC (controlled by the GICD_CTRL.DS bit) | |
1979 | * and if Group 0 interrupts can be delivered to Linux in the non-secure | |
1980 | * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the | |
29517170 | 1981 | * ICC_PMR_EL1 register and the priority that software assigns to |
33678059 AE |
1982 | * interrupts: |
1983 | * | |
1984 | * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority | |
1985 | * ----------------------------------------------------------- | |
1986 | * 1 | - | unchanged | unchanged | |
1987 | * ----------------------------------------------------------- | |
1988 | * 0 | 1 | non-secure | non-secure | |
1989 | * ----------------------------------------------------------- | |
1990 | * 0 | 0 | unchanged | non-secure | |
1991 | * | |
1992 | * where non-secure means that the value is right-shifted by one and the | |
1993 | * MSB bit set, to make it fit in the non-secure priority range. | |
1994 | * | |
1995 | * In the first two cases, where ICC_PMR_EL1 and the interrupt priority | |
1996 | * are both either modified or unchanged, we can use the same set of | |
1997 | * priorities. | |
1998 | * | |
1999 | * In the last case, where only the interrupt priorities are modified to | |
2000 | * be in the non-secure range, we use a different PMR value to mask IRQs | |
2001 | * and the rest of the values that we use remain unchanged. | |
2002 | */ | |
2003 | if (gic_has_group0() && !gic_dist_security_disabled()) | |
2004 | static_branch_enable(&gic_nonsecure_priorities); | |
2005 | ||
d98d0a99 | 2006 | static_branch_enable(&supports_pseudo_nmis); |
101b35f7 JT |
2007 | |
2008 | if (static_branch_likely(&supports_deactivate_key)) | |
2009 | gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
2010 | else | |
2011 | gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
d98d0a99 JT |
2012 | } |
2013 | ||
35727af2 SD |
2014 | static int __init gic_init_bases(phys_addr_t dist_phys_base, |
2015 | void __iomem *dist_base, | |
db57d746 TN |
2016 | struct redist_region *rdist_regs, |
2017 | u32 nr_redist_regions, | |
2018 | u64 redist_stride, | |
2019 | struct fwnode_handle *handle) | |
021f6537 | 2020 | { |
f5c1434c | 2021 | u32 typer; |
021f6537 | 2022 | int err; |
021f6537 | 2023 | |
0b6a3da9 | 2024 | if (!is_hyp_mode_available()) |
d01d3274 | 2025 | static_branch_disable(&supports_deactivate_key); |
0b6a3da9 | 2026 | |
d01d3274 | 2027 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
2028 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
2029 | ||
e3825ba1 | 2030 | gic_data.fwnode = handle; |
35727af2 | 2031 | gic_data.dist_phys_base = dist_phys_base; |
021f6537 | 2032 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
2033 | gic_data.redist_regions = rdist_regs; |
2034 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
2035 | gic_data.redist_stride = redist_stride; |
2036 | ||
2037 | /* | |
2038 | * Find out how many interrupts are supported. | |
021f6537 | 2039 | */ |
f5c1434c | 2040 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
a4f9edb2 | 2041 | gic_data.rdists.gicd_typer = typer; |
7f2481b3 MZ |
2042 | |
2043 | gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), | |
2044 | gic_quirks, &gic_data); | |
2045 | ||
211bddd2 MZ |
2046 | pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); |
2047 | pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); | |
f2d83409 | 2048 | |
d01fd161 MZ |
2049 | /* |
2050 | * ThunderX1 explodes on reading GICD_TYPER2, in violation of the | |
2051 | * architecture spec (which says that reserved registers are RES0). | |
2052 | */ | |
2053 | if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) | |
2054 | gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); | |
f2d83409 | 2055 | |
db57d746 TN |
2056 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
2057 | &gic_data); | |
f5c1434c | 2058 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
35727af2 SD |
2059 | if (!static_branch_unlikely(&gic_nvidia_t241_erratum)) { |
2060 | /* Disable GICv4.x features for the erratum T241-FABRIC-4 */ | |
2061 | gic_data.rdists.has_rvpeid = true; | |
2062 | gic_data.rdists.has_vlpis = true; | |
2063 | gic_data.rdists.has_direct_lpi = true; | |
2064 | gic_data.rdists.has_vpend_valid_dirty = true; | |
2065 | } | |
021f6537 | 2066 | |
f5c1434c | 2067 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
2068 | err = -ENOMEM; |
2069 | goto out_free; | |
2070 | } | |
2071 | ||
eeaa4b24 | 2072 | irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); |
2073 | ||
eda0d04a | 2074 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
eda0d04a | 2075 | |
50528752 MZ |
2076 | if (typer & GICD_TYPER_MBIS) { |
2077 | err = mbi_init(handle, gic_data.domain); | |
2078 | if (err) | |
2079 | pr_err("Failed to initialize MBIs\n"); | |
2080 | } | |
2081 | ||
021f6537 MZ |
2082 | set_handle_irq(gic_handle_irq); |
2083 | ||
1a60e1e6 | 2084 | gic_update_rdist_properties(); |
0edc23ea | 2085 | |
021f6537 MZ |
2086 | gic_dist_init(); |
2087 | gic_cpu_init(); | |
a02026bf | 2088 | gic_enable_nmi_support(); |
64b499d8 | 2089 | gic_smp_init(); |
3708d52f | 2090 | gic_cpu_pm_init(); |
021f6537 | 2091 | |
d38a71c5 MZ |
2092 | if (gic_dist_supports_lpis()) { |
2093 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
2094 | its_cpu_init(); | |
d23bc2bc | 2095 | its_lpi_memreserve_init(); |
90b4c555 ZZ |
2096 | } else { |
2097 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
2098 | gicv2m_init(handle, gic_data.domain); | |
d38a71c5 MZ |
2099 | } |
2100 | ||
021f6537 MZ |
2101 | return 0; |
2102 | ||
2103 | out_free: | |
2104 | if (gic_data.domain) | |
2105 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 2106 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
2107 | return err; |
2108 | } | |
2109 | ||
2110 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
2111 | { | |
2112 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
2113 | ||
2114 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
2115 | return -ENODEV; | |
2116 | ||
2117 | return 0; | |
2118 | } | |
2119 | ||
e3825ba1 | 2120 | /* Create all possible partitions at boot time */ |
7beaa24b | 2121 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
2122 | { |
2123 | struct device_node *parts_node, *child_part; | |
2124 | int part_idx = 0, i; | |
2125 | int nr_parts; | |
2126 | struct partition_affinity *parts; | |
2127 | ||
00ee9a1c | 2128 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
2129 | if (!parts_node) |
2130 | return; | |
2131 | ||
52085d3f MZ |
2132 | gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); |
2133 | if (!gic_data.ppi_descs) | |
ec8401a4 | 2134 | goto out_put_node; |
52085d3f | 2135 | |
e3825ba1 MZ |
2136 | nr_parts = of_get_child_count(parts_node); |
2137 | ||
2138 | if (!nr_parts) | |
00ee9a1c | 2139 | goto out_put_node; |
e3825ba1 | 2140 | |
6396bb22 | 2141 | parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); |
e3825ba1 | 2142 | if (WARN_ON(!parts)) |
00ee9a1c | 2143 | goto out_put_node; |
e3825ba1 MZ |
2144 | |
2145 | for_each_child_of_node(parts_node, child_part) { | |
2146 | struct partition_affinity *part; | |
2147 | int n; | |
2148 | ||
2149 | part = &parts[part_idx]; | |
2150 | ||
2151 | part->partition_id = of_node_to_fwnode(child_part); | |
2152 | ||
2ef790dc RH |
2153 | pr_info("GIC: PPI partition %pOFn[%d] { ", |
2154 | child_part, part_idx); | |
e3825ba1 MZ |
2155 | |
2156 | n = of_property_count_elems_of_size(child_part, "affinity", | |
2157 | sizeof(u32)); | |
2158 | WARN_ON(n <= 0); | |
2159 | ||
2160 | for (i = 0; i < n; i++) { | |
2161 | int err, cpu; | |
2162 | u32 cpu_phandle; | |
2163 | struct device_node *cpu_node; | |
2164 | ||
2165 | err = of_property_read_u32_index(child_part, "affinity", | |
2166 | i, &cpu_phandle); | |
2167 | if (WARN_ON(err)) | |
2168 | continue; | |
2169 | ||
2170 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
2171 | if (WARN_ON(!cpu_node)) | |
2172 | continue; | |
2173 | ||
c08ec7da | 2174 | cpu = of_cpu_node_to_id(cpu_node); |
fa1ad9d4 ML |
2175 | if (WARN_ON(cpu < 0)) { |
2176 | of_node_put(cpu_node); | |
e3825ba1 | 2177 | continue; |
fa1ad9d4 | 2178 | } |
e3825ba1 | 2179 | |
e81f54c6 | 2180 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
2181 | |
2182 | cpumask_set_cpu(cpu, &part->mask); | |
fa1ad9d4 | 2183 | of_node_put(cpu_node); |
e3825ba1 MZ |
2184 | } |
2185 | ||
2186 | pr_cont("}\n"); | |
2187 | part_idx++; | |
2188 | } | |
2189 | ||
52085d3f | 2190 | for (i = 0; i < gic_data.ppi_nr; i++) { |
e3825ba1 MZ |
2191 | unsigned int irq; |
2192 | struct partition_desc *desc; | |
2193 | struct irq_fwspec ppi_fwspec = { | |
2194 | .fwnode = gic_data.fwnode, | |
2195 | .param_count = 3, | |
2196 | .param = { | |
65da7d19 | 2197 | [0] = GIC_IRQ_TYPE_PARTITION, |
e3825ba1 MZ |
2198 | [1] = i, |
2199 | [2] = IRQ_TYPE_NONE, | |
2200 | }, | |
2201 | }; | |
2202 | ||
2203 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
2204 | if (WARN_ON(!irq)) | |
2205 | continue; | |
2206 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
2207 | irq, &partition_domain_ops); | |
2208 | if (WARN_ON(!desc)) | |
2209 | continue; | |
2210 | ||
2211 | gic_data.ppi_descs[i] = desc; | |
2212 | } | |
00ee9a1c JH |
2213 | |
2214 | out_put_node: | |
2215 | of_node_put(parts_node); | |
e3825ba1 MZ |
2216 | } |
2217 | ||
1839e576 JG |
2218 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
2219 | { | |
2220 | int ret; | |
2221 | struct resource r; | |
2222 | u32 gicv_idx; | |
2223 | ||
2224 | gic_v3_kvm_info.type = GIC_V3; | |
2225 | ||
2226 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
2227 | if (!gic_v3_kvm_info.maint_irq) | |
2228 | return; | |
2229 | ||
2230 | if (of_property_read_u32(node, "#redistributor-regions", | |
2231 | &gicv_idx)) | |
2232 | gicv_idx = 1; | |
2233 | ||
2234 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
2235 | ret = of_address_to_resource(node, gicv_idx, &r); | |
2236 | if (!ret) | |
2237 | gic_v3_kvm_info.vcpu = r; | |
2238 | ||
4bdf5025 | 2239 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 2240 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
0e5cb777 | 2241 | vgic_set_kvm_info(&gic_v3_kvm_info); |
1839e576 JG |
2242 | } |
2243 | ||
4deb96e3 RM |
2244 | static void gic_request_region(resource_size_t base, resource_size_t size, |
2245 | const char *name) | |
2246 | { | |
2247 | if (!request_mem_region(base, size, name)) | |
2248 | pr_warn_once(FW_BUG "%s region %pa has overlapping address\n", | |
2249 | name, &base); | |
2250 | } | |
2251 | ||
2252 | static void __iomem *gic_of_iomap(struct device_node *node, int idx, | |
2253 | const char *name, struct resource *res) | |
2254 | { | |
2255 | void __iomem *base; | |
2256 | int ret; | |
2257 | ||
2258 | ret = of_address_to_resource(node, idx, res); | |
2259 | if (ret) | |
2260 | return IOMEM_ERR_PTR(ret); | |
2261 | ||
2262 | gic_request_region(res->start, resource_size(res), name); | |
2263 | base = of_iomap(node, idx); | |
2264 | ||
2265 | return base ?: IOMEM_ERR_PTR(-ENOMEM); | |
2266 | } | |
2267 | ||
db57d746 TN |
2268 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
2269 | { | |
35727af2 | 2270 | phys_addr_t dist_phys_base; |
db57d746 TN |
2271 | void __iomem *dist_base; |
2272 | struct redist_region *rdist_regs; | |
4deb96e3 | 2273 | struct resource res; |
db57d746 TN |
2274 | u64 redist_stride; |
2275 | u32 nr_redist_regions; | |
2276 | int err, i; | |
2277 | ||
4deb96e3 | 2278 | dist_base = gic_of_iomap(node, 0, "GICD", &res); |
2b2cd74a | 2279 | if (IS_ERR(dist_base)) { |
e81f54c6 | 2280 | pr_err("%pOF: unable to map gic dist registers\n", node); |
2b2cd74a | 2281 | return PTR_ERR(dist_base); |
db57d746 TN |
2282 | } |
2283 | ||
35727af2 SD |
2284 | dist_phys_base = res.start; |
2285 | ||
db57d746 TN |
2286 | err = gic_validate_dist_version(dist_base); |
2287 | if (err) { | |
e81f54c6 | 2288 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
2289 | goto out_unmap_dist; |
2290 | } | |
2291 | ||
2292 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
2293 | nr_redist_regions = 1; | |
2294 | ||
6396bb22 KC |
2295 | rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), |
2296 | GFP_KERNEL); | |
db57d746 TN |
2297 | if (!rdist_regs) { |
2298 | err = -ENOMEM; | |
2299 | goto out_unmap_dist; | |
2300 | } | |
2301 | ||
2302 | for (i = 0; i < nr_redist_regions; i++) { | |
4deb96e3 RM |
2303 | rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res); |
2304 | if (IS_ERR(rdist_regs[i].redist_base)) { | |
e81f54c6 | 2305 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
2306 | err = -ENODEV; |
2307 | goto out_unmap_rdist; | |
2308 | } | |
2309 | rdist_regs[i].phys_base = res.start; | |
2310 | } | |
2311 | ||
2312 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
2313 | redist_stride = 0; | |
2314 | ||
f70fdb42 SK |
2315 | gic_enable_of_quirks(node, gic_quirks, &gic_data); |
2316 | ||
35727af2 SD |
2317 | err = gic_init_bases(dist_phys_base, dist_base, rdist_regs, |
2318 | nr_redist_regions, redist_stride, &node->fwnode); | |
e3825ba1 MZ |
2319 | if (err) |
2320 | goto out_unmap_rdist; | |
2321 | ||
2322 | gic_populate_ppi_partitions(node); | |
d33a3c8c | 2323 | |
d01d3274 | 2324 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 2325 | gic_of_setup_kvm_info(node); |
e3825ba1 | 2326 | return 0; |
db57d746 | 2327 | |
021f6537 | 2328 | out_unmap_rdist: |
f5c1434c | 2329 | for (i = 0; i < nr_redist_regions; i++) |
2b2cd74a | 2330 | if (rdist_regs[i].redist_base && !IS_ERR(rdist_regs[i].redist_base)) |
f5c1434c MZ |
2331 | iounmap(rdist_regs[i].redist_base); |
2332 | kfree(rdist_regs); | |
021f6537 MZ |
2333 | out_unmap_dist: |
2334 | iounmap(dist_base); | |
2335 | return err; | |
2336 | } | |
2337 | ||
2338 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
2339 | |
2340 | #ifdef CONFIG_ACPI | |
611f039f JG |
2341 | static struct |
2342 | { | |
2343 | void __iomem *dist_base; | |
2344 | struct redist_region *redist_regs; | |
2345 | u32 nr_redist_regions; | |
2346 | bool single_redist; | |
926b5dfa | 2347 | int enabled_rdists; |
1839e576 JG |
2348 | u32 maint_irq; |
2349 | int maint_irq_mode; | |
2350 | phys_addr_t vcpu_base; | |
611f039f | 2351 | } acpi_data __initdata; |
b70fb7af TN |
2352 | |
2353 | static void __init | |
2354 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
2355 | { | |
2356 | static int count = 0; | |
2357 | ||
611f039f JG |
2358 | acpi_data.redist_regs[count].phys_base = phys_base; |
2359 | acpi_data.redist_regs[count].redist_base = redist_base; | |
2360 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
2361 | count++; |
2362 | } | |
ffa7d616 TN |
2363 | |
2364 | static int __init | |
60574d1e | 2365 | gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, |
ffa7d616 TN |
2366 | const unsigned long end) |
2367 | { | |
2368 | struct acpi_madt_generic_redistributor *redist = | |
2369 | (struct acpi_madt_generic_redistributor *)header; | |
2370 | void __iomem *redist_base; | |
ffa7d616 TN |
2371 | |
2372 | redist_base = ioremap(redist->base_address, redist->length); | |
2373 | if (!redist_base) { | |
2374 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
2375 | return -ENOMEM; | |
2376 | } | |
4deb96e3 | 2377 | gic_request_region(redist->base_address, redist->length, "GICR"); |
ffa7d616 | 2378 | |
b70fb7af | 2379 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
2380 | return 0; |
2381 | } | |
2382 | ||
b70fb7af | 2383 | static int __init |
60574d1e | 2384 | gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
2385 | const unsigned long end) |
2386 | { | |
2387 | struct acpi_madt_generic_interrupt *gicc = | |
2388 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 2389 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
2390 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
2391 | void __iomem *redist_base; | |
2392 | ||
ebe2f871 SD |
2393 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
2394 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2395 | return 0; | |
2396 | ||
b70fb7af TN |
2397 | redist_base = ioremap(gicc->gicr_base_address, size); |
2398 | if (!redist_base) | |
2399 | return -ENOMEM; | |
4deb96e3 | 2400 | gic_request_region(gicc->gicr_base_address, size, "GICR"); |
b70fb7af TN |
2401 | |
2402 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
2403 | return 0; | |
2404 | } | |
2405 | ||
2406 | static int __init gic_acpi_collect_gicr_base(void) | |
2407 | { | |
2408 | acpi_tbl_entry_handler redist_parser; | |
2409 | enum acpi_madt_type type; | |
2410 | ||
611f039f | 2411 | if (acpi_data.single_redist) { |
b70fb7af TN |
2412 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
2413 | redist_parser = gic_acpi_parse_madt_gicc; | |
2414 | } else { | |
2415 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
2416 | redist_parser = gic_acpi_parse_madt_redist; | |
2417 | } | |
2418 | ||
2419 | /* Collect redistributor base addresses in GICR entries */ | |
2420 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
2421 | return 0; | |
2422 | ||
2423 | pr_info("No valid GICR entries exist\n"); | |
2424 | return -ENODEV; | |
2425 | } | |
2426 | ||
60574d1e | 2427 | static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, |
ffa7d616 TN |
2428 | const unsigned long end) |
2429 | { | |
2430 | /* Subtable presence means that redist exists, that's it */ | |
2431 | return 0; | |
2432 | } | |
2433 | ||
60574d1e | 2434 | static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
2435 | const unsigned long end) |
2436 | { | |
2437 | struct acpi_madt_generic_interrupt *gicc = | |
2438 | (struct acpi_madt_generic_interrupt *)header; | |
2439 | ||
2440 | /* | |
2441 | * If GICC is enabled and has valid gicr base address, then it means | |
2442 | * GICR base is presented via GICC | |
2443 | */ | |
926b5dfa MZ |
2444 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { |
2445 | acpi_data.enabled_rdists++; | |
b70fb7af | 2446 | return 0; |
926b5dfa | 2447 | } |
b70fb7af | 2448 | |
ebe2f871 SD |
2449 | /* |
2450 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
2451 | * should not treat as errors, skip the entry instead of probe fail. | |
2452 | */ | |
2453 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2454 | return 0; | |
2455 | ||
b70fb7af TN |
2456 | return -ENODEV; |
2457 | } | |
2458 | ||
2459 | static int __init gic_acpi_count_gicr_regions(void) | |
2460 | { | |
2461 | int count; | |
2462 | ||
2463 | /* | |
2464 | * Count how many redistributor regions we have. It is not allowed | |
2465 | * to mix redistributor description, GICR and GICC subtables have to be | |
2466 | * mutually exclusive. | |
2467 | */ | |
2468 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
2469 | gic_acpi_match_gicr, 0); | |
2470 | if (count > 0) { | |
611f039f | 2471 | acpi_data.single_redist = false; |
b70fb7af TN |
2472 | return count; |
2473 | } | |
2474 | ||
2475 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2476 | gic_acpi_match_gicc, 0); | |
926b5dfa | 2477 | if (count > 0) { |
611f039f | 2478 | acpi_data.single_redist = true; |
926b5dfa MZ |
2479 | count = acpi_data.enabled_rdists; |
2480 | } | |
b70fb7af TN |
2481 | |
2482 | return count; | |
2483 | } | |
2484 | ||
ffa7d616 TN |
2485 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
2486 | struct acpi_probe_entry *ape) | |
2487 | { | |
2488 | struct acpi_madt_generic_distributor *dist; | |
2489 | int count; | |
2490 | ||
2491 | dist = (struct acpi_madt_generic_distributor *)header; | |
2492 | if (dist->version != ape->driver_data) | |
2493 | return false; | |
2494 | ||
2495 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 2496 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
2497 | if (count <= 0) |
2498 | return false; | |
2499 | ||
611f039f | 2500 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
2501 | return true; |
2502 | } | |
2503 | ||
60574d1e | 2504 | static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, |
1839e576 JG |
2505 | const unsigned long end) |
2506 | { | |
2507 | struct acpi_madt_generic_interrupt *gicc = | |
2508 | (struct acpi_madt_generic_interrupt *)header; | |
2509 | int maint_irq_mode; | |
2510 | static int first_madt = true; | |
2511 | ||
2512 | /* Skip unusable CPUs */ | |
2513 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2514 | return 0; | |
2515 | ||
2516 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
2517 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
2518 | ||
2519 | if (first_madt) { | |
2520 | first_madt = false; | |
2521 | ||
2522 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
2523 | acpi_data.maint_irq_mode = maint_irq_mode; | |
2524 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
2525 | ||
2526 | return 0; | |
2527 | } | |
2528 | ||
2529 | /* | |
2530 | * The maintenance interrupt and GICV should be the same for every CPU | |
2531 | */ | |
2532 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
2533 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
2534 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
2535 | return -EINVAL; | |
2536 | ||
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | static bool __init gic_acpi_collect_virt_info(void) | |
2541 | { | |
2542 | int count; | |
2543 | ||
2544 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2545 | gic_acpi_parse_virt_madt_gicc, 0); | |
2546 | ||
2547 | return (count > 0); | |
2548 | } | |
2549 | ||
ffa7d616 | 2550 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
2551 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
2552 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
2553 | ||
2554 | static void __init gic_acpi_setup_kvm_info(void) | |
2555 | { | |
2556 | int irq; | |
2557 | ||
2558 | if (!gic_acpi_collect_virt_info()) { | |
2559 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
2560 | return; | |
2561 | } | |
2562 | ||
2563 | gic_v3_kvm_info.type = GIC_V3; | |
2564 | ||
2565 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
2566 | acpi_data.maint_irq_mode, | |
2567 | ACPI_ACTIVE_HIGH); | |
2568 | if (irq <= 0) | |
2569 | return; | |
2570 | ||
2571 | gic_v3_kvm_info.maint_irq = irq; | |
2572 | ||
2573 | if (acpi_data.vcpu_base) { | |
2574 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
2575 | ||
2576 | vcpu->flags = IORESOURCE_MEM; | |
2577 | vcpu->start = acpi_data.vcpu_base; | |
2578 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
2579 | } | |
2580 | ||
4bdf5025 | 2581 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 2582 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
0e5cb777 | 2583 | vgic_set_kvm_info(&gic_v3_kvm_info); |
1839e576 | 2584 | } |
ffa7d616 | 2585 | |
7327b16f MZ |
2586 | static struct fwnode_handle *gsi_domain_handle; |
2587 | ||
2588 | static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi) | |
2589 | { | |
2590 | return gsi_domain_handle; | |
2591 | } | |
2592 | ||
ffa7d616 | 2593 | static int __init |
aba3c7ed | 2594 | gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) |
ffa7d616 TN |
2595 | { |
2596 | struct acpi_madt_generic_distributor *dist; | |
611f039f | 2597 | size_t size; |
b70fb7af | 2598 | int i, err; |
ffa7d616 TN |
2599 | |
2600 | /* Get distributor base address */ | |
2601 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
2602 | acpi_data.dist_base = ioremap(dist->base_address, |
2603 | ACPI_GICV3_DIST_MEM_SIZE); | |
2604 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
2605 | pr_err("Unable to map GICD registers\n"); |
2606 | return -ENOMEM; | |
2607 | } | |
4deb96e3 | 2608 | gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); |
ffa7d616 | 2609 | |
611f039f | 2610 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 2611 | if (err) { |
71192a68 | 2612 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 2613 | acpi_data.dist_base); |
ffa7d616 TN |
2614 | goto out_dist_unmap; |
2615 | } | |
2616 | ||
611f039f JG |
2617 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
2618 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
2619 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
2620 | err = -ENOMEM; |
2621 | goto out_dist_unmap; | |
2622 | } | |
2623 | ||
b70fb7af TN |
2624 | err = gic_acpi_collect_gicr_base(); |
2625 | if (err) | |
ffa7d616 | 2626 | goto out_redist_unmap; |
ffa7d616 | 2627 | |
7327b16f MZ |
2628 | gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address); |
2629 | if (!gsi_domain_handle) { | |
ffa7d616 TN |
2630 | err = -ENOMEM; |
2631 | goto out_redist_unmap; | |
2632 | } | |
2633 | ||
35727af2 SD |
2634 | err = gic_init_bases(dist->base_address, acpi_data.dist_base, |
2635 | acpi_data.redist_regs, acpi_data.nr_redist_regions, | |
2636 | 0, gsi_domain_handle); | |
ffa7d616 TN |
2637 | if (err) |
2638 | goto out_fwhandle_free; | |
2639 | ||
7327b16f | 2640 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id); |
d33a3c8c | 2641 | |
d01d3274 | 2642 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 2643 | gic_acpi_setup_kvm_info(); |
1839e576 | 2644 | |
ffa7d616 TN |
2645 | return 0; |
2646 | ||
2647 | out_fwhandle_free: | |
7327b16f | 2648 | irq_domain_free_fwnode(gsi_domain_handle); |
ffa7d616 | 2649 | out_redist_unmap: |
611f039f JG |
2650 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
2651 | if (acpi_data.redist_regs[i].redist_base) | |
2652 | iounmap(acpi_data.redist_regs[i].redist_base); | |
2653 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 2654 | out_dist_unmap: |
611f039f | 2655 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
2656 | return err; |
2657 | } | |
2658 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2659 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
2660 | gic_acpi_init); | |
2661 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2662 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
2663 | gic_acpi_init); | |
2664 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2665 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
2666 | gic_acpi_init); | |
2667 | #endif |