Commit | Line | Data |
---|---|---|
021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
68628bb8 JG |
18 | #define pr_fmt(fmt) "GICv3: " fmt |
19 | ||
ffa7d616 | 20 | #include <linux/acpi.h> |
021f6537 | 21 | #include <linux/cpu.h> |
3708d52f | 22 | #include <linux/cpu_pm.h> |
021f6537 MZ |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
ffa7d616 | 25 | #include <linux/irqdomain.h> |
021f6537 MZ |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
31 | ||
41a83e06 | 32 | #include <linux/irqchip.h> |
021f6537 MZ |
33 | #include <linux/irqchip/arm-gic-v3.h> |
34 | ||
35 | #include <asm/cputype.h> | |
36 | #include <asm/exception.h> | |
37 | #include <asm/smp_plat.h> | |
0b6a3da9 | 38 | #include <asm/virt.h> |
021f6537 MZ |
39 | |
40 | #include "irq-gic-common.h" | |
021f6537 | 41 | |
f5c1434c MZ |
42 | struct redist_region { |
43 | void __iomem *redist_base; | |
44 | phys_addr_t phys_base; | |
b70fb7af | 45 | bool single_redist; |
f5c1434c MZ |
46 | }; |
47 | ||
021f6537 MZ |
48 | struct gic_chip_data { |
49 | void __iomem *dist_base; | |
f5c1434c MZ |
50 | struct redist_region *redist_regions; |
51 | struct rdists rdists; | |
021f6537 MZ |
52 | struct irq_domain *domain; |
53 | u64 redist_stride; | |
f5c1434c | 54 | u32 nr_redist_regions; |
021f6537 MZ |
55 | unsigned int irq_nr; |
56 | }; | |
57 | ||
58 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 59 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 60 | |
f5c1434c MZ |
61 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
62 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
63 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
64 | ||
65 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
66 | #define DEFAULT_PMR_VALUE 0xf0 | |
67 | ||
68 | static inline unsigned int gic_irq(struct irq_data *d) | |
69 | { | |
70 | return d->hwirq; | |
71 | } | |
72 | ||
73 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
74 | { | |
75 | return gic_irq(d) < 32; | |
76 | } | |
77 | ||
78 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
79 | { | |
80 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
81 | return gic_data_rdist_sgi_base(); | |
82 | ||
83 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
84 | return gic_data.dist_base; | |
85 | ||
021f6537 MZ |
86 | return NULL; |
87 | } | |
88 | ||
89 | static void gic_do_wait_for_rwp(void __iomem *base) | |
90 | { | |
91 | u32 count = 1000000; /* 1s! */ | |
92 | ||
93 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
94 | count--; | |
95 | if (!count) { | |
96 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
97 | return; | |
98 | } | |
99 | cpu_relax(); | |
100 | udelay(1); | |
101 | }; | |
102 | } | |
103 | ||
104 | /* Wait for completion of a distributor change */ | |
105 | static void gic_dist_wait_for_rwp(void) | |
106 | { | |
107 | gic_do_wait_for_rwp(gic_data.dist_base); | |
108 | } | |
109 | ||
110 | /* Wait for completion of a redistributor change */ | |
111 | static void gic_redist_wait_for_rwp(void) | |
112 | { | |
113 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
114 | } | |
115 | ||
7936e914 | 116 | #ifdef CONFIG_ARM64 |
8ac2a170 | 117 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
6d4e11c5 RR |
118 | |
119 | static u64 __maybe_unused gic_read_iar(void) | |
120 | { | |
8ac2a170 | 121 | if (static_branch_unlikely(&is_cavium_thunderx)) |
6d4e11c5 RR |
122 | return gic_read_iar_cavium_thunderx(); |
123 | else | |
124 | return gic_read_iar_common(); | |
125 | } | |
7936e914 | 126 | #endif |
021f6537 | 127 | |
a2c22510 | 128 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
129 | { |
130 | void __iomem *rbase; | |
131 | u32 count = 1000000; /* 1s! */ | |
132 | u32 val; | |
133 | ||
134 | rbase = gic_data_rdist_rd_base(); | |
135 | ||
021f6537 | 136 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
137 | if (enable) |
138 | /* Wake up this CPU redistributor */ | |
139 | val &= ~GICR_WAKER_ProcessorSleep; | |
140 | else | |
141 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
142 | writel_relaxed(val, rbase + GICR_WAKER); |
143 | ||
a2c22510 SH |
144 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
145 | val = readl_relaxed(rbase + GICR_WAKER); | |
146 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
147 | return; /* No PM support in this redistributor */ | |
148 | } | |
149 | ||
150 | while (count--) { | |
151 | val = readl_relaxed(rbase + GICR_WAKER); | |
152 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
153 | break; | |
021f6537 MZ |
154 | cpu_relax(); |
155 | udelay(1); | |
156 | }; | |
a2c22510 SH |
157 | if (!count) |
158 | pr_err_ratelimited("redistributor failed to %s...\n", | |
159 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
160 | } |
161 | ||
162 | /* | |
163 | * Routines to disable, enable, EOI and route interrupts | |
164 | */ | |
b594c6e2 MZ |
165 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
166 | { | |
167 | u32 mask = 1 << (gic_irq(d) % 32); | |
168 | void __iomem *base; | |
169 | ||
170 | if (gic_irq_in_rdist(d)) | |
171 | base = gic_data_rdist_sgi_base(); | |
172 | else | |
173 | base = gic_data.dist_base; | |
174 | ||
175 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
176 | } | |
177 | ||
021f6537 MZ |
178 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
179 | { | |
180 | u32 mask = 1 << (gic_irq(d) % 32); | |
181 | void (*rwp_wait)(void); | |
182 | void __iomem *base; | |
183 | ||
184 | if (gic_irq_in_rdist(d)) { | |
185 | base = gic_data_rdist_sgi_base(); | |
186 | rwp_wait = gic_redist_wait_for_rwp; | |
187 | } else { | |
188 | base = gic_data.dist_base; | |
189 | rwp_wait = gic_dist_wait_for_rwp; | |
190 | } | |
191 | ||
192 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
193 | rwp_wait(); | |
194 | } | |
195 | ||
021f6537 MZ |
196 | static void gic_mask_irq(struct irq_data *d) |
197 | { | |
198 | gic_poke_irq(d, GICD_ICENABLER); | |
199 | } | |
200 | ||
0b6a3da9 MZ |
201 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
202 | { | |
203 | gic_mask_irq(d); | |
530bf353 MZ |
204 | /* |
205 | * When masking a forwarded interrupt, make sure it is | |
206 | * deactivated as well. | |
207 | * | |
208 | * This ensures that an interrupt that is getting | |
209 | * disabled/masked will not get "stuck", because there is | |
210 | * noone to deactivate it (guest is being terminated). | |
211 | */ | |
4df7f54d | 212 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 213 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
214 | } |
215 | ||
021f6537 MZ |
216 | static void gic_unmask_irq(struct irq_data *d) |
217 | { | |
218 | gic_poke_irq(d, GICD_ISENABLER); | |
219 | } | |
220 | ||
b594c6e2 MZ |
221 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
222 | enum irqchip_irq_state which, bool val) | |
223 | { | |
224 | u32 reg; | |
225 | ||
226 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
227 | return -EINVAL; | |
228 | ||
229 | switch (which) { | |
230 | case IRQCHIP_STATE_PENDING: | |
231 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
232 | break; | |
233 | ||
234 | case IRQCHIP_STATE_ACTIVE: | |
235 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
236 | break; | |
237 | ||
238 | case IRQCHIP_STATE_MASKED: | |
239 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
240 | break; | |
241 | ||
242 | default: | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | gic_poke_irq(d, reg); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
251 | enum irqchip_irq_state which, bool *val) | |
252 | { | |
253 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
254 | return -EINVAL; | |
255 | ||
256 | switch (which) { | |
257 | case IRQCHIP_STATE_PENDING: | |
258 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
259 | break; | |
260 | ||
261 | case IRQCHIP_STATE_ACTIVE: | |
262 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
263 | break; | |
264 | ||
265 | case IRQCHIP_STATE_MASKED: | |
266 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
267 | break; | |
268 | ||
269 | default: | |
270 | return -EINVAL; | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
021f6537 MZ |
276 | static void gic_eoi_irq(struct irq_data *d) |
277 | { | |
278 | gic_write_eoir(gic_irq(d)); | |
279 | } | |
280 | ||
0b6a3da9 MZ |
281 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
282 | { | |
283 | /* | |
530bf353 MZ |
284 | * No need to deactivate an LPI, or an interrupt that |
285 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 286 | */ |
4df7f54d | 287 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
288 | return; |
289 | gic_write_dir(gic_irq(d)); | |
290 | } | |
291 | ||
021f6537 MZ |
292 | static int gic_set_type(struct irq_data *d, unsigned int type) |
293 | { | |
294 | unsigned int irq = gic_irq(d); | |
295 | void (*rwp_wait)(void); | |
296 | void __iomem *base; | |
297 | ||
298 | /* Interrupt configuration for SGIs can't be changed */ | |
299 | if (irq < 16) | |
300 | return -EINVAL; | |
301 | ||
fb7e7deb LD |
302 | /* SPIs have restrictions on the supported types */ |
303 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
304 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
305 | return -EINVAL; |
306 | ||
307 | if (gic_irq_in_rdist(d)) { | |
308 | base = gic_data_rdist_sgi_base(); | |
309 | rwp_wait = gic_redist_wait_for_rwp; | |
310 | } else { | |
311 | base = gic_data.dist_base; | |
312 | rwp_wait = gic_dist_wait_for_rwp; | |
313 | } | |
314 | ||
fb7e7deb | 315 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
316 | } |
317 | ||
530bf353 MZ |
318 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
319 | { | |
4df7f54d TG |
320 | if (vcpu) |
321 | irqd_set_forwarded_to_vcpu(d); | |
322 | else | |
323 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
324 | return 0; |
325 | } | |
326 | ||
f6c86a41 | 327 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
328 | { |
329 | u64 aff; | |
330 | ||
f6c86a41 | 331 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
332 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
333 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
334 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
335 | ||
336 | return aff; | |
337 | } | |
338 | ||
339 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
340 | { | |
f6c86a41 | 341 | u32 irqnr; |
021f6537 MZ |
342 | |
343 | do { | |
344 | irqnr = gic_read_iar(); | |
345 | ||
da33f31d | 346 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 347 | int err; |
0b6a3da9 MZ |
348 | |
349 | if (static_key_true(&supports_deactivate)) | |
350 | gic_write_eoir(irqnr); | |
351 | ||
ebc6de00 MZ |
352 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
353 | if (err) { | |
da33f31d | 354 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
355 | if (static_key_true(&supports_deactivate)) { |
356 | if (irqnr < 8192) | |
357 | gic_write_dir(irqnr); | |
358 | } else { | |
359 | gic_write_eoir(irqnr); | |
360 | } | |
021f6537 | 361 | } |
ebc6de00 | 362 | continue; |
021f6537 MZ |
363 | } |
364 | if (irqnr < 16) { | |
365 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
366 | if (static_key_true(&supports_deactivate)) |
367 | gic_write_dir(irqnr); | |
021f6537 MZ |
368 | #ifdef CONFIG_SMP |
369 | handle_IPI(irqnr, regs); | |
370 | #else | |
371 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
372 | #endif | |
373 | continue; | |
374 | } | |
375 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
376 | } | |
377 | ||
378 | static void __init gic_dist_init(void) | |
379 | { | |
380 | unsigned int i; | |
381 | u64 affinity; | |
382 | void __iomem *base = gic_data.dist_base; | |
383 | ||
384 | /* Disable the distributor */ | |
385 | writel_relaxed(0, base + GICD_CTLR); | |
386 | gic_dist_wait_for_rwp(); | |
387 | ||
388 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
389 | ||
390 | /* Enable distributor with ARE, Group1 */ | |
391 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
392 | base + GICD_CTLR); | |
393 | ||
394 | /* | |
395 | * Set all global interrupts to the boot CPU only. ARE must be | |
396 | * enabled. | |
397 | */ | |
398 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
399 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 400 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
401 | } |
402 | ||
403 | static int gic_populate_rdist(void) | |
404 | { | |
f6c86a41 | 405 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
021f6537 MZ |
406 | u64 typer; |
407 | u32 aff; | |
408 | int i; | |
409 | ||
410 | /* | |
411 | * Convert affinity to a 32bit value that can be matched to | |
412 | * GICR_TYPER bits [63:32]. | |
413 | */ | |
414 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
415 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
416 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
417 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
418 | ||
f5c1434c MZ |
419 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
420 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
421 | u32 reg; |
422 | ||
423 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
424 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
425 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
426 | pr_warn("No redistributor present @%p\n", ptr); | |
427 | break; | |
428 | } | |
429 | ||
430 | do { | |
72c97126 | 431 | typer = gic_read_typer(ptr + GICR_TYPER); |
021f6537 | 432 | if ((typer >> 32) == aff) { |
f5c1434c | 433 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 434 | gic_data_rdist_rd_base() = ptr; |
f5c1434c | 435 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
f6c86a41 JPB |
436 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
437 | smp_processor_id(), mpidr, i, | |
438 | &gic_data_rdist()->phys_base); | |
021f6537 MZ |
439 | return 0; |
440 | } | |
441 | ||
b70fb7af TN |
442 | if (gic_data.redist_regions[i].single_redist) |
443 | break; | |
444 | ||
021f6537 MZ |
445 | if (gic_data.redist_stride) { |
446 | ptr += gic_data.redist_stride; | |
447 | } else { | |
448 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
449 | if (typer & GICR_TYPER_VLPIS) | |
450 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
451 | } | |
452 | } while (!(typer & GICR_TYPER_LAST)); | |
453 | } | |
454 | ||
455 | /* We couldn't even deal with ourselves... */ | |
f6c86a41 JPB |
456 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
457 | smp_processor_id(), mpidr); | |
021f6537 MZ |
458 | return -ENODEV; |
459 | } | |
460 | ||
3708d52f SH |
461 | static void gic_cpu_sys_reg_init(void) |
462 | { | |
7cabd008 MZ |
463 | /* |
464 | * Need to check that the SRE bit has actually been set. If | |
465 | * not, it means that SRE is disabled at EL2. We're going to | |
466 | * die painfully, and there is nothing we can do about it. | |
467 | * | |
468 | * Kindly inform the luser. | |
469 | */ | |
470 | if (!gic_enable_sre()) | |
471 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f SH |
472 | |
473 | /* Set priority mask register */ | |
474 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
475 | ||
0b6a3da9 MZ |
476 | if (static_key_true(&supports_deactivate)) { |
477 | /* EOI drops priority only (mode 1) */ | |
478 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
479 | } else { | |
480 | /* EOI deactivates interrupt too (mode 0) */ | |
481 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
482 | } | |
3708d52f SH |
483 | |
484 | /* ... and let's hit the road... */ | |
485 | gic_write_grpen1(1); | |
486 | } | |
487 | ||
da33f31d MZ |
488 | static int gic_dist_supports_lpis(void) |
489 | { | |
490 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
491 | } | |
492 | ||
021f6537 MZ |
493 | static void gic_cpu_init(void) |
494 | { | |
495 | void __iomem *rbase; | |
496 | ||
497 | /* Register ourselves with the rest of the world */ | |
498 | if (gic_populate_rdist()) | |
499 | return; | |
500 | ||
a2c22510 | 501 | gic_enable_redist(true); |
021f6537 MZ |
502 | |
503 | rbase = gic_data_rdist_sgi_base(); | |
504 | ||
505 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
506 | ||
da33f31d MZ |
507 | /* Give LPIs a spin */ |
508 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
509 | its_cpu_init(); | |
510 | ||
3708d52f SH |
511 | /* initialise system registers */ |
512 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
513 | } |
514 | ||
515 | #ifdef CONFIG_SMP | |
516 | static int gic_secondary_init(struct notifier_block *nfb, | |
517 | unsigned long action, void *hcpu) | |
518 | { | |
519 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
520 | gic_cpu_init(); | |
521 | return NOTIFY_OK; | |
522 | } | |
523 | ||
524 | /* | |
525 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
526 | * priority because the GIC needs to be up before the ARM generic timers. | |
527 | */ | |
528 | static struct notifier_block gic_cpu_notifier = { | |
529 | .notifier_call = gic_secondary_init, | |
530 | .priority = 100, | |
531 | }; | |
532 | ||
533 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
f6c86a41 | 534 | unsigned long cluster_id) |
021f6537 MZ |
535 | { |
536 | int cpu = *base_cpu; | |
f6c86a41 | 537 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
538 | u16 tlist = 0; |
539 | ||
540 | while (cpu < nr_cpu_ids) { | |
541 | /* | |
542 | * If we ever get a cluster of more than 16 CPUs, just | |
543 | * scream and skip that CPU. | |
544 | */ | |
545 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
546 | goto out; | |
547 | ||
548 | tlist |= 1 << (mpidr & 0xf); | |
549 | ||
550 | cpu = cpumask_next(cpu, mask); | |
614be385 | 551 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
552 | goto out; |
553 | ||
554 | mpidr = cpu_logical_map(cpu); | |
555 | ||
556 | if (cluster_id != (mpidr & ~0xffUL)) { | |
557 | cpu--; | |
558 | goto out; | |
559 | } | |
560 | } | |
561 | out: | |
562 | *base_cpu = cpu; | |
563 | return tlist; | |
564 | } | |
565 | ||
7e580278 AP |
566 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
567 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
568 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
569 | ||
021f6537 MZ |
570 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
571 | { | |
572 | u64 val; | |
573 | ||
7e580278 AP |
574 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
575 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
576 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
577 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
578 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
579 | |
580 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
581 | gic_write_sgi1r(val); | |
582 | } | |
583 | ||
584 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
585 | { | |
586 | int cpu; | |
587 | ||
588 | if (WARN_ON(irq >= 16)) | |
589 | return; | |
590 | ||
591 | /* | |
592 | * Ensure that stores to Normal memory are visible to the | |
593 | * other CPUs before issuing the IPI. | |
594 | */ | |
595 | smp_wmb(); | |
596 | ||
f9b531fe | 597 | for_each_cpu(cpu, mask) { |
f6c86a41 | 598 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
021f6537 MZ |
599 | u16 tlist; |
600 | ||
601 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
602 | gic_send_sgi(cluster_id, tlist, irq); | |
603 | } | |
604 | ||
605 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
606 | isb(); | |
607 | } | |
608 | ||
609 | static void gic_smp_init(void) | |
610 | { | |
611 | set_smp_cross_call(gic_raise_softirq); | |
612 | register_cpu_notifier(&gic_cpu_notifier); | |
613 | } | |
614 | ||
615 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
616 | bool force) | |
617 | { | |
618 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
619 | void __iomem *reg; | |
620 | int enabled; | |
621 | u64 val; | |
622 | ||
623 | if (gic_irq_in_rdist(d)) | |
624 | return -EINVAL; | |
625 | ||
626 | /* If interrupt was enabled, disable it first */ | |
627 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
628 | if (enabled) | |
629 | gic_mask_irq(d); | |
630 | ||
631 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
632 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
633 | ||
72c97126 | 634 | gic_write_irouter(val, reg); |
021f6537 MZ |
635 | |
636 | /* | |
637 | * If the interrupt was enabled, enabled it again. Otherwise, | |
638 | * just wait for the distributor to have digested our changes. | |
639 | */ | |
640 | if (enabled) | |
641 | gic_unmask_irq(d); | |
642 | else | |
643 | gic_dist_wait_for_rwp(); | |
644 | ||
0fc6fa29 | 645 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
646 | } |
647 | #else | |
648 | #define gic_set_affinity NULL | |
649 | #define gic_smp_init() do { } while(0) | |
650 | #endif | |
651 | ||
3708d52f SH |
652 | #ifdef CONFIG_CPU_PM |
653 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
654 | unsigned long cmd, void *v) | |
655 | { | |
656 | if (cmd == CPU_PM_EXIT) { | |
657 | gic_enable_redist(true); | |
658 | gic_cpu_sys_reg_init(); | |
659 | } else if (cmd == CPU_PM_ENTER) { | |
660 | gic_write_grpen1(0); | |
661 | gic_enable_redist(false); | |
662 | } | |
663 | return NOTIFY_OK; | |
664 | } | |
665 | ||
666 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
667 | .notifier_call = gic_cpu_pm_notifier, | |
668 | }; | |
669 | ||
670 | static void gic_cpu_pm_init(void) | |
671 | { | |
672 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
673 | } | |
674 | ||
675 | #else | |
676 | static inline void gic_cpu_pm_init(void) { } | |
677 | #endif /* CONFIG_CPU_PM */ | |
678 | ||
021f6537 MZ |
679 | static struct irq_chip gic_chip = { |
680 | .name = "GICv3", | |
681 | .irq_mask = gic_mask_irq, | |
682 | .irq_unmask = gic_unmask_irq, | |
683 | .irq_eoi = gic_eoi_irq, | |
684 | .irq_set_type = gic_set_type, | |
685 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
686 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
687 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 688 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
689 | }; |
690 | ||
0b6a3da9 MZ |
691 | static struct irq_chip gic_eoimode1_chip = { |
692 | .name = "GICv3", | |
693 | .irq_mask = gic_eoimode1_mask_irq, | |
694 | .irq_unmask = gic_unmask_irq, | |
695 | .irq_eoi = gic_eoimode1_eoi_irq, | |
696 | .irq_set_type = gic_set_type, | |
697 | .irq_set_affinity = gic_set_affinity, | |
698 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
699 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 700 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
701 | .flags = IRQCHIP_SET_TYPE_MASKED, |
702 | }; | |
703 | ||
da33f31d MZ |
704 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
705 | ||
021f6537 MZ |
706 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
707 | irq_hw_number_t hw) | |
708 | { | |
0b6a3da9 MZ |
709 | struct irq_chip *chip = &gic_chip; |
710 | ||
711 | if (static_key_true(&supports_deactivate)) | |
712 | chip = &gic_eoimode1_chip; | |
713 | ||
021f6537 MZ |
714 | /* SGIs are private to the core kernel */ |
715 | if (hw < 16) | |
716 | return -EPERM; | |
da33f31d MZ |
717 | /* Nothing here */ |
718 | if (hw >= gic_data.irq_nr && hw < 8192) | |
719 | return -EPERM; | |
720 | /* Off limits */ | |
721 | if (hw >= GIC_ID_NR) | |
722 | return -EPERM; | |
723 | ||
021f6537 MZ |
724 | /* PPIs */ |
725 | if (hw < 32) { | |
726 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 727 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 728 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 729 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
730 | } |
731 | /* SPIs */ | |
732 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 733 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 734 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 735 | irq_set_probe(irq); |
021f6537 | 736 | } |
da33f31d MZ |
737 | /* LPIs */ |
738 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
739 | if (!gic_dist_supports_lpis()) | |
740 | return -EPERM; | |
0b6a3da9 | 741 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 742 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
743 | } |
744 | ||
021f6537 MZ |
745 | return 0; |
746 | } | |
747 | ||
f833f57f MZ |
748 | static int gic_irq_domain_translate(struct irq_domain *d, |
749 | struct irq_fwspec *fwspec, | |
750 | unsigned long *hwirq, | |
751 | unsigned int *type) | |
021f6537 | 752 | { |
f833f57f MZ |
753 | if (is_of_node(fwspec->fwnode)) { |
754 | if (fwspec->param_count < 3) | |
755 | return -EINVAL; | |
021f6537 | 756 | |
db8c70ec MZ |
757 | switch (fwspec->param[0]) { |
758 | case 0: /* SPI */ | |
759 | *hwirq = fwspec->param[1] + 32; | |
760 | break; | |
761 | case 1: /* PPI */ | |
762 | *hwirq = fwspec->param[1] + 16; | |
763 | break; | |
764 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
765 | *hwirq = fwspec->param[1]; | |
766 | break; | |
767 | default: | |
768 | return -EINVAL; | |
769 | } | |
f833f57f MZ |
770 | |
771 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
772 | return 0; | |
021f6537 MZ |
773 | } |
774 | ||
ffa7d616 TN |
775 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
776 | if(fwspec->param_count != 2) | |
777 | return -EINVAL; | |
778 | ||
779 | *hwirq = fwspec->param[0]; | |
780 | *type = fwspec->param[1]; | |
781 | return 0; | |
782 | } | |
783 | ||
f833f57f | 784 | return -EINVAL; |
021f6537 MZ |
785 | } |
786 | ||
443acc4f MZ |
787 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
788 | unsigned int nr_irqs, void *arg) | |
789 | { | |
790 | int i, ret; | |
791 | irq_hw_number_t hwirq; | |
792 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 793 | struct irq_fwspec *fwspec = arg; |
443acc4f | 794 | |
f833f57f | 795 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
796 | if (ret) |
797 | return ret; | |
798 | ||
799 | for (i = 0; i < nr_irqs; i++) | |
800 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
806 | unsigned int nr_irqs) | |
807 | { | |
808 | int i; | |
809 | ||
810 | for (i = 0; i < nr_irqs; i++) { | |
811 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
812 | irq_set_handler(virq + i, NULL); | |
813 | irq_domain_reset_irq_data(d); | |
814 | } | |
815 | } | |
816 | ||
021f6537 | 817 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 818 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
819 | .alloc = gic_irq_domain_alloc, |
820 | .free = gic_irq_domain_free, | |
021f6537 MZ |
821 | }; |
822 | ||
6d4e11c5 RR |
823 | static void gicv3_enable_quirks(void) |
824 | { | |
7936e914 | 825 | #ifdef CONFIG_ARM64 |
6d4e11c5 | 826 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
8ac2a170 | 827 | static_branch_enable(&is_cavium_thunderx); |
7936e914 | 828 | #endif |
6d4e11c5 RR |
829 | } |
830 | ||
db57d746 TN |
831 | static int __init gic_init_bases(void __iomem *dist_base, |
832 | struct redist_region *rdist_regs, | |
833 | u32 nr_redist_regions, | |
834 | u64 redist_stride, | |
835 | struct fwnode_handle *handle) | |
021f6537 | 836 | { |
db57d746 | 837 | struct device_node *node; |
f5c1434c | 838 | u32 typer; |
021f6537 MZ |
839 | int gic_irqs; |
840 | int err; | |
021f6537 | 841 | |
0b6a3da9 MZ |
842 | if (!is_hyp_mode_available()) |
843 | static_key_slow_dec(&supports_deactivate); | |
844 | ||
845 | if (static_key_true(&supports_deactivate)) | |
846 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
847 | ||
021f6537 | 848 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
849 | gic_data.redist_regions = rdist_regs; |
850 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
851 | gic_data.redist_stride = redist_stride; |
852 | ||
6d4e11c5 RR |
853 | gicv3_enable_quirks(); |
854 | ||
021f6537 MZ |
855 | /* |
856 | * Find out how many interrupts are supported. | |
857 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
858 | */ | |
f5c1434c MZ |
859 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
860 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
861 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
862 | if (gic_irqs > 1020) |
863 | gic_irqs = 1020; | |
864 | gic_data.irq_nr = gic_irqs; | |
865 | ||
db57d746 TN |
866 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
867 | &gic_data); | |
f5c1434c | 868 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 869 | |
f5c1434c | 870 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
871 | err = -ENOMEM; |
872 | goto out_free; | |
873 | } | |
874 | ||
875 | set_handle_irq(gic_handle_irq); | |
876 | ||
db57d746 TN |
877 | node = to_of_node(handle); |
878 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && | |
879 | node) /* Temp hack to prevent ITS init for ACPI */ | |
da33f31d MZ |
880 | its_init(node, &gic_data.rdists, gic_data.domain); |
881 | ||
021f6537 MZ |
882 | gic_smp_init(); |
883 | gic_dist_init(); | |
884 | gic_cpu_init(); | |
3708d52f | 885 | gic_cpu_pm_init(); |
021f6537 MZ |
886 | |
887 | return 0; | |
888 | ||
889 | out_free: | |
890 | if (gic_data.domain) | |
891 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 892 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
893 | return err; |
894 | } | |
895 | ||
896 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
897 | { | |
898 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
899 | ||
900 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
901 | return -ENODEV; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
907 | { | |
908 | void __iomem *dist_base; | |
909 | struct redist_region *rdist_regs; | |
910 | u64 redist_stride; | |
911 | u32 nr_redist_regions; | |
912 | int err, i; | |
913 | ||
914 | dist_base = of_iomap(node, 0); | |
915 | if (!dist_base) { | |
916 | pr_err("%s: unable to map gic dist registers\n", | |
917 | node->full_name); | |
918 | return -ENXIO; | |
919 | } | |
920 | ||
921 | err = gic_validate_dist_version(dist_base); | |
922 | if (err) { | |
923 | pr_err("%s: no distributor detected, giving up\n", | |
924 | node->full_name); | |
925 | goto out_unmap_dist; | |
926 | } | |
927 | ||
928 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
929 | nr_redist_regions = 1; | |
930 | ||
931 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); | |
932 | if (!rdist_regs) { | |
933 | err = -ENOMEM; | |
934 | goto out_unmap_dist; | |
935 | } | |
936 | ||
937 | for (i = 0; i < nr_redist_regions; i++) { | |
938 | struct resource res; | |
939 | int ret; | |
940 | ||
941 | ret = of_address_to_resource(node, 1 + i, &res); | |
942 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
943 | if (ret || !rdist_regs[i].redist_base) { | |
944 | pr_err("%s: couldn't map region %d\n", | |
945 | node->full_name, i); | |
946 | err = -ENODEV; | |
947 | goto out_unmap_rdist; | |
948 | } | |
949 | rdist_regs[i].phys_base = res.start; | |
950 | } | |
951 | ||
952 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
953 | redist_stride = 0; | |
954 | ||
955 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
956 | redist_stride, &node->fwnode); | |
957 | if (!err) | |
958 | return 0; | |
959 | ||
021f6537 | 960 | out_unmap_rdist: |
f5c1434c MZ |
961 | for (i = 0; i < nr_redist_regions; i++) |
962 | if (rdist_regs[i].redist_base) | |
963 | iounmap(rdist_regs[i].redist_base); | |
964 | kfree(rdist_regs); | |
021f6537 MZ |
965 | out_unmap_dist: |
966 | iounmap(dist_base); | |
967 | return err; | |
968 | } | |
969 | ||
970 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
971 | |
972 | #ifdef CONFIG_ACPI | |
b70fb7af | 973 | static void __iomem *dist_base; |
ffa7d616 TN |
974 | static struct redist_region *redist_regs __initdata; |
975 | static u32 nr_redist_regions __initdata; | |
b70fb7af TN |
976 | static bool single_redist; |
977 | ||
978 | static void __init | |
979 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
980 | { | |
981 | static int count = 0; | |
982 | ||
983 | redist_regs[count].phys_base = phys_base; | |
984 | redist_regs[count].redist_base = redist_base; | |
985 | redist_regs[count].single_redist = single_redist; | |
986 | count++; | |
987 | } | |
ffa7d616 TN |
988 | |
989 | static int __init | |
990 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
991 | const unsigned long end) | |
992 | { | |
993 | struct acpi_madt_generic_redistributor *redist = | |
994 | (struct acpi_madt_generic_redistributor *)header; | |
995 | void __iomem *redist_base; | |
ffa7d616 TN |
996 | |
997 | redist_base = ioremap(redist->base_address, redist->length); | |
998 | if (!redist_base) { | |
999 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1000 | return -ENOMEM; | |
1001 | } | |
1002 | ||
b70fb7af | 1003 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1004 | return 0; |
1005 | } | |
1006 | ||
b70fb7af TN |
1007 | static int __init |
1008 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1009 | const unsigned long end) | |
1010 | { | |
1011 | struct acpi_madt_generic_interrupt *gicc = | |
1012 | (struct acpi_madt_generic_interrupt *)header; | |
1013 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1014 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; | |
1015 | void __iomem *redist_base; | |
1016 | ||
1017 | redist_base = ioremap(gicc->gicr_base_address, size); | |
1018 | if (!redist_base) | |
1019 | return -ENOMEM; | |
1020 | ||
1021 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static int __init gic_acpi_collect_gicr_base(void) | |
1026 | { | |
1027 | acpi_tbl_entry_handler redist_parser; | |
1028 | enum acpi_madt_type type; | |
1029 | ||
1030 | if (single_redist) { | |
1031 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; | |
1032 | redist_parser = gic_acpi_parse_madt_gicc; | |
1033 | } else { | |
1034 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1035 | redist_parser = gic_acpi_parse_madt_redist; | |
1036 | } | |
1037 | ||
1038 | /* Collect redistributor base addresses in GICR entries */ | |
1039 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1040 | return 0; | |
1041 | ||
1042 | pr_info("No valid GICR entries exist\n"); | |
1043 | return -ENODEV; | |
1044 | } | |
1045 | ||
ffa7d616 TN |
1046 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1047 | const unsigned long end) | |
1048 | { | |
1049 | /* Subtable presence means that redist exists, that's it */ | |
1050 | return 0; | |
1051 | } | |
1052 | ||
b70fb7af TN |
1053 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1054 | const unsigned long end) | |
1055 | { | |
1056 | struct acpi_madt_generic_interrupt *gicc = | |
1057 | (struct acpi_madt_generic_interrupt *)header; | |
1058 | ||
1059 | /* | |
1060 | * If GICC is enabled and has valid gicr base address, then it means | |
1061 | * GICR base is presented via GICC | |
1062 | */ | |
1063 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1064 | return 0; | |
1065 | ||
1066 | return -ENODEV; | |
1067 | } | |
1068 | ||
1069 | static int __init gic_acpi_count_gicr_regions(void) | |
1070 | { | |
1071 | int count; | |
1072 | ||
1073 | /* | |
1074 | * Count how many redistributor regions we have. It is not allowed | |
1075 | * to mix redistributor description, GICR and GICC subtables have to be | |
1076 | * mutually exclusive. | |
1077 | */ | |
1078 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1079 | gic_acpi_match_gicr, 0); | |
1080 | if (count > 0) { | |
1081 | single_redist = false; | |
1082 | return count; | |
1083 | } | |
1084 | ||
1085 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1086 | gic_acpi_match_gicc, 0); | |
1087 | if (count > 0) | |
1088 | single_redist = true; | |
1089 | ||
1090 | return count; | |
1091 | } | |
1092 | ||
ffa7d616 TN |
1093 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1094 | struct acpi_probe_entry *ape) | |
1095 | { | |
1096 | struct acpi_madt_generic_distributor *dist; | |
1097 | int count; | |
1098 | ||
1099 | dist = (struct acpi_madt_generic_distributor *)header; | |
1100 | if (dist->version != ape->driver_data) | |
1101 | return false; | |
1102 | ||
1103 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1104 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1105 | if (count <= 0) |
1106 | return false; | |
1107 | ||
1108 | nr_redist_regions = count; | |
1109 | return true; | |
1110 | } | |
1111 | ||
1112 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) | |
1113 | ||
1114 | static int __init | |
1115 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1116 | { | |
1117 | struct acpi_madt_generic_distributor *dist; | |
1118 | struct fwnode_handle *domain_handle; | |
b70fb7af | 1119 | int i, err; |
ffa7d616 TN |
1120 | |
1121 | /* Get distributor base address */ | |
1122 | dist = (struct acpi_madt_generic_distributor *)header; | |
1123 | dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); | |
1124 | if (!dist_base) { | |
1125 | pr_err("Unable to map GICD registers\n"); | |
1126 | return -ENOMEM; | |
1127 | } | |
1128 | ||
1129 | err = gic_validate_dist_version(dist_base); | |
1130 | if (err) { | |
1131 | pr_err("No distributor detected at @%p, giving up", dist_base); | |
1132 | goto out_dist_unmap; | |
1133 | } | |
1134 | ||
1135 | redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, | |
1136 | GFP_KERNEL); | |
1137 | if (!redist_regs) { | |
1138 | err = -ENOMEM; | |
1139 | goto out_dist_unmap; | |
1140 | } | |
1141 | ||
b70fb7af TN |
1142 | err = gic_acpi_collect_gicr_base(); |
1143 | if (err) | |
ffa7d616 | 1144 | goto out_redist_unmap; |
ffa7d616 TN |
1145 | |
1146 | domain_handle = irq_domain_alloc_fwnode(dist_base); | |
1147 | if (!domain_handle) { | |
1148 | err = -ENOMEM; | |
1149 | goto out_redist_unmap; | |
1150 | } | |
1151 | ||
1152 | err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, | |
1153 | domain_handle); | |
1154 | if (err) | |
1155 | goto out_fwhandle_free; | |
1156 | ||
1157 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
1158 | return 0; | |
1159 | ||
1160 | out_fwhandle_free: | |
1161 | irq_domain_free_fwnode(domain_handle); | |
1162 | out_redist_unmap: | |
1163 | for (i = 0; i < nr_redist_regions; i++) | |
1164 | if (redist_regs[i].redist_base) | |
1165 | iounmap(redist_regs[i].redist_base); | |
1166 | kfree(redist_regs); | |
1167 | out_dist_unmap: | |
1168 | iounmap(dist_base); | |
1169 | return err; | |
1170 | } | |
1171 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1172 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1173 | gic_acpi_init); | |
1174 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1175 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1176 | gic_acpi_init); | |
1177 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1178 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1179 | gic_acpi_init); | |
1180 | #endif |