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021f6537 | 1 | /* |
0edc23ea | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
68628bb8 JG |
18 | #define pr_fmt(fmt) "GICv3: " fmt |
19 | ||
ffa7d616 | 20 | #include <linux/acpi.h> |
021f6537 | 21 | #include <linux/cpu.h> |
3708d52f | 22 | #include <linux/cpu_pm.h> |
021f6537 MZ |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
ffa7d616 | 25 | #include <linux/irqdomain.h> |
021f6537 MZ |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
31 | ||
41a83e06 | 32 | #include <linux/irqchip.h> |
1839e576 | 33 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 34 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 35 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
36 | |
37 | #include <asm/cputype.h> | |
38 | #include <asm/exception.h> | |
39 | #include <asm/smp_plat.h> | |
0b6a3da9 | 40 | #include <asm/virt.h> |
021f6537 MZ |
41 | |
42 | #include "irq-gic-common.h" | |
021f6537 | 43 | |
f5c1434c MZ |
44 | struct redist_region { |
45 | void __iomem *redist_base; | |
46 | phys_addr_t phys_base; | |
b70fb7af | 47 | bool single_redist; |
f5c1434c MZ |
48 | }; |
49 | ||
021f6537 | 50 | struct gic_chip_data { |
e3825ba1 | 51 | struct fwnode_handle *fwnode; |
021f6537 | 52 | void __iomem *dist_base; |
f5c1434c MZ |
53 | struct redist_region *redist_regions; |
54 | struct rdists rdists; | |
021f6537 MZ |
55 | struct irq_domain *domain; |
56 | u64 redist_stride; | |
f5c1434c | 57 | u32 nr_redist_regions; |
eda0d04a | 58 | bool has_rss; |
021f6537 | 59 | unsigned int irq_nr; |
e3825ba1 | 60 | struct partition_desc *ppi_descs[16]; |
021f6537 MZ |
61 | }; |
62 | ||
63 | static struct gic_chip_data gic_data __read_mostly; | |
d01d3274 | 64 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
021f6537 | 65 | |
1839e576 | 66 | static struct gic_kvm_info gic_v3_kvm_info; |
eda0d04a | 67 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 68 | |
eda0d04a | 69 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
70 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
71 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
72 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
73 | ||
74 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
75 | #define DEFAULT_PMR_VALUE 0xf0 | |
76 | ||
77 | static inline unsigned int gic_irq(struct irq_data *d) | |
78 | { | |
79 | return d->hwirq; | |
80 | } | |
81 | ||
82 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
83 | { | |
84 | return gic_irq(d) < 32; | |
85 | } | |
86 | ||
87 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
88 | { | |
89 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
90 | return gic_data_rdist_sgi_base(); | |
91 | ||
92 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
93 | return gic_data.dist_base; | |
94 | ||
021f6537 MZ |
95 | return NULL; |
96 | } | |
97 | ||
98 | static void gic_do_wait_for_rwp(void __iomem *base) | |
99 | { | |
100 | u32 count = 1000000; /* 1s! */ | |
101 | ||
102 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
103 | count--; | |
104 | if (!count) { | |
105 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
106 | return; | |
107 | } | |
108 | cpu_relax(); | |
109 | udelay(1); | |
110 | }; | |
111 | } | |
112 | ||
113 | /* Wait for completion of a distributor change */ | |
114 | static void gic_dist_wait_for_rwp(void) | |
115 | { | |
116 | gic_do_wait_for_rwp(gic_data.dist_base); | |
117 | } | |
118 | ||
119 | /* Wait for completion of a redistributor change */ | |
120 | static void gic_redist_wait_for_rwp(void) | |
121 | { | |
122 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
123 | } | |
124 | ||
7936e914 | 125 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
126 | |
127 | static u64 __maybe_unused gic_read_iar(void) | |
128 | { | |
a4023f68 | 129 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
130 | return gic_read_iar_cavium_thunderx(); |
131 | else | |
132 | return gic_read_iar_common(); | |
133 | } | |
7936e914 | 134 | #endif |
021f6537 | 135 | |
a2c22510 | 136 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
137 | { |
138 | void __iomem *rbase; | |
139 | u32 count = 1000000; /* 1s! */ | |
140 | u32 val; | |
141 | ||
142 | rbase = gic_data_rdist_rd_base(); | |
143 | ||
021f6537 | 144 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
145 | if (enable) |
146 | /* Wake up this CPU redistributor */ | |
147 | val &= ~GICR_WAKER_ProcessorSleep; | |
148 | else | |
149 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
150 | writel_relaxed(val, rbase + GICR_WAKER); |
151 | ||
a2c22510 SH |
152 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
153 | val = readl_relaxed(rbase + GICR_WAKER); | |
154 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
155 | return; /* No PM support in this redistributor */ | |
156 | } | |
157 | ||
d102eb5c | 158 | while (--count) { |
a2c22510 | 159 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 160 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 161 | break; |
021f6537 MZ |
162 | cpu_relax(); |
163 | udelay(1); | |
164 | }; | |
a2c22510 SH |
165 | if (!count) |
166 | pr_err_ratelimited("redistributor failed to %s...\n", | |
167 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
168 | } |
169 | ||
170 | /* | |
171 | * Routines to disable, enable, EOI and route interrupts | |
172 | */ | |
b594c6e2 MZ |
173 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
174 | { | |
175 | u32 mask = 1 << (gic_irq(d) % 32); | |
176 | void __iomem *base; | |
177 | ||
178 | if (gic_irq_in_rdist(d)) | |
179 | base = gic_data_rdist_sgi_base(); | |
180 | else | |
181 | base = gic_data.dist_base; | |
182 | ||
183 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
184 | } | |
185 | ||
021f6537 MZ |
186 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
187 | { | |
188 | u32 mask = 1 << (gic_irq(d) % 32); | |
189 | void (*rwp_wait)(void); | |
190 | void __iomem *base; | |
191 | ||
192 | if (gic_irq_in_rdist(d)) { | |
193 | base = gic_data_rdist_sgi_base(); | |
194 | rwp_wait = gic_redist_wait_for_rwp; | |
195 | } else { | |
196 | base = gic_data.dist_base; | |
197 | rwp_wait = gic_dist_wait_for_rwp; | |
198 | } | |
199 | ||
200 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
201 | rwp_wait(); | |
202 | } | |
203 | ||
021f6537 MZ |
204 | static void gic_mask_irq(struct irq_data *d) |
205 | { | |
206 | gic_poke_irq(d, GICD_ICENABLER); | |
207 | } | |
208 | ||
0b6a3da9 MZ |
209 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
210 | { | |
211 | gic_mask_irq(d); | |
530bf353 MZ |
212 | /* |
213 | * When masking a forwarded interrupt, make sure it is | |
214 | * deactivated as well. | |
215 | * | |
216 | * This ensures that an interrupt that is getting | |
217 | * disabled/masked will not get "stuck", because there is | |
218 | * noone to deactivate it (guest is being terminated). | |
219 | */ | |
4df7f54d | 220 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 221 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
222 | } |
223 | ||
021f6537 MZ |
224 | static void gic_unmask_irq(struct irq_data *d) |
225 | { | |
226 | gic_poke_irq(d, GICD_ISENABLER); | |
227 | } | |
228 | ||
b594c6e2 MZ |
229 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
230 | enum irqchip_irq_state which, bool val) | |
231 | { | |
232 | u32 reg; | |
233 | ||
234 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
235 | return -EINVAL; | |
236 | ||
237 | switch (which) { | |
238 | case IRQCHIP_STATE_PENDING: | |
239 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
240 | break; | |
241 | ||
242 | case IRQCHIP_STATE_ACTIVE: | |
243 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
244 | break; | |
245 | ||
246 | case IRQCHIP_STATE_MASKED: | |
247 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
248 | break; | |
249 | ||
250 | default: | |
251 | return -EINVAL; | |
252 | } | |
253 | ||
254 | gic_poke_irq(d, reg); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
259 | enum irqchip_irq_state which, bool *val) | |
260 | { | |
261 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
262 | return -EINVAL; | |
263 | ||
264 | switch (which) { | |
265 | case IRQCHIP_STATE_PENDING: | |
266 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
267 | break; | |
268 | ||
269 | case IRQCHIP_STATE_ACTIVE: | |
270 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
271 | break; | |
272 | ||
273 | case IRQCHIP_STATE_MASKED: | |
274 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
275 | break; | |
276 | ||
277 | default: | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
021f6537 MZ |
284 | static void gic_eoi_irq(struct irq_data *d) |
285 | { | |
286 | gic_write_eoir(gic_irq(d)); | |
287 | } | |
288 | ||
0b6a3da9 MZ |
289 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
290 | { | |
291 | /* | |
530bf353 MZ |
292 | * No need to deactivate an LPI, or an interrupt that |
293 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 294 | */ |
4df7f54d | 295 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
296 | return; |
297 | gic_write_dir(gic_irq(d)); | |
298 | } | |
299 | ||
021f6537 MZ |
300 | static int gic_set_type(struct irq_data *d, unsigned int type) |
301 | { | |
302 | unsigned int irq = gic_irq(d); | |
303 | void (*rwp_wait)(void); | |
304 | void __iomem *base; | |
305 | ||
306 | /* Interrupt configuration for SGIs can't be changed */ | |
307 | if (irq < 16) | |
308 | return -EINVAL; | |
309 | ||
fb7e7deb LD |
310 | /* SPIs have restrictions on the supported types */ |
311 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
312 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
313 | return -EINVAL; |
314 | ||
315 | if (gic_irq_in_rdist(d)) { | |
316 | base = gic_data_rdist_sgi_base(); | |
317 | rwp_wait = gic_redist_wait_for_rwp; | |
318 | } else { | |
319 | base = gic_data.dist_base; | |
320 | rwp_wait = gic_dist_wait_for_rwp; | |
321 | } | |
322 | ||
fb7e7deb | 323 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
324 | } |
325 | ||
530bf353 MZ |
326 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
327 | { | |
4df7f54d TG |
328 | if (vcpu) |
329 | irqd_set_forwarded_to_vcpu(d); | |
330 | else | |
331 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
332 | return 0; |
333 | } | |
334 | ||
f6c86a41 | 335 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
336 | { |
337 | u64 aff; | |
338 | ||
f6c86a41 | 339 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
340 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
341 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
342 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
343 | ||
344 | return aff; | |
345 | } | |
346 | ||
347 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
348 | { | |
f6c86a41 | 349 | u32 irqnr; |
021f6537 MZ |
350 | |
351 | do { | |
352 | irqnr = gic_read_iar(); | |
353 | ||
da33f31d | 354 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 355 | int err; |
0b6a3da9 | 356 | |
d01d3274 | 357 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 | 358 | gic_write_eoir(irqnr); |
39a06b67 WD |
359 | else |
360 | isb(); | |
0b6a3da9 | 361 | |
ebc6de00 MZ |
362 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
363 | if (err) { | |
da33f31d | 364 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
d01d3274 | 365 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
366 | if (irqnr < 8192) |
367 | gic_write_dir(irqnr); | |
368 | } else { | |
369 | gic_write_eoir(irqnr); | |
370 | } | |
021f6537 | 371 | } |
ebc6de00 | 372 | continue; |
021f6537 MZ |
373 | } |
374 | if (irqnr < 16) { | |
375 | gic_write_eoir(irqnr); | |
d01d3274 | 376 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 | 377 | gic_write_dir(irqnr); |
021f6537 | 378 | #ifdef CONFIG_SMP |
f86c4fbd WD |
379 | /* |
380 | * Unlike GICv2, we don't need an smp_rmb() here. | |
381 | * The control dependency from gic_read_iar to | |
382 | * the ISB in gic_write_eoir is enough to ensure | |
383 | * that any shared data read by handle_IPI will | |
384 | * be read after the ACK. | |
385 | */ | |
021f6537 MZ |
386 | handle_IPI(irqnr, regs); |
387 | #else | |
388 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
389 | #endif | |
390 | continue; | |
391 | } | |
392 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
393 | } | |
394 | ||
395 | static void __init gic_dist_init(void) | |
396 | { | |
397 | unsigned int i; | |
398 | u64 affinity; | |
399 | void __iomem *base = gic_data.dist_base; | |
400 | ||
401 | /* Disable the distributor */ | |
402 | writel_relaxed(0, base + GICD_CTLR); | |
403 | gic_dist_wait_for_rwp(); | |
404 | ||
7c9b9730 MZ |
405 | /* |
406 | * Configure SPIs as non-secure Group-1. This will only matter | |
407 | * if the GIC only has a single security state. This will not | |
408 | * do the right thing if the kernel is running in secure mode, | |
409 | * but that's not the intended use case anyway. | |
410 | */ | |
411 | for (i = 32; i < gic_data.irq_nr; i += 32) | |
412 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); | |
413 | ||
021f6537 MZ |
414 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
415 | ||
416 | /* Enable distributor with ARE, Group1 */ | |
417 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
418 | base + GICD_CTLR); | |
419 | ||
420 | /* | |
421 | * Set all global interrupts to the boot CPU only. ARE must be | |
422 | * enabled. | |
423 | */ | |
424 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
425 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 426 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
427 | } |
428 | ||
0d94ded2 | 429 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 430 | { |
0d94ded2 | 431 | int ret = -ENODEV; |
021f6537 MZ |
432 | int i; |
433 | ||
f5c1434c MZ |
434 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
435 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 436 | u64 typer; |
021f6537 MZ |
437 | u32 reg; |
438 | ||
439 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
440 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
441 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
442 | pr_warn("No redistributor present @%p\n", ptr); | |
443 | break; | |
444 | } | |
445 | ||
446 | do { | |
72c97126 | 447 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
448 | ret = fn(gic_data.redist_regions + i, ptr); |
449 | if (!ret) | |
021f6537 | 450 | return 0; |
021f6537 | 451 | |
b70fb7af TN |
452 | if (gic_data.redist_regions[i].single_redist) |
453 | break; | |
454 | ||
021f6537 MZ |
455 | if (gic_data.redist_stride) { |
456 | ptr += gic_data.redist_stride; | |
457 | } else { | |
458 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
459 | if (typer & GICR_TYPER_VLPIS) | |
460 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
461 | } | |
462 | } while (!(typer & GICR_TYPER_LAST)); | |
463 | } | |
464 | ||
0d94ded2 MZ |
465 | return ret ? -ENODEV : 0; |
466 | } | |
467 | ||
468 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
469 | { | |
470 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); | |
471 | u64 typer; | |
472 | u32 aff; | |
473 | ||
474 | /* | |
475 | * Convert affinity to a 32bit value that can be matched to | |
476 | * GICR_TYPER bits [63:32]. | |
477 | */ | |
478 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
479 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
480 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
481 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
482 | ||
483 | typer = gic_read_typer(ptr + GICR_TYPER); | |
484 | if ((typer >> 32) == aff) { | |
485 | u64 offset = ptr - region->redist_base; | |
486 | gic_data_rdist_rd_base() = ptr; | |
487 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
488 | ||
489 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
490 | smp_processor_id(), mpidr, | |
491 | (int)(region - gic_data.redist_regions), | |
492 | &gic_data_rdist()->phys_base); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | /* Try next one */ | |
497 | return 1; | |
498 | } | |
499 | ||
500 | static int gic_populate_rdist(void) | |
501 | { | |
502 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
503 | return 0; | |
504 | ||
021f6537 | 505 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 506 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
507 | smp_processor_id(), |
508 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
509 | return -ENODEV; |
510 | } | |
511 | ||
0edc23ea MZ |
512 | static int __gic_update_vlpi_properties(struct redist_region *region, |
513 | void __iomem *ptr) | |
514 | { | |
515 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
516 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); | |
517 | gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); | |
518 | ||
519 | return 1; | |
520 | } | |
521 | ||
522 | static void gic_update_vlpi_properties(void) | |
523 | { | |
524 | gic_iterate_rdists(__gic_update_vlpi_properties); | |
525 | pr_info("%sVLPI support, %sdirect LPI support\n", | |
526 | !gic_data.rdists.has_vlpis ? "no " : "", | |
527 | !gic_data.rdists.has_direct_lpi ? "no " : ""); | |
528 | } | |
529 | ||
3708d52f SH |
530 | static void gic_cpu_sys_reg_init(void) |
531 | { | |
eda0d04a SD |
532 | int i, cpu = smp_processor_id(); |
533 | u64 mpidr = cpu_logical_map(cpu); | |
534 | u64 need_rss = MPIDR_RS(mpidr); | |
33625282 MZ |
535 | bool group0; |
536 | u32 val, pribits; | |
eda0d04a | 537 | |
7cabd008 MZ |
538 | /* |
539 | * Need to check that the SRE bit has actually been set. If | |
540 | * not, it means that SRE is disabled at EL2. We're going to | |
541 | * die painfully, and there is nothing we can do about it. | |
542 | * | |
543 | * Kindly inform the luser. | |
544 | */ | |
545 | if (!gic_enable_sre()) | |
546 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f | 547 | |
33625282 MZ |
548 | pribits = gic_read_ctlr(); |
549 | pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
550 | pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
551 | pribits++; | |
552 | ||
553 | /* | |
554 | * Let's find out if Group0 is under control of EL3 or not by | |
555 | * setting the highest possible, non-zero priority in PMR. | |
556 | * | |
557 | * If SCR_EL3.FIQ is set, the priority gets shifted down in | |
558 | * order for the CPU interface to set bit 7, and keep the | |
559 | * actual priority in the non-secure range. In the process, it | |
560 | * looses the least significant bit and the actual priority | |
561 | * becomes 0x80. Reading it back returns 0, indicating that | |
562 | * we're don't have access to Group0. | |
563 | */ | |
564 | write_gicreg(BIT(8 - pribits), ICC_PMR_EL1); | |
565 | val = read_gicreg(ICC_PMR_EL1); | |
566 | group0 = val != 0; | |
567 | ||
3708d52f | 568 | /* Set priority mask register */ |
33625282 | 569 | write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); |
3708d52f | 570 | |
91ef8442 DT |
571 | /* |
572 | * Some firmwares hand over to the kernel with the BPR changed from | |
573 | * its reset value (and with a value large enough to prevent | |
574 | * any pre-emptive interrupts from working at all). Writing a zero | |
575 | * to BPR restores is reset value. | |
576 | */ | |
577 | gic_write_bpr1(0); | |
578 | ||
d01d3274 | 579 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
580 | /* EOI drops priority only (mode 1) */ |
581 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
582 | } else { | |
583 | /* EOI deactivates interrupt too (mode 0) */ | |
584 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
585 | } | |
3708d52f | 586 | |
33625282 MZ |
587 | /* Always whack Group0 before Group1 */ |
588 | if (group0) { | |
589 | switch(pribits) { | |
590 | case 8: | |
591 | case 7: | |
592 | write_gicreg(0, ICC_AP0R3_EL1); | |
593 | write_gicreg(0, ICC_AP0R2_EL1); | |
594 | case 6: | |
595 | write_gicreg(0, ICC_AP0R1_EL1); | |
596 | case 5: | |
597 | case 4: | |
598 | write_gicreg(0, ICC_AP0R0_EL1); | |
599 | } | |
600 | ||
601 | isb(); | |
602 | } | |
d6062a6d | 603 | |
33625282 | 604 | switch(pribits) { |
d6062a6d MZ |
605 | case 8: |
606 | case 7: | |
d6062a6d | 607 | write_gicreg(0, ICC_AP1R3_EL1); |
d6062a6d MZ |
608 | write_gicreg(0, ICC_AP1R2_EL1); |
609 | case 6: | |
d6062a6d MZ |
610 | write_gicreg(0, ICC_AP1R1_EL1); |
611 | case 5: | |
612 | case 4: | |
d6062a6d MZ |
613 | write_gicreg(0, ICC_AP1R0_EL1); |
614 | } | |
615 | ||
616 | isb(); | |
617 | ||
3708d52f SH |
618 | /* ... and let's hit the road... */ |
619 | gic_write_grpen1(1); | |
eda0d04a SD |
620 | |
621 | /* Keep the RSS capability status in per_cpu variable */ | |
622 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
623 | ||
624 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
625 | for_each_online_cpu(i) { | |
626 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
627 | ||
628 | need_rss |= MPIDR_RS(cpu_logical_map(i)); | |
629 | if (need_rss && (!have_rss)) | |
630 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
631 | cpu, (unsigned long)mpidr, | |
632 | i, (unsigned long)cpu_logical_map(i)); | |
633 | } | |
634 | ||
635 | /** | |
636 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
637 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
638 | * UNPREDICTABLE choice of : | |
639 | * - The write is ignored. | |
640 | * - The RS field is treated as 0. | |
641 | */ | |
642 | if (need_rss && (!gic_data.has_rss)) | |
643 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
644 | } |
645 | ||
f736d65d MZ |
646 | static bool gicv3_nolpi; |
647 | ||
648 | static int __init gicv3_nolpi_cfg(char *buf) | |
649 | { | |
650 | return strtobool(buf, &gicv3_nolpi); | |
651 | } | |
652 | early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); | |
653 | ||
da33f31d MZ |
654 | static int gic_dist_supports_lpis(void) |
655 | { | |
f736d65d | 656 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi; |
da33f31d MZ |
657 | } |
658 | ||
021f6537 MZ |
659 | static void gic_cpu_init(void) |
660 | { | |
661 | void __iomem *rbase; | |
662 | ||
663 | /* Register ourselves with the rest of the world */ | |
664 | if (gic_populate_rdist()) | |
665 | return; | |
666 | ||
a2c22510 | 667 | gic_enable_redist(true); |
021f6537 MZ |
668 | |
669 | rbase = gic_data_rdist_sgi_base(); | |
670 | ||
7c9b9730 MZ |
671 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
672 | writel_relaxed(~0, rbase + GICR_IGROUPR0); | |
673 | ||
021f6537 MZ |
674 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
675 | ||
da33f31d MZ |
676 | /* Give LPIs a spin */ |
677 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
678 | its_cpu_init(); | |
679 | ||
3708d52f SH |
680 | /* initialise system registers */ |
681 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
682 | } |
683 | ||
684 | #ifdef CONFIG_SMP | |
6670a6d8 | 685 | |
eda0d04a SD |
686 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
687 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
688 | ||
6670a6d8 | 689 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 690 | { |
6670a6d8 RC |
691 | gic_cpu_init(); |
692 | return 0; | |
021f6537 MZ |
693 | } |
694 | ||
021f6537 | 695 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 696 | unsigned long cluster_id) |
021f6537 | 697 | { |
727653d6 | 698 | int next_cpu, cpu = *base_cpu; |
f6c86a41 | 699 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
700 | u16 tlist = 0; |
701 | ||
702 | while (cpu < nr_cpu_ids) { | |
021f6537 MZ |
703 | tlist |= 1 << (mpidr & 0xf); |
704 | ||
727653d6 JM |
705 | next_cpu = cpumask_next(cpu, mask); |
706 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 707 | goto out; |
727653d6 | 708 | cpu = next_cpu; |
021f6537 MZ |
709 | |
710 | mpidr = cpu_logical_map(cpu); | |
711 | ||
eda0d04a | 712 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
713 | cpu--; |
714 | goto out; | |
715 | } | |
716 | } | |
717 | out: | |
718 | *base_cpu = cpu; | |
719 | return tlist; | |
720 | } | |
721 | ||
7e580278 AP |
722 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
723 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
724 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
725 | ||
021f6537 MZ |
726 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
727 | { | |
728 | u64 val; | |
729 | ||
7e580278 AP |
730 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
731 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
732 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
733 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 734 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 735 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 736 | |
b6dd4d83 | 737 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
738 | gic_write_sgi1r(val); |
739 | } | |
740 | ||
741 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
742 | { | |
743 | int cpu; | |
744 | ||
745 | if (WARN_ON(irq >= 16)) | |
746 | return; | |
747 | ||
748 | /* | |
749 | * Ensure that stores to Normal memory are visible to the | |
750 | * other CPUs before issuing the IPI. | |
751 | */ | |
21ec30c0 | 752 | wmb(); |
021f6537 | 753 | |
f9b531fe | 754 | for_each_cpu(cpu, mask) { |
eda0d04a | 755 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); |
021f6537 MZ |
756 | u16 tlist; |
757 | ||
758 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
759 | gic_send_sgi(cluster_id, tlist, irq); | |
760 | } | |
761 | ||
762 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
763 | isb(); | |
764 | } | |
765 | ||
766 | static void gic_smp_init(void) | |
767 | { | |
768 | set_smp_cross_call(gic_raise_softirq); | |
6896bcd1 | 769 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
770 | "irqchip/arm/gicv3:starting", |
771 | gic_starting_cpu, NULL); | |
021f6537 MZ |
772 | } |
773 | ||
774 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
775 | bool force) | |
776 | { | |
65a30f8b | 777 | unsigned int cpu; |
021f6537 MZ |
778 | void __iomem *reg; |
779 | int enabled; | |
780 | u64 val; | |
781 | ||
65a30f8b SP |
782 | if (force) |
783 | cpu = cpumask_first(mask_val); | |
784 | else | |
785 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
786 | ||
866d7c1b SP |
787 | if (cpu >= nr_cpu_ids) |
788 | return -EINVAL; | |
789 | ||
021f6537 MZ |
790 | if (gic_irq_in_rdist(d)) |
791 | return -EINVAL; | |
792 | ||
793 | /* If interrupt was enabled, disable it first */ | |
794 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
795 | if (enabled) | |
796 | gic_mask_irq(d); | |
797 | ||
798 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
799 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
800 | ||
72c97126 | 801 | gic_write_irouter(val, reg); |
021f6537 MZ |
802 | |
803 | /* | |
804 | * If the interrupt was enabled, enabled it again. Otherwise, | |
805 | * just wait for the distributor to have digested our changes. | |
806 | */ | |
807 | if (enabled) | |
808 | gic_unmask_irq(d); | |
809 | else | |
810 | gic_dist_wait_for_rwp(); | |
811 | ||
956ae91a MZ |
812 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
813 | ||
0fc6fa29 | 814 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
815 | } |
816 | #else | |
817 | #define gic_set_affinity NULL | |
818 | #define gic_smp_init() do { } while(0) | |
819 | #endif | |
820 | ||
3708d52f | 821 | #ifdef CONFIG_CPU_PM |
ccd9432a SH |
822 | /* Check whether it's single security state view */ |
823 | static bool gic_dist_security_disabled(void) | |
824 | { | |
825 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
826 | } | |
827 | ||
3708d52f SH |
828 | static int gic_cpu_pm_notifier(struct notifier_block *self, |
829 | unsigned long cmd, void *v) | |
830 | { | |
831 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
832 | if (gic_dist_security_disabled()) |
833 | gic_enable_redist(true); | |
3708d52f | 834 | gic_cpu_sys_reg_init(); |
ccd9432a | 835 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
836 | gic_write_grpen1(0); |
837 | gic_enable_redist(false); | |
838 | } | |
839 | return NOTIFY_OK; | |
840 | } | |
841 | ||
842 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
843 | .notifier_call = gic_cpu_pm_notifier, | |
844 | }; | |
845 | ||
846 | static void gic_cpu_pm_init(void) | |
847 | { | |
848 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
849 | } | |
850 | ||
851 | #else | |
852 | static inline void gic_cpu_pm_init(void) { } | |
853 | #endif /* CONFIG_CPU_PM */ | |
854 | ||
021f6537 MZ |
855 | static struct irq_chip gic_chip = { |
856 | .name = "GICv3", | |
857 | .irq_mask = gic_mask_irq, | |
858 | .irq_unmask = gic_unmask_irq, | |
859 | .irq_eoi = gic_eoi_irq, | |
860 | .irq_set_type = gic_set_type, | |
861 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
862 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
863 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 864 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
865 | }; |
866 | ||
0b6a3da9 MZ |
867 | static struct irq_chip gic_eoimode1_chip = { |
868 | .name = "GICv3", | |
869 | .irq_mask = gic_eoimode1_mask_irq, | |
870 | .irq_unmask = gic_unmask_irq, | |
871 | .irq_eoi = gic_eoimode1_eoi_irq, | |
872 | .irq_set_type = gic_set_type, | |
873 | .irq_set_affinity = gic_set_affinity, | |
874 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
875 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 876 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
877 | .flags = IRQCHIP_SET_TYPE_MASKED, |
878 | }; | |
879 | ||
da33f31d MZ |
880 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
881 | ||
021f6537 MZ |
882 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
883 | irq_hw_number_t hw) | |
884 | { | |
0b6a3da9 MZ |
885 | struct irq_chip *chip = &gic_chip; |
886 | ||
d01d3274 | 887 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
888 | chip = &gic_eoimode1_chip; |
889 | ||
021f6537 MZ |
890 | /* SGIs are private to the core kernel */ |
891 | if (hw < 16) | |
892 | return -EPERM; | |
da33f31d MZ |
893 | /* Nothing here */ |
894 | if (hw >= gic_data.irq_nr && hw < 8192) | |
895 | return -EPERM; | |
896 | /* Off limits */ | |
897 | if (hw >= GIC_ID_NR) | |
898 | return -EPERM; | |
899 | ||
021f6537 MZ |
900 | /* PPIs */ |
901 | if (hw < 32) { | |
902 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 903 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 904 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 905 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
906 | } |
907 | /* SPIs */ | |
908 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 909 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 910 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 911 | irq_set_probe(irq); |
956ae91a | 912 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); |
021f6537 | 913 | } |
da33f31d MZ |
914 | /* LPIs */ |
915 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
916 | if (!gic_dist_supports_lpis()) | |
917 | return -EPERM; | |
0b6a3da9 | 918 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 919 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
920 | } |
921 | ||
021f6537 MZ |
922 | return 0; |
923 | } | |
924 | ||
65da7d19 MZ |
925 | #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) |
926 | ||
f833f57f MZ |
927 | static int gic_irq_domain_translate(struct irq_domain *d, |
928 | struct irq_fwspec *fwspec, | |
929 | unsigned long *hwirq, | |
930 | unsigned int *type) | |
021f6537 | 931 | { |
f833f57f MZ |
932 | if (is_of_node(fwspec->fwnode)) { |
933 | if (fwspec->param_count < 3) | |
934 | return -EINVAL; | |
021f6537 | 935 | |
db8c70ec MZ |
936 | switch (fwspec->param[0]) { |
937 | case 0: /* SPI */ | |
938 | *hwirq = fwspec->param[1] + 32; | |
939 | break; | |
940 | case 1: /* PPI */ | |
65da7d19 | 941 | case GIC_IRQ_TYPE_PARTITION: |
db8c70ec MZ |
942 | *hwirq = fwspec->param[1] + 16; |
943 | break; | |
944 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
945 | *hwirq = fwspec->param[1]; | |
946 | break; | |
947 | default: | |
948 | return -EINVAL; | |
949 | } | |
f833f57f MZ |
950 | |
951 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
6ef6386e | 952 | |
65da7d19 MZ |
953 | /* |
954 | * Make it clear that broken DTs are... broken. | |
955 | * Partitionned PPIs are an unfortunate exception. | |
956 | */ | |
957 | WARN_ON(*type == IRQ_TYPE_NONE && | |
958 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | |
f833f57f | 959 | return 0; |
021f6537 MZ |
960 | } |
961 | ||
ffa7d616 TN |
962 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
963 | if(fwspec->param_count != 2) | |
964 | return -EINVAL; | |
965 | ||
966 | *hwirq = fwspec->param[0]; | |
967 | *type = fwspec->param[1]; | |
6ef6386e MZ |
968 | |
969 | WARN_ON(*type == IRQ_TYPE_NONE); | |
ffa7d616 TN |
970 | return 0; |
971 | } | |
972 | ||
f833f57f | 973 | return -EINVAL; |
021f6537 MZ |
974 | } |
975 | ||
443acc4f MZ |
976 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
977 | unsigned int nr_irqs, void *arg) | |
978 | { | |
979 | int i, ret; | |
980 | irq_hw_number_t hwirq; | |
981 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 982 | struct irq_fwspec *fwspec = arg; |
443acc4f | 983 | |
f833f57f | 984 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
985 | if (ret) |
986 | return ret; | |
987 | ||
63c16c6e SP |
988 | for (i = 0; i < nr_irqs; i++) { |
989 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
990 | if (ret) | |
991 | return ret; | |
992 | } | |
443acc4f MZ |
993 | |
994 | return 0; | |
995 | } | |
996 | ||
997 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
998 | unsigned int nr_irqs) | |
999 | { | |
1000 | int i; | |
1001 | ||
1002 | for (i = 0; i < nr_irqs; i++) { | |
1003 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
1004 | irq_set_handler(virq + i, NULL); | |
1005 | irq_domain_reset_irq_data(d); | |
1006 | } | |
1007 | } | |
1008 | ||
e3825ba1 MZ |
1009 | static int gic_irq_domain_select(struct irq_domain *d, |
1010 | struct irq_fwspec *fwspec, | |
1011 | enum irq_domain_bus_token bus_token) | |
1012 | { | |
1013 | /* Not for us */ | |
1014 | if (fwspec->fwnode != d->fwnode) | |
1015 | return 0; | |
1016 | ||
1017 | /* If this is not DT, then we have a single domain */ | |
1018 | if (!is_of_node(fwspec->fwnode)) | |
1019 | return 1; | |
1020 | ||
1021 | /* | |
1022 | * If this is a PPI and we have a 4th (non-null) parameter, | |
1023 | * then we need to match the partition domain. | |
1024 | */ | |
1025 | if (fwspec->param_count >= 4 && | |
1026 | fwspec->param[0] == 1 && fwspec->param[3] != 0) | |
1027 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); | |
1028 | ||
1029 | return d == gic_data.domain; | |
1030 | } | |
1031 | ||
021f6537 | 1032 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 1033 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
1034 | .alloc = gic_irq_domain_alloc, |
1035 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
1036 | .select = gic_irq_domain_select, |
1037 | }; | |
1038 | ||
1039 | static int partition_domain_translate(struct irq_domain *d, | |
1040 | struct irq_fwspec *fwspec, | |
1041 | unsigned long *hwirq, | |
1042 | unsigned int *type) | |
1043 | { | |
1044 | struct device_node *np; | |
1045 | int ret; | |
1046 | ||
1047 | np = of_find_node_by_phandle(fwspec->param[3]); | |
1048 | if (WARN_ON(!np)) | |
1049 | return -EINVAL; | |
1050 | ||
1051 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
1052 | of_node_to_fwnode(np)); | |
1053 | if (ret < 0) | |
1054 | return ret; | |
1055 | ||
1056 | *hwirq = ret; | |
1057 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static const struct irq_domain_ops partition_domain_ops = { | |
1063 | .translate = partition_domain_translate, | |
1064 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1065 | }; |
1066 | ||
db57d746 TN |
1067 | static int __init gic_init_bases(void __iomem *dist_base, |
1068 | struct redist_region *rdist_regs, | |
1069 | u32 nr_redist_regions, | |
1070 | u64 redist_stride, | |
1071 | struct fwnode_handle *handle) | |
021f6537 | 1072 | { |
f5c1434c | 1073 | u32 typer; |
021f6537 MZ |
1074 | int gic_irqs; |
1075 | int err; | |
021f6537 | 1076 | |
0b6a3da9 | 1077 | if (!is_hyp_mode_available()) |
d01d3274 | 1078 | static_branch_disable(&supports_deactivate_key); |
0b6a3da9 | 1079 | |
d01d3274 | 1080 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1081 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
1082 | ||
e3825ba1 | 1083 | gic_data.fwnode = handle; |
021f6537 | 1084 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
1085 | gic_data.redist_regions = rdist_regs; |
1086 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
1087 | gic_data.redist_stride = redist_stride; |
1088 | ||
1089 | /* | |
1090 | * Find out how many interrupts are supported. | |
1091 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
1092 | */ | |
f5c1434c MZ |
1093 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
1094 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
1095 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
1096 | if (gic_irqs > 1020) |
1097 | gic_irqs = 1020; | |
1098 | gic_data.irq_nr = gic_irqs; | |
1099 | ||
db57d746 TN |
1100 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
1101 | &gic_data); | |
b2425b51 | 1102 | irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); |
f5c1434c | 1103 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
0edc23ea MZ |
1104 | gic_data.rdists.has_vlpis = true; |
1105 | gic_data.rdists.has_direct_lpi = true; | |
021f6537 | 1106 | |
f5c1434c | 1107 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
1108 | err = -ENOMEM; |
1109 | goto out_free; | |
1110 | } | |
1111 | ||
eda0d04a SD |
1112 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
1113 | pr_info("Distributor has %sRange Selector support\n", | |
1114 | gic_data.has_rss ? "" : "no "); | |
1115 | ||
50528752 MZ |
1116 | if (typer & GICD_TYPER_MBIS) { |
1117 | err = mbi_init(handle, gic_data.domain); | |
1118 | if (err) | |
1119 | pr_err("Failed to initialize MBIs\n"); | |
1120 | } | |
1121 | ||
021f6537 MZ |
1122 | set_handle_irq(gic_handle_irq); |
1123 | ||
0edc23ea MZ |
1124 | gic_update_vlpi_properties(); |
1125 | ||
db40f0a7 TN |
1126 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
1127 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
da33f31d | 1128 | |
021f6537 MZ |
1129 | gic_smp_init(); |
1130 | gic_dist_init(); | |
1131 | gic_cpu_init(); | |
3708d52f | 1132 | gic_cpu_pm_init(); |
021f6537 MZ |
1133 | |
1134 | return 0; | |
1135 | ||
1136 | out_free: | |
1137 | if (gic_data.domain) | |
1138 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 1139 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
1140 | return err; |
1141 | } | |
1142 | ||
1143 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
1144 | { | |
1145 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1146 | ||
1147 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
1148 | return -ENODEV; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
e3825ba1 | 1153 | /* Create all possible partitions at boot time */ |
7beaa24b | 1154 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
1155 | { |
1156 | struct device_node *parts_node, *child_part; | |
1157 | int part_idx = 0, i; | |
1158 | int nr_parts; | |
1159 | struct partition_affinity *parts; | |
1160 | ||
00ee9a1c | 1161 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
1162 | if (!parts_node) |
1163 | return; | |
1164 | ||
1165 | nr_parts = of_get_child_count(parts_node); | |
1166 | ||
1167 | if (!nr_parts) | |
00ee9a1c | 1168 | goto out_put_node; |
e3825ba1 | 1169 | |
6396bb22 | 1170 | parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); |
e3825ba1 | 1171 | if (WARN_ON(!parts)) |
00ee9a1c | 1172 | goto out_put_node; |
e3825ba1 MZ |
1173 | |
1174 | for_each_child_of_node(parts_node, child_part) { | |
1175 | struct partition_affinity *part; | |
1176 | int n; | |
1177 | ||
1178 | part = &parts[part_idx]; | |
1179 | ||
1180 | part->partition_id = of_node_to_fwnode(child_part); | |
1181 | ||
1182 | pr_info("GIC: PPI partition %s[%d] { ", | |
1183 | child_part->name, part_idx); | |
1184 | ||
1185 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1186 | sizeof(u32)); | |
1187 | WARN_ON(n <= 0); | |
1188 | ||
1189 | for (i = 0; i < n; i++) { | |
1190 | int err, cpu; | |
1191 | u32 cpu_phandle; | |
1192 | struct device_node *cpu_node; | |
1193 | ||
1194 | err = of_property_read_u32_index(child_part, "affinity", | |
1195 | i, &cpu_phandle); | |
1196 | if (WARN_ON(err)) | |
1197 | continue; | |
1198 | ||
1199 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1200 | if (WARN_ON(!cpu_node)) | |
1201 | continue; | |
1202 | ||
c08ec7da SP |
1203 | cpu = of_cpu_node_to_id(cpu_node); |
1204 | if (WARN_ON(cpu < 0)) | |
e3825ba1 MZ |
1205 | continue; |
1206 | ||
e81f54c6 | 1207 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
1208 | |
1209 | cpumask_set_cpu(cpu, &part->mask); | |
1210 | } | |
1211 | ||
1212 | pr_cont("}\n"); | |
1213 | part_idx++; | |
1214 | } | |
1215 | ||
1216 | for (i = 0; i < 16; i++) { | |
1217 | unsigned int irq; | |
1218 | struct partition_desc *desc; | |
1219 | struct irq_fwspec ppi_fwspec = { | |
1220 | .fwnode = gic_data.fwnode, | |
1221 | .param_count = 3, | |
1222 | .param = { | |
65da7d19 | 1223 | [0] = GIC_IRQ_TYPE_PARTITION, |
e3825ba1 MZ |
1224 | [1] = i, |
1225 | [2] = IRQ_TYPE_NONE, | |
1226 | }, | |
1227 | }; | |
1228 | ||
1229 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1230 | if (WARN_ON(!irq)) | |
1231 | continue; | |
1232 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1233 | irq, &partition_domain_ops); | |
1234 | if (WARN_ON(!desc)) | |
1235 | continue; | |
1236 | ||
1237 | gic_data.ppi_descs[i] = desc; | |
1238 | } | |
00ee9a1c JH |
1239 | |
1240 | out_put_node: | |
1241 | of_node_put(parts_node); | |
e3825ba1 MZ |
1242 | } |
1243 | ||
1839e576 JG |
1244 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1245 | { | |
1246 | int ret; | |
1247 | struct resource r; | |
1248 | u32 gicv_idx; | |
1249 | ||
1250 | gic_v3_kvm_info.type = GIC_V3; | |
1251 | ||
1252 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1253 | if (!gic_v3_kvm_info.maint_irq) | |
1254 | return; | |
1255 | ||
1256 | if (of_property_read_u32(node, "#redistributor-regions", | |
1257 | &gicv_idx)) | |
1258 | gicv_idx = 1; | |
1259 | ||
1260 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
1261 | ret = of_address_to_resource(node, gicv_idx, &r); | |
1262 | if (!ret) | |
1263 | gic_v3_kvm_info.vcpu = r; | |
1264 | ||
4bdf5025 | 1265 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1266 | gic_set_kvm_info(&gic_v3_kvm_info); |
1267 | } | |
1268 | ||
db57d746 TN |
1269 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1270 | { | |
1271 | void __iomem *dist_base; | |
1272 | struct redist_region *rdist_regs; | |
1273 | u64 redist_stride; | |
1274 | u32 nr_redist_regions; | |
1275 | int err, i; | |
1276 | ||
1277 | dist_base = of_iomap(node, 0); | |
1278 | if (!dist_base) { | |
e81f54c6 | 1279 | pr_err("%pOF: unable to map gic dist registers\n", node); |
db57d746 TN |
1280 | return -ENXIO; |
1281 | } | |
1282 | ||
1283 | err = gic_validate_dist_version(dist_base); | |
1284 | if (err) { | |
e81f54c6 | 1285 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
1286 | goto out_unmap_dist; |
1287 | } | |
1288 | ||
1289 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1290 | nr_redist_regions = 1; | |
1291 | ||
6396bb22 KC |
1292 | rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), |
1293 | GFP_KERNEL); | |
db57d746 TN |
1294 | if (!rdist_regs) { |
1295 | err = -ENOMEM; | |
1296 | goto out_unmap_dist; | |
1297 | } | |
1298 | ||
1299 | for (i = 0; i < nr_redist_regions; i++) { | |
1300 | struct resource res; | |
1301 | int ret; | |
1302 | ||
1303 | ret = of_address_to_resource(node, 1 + i, &res); | |
1304 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1305 | if (ret || !rdist_regs[i].redist_base) { | |
e81f54c6 | 1306 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
1307 | err = -ENODEV; |
1308 | goto out_unmap_rdist; | |
1309 | } | |
1310 | rdist_regs[i].phys_base = res.start; | |
1311 | } | |
1312 | ||
1313 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1314 | redist_stride = 0; | |
1315 | ||
1316 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
1317 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1318 | if (err) |
1319 | goto out_unmap_rdist; | |
1320 | ||
1321 | gic_populate_ppi_partitions(node); | |
d33a3c8c | 1322 | |
d01d3274 | 1323 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1324 | gic_of_setup_kvm_info(node); |
e3825ba1 | 1325 | return 0; |
db57d746 | 1326 | |
021f6537 | 1327 | out_unmap_rdist: |
f5c1434c MZ |
1328 | for (i = 0; i < nr_redist_regions; i++) |
1329 | if (rdist_regs[i].redist_base) | |
1330 | iounmap(rdist_regs[i].redist_base); | |
1331 | kfree(rdist_regs); | |
021f6537 MZ |
1332 | out_unmap_dist: |
1333 | iounmap(dist_base); | |
1334 | return err; | |
1335 | } | |
1336 | ||
1337 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1338 | |
1339 | #ifdef CONFIG_ACPI | |
611f039f JG |
1340 | static struct |
1341 | { | |
1342 | void __iomem *dist_base; | |
1343 | struct redist_region *redist_regs; | |
1344 | u32 nr_redist_regions; | |
1345 | bool single_redist; | |
1839e576 JG |
1346 | u32 maint_irq; |
1347 | int maint_irq_mode; | |
1348 | phys_addr_t vcpu_base; | |
611f039f | 1349 | } acpi_data __initdata; |
b70fb7af TN |
1350 | |
1351 | static void __init | |
1352 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1353 | { | |
1354 | static int count = 0; | |
1355 | ||
611f039f JG |
1356 | acpi_data.redist_regs[count].phys_base = phys_base; |
1357 | acpi_data.redist_regs[count].redist_base = redist_base; | |
1358 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
1359 | count++; |
1360 | } | |
ffa7d616 TN |
1361 | |
1362 | static int __init | |
1363 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
1364 | const unsigned long end) | |
1365 | { | |
1366 | struct acpi_madt_generic_redistributor *redist = | |
1367 | (struct acpi_madt_generic_redistributor *)header; | |
1368 | void __iomem *redist_base; | |
ffa7d616 TN |
1369 | |
1370 | redist_base = ioremap(redist->base_address, redist->length); | |
1371 | if (!redist_base) { | |
1372 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1373 | return -ENOMEM; | |
1374 | } | |
1375 | ||
b70fb7af | 1376 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1377 | return 0; |
1378 | } | |
1379 | ||
b70fb7af TN |
1380 | static int __init |
1381 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1382 | const unsigned long end) | |
1383 | { | |
1384 | struct acpi_madt_generic_interrupt *gicc = | |
1385 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 1386 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
1387 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
1388 | void __iomem *redist_base; | |
1389 | ||
ebe2f871 SD |
1390 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
1391 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1392 | return 0; | |
1393 | ||
b70fb7af TN |
1394 | redist_base = ioremap(gicc->gicr_base_address, size); |
1395 | if (!redist_base) | |
1396 | return -ENOMEM; | |
1397 | ||
1398 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | static int __init gic_acpi_collect_gicr_base(void) | |
1403 | { | |
1404 | acpi_tbl_entry_handler redist_parser; | |
1405 | enum acpi_madt_type type; | |
1406 | ||
611f039f | 1407 | if (acpi_data.single_redist) { |
b70fb7af TN |
1408 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
1409 | redist_parser = gic_acpi_parse_madt_gicc; | |
1410 | } else { | |
1411 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1412 | redist_parser = gic_acpi_parse_madt_redist; | |
1413 | } | |
1414 | ||
1415 | /* Collect redistributor base addresses in GICR entries */ | |
1416 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1417 | return 0; | |
1418 | ||
1419 | pr_info("No valid GICR entries exist\n"); | |
1420 | return -ENODEV; | |
1421 | } | |
1422 | ||
ffa7d616 TN |
1423 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1424 | const unsigned long end) | |
1425 | { | |
1426 | /* Subtable presence means that redist exists, that's it */ | |
1427 | return 0; | |
1428 | } | |
1429 | ||
b70fb7af TN |
1430 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1431 | const unsigned long end) | |
1432 | { | |
1433 | struct acpi_madt_generic_interrupt *gicc = | |
1434 | (struct acpi_madt_generic_interrupt *)header; | |
1435 | ||
1436 | /* | |
1437 | * If GICC is enabled and has valid gicr base address, then it means | |
1438 | * GICR base is presented via GICC | |
1439 | */ | |
1440 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1441 | return 0; | |
1442 | ||
ebe2f871 SD |
1443 | /* |
1444 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
1445 | * should not treat as errors, skip the entry instead of probe fail. | |
1446 | */ | |
1447 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1448 | return 0; | |
1449 | ||
b70fb7af TN |
1450 | return -ENODEV; |
1451 | } | |
1452 | ||
1453 | static int __init gic_acpi_count_gicr_regions(void) | |
1454 | { | |
1455 | int count; | |
1456 | ||
1457 | /* | |
1458 | * Count how many redistributor regions we have. It is not allowed | |
1459 | * to mix redistributor description, GICR and GICC subtables have to be | |
1460 | * mutually exclusive. | |
1461 | */ | |
1462 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1463 | gic_acpi_match_gicr, 0); | |
1464 | if (count > 0) { | |
611f039f | 1465 | acpi_data.single_redist = false; |
b70fb7af TN |
1466 | return count; |
1467 | } | |
1468 | ||
1469 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1470 | gic_acpi_match_gicc, 0); | |
1471 | if (count > 0) | |
611f039f | 1472 | acpi_data.single_redist = true; |
b70fb7af TN |
1473 | |
1474 | return count; | |
1475 | } | |
1476 | ||
ffa7d616 TN |
1477 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1478 | struct acpi_probe_entry *ape) | |
1479 | { | |
1480 | struct acpi_madt_generic_distributor *dist; | |
1481 | int count; | |
1482 | ||
1483 | dist = (struct acpi_madt_generic_distributor *)header; | |
1484 | if (dist->version != ape->driver_data) | |
1485 | return false; | |
1486 | ||
1487 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1488 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1489 | if (count <= 0) |
1490 | return false; | |
1491 | ||
611f039f | 1492 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
1493 | return true; |
1494 | } | |
1495 | ||
1839e576 JG |
1496 | static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, |
1497 | const unsigned long end) | |
1498 | { | |
1499 | struct acpi_madt_generic_interrupt *gicc = | |
1500 | (struct acpi_madt_generic_interrupt *)header; | |
1501 | int maint_irq_mode; | |
1502 | static int first_madt = true; | |
1503 | ||
1504 | /* Skip unusable CPUs */ | |
1505 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1506 | return 0; | |
1507 | ||
1508 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1509 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1510 | ||
1511 | if (first_madt) { | |
1512 | first_madt = false; | |
1513 | ||
1514 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
1515 | acpi_data.maint_irq_mode = maint_irq_mode; | |
1516 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | /* | |
1522 | * The maintenance interrupt and GICV should be the same for every CPU | |
1523 | */ | |
1524 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
1525 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
1526 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
1527 | return -EINVAL; | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static bool __init gic_acpi_collect_virt_info(void) | |
1533 | { | |
1534 | int count; | |
1535 | ||
1536 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1537 | gic_acpi_parse_virt_madt_gicc, 0); | |
1538 | ||
1539 | return (count > 0); | |
1540 | } | |
1541 | ||
ffa7d616 | 1542 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
1543 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1544 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1545 | ||
1546 | static void __init gic_acpi_setup_kvm_info(void) | |
1547 | { | |
1548 | int irq; | |
1549 | ||
1550 | if (!gic_acpi_collect_virt_info()) { | |
1551 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
1552 | return; | |
1553 | } | |
1554 | ||
1555 | gic_v3_kvm_info.type = GIC_V3; | |
1556 | ||
1557 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1558 | acpi_data.maint_irq_mode, | |
1559 | ACPI_ACTIVE_HIGH); | |
1560 | if (irq <= 0) | |
1561 | return; | |
1562 | ||
1563 | gic_v3_kvm_info.maint_irq = irq; | |
1564 | ||
1565 | if (acpi_data.vcpu_base) { | |
1566 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
1567 | ||
1568 | vcpu->flags = IORESOURCE_MEM; | |
1569 | vcpu->start = acpi_data.vcpu_base; | |
1570 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1571 | } | |
1572 | ||
4bdf5025 | 1573 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1574 | gic_set_kvm_info(&gic_v3_kvm_info); |
1575 | } | |
ffa7d616 TN |
1576 | |
1577 | static int __init | |
1578 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1579 | { | |
1580 | struct acpi_madt_generic_distributor *dist; | |
1581 | struct fwnode_handle *domain_handle; | |
611f039f | 1582 | size_t size; |
b70fb7af | 1583 | int i, err; |
ffa7d616 TN |
1584 | |
1585 | /* Get distributor base address */ | |
1586 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
1587 | acpi_data.dist_base = ioremap(dist->base_address, |
1588 | ACPI_GICV3_DIST_MEM_SIZE); | |
1589 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
1590 | pr_err("Unable to map GICD registers\n"); |
1591 | return -ENOMEM; | |
1592 | } | |
1593 | ||
611f039f | 1594 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 1595 | if (err) { |
71192a68 | 1596 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 1597 | acpi_data.dist_base); |
ffa7d616 TN |
1598 | goto out_dist_unmap; |
1599 | } | |
1600 | ||
611f039f JG |
1601 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
1602 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
1603 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
1604 | err = -ENOMEM; |
1605 | goto out_dist_unmap; | |
1606 | } | |
1607 | ||
b70fb7af TN |
1608 | err = gic_acpi_collect_gicr_base(); |
1609 | if (err) | |
ffa7d616 | 1610 | goto out_redist_unmap; |
ffa7d616 | 1611 | |
611f039f | 1612 | domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); |
ffa7d616 TN |
1613 | if (!domain_handle) { |
1614 | err = -ENOMEM; | |
1615 | goto out_redist_unmap; | |
1616 | } | |
1617 | ||
611f039f JG |
1618 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
1619 | acpi_data.nr_redist_regions, 0, domain_handle); | |
ffa7d616 TN |
1620 | if (err) |
1621 | goto out_fwhandle_free; | |
1622 | ||
1623 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
d33a3c8c | 1624 | |
d01d3274 | 1625 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1626 | gic_acpi_setup_kvm_info(); |
1839e576 | 1627 | |
ffa7d616 TN |
1628 | return 0; |
1629 | ||
1630 | out_fwhandle_free: | |
1631 | irq_domain_free_fwnode(domain_handle); | |
1632 | out_redist_unmap: | |
611f039f JG |
1633 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
1634 | if (acpi_data.redist_regs[i].redist_base) | |
1635 | iounmap(acpi_data.redist_regs[i].redist_base); | |
1636 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 1637 | out_dist_unmap: |
611f039f | 1638 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
1639 | return err; |
1640 | } | |
1641 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1642 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1643 | gic_acpi_init); | |
1644 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1645 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1646 | gic_acpi_init); | |
1647 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1648 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1649 | gic_acpi_init); | |
1650 | #endif |