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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
021f6537 | 2 | /* |
0edc23ea | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
021f6537 MZ |
5 | */ |
6 | ||
68628bb8 JG |
7 | #define pr_fmt(fmt) "GICv3: " fmt |
8 | ||
ffa7d616 | 9 | #include <linux/acpi.h> |
021f6537 | 10 | #include <linux/cpu.h> |
3708d52f | 11 | #include <linux/cpu_pm.h> |
021f6537 MZ |
12 | #include <linux/delay.h> |
13 | #include <linux/interrupt.h> | |
ffa7d616 | 14 | #include <linux/irqdomain.h> |
5e279739 | 15 | #include <linux/kstrtox.h> |
021f6537 MZ |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/percpu.h> | |
101b35f7 | 20 | #include <linux/refcount.h> |
021f6537 MZ |
21 | #include <linux/slab.h> |
22 | ||
41a83e06 | 23 | #include <linux/irqchip.h> |
1839e576 | 24 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 26 | #include <linux/irqchip/irq-partition-percpu.h> |
35727af2 SD |
27 | #include <linux/bitfield.h> |
28 | #include <linux/bits.h> | |
29 | #include <linux/arm-smccc.h> | |
021f6537 MZ |
30 | |
31 | #include <asm/cputype.h> | |
32 | #include <asm/exception.h> | |
33 | #include <asm/smp_plat.h> | |
0b6a3da9 | 34 | #include <asm/virt.h> |
021f6537 MZ |
35 | |
36 | #include "irq-gic-common.h" | |
021f6537 | 37 | |
f32c9266 JT |
38 | #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) |
39 | ||
9c8114c2 | 40 | #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) |
d01fd161 | 41 | #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) |
44bd78dd | 42 | #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) |
9c8114c2 | 43 | |
64b499d8 MZ |
44 | #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) |
45 | ||
f5c1434c MZ |
46 | struct redist_region { |
47 | void __iomem *redist_base; | |
48 | phys_addr_t phys_base; | |
b70fb7af | 49 | bool single_redist; |
f5c1434c MZ |
50 | }; |
51 | ||
021f6537 | 52 | struct gic_chip_data { |
e3825ba1 | 53 | struct fwnode_handle *fwnode; |
35727af2 | 54 | phys_addr_t dist_phys_base; |
021f6537 | 55 | void __iomem *dist_base; |
f5c1434c MZ |
56 | struct redist_region *redist_regions; |
57 | struct rdists rdists; | |
021f6537 MZ |
58 | struct irq_domain *domain; |
59 | u64 redist_stride; | |
f5c1434c | 60 | u32 nr_redist_regions; |
9c8114c2 | 61 | u64 flags; |
eda0d04a | 62 | bool has_rss; |
1a60e1e6 | 63 | unsigned int ppi_nr; |
52085d3f | 64 | struct partition_desc **ppi_descs; |
021f6537 MZ |
65 | }; |
66 | ||
35727af2 SD |
67 | #define T241_CHIPS_MAX 4 |
68 | static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly; | |
69 | static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum); | |
70 | ||
021f6537 | 71 | static struct gic_chip_data gic_data __read_mostly; |
d01d3274 | 72 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
021f6537 | 73 | |
211bddd2 | 74 | #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) |
c107d613 | 75 | #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) |
211bddd2 MZ |
76 | #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) |
77 | ||
d98d0a99 JT |
78 | /* |
79 | * The behaviours of RPR and PMR registers differ depending on the value of | |
80 | * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the | |
81 | * distributor and redistributors depends on whether security is enabled in the | |
82 | * GIC. | |
83 | * | |
84 | * When security is enabled, non-secure priority values from the (re)distributor | |
85 | * are presented to the GIC CPUIF as follow: | |
86 | * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; | |
87 | * | |
d4034114 | 88 | * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure |
d98d0a99 | 89 | * EL1 are subject to a similar operation thus matching the priorities presented |
33678059 | 90 | * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, |
d4034114 | 91 | * these values are unchanged by the GIC. |
d98d0a99 JT |
92 | * |
93 | * see GICv3/GICv4 Architecture Specification (IHI0069D): | |
94 | * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt | |
95 | * priorities. | |
96 | * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 | |
97 | * interrupt. | |
d98d0a99 JT |
98 | */ |
99 | static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); | |
100 | ||
33678059 AE |
101 | DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); |
102 | EXPORT_SYMBOL(gic_nonsecure_priorities); | |
103 | ||
8d474dea CYT |
104 | /* |
105 | * When the Non-secure world has access to group 0 interrupts (as a | |
106 | * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will | |
107 | * return the Distributor's view of the interrupt priority. | |
108 | * | |
109 | * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority | |
110 | * written by software is moved to the Non-secure range by the Distributor. | |
111 | * | |
112 | * If both are true (which is when gic_nonsecure_priorities gets enabled), | |
113 | * we need to shift down the priority programmed by software to match it | |
114 | * against the value returned by ICC_RPR_EL1. | |
115 | */ | |
116 | #define GICD_INT_RPR_PRI(priority) \ | |
117 | ({ \ | |
118 | u32 __priority = (priority); \ | |
119 | if (static_branch_unlikely(&gic_nonsecure_priorities)) \ | |
120 | __priority = 0x80 | (__priority >> 1); \ | |
121 | \ | |
122 | __priority; \ | |
123 | }) | |
124 | ||
101b35f7 | 125 | /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ |
81a43273 | 126 | static refcount_t *ppi_nmi_refs; |
101b35f7 | 127 | |
0e5cb777 | 128 | static struct gic_kvm_info gic_v3_kvm_info __initdata; |
eda0d04a | 129 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 130 | |
eda0d04a | 131 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
132 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
133 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
134 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
135 | ||
136 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
137 | #define DEFAULT_PMR_VALUE 0xf0 | |
138 | ||
e91b036e | 139 | enum gic_intid_range { |
70a29c32 | 140 | SGI_RANGE, |
e91b036e MZ |
141 | PPI_RANGE, |
142 | SPI_RANGE, | |
5f51f803 | 143 | EPPI_RANGE, |
211bddd2 | 144 | ESPI_RANGE, |
e91b036e MZ |
145 | LPI_RANGE, |
146 | __INVALID_RANGE__ | |
147 | }; | |
148 | ||
149 | static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) | |
150 | { | |
151 | switch (hwirq) { | |
70a29c32 MZ |
152 | case 0 ... 15: |
153 | return SGI_RANGE; | |
e91b036e MZ |
154 | case 16 ... 31: |
155 | return PPI_RANGE; | |
156 | case 32 ... 1019: | |
157 | return SPI_RANGE; | |
5f51f803 MZ |
158 | case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): |
159 | return EPPI_RANGE; | |
211bddd2 MZ |
160 | case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): |
161 | return ESPI_RANGE; | |
e91b036e MZ |
162 | case 8192 ... GENMASK(23, 0): |
163 | return LPI_RANGE; | |
164 | default: | |
165 | return __INVALID_RANGE__; | |
166 | } | |
167 | } | |
168 | ||
169 | static enum gic_intid_range get_intid_range(struct irq_data *d) | |
170 | { | |
171 | return __get_intid_range(d->hwirq); | |
172 | } | |
173 | ||
021f6537 MZ |
174 | static inline unsigned int gic_irq(struct irq_data *d) |
175 | { | |
176 | return d->hwirq; | |
177 | } | |
178 | ||
70a29c32 | 179 | static inline bool gic_irq_in_rdist(struct irq_data *d) |
021f6537 | 180 | { |
70a29c32 MZ |
181 | switch (get_intid_range(d)) { |
182 | case SGI_RANGE: | |
183 | case PPI_RANGE: | |
184 | case EPPI_RANGE: | |
185 | return true; | |
186 | default: | |
187 | return false; | |
188 | } | |
021f6537 MZ |
189 | } |
190 | ||
35727af2 SD |
191 | static inline void __iomem *gic_dist_base_alias(struct irq_data *d) |
192 | { | |
193 | if (static_branch_unlikely(&gic_nvidia_t241_erratum)) { | |
194 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
195 | u32 chip; | |
196 | ||
197 | /* | |
198 | * For the erratum T241-FABRIC-4, read accesses to GICD_In{E} | |
199 | * registers are directed to the chip that owns the SPI. The | |
200 | * the alias region can also be used for writes to the | |
201 | * GICD_In{E} except GICD_ICENABLERn. Each chip has support | |
202 | * for 320 {E}SPIs. Mappings for all 4 chips: | |
203 | * Chip0 = 32-351 | |
204 | * Chip1 = 352-671 | |
205 | * Chip2 = 672-991 | |
206 | * Chip3 = 4096-4415 | |
207 | */ | |
208 | switch (__get_intid_range(hwirq)) { | |
209 | case SPI_RANGE: | |
210 | chip = (hwirq - 32) / 320; | |
211 | break; | |
212 | case ESPI_RANGE: | |
213 | chip = 3; | |
214 | break; | |
215 | default: | |
216 | unreachable(); | |
217 | } | |
218 | return t241_dist_base_alias[chip]; | |
219 | } | |
220 | ||
221 | return gic_data.dist_base; | |
222 | } | |
223 | ||
021f6537 MZ |
224 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
225 | { | |
e91b036e | 226 | switch (get_intid_range(d)) { |
70a29c32 | 227 | case SGI_RANGE: |
e91b036e | 228 | case PPI_RANGE: |
5f51f803 | 229 | case EPPI_RANGE: |
e91b036e | 230 | /* SGI+PPI -> SGI_base for this CPU */ |
021f6537 MZ |
231 | return gic_data_rdist_sgi_base(); |
232 | ||
e91b036e | 233 | case SPI_RANGE: |
211bddd2 | 234 | case ESPI_RANGE: |
e91b036e | 235 | /* SPI -> dist_base */ |
021f6537 MZ |
236 | return gic_data.dist_base; |
237 | ||
e91b036e MZ |
238 | default: |
239 | return NULL; | |
240 | } | |
021f6537 MZ |
241 | } |
242 | ||
0df66645 | 243 | static void gic_do_wait_for_rwp(void __iomem *base, u32 bit) |
021f6537 MZ |
244 | { |
245 | u32 count = 1000000; /* 1s! */ | |
246 | ||
0df66645 | 247 | while (readl_relaxed(base + GICD_CTLR) & bit) { |
021f6537 MZ |
248 | count--; |
249 | if (!count) { | |
250 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
251 | return; | |
252 | } | |
253 | cpu_relax(); | |
254 | udelay(1); | |
2c542426 | 255 | } |
021f6537 MZ |
256 | } |
257 | ||
258 | /* Wait for completion of a distributor change */ | |
259 | static void gic_dist_wait_for_rwp(void) | |
260 | { | |
0df66645 | 261 | gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP); |
021f6537 MZ |
262 | } |
263 | ||
264 | /* Wait for completion of a redistributor change */ | |
265 | static void gic_redist_wait_for_rwp(void) | |
266 | { | |
0df66645 | 267 | gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP); |
021f6537 MZ |
268 | } |
269 | ||
7936e914 | 270 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
271 | |
272 | static u64 __maybe_unused gic_read_iar(void) | |
273 | { | |
a4023f68 | 274 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
275 | return gic_read_iar_cavium_thunderx(); |
276 | else | |
277 | return gic_read_iar_common(); | |
278 | } | |
7936e914 | 279 | #endif |
021f6537 | 280 | |
a2c22510 | 281 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
282 | { |
283 | void __iomem *rbase; | |
284 | u32 count = 1000000; /* 1s! */ | |
285 | u32 val; | |
286 | ||
9c8114c2 SK |
287 | if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) |
288 | return; | |
289 | ||
021f6537 MZ |
290 | rbase = gic_data_rdist_rd_base(); |
291 | ||
021f6537 | 292 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
293 | if (enable) |
294 | /* Wake up this CPU redistributor */ | |
295 | val &= ~GICR_WAKER_ProcessorSleep; | |
296 | else | |
297 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
298 | writel_relaxed(val, rbase + GICR_WAKER); |
299 | ||
a2c22510 SH |
300 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
301 | val = readl_relaxed(rbase + GICR_WAKER); | |
302 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
303 | return; /* No PM support in this redistributor */ | |
304 | } | |
305 | ||
d102eb5c | 306 | while (--count) { |
a2c22510 | 307 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 308 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 309 | break; |
021f6537 MZ |
310 | cpu_relax(); |
311 | udelay(1); | |
2c542426 | 312 | } |
a2c22510 SH |
313 | if (!count) |
314 | pr_err_ratelimited("redistributor failed to %s...\n", | |
315 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
316 | } |
317 | ||
318 | /* | |
319 | * Routines to disable, enable, EOI and route interrupts | |
320 | */ | |
e91b036e MZ |
321 | static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) |
322 | { | |
323 | switch (get_intid_range(d)) { | |
70a29c32 | 324 | case SGI_RANGE: |
e91b036e MZ |
325 | case PPI_RANGE: |
326 | case SPI_RANGE: | |
327 | *index = d->hwirq; | |
328 | return offset; | |
5f51f803 MZ |
329 | case EPPI_RANGE: |
330 | /* | |
331 | * Contrary to the ESPI range, the EPPI range is contiguous | |
332 | * to the PPI range in the registers, so let's adjust the | |
333 | * displacement accordingly. Consistency is overrated. | |
334 | */ | |
335 | *index = d->hwirq - EPPI_BASE_INTID + 32; | |
336 | return offset; | |
211bddd2 MZ |
337 | case ESPI_RANGE: |
338 | *index = d->hwirq - ESPI_BASE_INTID; | |
339 | switch (offset) { | |
340 | case GICD_ISENABLER: | |
341 | return GICD_ISENABLERnE; | |
342 | case GICD_ICENABLER: | |
343 | return GICD_ICENABLERnE; | |
344 | case GICD_ISPENDR: | |
345 | return GICD_ISPENDRnE; | |
346 | case GICD_ICPENDR: | |
347 | return GICD_ICPENDRnE; | |
348 | case GICD_ISACTIVER: | |
349 | return GICD_ISACTIVERnE; | |
350 | case GICD_ICACTIVER: | |
351 | return GICD_ICACTIVERnE; | |
352 | case GICD_IPRIORITYR: | |
353 | return GICD_IPRIORITYRnE; | |
354 | case GICD_ICFGR: | |
355 | return GICD_ICFGRnE; | |
356 | case GICD_IROUTER: | |
357 | return GICD_IROUTERnE; | |
358 | default: | |
359 | break; | |
360 | } | |
361 | break; | |
e91b036e MZ |
362 | default: |
363 | break; | |
364 | } | |
365 | ||
366 | WARN_ON(1); | |
367 | *index = d->hwirq; | |
368 | return offset; | |
369 | } | |
370 | ||
b594c6e2 MZ |
371 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
372 | { | |
b594c6e2 | 373 | void __iomem *base; |
e91b036e MZ |
374 | u32 index, mask; |
375 | ||
376 | offset = convert_offset_index(d, offset, &index); | |
377 | mask = 1 << (index % 32); | |
b594c6e2 MZ |
378 | |
379 | if (gic_irq_in_rdist(d)) | |
380 | base = gic_data_rdist_sgi_base(); | |
381 | else | |
35727af2 | 382 | base = gic_dist_base_alias(d); |
b594c6e2 | 383 | |
e91b036e | 384 | return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); |
b594c6e2 MZ |
385 | } |
386 | ||
021f6537 MZ |
387 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
388 | { | |
021f6537 | 389 | void __iomem *base; |
e91b036e MZ |
390 | u32 index, mask; |
391 | ||
392 | offset = convert_offset_index(d, offset, &index); | |
393 | mask = 1 << (index % 32); | |
021f6537 | 394 | |
63f13483 | 395 | if (gic_irq_in_rdist(d)) |
021f6537 | 396 | base = gic_data_rdist_sgi_base(); |
63f13483 | 397 | else |
021f6537 | 398 | base = gic_data.dist_base; |
021f6537 | 399 | |
e91b036e | 400 | writel_relaxed(mask, base + offset + (index / 32) * 4); |
021f6537 MZ |
401 | } |
402 | ||
021f6537 MZ |
403 | static void gic_mask_irq(struct irq_data *d) |
404 | { | |
405 | gic_poke_irq(d, GICD_ICENABLER); | |
63f13483 MZ |
406 | if (gic_irq_in_rdist(d)) |
407 | gic_redist_wait_for_rwp(); | |
408 | else | |
409 | gic_dist_wait_for_rwp(); | |
021f6537 MZ |
410 | } |
411 | ||
0b6a3da9 MZ |
412 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
413 | { | |
414 | gic_mask_irq(d); | |
530bf353 MZ |
415 | /* |
416 | * When masking a forwarded interrupt, make sure it is | |
417 | * deactivated as well. | |
418 | * | |
419 | * This ensures that an interrupt that is getting | |
420 | * disabled/masked will not get "stuck", because there is | |
421 | * noone to deactivate it (guest is being terminated). | |
422 | */ | |
4df7f54d | 423 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 424 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
425 | } |
426 | ||
021f6537 MZ |
427 | static void gic_unmask_irq(struct irq_data *d) |
428 | { | |
429 | gic_poke_irq(d, GICD_ISENABLER); | |
430 | } | |
431 | ||
d98d0a99 JT |
432 | static inline bool gic_supports_nmi(void) |
433 | { | |
434 | return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && | |
435 | static_branch_likely(&supports_pseudo_nmis); | |
436 | } | |
437 | ||
b594c6e2 MZ |
438 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
439 | enum irqchip_irq_state which, bool val) | |
440 | { | |
441 | u32 reg; | |
442 | ||
64b499d8 | 443 | if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ |
b594c6e2 MZ |
444 | return -EINVAL; |
445 | ||
446 | switch (which) { | |
447 | case IRQCHIP_STATE_PENDING: | |
448 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
449 | break; | |
450 | ||
451 | case IRQCHIP_STATE_ACTIVE: | |
452 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
453 | break; | |
454 | ||
455 | case IRQCHIP_STATE_MASKED: | |
63f13483 MZ |
456 | if (val) { |
457 | gic_mask_irq(d); | |
458 | return 0; | |
459 | } | |
460 | reg = GICD_ISENABLER; | |
b594c6e2 MZ |
461 | break; |
462 | ||
463 | default: | |
464 | return -EINVAL; | |
465 | } | |
466 | ||
467 | gic_poke_irq(d, reg); | |
468 | return 0; | |
469 | } | |
470 | ||
471 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
472 | enum irqchip_irq_state which, bool *val) | |
473 | { | |
211bddd2 | 474 | if (d->hwirq >= 8192) /* PPI/SPI only */ |
b594c6e2 MZ |
475 | return -EINVAL; |
476 | ||
477 | switch (which) { | |
478 | case IRQCHIP_STATE_PENDING: | |
479 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
480 | break; | |
481 | ||
482 | case IRQCHIP_STATE_ACTIVE: | |
483 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
484 | break; | |
485 | ||
486 | case IRQCHIP_STATE_MASKED: | |
487 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
488 | break; | |
489 | ||
490 | default: | |
491 | return -EINVAL; | |
492 | } | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
101b35f7 JT |
497 | static void gic_irq_set_prio(struct irq_data *d, u8 prio) |
498 | { | |
499 | void __iomem *base = gic_dist_base(d); | |
e91b036e | 500 | u32 offset, index; |
101b35f7 | 501 | |
e91b036e MZ |
502 | offset = convert_offset_index(d, GICD_IPRIORITYR, &index); |
503 | ||
504 | writeb_relaxed(prio, base + offset + index); | |
101b35f7 JT |
505 | } |
506 | ||
bfa80ee9 | 507 | static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) |
81a43273 | 508 | { |
bfa80ee9 | 509 | switch (__get_intid_range(hwirq)) { |
81a43273 | 510 | case PPI_RANGE: |
bfa80ee9 | 511 | return hwirq - 16; |
5f51f803 | 512 | case EPPI_RANGE: |
bfa80ee9 | 513 | return hwirq - EPPI_BASE_INTID + 16; |
81a43273 MZ |
514 | default: |
515 | unreachable(); | |
516 | } | |
517 | } | |
518 | ||
bfa80ee9 JM |
519 | static u32 gic_get_ppi_index(struct irq_data *d) |
520 | { | |
521 | return __gic_get_ppi_index(d->hwirq); | |
522 | } | |
523 | ||
101b35f7 JT |
524 | static int gic_irq_nmi_setup(struct irq_data *d) |
525 | { | |
526 | struct irq_desc *desc = irq_to_desc(d->irq); | |
527 | ||
528 | if (!gic_supports_nmi()) | |
529 | return -EINVAL; | |
530 | ||
531 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
532 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | /* | |
537 | * A secondary irq_chip should be in charge of LPI request, | |
538 | * it should not be possible to get there | |
539 | */ | |
540 | if (WARN_ON(gic_irq(d) >= 8192)) | |
541 | return -EINVAL; | |
542 | ||
543 | /* desc lock should already be held */ | |
81a43273 MZ |
544 | if (gic_irq_in_rdist(d)) { |
545 | u32 idx = gic_get_ppi_index(d); | |
546 | ||
101b35f7 | 547 | /* Setting up PPI as NMI, only switch handler for first NMI */ |
81a43273 MZ |
548 | if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { |
549 | refcount_set(&ppi_nmi_refs[idx], 1); | |
101b35f7 JT |
550 | desc->handle_irq = handle_percpu_devid_fasteoi_nmi; |
551 | } | |
552 | } else { | |
553 | desc->handle_irq = handle_fasteoi_nmi; | |
554 | } | |
555 | ||
556 | gic_irq_set_prio(d, GICD_INT_NMI_PRI); | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | static void gic_irq_nmi_teardown(struct irq_data *d) | |
562 | { | |
563 | struct irq_desc *desc = irq_to_desc(d->irq); | |
564 | ||
565 | if (WARN_ON(!gic_supports_nmi())) | |
566 | return; | |
567 | ||
568 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
569 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
570 | return; | |
571 | } | |
572 | ||
573 | /* | |
574 | * A secondary irq_chip should be in charge of LPI request, | |
575 | * it should not be possible to get there | |
576 | */ | |
577 | if (WARN_ON(gic_irq(d) >= 8192)) | |
578 | return; | |
579 | ||
580 | /* desc lock should already be held */ | |
81a43273 MZ |
581 | if (gic_irq_in_rdist(d)) { |
582 | u32 idx = gic_get_ppi_index(d); | |
583 | ||
101b35f7 | 584 | /* Tearing down NMI, only switch handler for last NMI */ |
81a43273 | 585 | if (refcount_dec_and_test(&ppi_nmi_refs[idx])) |
101b35f7 JT |
586 | desc->handle_irq = handle_percpu_devid_irq; |
587 | } else { | |
588 | desc->handle_irq = handle_fasteoi_irq; | |
589 | } | |
590 | ||
591 | gic_irq_set_prio(d, GICD_INT_DEF_PRI); | |
592 | } | |
593 | ||
021f6537 MZ |
594 | static void gic_eoi_irq(struct irq_data *d) |
595 | { | |
6efb5092 MR |
596 | write_gicreg(gic_irq(d), ICC_EOIR1_EL1); |
597 | isb(); | |
021f6537 MZ |
598 | } |
599 | ||
0b6a3da9 MZ |
600 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
601 | { | |
602 | /* | |
530bf353 MZ |
603 | * No need to deactivate an LPI, or an interrupt that |
604 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 605 | */ |
4df7f54d | 606 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
607 | return; |
608 | gic_write_dir(gic_irq(d)); | |
609 | } | |
610 | ||
021f6537 MZ |
611 | static int gic_set_type(struct irq_data *d, unsigned int type) |
612 | { | |
5f51f803 | 613 | enum gic_intid_range range; |
021f6537 | 614 | unsigned int irq = gic_irq(d); |
021f6537 | 615 | void __iomem *base; |
e91b036e | 616 | u32 offset, index; |
13d22e2e | 617 | int ret; |
021f6537 | 618 | |
5f51f803 MZ |
619 | range = get_intid_range(d); |
620 | ||
64b499d8 MZ |
621 | /* Interrupt configuration for SGIs can't be changed */ |
622 | if (range == SGI_RANGE) | |
623 | return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; | |
624 | ||
fb7e7deb | 625 | /* SPIs have restrictions on the supported types */ |
5f51f803 MZ |
626 | if ((range == SPI_RANGE || range == ESPI_RANGE) && |
627 | type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
628 | return -EINVAL; |
629 | ||
63f13483 | 630 | if (gic_irq_in_rdist(d)) |
021f6537 | 631 | base = gic_data_rdist_sgi_base(); |
63f13483 | 632 | else |
35727af2 | 633 | base = gic_dist_base_alias(d); |
021f6537 | 634 | |
e91b036e | 635 | offset = convert_offset_index(d, GICD_ICFGR, &index); |
13d22e2e | 636 | |
63f13483 | 637 | ret = gic_configure_irq(index, type, base + offset, NULL); |
5f51f803 | 638 | if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { |
13d22e2e | 639 | /* Misconfigured PPIs are usually not fatal */ |
5f51f803 | 640 | pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); |
13d22e2e MZ |
641 | ret = 0; |
642 | } | |
643 | ||
644 | return ret; | |
021f6537 MZ |
645 | } |
646 | ||
530bf353 MZ |
647 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
648 | { | |
64b499d8 MZ |
649 | if (get_intid_range(d) == SGI_RANGE) |
650 | return -EINVAL; | |
651 | ||
4df7f54d TG |
652 | if (vcpu) |
653 | irqd_set_forwarded_to_vcpu(d); | |
654 | else | |
655 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
656 | return 0; |
657 | } | |
658 | ||
3c65cbb7 | 659 | static u64 gic_cpu_to_affinity(int cpu) |
021f6537 | 660 | { |
3c65cbb7 | 661 | u64 mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
662 | u64 aff; |
663 | ||
f6c86a41 | 664 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
665 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
666 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
667 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
668 | ||
669 | return aff; | |
670 | } | |
671 | ||
f32c9266 JT |
672 | static void gic_deactivate_unhandled(u32 irqnr) |
673 | { | |
674 | if (static_branch_likely(&supports_deactivate_key)) { | |
675 | if (irqnr < 8192) | |
676 | gic_write_dir(irqnr); | |
677 | } else { | |
6efb5092 MR |
678 | write_gicreg(irqnr, ICC_EOIR1_EL1); |
679 | isb(); | |
f32c9266 JT |
680 | } |
681 | } | |
682 | ||
6efb5092 MR |
683 | /* |
684 | * Follow a read of the IAR with any HW maintenance that needs to happen prior | |
685 | * to invoking the relevant IRQ handler. We must do two things: | |
686 | * | |
687 | * (1) Ensure instruction ordering between a read of IAR and subsequent | |
688 | * instructions in the IRQ handler using an ISB. | |
689 | * | |
690 | * It is possible for the IAR to report an IRQ which was signalled *after* | |
691 | * the CPU took an IRQ exception as multiple interrupts can race to be | |
692 | * recognized by the GIC, earlier interrupts could be withdrawn, and/or | |
693 | * later interrupts could be prioritized by the GIC. | |
694 | * | |
695 | * For devices which are tightly coupled to the CPU, such as PMUs, a | |
696 | * context synchronization event is necessary to ensure that system | |
697 | * register state is not stale, as these may have been indirectly written | |
698 | * *after* exception entry. | |
699 | * | |
700 | * (2) Deactivate the interrupt when EOI mode 1 is in use. | |
701 | */ | |
702 | static inline void gic_complete_ack(u32 irqnr) | |
f32c9266 | 703 | { |
f32c9266 | 704 | if (static_branch_likely(&supports_deactivate_key)) |
6efb5092 | 705 | write_gicreg(irqnr, ICC_EOIR1_EL1); |
17ce302f | 706 | |
6efb5092 | 707 | isb(); |
f32c9266 JT |
708 | } |
709 | ||
614ab80c | 710 | static bool gic_rpr_is_nmi_prio(void) |
382e6e17 | 711 | { |
614ab80c MR |
712 | if (!gic_supports_nmi()) |
713 | return false; | |
f32c9266 | 714 | |
614ab80c MR |
715 | return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI)); |
716 | } | |
382e6e17 | 717 | |
614ab80c MR |
718 | static bool gic_irqnr_is_special(u32 irqnr) |
719 | { | |
720 | return irqnr >= 1020 && irqnr <= 1023; | |
721 | } | |
382e6e17 | 722 | |
614ab80c MR |
723 | static void __gic_handle_irq(u32 irqnr, struct pt_regs *regs) |
724 | { | |
725 | if (gic_irqnr_is_special(irqnr)) | |
726 | return; | |
382e6e17 | 727 | |
6efb5092 | 728 | gic_complete_ack(irqnr); |
382e6e17 | 729 | |
614ab80c MR |
730 | if (generic_handle_domain_irq(gic_data.domain, irqnr)) { |
731 | WARN_ONCE(true, "Unexpected interrupt (irqnr %u)\n", irqnr); | |
f32c9266 | 732 | gic_deactivate_unhandled(irqnr); |
382e6e17 | 733 | } |
f32c9266 JT |
734 | } |
735 | ||
614ab80c | 736 | static void __gic_handle_nmi(u32 irqnr, struct pt_regs *regs) |
382e6e17 | 737 | { |
614ab80c MR |
738 | if (gic_irqnr_is_special(irqnr)) |
739 | return; | |
382e6e17 | 740 | |
614ab80c | 741 | gic_complete_ack(irqnr); |
382e6e17 | 742 | |
614ab80c MR |
743 | if (generic_handle_domain_nmi(gic_data.domain, irqnr)) { |
744 | WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr); | |
745 | gic_deactivate_unhandled(irqnr); | |
382e6e17 | 746 | } |
382e6e17 MZ |
747 | } |
748 | ||
614ab80c MR |
749 | /* |
750 | * An exception has been taken from a context with IRQs enabled, and this could | |
751 | * be an IRQ or an NMI. | |
752 | * | |
753 | * The entry code called us with DAIF.IF set to keep NMIs masked. We must clear | |
754 | * DAIF.IF (and update ICC_PMR_EL1 to mask regular IRQs) prior to returning, | |
755 | * after handling any NMI but before handling any IRQ. | |
756 | * | |
757 | * The entry code has performed IRQ entry, and if an NMI is detected we must | |
758 | * perform NMI entry/exit around invoking the handler. | |
759 | */ | |
760 | static void __gic_handle_irq_from_irqson(struct pt_regs *regs) | |
021f6537 | 761 | { |
614ab80c | 762 | bool is_nmi; |
f6c86a41 | 763 | u32 irqnr; |
021f6537 | 764 | |
614ab80c | 765 | irqnr = gic_read_iar(); |
021f6537 | 766 | |
614ab80c | 767 | is_nmi = gic_rpr_is_nmi_prio(); |
a97709f5 | 768 | |
614ab80c MR |
769 | if (is_nmi) { |
770 | nmi_enter(); | |
771 | __gic_handle_nmi(irqnr, regs); | |
772 | nmi_exit(); | |
f32c9266 JT |
773 | } |
774 | ||
3f1f3234 JT |
775 | if (gic_prio_masking_enabled()) { |
776 | gic_pmr_mask_irqs(); | |
777 | gic_arch_enable_irqs(); | |
778 | } | |
779 | ||
614ab80c MR |
780 | if (!is_nmi) |
781 | __gic_handle_irq(irqnr, regs); | |
782 | } | |
64b499d8 | 783 | |
614ab80c MR |
784 | /* |
785 | * An exception has been taken from a context with IRQs disabled, which can only | |
786 | * be an NMI. | |
787 | * | |
788 | * The entry code called us with DAIF.IF set to keep NMIs masked. We must leave | |
789 | * DAIF.IF (and ICC_PMR_EL1) unchanged. | |
790 | * | |
791 | * The entry code has performed NMI entry. | |
792 | */ | |
793 | static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs) | |
794 | { | |
795 | u64 pmr; | |
796 | u32 irqnr; | |
797 | ||
798 | /* | |
799 | * We were in a context with IRQs disabled. However, the | |
800 | * entry code has set PMR to a value that allows any | |
801 | * interrupt to be acknowledged, and not just NMIs. This can | |
802 | * lead to surprising effects if the NMI has been retired in | |
803 | * the meantime, and that there is an IRQ pending. The IRQ | |
804 | * would then be taken in NMI context, something that nobody | |
805 | * wants to debug twice. | |
806 | * | |
807 | * Until we sort this, drop PMR again to a level that will | |
808 | * actually only allow NMIs before reading IAR, and then | |
809 | * restore it to what it was. | |
810 | */ | |
811 | pmr = gic_read_pmr(); | |
812 | gic_pmr_mask_irqs(); | |
813 | isb(); | |
814 | irqnr = gic_read_iar(); | |
815 | gic_write_pmr(pmr); | |
816 | ||
817 | __gic_handle_nmi(irqnr, regs); | |
818 | } | |
819 | ||
820 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
821 | { | |
822 | if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs))) | |
823 | __gic_handle_irq_from_irqsoff(regs); | |
824 | else | |
825 | __gic_handle_irq_from_irqson(regs); | |
021f6537 MZ |
826 | } |
827 | ||
b5cf6073 JT |
828 | static u32 gic_get_pribits(void) |
829 | { | |
830 | u32 pribits; | |
831 | ||
832 | pribits = gic_read_ctlr(); | |
833 | pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
834 | pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
835 | pribits++; | |
836 | ||
837 | return pribits; | |
838 | } | |
839 | ||
840 | static bool gic_has_group0(void) | |
841 | { | |
842 | u32 val; | |
e7932188 JT |
843 | u32 old_pmr; |
844 | ||
845 | old_pmr = gic_read_pmr(); | |
b5cf6073 JT |
846 | |
847 | /* | |
848 | * Let's find out if Group0 is under control of EL3 or not by | |
849 | * setting the highest possible, non-zero priority in PMR. | |
850 | * | |
851 | * If SCR_EL3.FIQ is set, the priority gets shifted down in | |
852 | * order for the CPU interface to set bit 7, and keep the | |
853 | * actual priority in the non-secure range. In the process, it | |
854 | * looses the least significant bit and the actual priority | |
855 | * becomes 0x80. Reading it back returns 0, indicating that | |
856 | * we're don't have access to Group0. | |
857 | */ | |
858 | gic_write_pmr(BIT(8 - gic_get_pribits())); | |
859 | val = gic_read_pmr(); | |
860 | ||
e7932188 JT |
861 | gic_write_pmr(old_pmr); |
862 | ||
b5cf6073 JT |
863 | return val != 0; |
864 | } | |
865 | ||
021f6537 MZ |
866 | static void __init gic_dist_init(void) |
867 | { | |
868 | unsigned int i; | |
869 | u64 affinity; | |
870 | void __iomem *base = gic_data.dist_base; | |
0b04758b | 871 | u32 val; |
021f6537 MZ |
872 | |
873 | /* Disable the distributor */ | |
874 | writel_relaxed(0, base + GICD_CTLR); | |
875 | gic_dist_wait_for_rwp(); | |
876 | ||
7c9b9730 MZ |
877 | /* |
878 | * Configure SPIs as non-secure Group-1. This will only matter | |
879 | * if the GIC only has a single security state. This will not | |
880 | * do the right thing if the kernel is running in secure mode, | |
881 | * but that's not the intended use case anyway. | |
882 | */ | |
211bddd2 | 883 | for (i = 32; i < GIC_LINE_NR; i += 32) |
7c9b9730 MZ |
884 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); |
885 | ||
211bddd2 MZ |
886 | /* Extended SPI range, not handled by the GICv2/GICv3 common code */ |
887 | for (i = 0; i < GIC_ESPI_NR; i += 32) { | |
888 | writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); | |
889 | writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); | |
890 | } | |
891 | ||
892 | for (i = 0; i < GIC_ESPI_NR; i += 32) | |
893 | writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); | |
894 | ||
895 | for (i = 0; i < GIC_ESPI_NR; i += 16) | |
896 | writel_relaxed(0, base + GICD_ICFGRnE + i / 4); | |
897 | ||
898 | for (i = 0; i < GIC_ESPI_NR; i += 4) | |
899 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); | |
900 | ||
63f13483 MZ |
901 | /* Now do the common stuff */ |
902 | gic_dist_config(base, GIC_LINE_NR, NULL); | |
021f6537 | 903 | |
0b04758b MZ |
904 | val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; |
905 | if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { | |
906 | pr_info("Enabling SGIs without active state\n"); | |
907 | val |= GICD_CTLR_nASSGIreq; | |
908 | } | |
909 | ||
63f13483 | 910 | /* Enable distributor with ARE, Group1, and wait for it to drain */ |
0b04758b | 911 | writel_relaxed(val, base + GICD_CTLR); |
63f13483 | 912 | gic_dist_wait_for_rwp(); |
021f6537 MZ |
913 | |
914 | /* | |
915 | * Set all global interrupts to the boot CPU only. ARE must be | |
916 | * enabled. | |
917 | */ | |
3c65cbb7 | 918 | affinity = gic_cpu_to_affinity(smp_processor_id()); |
211bddd2 | 919 | for (i = 32; i < GIC_LINE_NR; i++) |
72c97126 | 920 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
211bddd2 MZ |
921 | |
922 | for (i = 0; i < GIC_ESPI_NR; i++) | |
923 | gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); | |
021f6537 MZ |
924 | } |
925 | ||
0d94ded2 | 926 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 927 | { |
0d94ded2 | 928 | int ret = -ENODEV; |
021f6537 MZ |
929 | int i; |
930 | ||
f5c1434c MZ |
931 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
932 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 933 | u64 typer; |
021f6537 MZ |
934 | u32 reg; |
935 | ||
936 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
937 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
938 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
939 | pr_warn("No redistributor present @%p\n", ptr); | |
940 | break; | |
941 | } | |
942 | ||
943 | do { | |
72c97126 | 944 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
945 | ret = fn(gic_data.redist_regions + i, ptr); |
946 | if (!ret) | |
021f6537 | 947 | return 0; |
021f6537 | 948 | |
b70fb7af TN |
949 | if (gic_data.redist_regions[i].single_redist) |
950 | break; | |
951 | ||
021f6537 MZ |
952 | if (gic_data.redist_stride) { |
953 | ptr += gic_data.redist_stride; | |
954 | } else { | |
955 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
956 | if (typer & GICR_TYPER_VLPIS) | |
957 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
958 | } | |
959 | } while (!(typer & GICR_TYPER_LAST)); | |
960 | } | |
961 | ||
0d94ded2 MZ |
962 | return ret ? -ENODEV : 0; |
963 | } | |
964 | ||
965 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
966 | { | |
3c65cbb7 | 967 | unsigned long mpidr; |
0d94ded2 MZ |
968 | u64 typer; |
969 | u32 aff; | |
970 | ||
971 | /* | |
972 | * Convert affinity to a 32bit value that can be matched to | |
973 | * GICR_TYPER bits [63:32]. | |
974 | */ | |
3c65cbb7 MZ |
975 | mpidr = gic_cpu_to_affinity(smp_processor_id()); |
976 | ||
0d94ded2 MZ |
977 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | |
978 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
979 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
980 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
981 | ||
982 | typer = gic_read_typer(ptr + GICR_TYPER); | |
983 | if ((typer >> 32) == aff) { | |
984 | u64 offset = ptr - region->redist_base; | |
9058a4e9 | 985 | raw_spin_lock_init(&gic_data_rdist()->rd_lock); |
0d94ded2 MZ |
986 | gic_data_rdist_rd_base() = ptr; |
987 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
988 | ||
989 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
990 | smp_processor_id(), mpidr, | |
991 | (int)(region - gic_data.redist_regions), | |
992 | &gic_data_rdist()->phys_base); | |
993 | return 0; | |
994 | } | |
995 | ||
996 | /* Try next one */ | |
997 | return 1; | |
998 | } | |
999 | ||
1000 | static int gic_populate_rdist(void) | |
1001 | { | |
1002 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
1003 | return 0; | |
1004 | ||
021f6537 | 1005 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 1006 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
1007 | smp_processor_id(), |
1008 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
1009 | return -ENODEV; |
1010 | } | |
1011 | ||
1a60e1e6 MZ |
1012 | static int __gic_update_rdist_properties(struct redist_region *region, |
1013 | void __iomem *ptr) | |
0edc23ea MZ |
1014 | { |
1015 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
a837ed36 | 1016 | u32 ctlr = readl_relaxed(ptr + GICR_CTLR); |
b25319d2 | 1017 | |
4d968297 | 1018 | /* Boot-time cleanup */ |
79a7f77b MZ |
1019 | if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { |
1020 | u64 val; | |
1021 | ||
1022 | /* Deactivate any present vPE */ | |
1023 | val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER); | |
1024 | if (val & GICR_VPENDBASER_Valid) | |
1025 | gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast, | |
1026 | ptr + SZ_128K + GICR_VPENDBASER); | |
1027 | ||
1028 | /* Mark the VPE table as invalid */ | |
1029 | val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER); | |
1030 | val &= ~GICR_VPROPBASER_4_1_VALID; | |
1031 | gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER); | |
1032 | } | |
1033 | ||
0edc23ea | 1034 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); |
b25319d2 | 1035 | |
a837ed36 MZ |
1036 | /* |
1037 | * TYPER.RVPEID implies some form of DirectLPI, no matter what the | |
1038 | * doc says... :-/ And CTLR.IR implies another subset of DirectLPI | |
1039 | * that the ITS driver can make use of for LPIs (and not VLPIs). | |
1040 | * | |
1041 | * These are 3 different ways to express the same thing, depending | |
1042 | * on the revision of the architecture and its relaxations over | |
1043 | * time. Just group them under the 'direct_lpi' banner. | |
1044 | */ | |
b25319d2 MZ |
1045 | gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); |
1046 | gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | | |
a837ed36 | 1047 | !!(ctlr & GICR_CTLR_IR) | |
b25319d2 | 1048 | gic_data.rdists.has_rvpeid); |
96806229 | 1049 | gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); |
b25319d2 MZ |
1050 | |
1051 | /* Detect non-sensical configurations */ | |
1052 | if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { | |
1053 | gic_data.rdists.has_direct_lpi = false; | |
1054 | gic_data.rdists.has_vlpis = false; | |
1055 | gic_data.rdists.has_rvpeid = false; | |
1056 | } | |
1057 | ||
5f51f803 | 1058 | gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); |
0edc23ea MZ |
1059 | |
1060 | return 1; | |
1061 | } | |
1062 | ||
1a60e1e6 | 1063 | static void gic_update_rdist_properties(void) |
0edc23ea | 1064 | { |
1a60e1e6 MZ |
1065 | gic_data.ppi_nr = UINT_MAX; |
1066 | gic_iterate_rdists(__gic_update_rdist_properties); | |
1067 | if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) | |
1068 | gic_data.ppi_nr = 0; | |
a837ed36 MZ |
1069 | pr_info("GICv3 features: %d PPIs%s%s\n", |
1070 | gic_data.ppi_nr, | |
1071 | gic_data.has_rss ? ", RSS" : "", | |
1072 | gic_data.rdists.has_direct_lpi ? ", DirectLPI" : ""); | |
1073 | ||
96806229 MZ |
1074 | if (gic_data.rdists.has_vlpis) |
1075 | pr_info("GICv4 features: %s%s%s\n", | |
1076 | gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", | |
1077 | gic_data.rdists.has_rvpeid ? "RVPEID " : "", | |
1078 | gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); | |
0edc23ea MZ |
1079 | } |
1080 | ||
d98d0a99 JT |
1081 | /* Check whether it's single security state view */ |
1082 | static inline bool gic_dist_security_disabled(void) | |
1083 | { | |
1084 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
1085 | } | |
1086 | ||
3708d52f SH |
1087 | static void gic_cpu_sys_reg_init(void) |
1088 | { | |
eda0d04a | 1089 | int i, cpu = smp_processor_id(); |
3c65cbb7 | 1090 | u64 mpidr = gic_cpu_to_affinity(cpu); |
eda0d04a | 1091 | u64 need_rss = MPIDR_RS(mpidr); |
33625282 | 1092 | bool group0; |
b5cf6073 | 1093 | u32 pribits; |
eda0d04a | 1094 | |
7cabd008 MZ |
1095 | /* |
1096 | * Need to check that the SRE bit has actually been set. If | |
1097 | * not, it means that SRE is disabled at EL2. We're going to | |
1098 | * die painfully, and there is nothing we can do about it. | |
1099 | * | |
1100 | * Kindly inform the luser. | |
1101 | */ | |
1102 | if (!gic_enable_sre()) | |
1103 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f | 1104 | |
b5cf6073 | 1105 | pribits = gic_get_pribits(); |
33625282 | 1106 | |
b5cf6073 | 1107 | group0 = gic_has_group0(); |
33625282 | 1108 | |
3708d52f | 1109 | /* Set priority mask register */ |
d98d0a99 | 1110 | if (!gic_prio_masking_enabled()) { |
e7932188 | 1111 | write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); |
33678059 | 1112 | } else if (gic_supports_nmi()) { |
d98d0a99 JT |
1113 | /* |
1114 | * Mismatch configuration with boot CPU, the system is likely | |
1115 | * to die as interrupt masking will not work properly on all | |
1116 | * CPUs | |
33678059 AE |
1117 | * |
1118 | * The boot CPU calls this function before enabling NMI support, | |
1119 | * and as a result we'll never see this warning in the boot path | |
1120 | * for that CPU. | |
d98d0a99 | 1121 | */ |
33678059 AE |
1122 | if (static_branch_unlikely(&gic_nonsecure_priorities)) |
1123 | WARN_ON(!group0 || gic_dist_security_disabled()); | |
1124 | else | |
1125 | WARN_ON(group0 && !gic_dist_security_disabled()); | |
d98d0a99 | 1126 | } |
3708d52f | 1127 | |
91ef8442 DT |
1128 | /* |
1129 | * Some firmwares hand over to the kernel with the BPR changed from | |
1130 | * its reset value (and with a value large enough to prevent | |
1131 | * any pre-emptive interrupts from working at all). Writing a zero | |
1132 | * to BPR restores is reset value. | |
1133 | */ | |
1134 | gic_write_bpr1(0); | |
1135 | ||
d01d3274 | 1136 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
1137 | /* EOI drops priority only (mode 1) */ |
1138 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
1139 | } else { | |
1140 | /* EOI deactivates interrupt too (mode 0) */ | |
1141 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
1142 | } | |
3708d52f | 1143 | |
33625282 MZ |
1144 | /* Always whack Group0 before Group1 */ |
1145 | if (group0) { | |
1146 | switch(pribits) { | |
1147 | case 8: | |
1148 | case 7: | |
1149 | write_gicreg(0, ICC_AP0R3_EL1); | |
1150 | write_gicreg(0, ICC_AP0R2_EL1); | |
df561f66 | 1151 | fallthrough; |
33625282 MZ |
1152 | case 6: |
1153 | write_gicreg(0, ICC_AP0R1_EL1); | |
df561f66 | 1154 | fallthrough; |
33625282 MZ |
1155 | case 5: |
1156 | case 4: | |
1157 | write_gicreg(0, ICC_AP0R0_EL1); | |
1158 | } | |
1159 | ||
1160 | isb(); | |
1161 | } | |
d6062a6d | 1162 | |
33625282 | 1163 | switch(pribits) { |
d6062a6d MZ |
1164 | case 8: |
1165 | case 7: | |
d6062a6d | 1166 | write_gicreg(0, ICC_AP1R3_EL1); |
d6062a6d | 1167 | write_gicreg(0, ICC_AP1R2_EL1); |
df561f66 | 1168 | fallthrough; |
d6062a6d | 1169 | case 6: |
d6062a6d | 1170 | write_gicreg(0, ICC_AP1R1_EL1); |
df561f66 | 1171 | fallthrough; |
d6062a6d MZ |
1172 | case 5: |
1173 | case 4: | |
d6062a6d MZ |
1174 | write_gicreg(0, ICC_AP1R0_EL1); |
1175 | } | |
1176 | ||
1177 | isb(); | |
1178 | ||
3708d52f SH |
1179 | /* ... and let's hit the road... */ |
1180 | gic_write_grpen1(1); | |
eda0d04a SD |
1181 | |
1182 | /* Keep the RSS capability status in per_cpu variable */ | |
1183 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
1184 | ||
1185 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
1186 | for_each_online_cpu(i) { | |
1187 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
1188 | ||
3c65cbb7 | 1189 | need_rss |= MPIDR_RS(gic_cpu_to_affinity(i)); |
eda0d04a SD |
1190 | if (need_rss && (!have_rss)) |
1191 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
1192 | cpu, (unsigned long)mpidr, | |
3c65cbb7 | 1193 | i, (unsigned long)gic_cpu_to_affinity(i)); |
eda0d04a SD |
1194 | } |
1195 | ||
1196 | /** | |
1197 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
1198 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
1199 | * UNPREDICTABLE choice of : | |
1200 | * - The write is ignored. | |
1201 | * - The RS field is treated as 0. | |
1202 | */ | |
1203 | if (need_rss && (!gic_data.has_rss)) | |
1204 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
1205 | } |
1206 | ||
f736d65d MZ |
1207 | static bool gicv3_nolpi; |
1208 | ||
1209 | static int __init gicv3_nolpi_cfg(char *buf) | |
1210 | { | |
5e279739 | 1211 | return kstrtobool(buf, &gicv3_nolpi); |
f736d65d MZ |
1212 | } |
1213 | early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); | |
1214 | ||
da33f31d MZ |
1215 | static int gic_dist_supports_lpis(void) |
1216 | { | |
d38a71c5 MZ |
1217 | return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && |
1218 | !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && | |
1219 | !gicv3_nolpi); | |
da33f31d MZ |
1220 | } |
1221 | ||
021f6537 MZ |
1222 | static void gic_cpu_init(void) |
1223 | { | |
1224 | void __iomem *rbase; | |
1a60e1e6 | 1225 | int i; |
021f6537 MZ |
1226 | |
1227 | /* Register ourselves with the rest of the world */ | |
1228 | if (gic_populate_rdist()) | |
1229 | return; | |
1230 | ||
a2c22510 | 1231 | gic_enable_redist(true); |
021f6537 | 1232 | |
ad5a78d3 MZ |
1233 | WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && |
1234 | !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), | |
1235 | "Distributor has extended ranges, but CPU%d doesn't\n", | |
1236 | smp_processor_id()); | |
1237 | ||
021f6537 MZ |
1238 | rbase = gic_data_rdist_sgi_base(); |
1239 | ||
7c9b9730 | 1240 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
1a60e1e6 MZ |
1241 | for (i = 0; i < gic_data.ppi_nr + 16; i += 32) |
1242 | writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); | |
7c9b9730 | 1243 | |
1a60e1e6 | 1244 | gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); |
021f6537 | 1245 | |
3708d52f SH |
1246 | /* initialise system registers */ |
1247 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
1248 | } |
1249 | ||
1250 | #ifdef CONFIG_SMP | |
6670a6d8 | 1251 | |
eda0d04a SD |
1252 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
1253 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
1254 | ||
6670a6d8 | 1255 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 1256 | { |
6670a6d8 | 1257 | gic_cpu_init(); |
d38a71c5 MZ |
1258 | |
1259 | if (gic_dist_supports_lpis()) | |
1260 | its_cpu_init(); | |
1261 | ||
6670a6d8 | 1262 | return 0; |
021f6537 MZ |
1263 | } |
1264 | ||
021f6537 | 1265 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 1266 | unsigned long cluster_id) |
021f6537 | 1267 | { |
727653d6 | 1268 | int next_cpu, cpu = *base_cpu; |
3c65cbb7 | 1269 | unsigned long mpidr; |
021f6537 MZ |
1270 | u16 tlist = 0; |
1271 | ||
3c65cbb7 MZ |
1272 | mpidr = gic_cpu_to_affinity(cpu); |
1273 | ||
021f6537 | 1274 | while (cpu < nr_cpu_ids) { |
021f6537 MZ |
1275 | tlist |= 1 << (mpidr & 0xf); |
1276 | ||
727653d6 JM |
1277 | next_cpu = cpumask_next(cpu, mask); |
1278 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 1279 | goto out; |
727653d6 | 1280 | cpu = next_cpu; |
021f6537 | 1281 | |
3c65cbb7 | 1282 | mpidr = gic_cpu_to_affinity(cpu); |
021f6537 | 1283 | |
eda0d04a | 1284 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
1285 | cpu--; |
1286 | goto out; | |
1287 | } | |
1288 | } | |
1289 | out: | |
1290 | *base_cpu = cpu; | |
1291 | return tlist; | |
1292 | } | |
1293 | ||
7e580278 AP |
1294 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
1295 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
1296 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
1297 | ||
021f6537 MZ |
1298 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
1299 | { | |
1300 | u64 val; | |
1301 | ||
7e580278 AP |
1302 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
1303 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
1304 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
1305 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 1306 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 1307 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 1308 | |
b6dd4d83 | 1309 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
1310 | gic_write_sgi1r(val); |
1311 | } | |
1312 | ||
64b499d8 | 1313 | static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) |
021f6537 MZ |
1314 | { |
1315 | int cpu; | |
1316 | ||
64b499d8 | 1317 | if (WARN_ON(d->hwirq >= 16)) |
021f6537 MZ |
1318 | return; |
1319 | ||
1320 | /* | |
1321 | * Ensure that stores to Normal memory are visible to the | |
1322 | * other CPUs before issuing the IPI. | |
1323 | */ | |
80e4e1f4 | 1324 | dsb(ishst); |
021f6537 | 1325 | |
f9b531fe | 1326 | for_each_cpu(cpu, mask) { |
3c65cbb7 | 1327 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu)); |
021f6537 MZ |
1328 | u16 tlist; |
1329 | ||
1330 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
64b499d8 | 1331 | gic_send_sgi(cluster_id, tlist, d->hwirq); |
021f6537 MZ |
1332 | } |
1333 | ||
1334 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
1335 | isb(); | |
1336 | } | |
1337 | ||
8a94c1ab | 1338 | static void __init gic_smp_init(void) |
021f6537 | 1339 | { |
64b499d8 MZ |
1340 | struct irq_fwspec sgi_fwspec = { |
1341 | .fwnode = gic_data.fwnode, | |
1342 | .param_count = 1, | |
1343 | }; | |
1344 | int base_sgi; | |
1345 | ||
6896bcd1 | 1346 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
1347 | "irqchip/arm/gicv3:starting", |
1348 | gic_starting_cpu, NULL); | |
64b499d8 MZ |
1349 | |
1350 | /* Register all 8 non-secure SGIs */ | |
0e2213fe | 1351 | base_sgi = irq_domain_alloc_irqs(gic_data.domain, 8, NUMA_NO_NODE, &sgi_fwspec); |
64b499d8 MZ |
1352 | if (WARN_ON(base_sgi <= 0)) |
1353 | return; | |
1354 | ||
1355 | set_smp_ipi_range(base_sgi, 8); | |
021f6537 MZ |
1356 | } |
1357 | ||
1358 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
1359 | bool force) | |
1360 | { | |
65a30f8b | 1361 | unsigned int cpu; |
e91b036e | 1362 | u32 offset, index; |
021f6537 MZ |
1363 | void __iomem *reg; |
1364 | int enabled; | |
1365 | u64 val; | |
1366 | ||
65a30f8b SP |
1367 | if (force) |
1368 | cpu = cpumask_first(mask_val); | |
1369 | else | |
1370 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
1371 | ||
866d7c1b SP |
1372 | if (cpu >= nr_cpu_ids) |
1373 | return -EINVAL; | |
1374 | ||
021f6537 MZ |
1375 | if (gic_irq_in_rdist(d)) |
1376 | return -EINVAL; | |
1377 | ||
1378 | /* If interrupt was enabled, disable it first */ | |
1379 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
1380 | if (enabled) | |
1381 | gic_mask_irq(d); | |
1382 | ||
e91b036e MZ |
1383 | offset = convert_offset_index(d, GICD_IROUTER, &index); |
1384 | reg = gic_dist_base(d) + offset + (index * 8); | |
3c65cbb7 | 1385 | val = gic_cpu_to_affinity(cpu); |
021f6537 | 1386 | |
72c97126 | 1387 | gic_write_irouter(val, reg); |
021f6537 MZ |
1388 | |
1389 | /* | |
1390 | * If the interrupt was enabled, enabled it again. Otherwise, | |
1391 | * just wait for the distributor to have digested our changes. | |
1392 | */ | |
1393 | if (enabled) | |
1394 | gic_unmask_irq(d); | |
021f6537 | 1395 | |
956ae91a MZ |
1396 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
1397 | ||
0fc6fa29 | 1398 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
1399 | } |
1400 | #else | |
1401 | #define gic_set_affinity NULL | |
64b499d8 | 1402 | #define gic_ipi_send_mask NULL |
021f6537 MZ |
1403 | #define gic_smp_init() do { } while(0) |
1404 | #endif | |
1405 | ||
17f644e9 VS |
1406 | static int gic_retrigger(struct irq_data *data) |
1407 | { | |
1408 | return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); | |
1409 | } | |
1410 | ||
3708d52f SH |
1411 | #ifdef CONFIG_CPU_PM |
1412 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
1413 | unsigned long cmd, void *v) | |
1414 | { | |
1415 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
1416 | if (gic_dist_security_disabled()) |
1417 | gic_enable_redist(true); | |
3708d52f | 1418 | gic_cpu_sys_reg_init(); |
ccd9432a | 1419 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
1420 | gic_write_grpen1(0); |
1421 | gic_enable_redist(false); | |
1422 | } | |
1423 | return NOTIFY_OK; | |
1424 | } | |
1425 | ||
1426 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
1427 | .notifier_call = gic_cpu_pm_notifier, | |
1428 | }; | |
1429 | ||
1430 | static void gic_cpu_pm_init(void) | |
1431 | { | |
1432 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
1433 | } | |
1434 | ||
1435 | #else | |
1436 | static inline void gic_cpu_pm_init(void) { } | |
1437 | #endif /* CONFIG_CPU_PM */ | |
1438 | ||
021f6537 MZ |
1439 | static struct irq_chip gic_chip = { |
1440 | .name = "GICv3", | |
1441 | .irq_mask = gic_mask_irq, | |
1442 | .irq_unmask = gic_unmask_irq, | |
1443 | .irq_eoi = gic_eoi_irq, | |
1444 | .irq_set_type = gic_set_type, | |
1445 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1446 | .irq_retrigger = gic_retrigger, |
b594c6e2 MZ |
1447 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1448 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
101b35f7 JT |
1449 | .irq_nmi_setup = gic_irq_nmi_setup, |
1450 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1451 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1452 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1453 | IRQCHIP_SKIP_SET_WAKE | | |
1454 | IRQCHIP_MASK_ON_SUSPEND, | |
021f6537 MZ |
1455 | }; |
1456 | ||
0b6a3da9 MZ |
1457 | static struct irq_chip gic_eoimode1_chip = { |
1458 | .name = "GICv3", | |
1459 | .irq_mask = gic_eoimode1_mask_irq, | |
1460 | .irq_unmask = gic_unmask_irq, | |
1461 | .irq_eoi = gic_eoimode1_eoi_irq, | |
1462 | .irq_set_type = gic_set_type, | |
1463 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1464 | .irq_retrigger = gic_retrigger, |
0b6a3da9 MZ |
1465 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1466 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 1467 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
101b35f7 JT |
1468 | .irq_nmi_setup = gic_irq_nmi_setup, |
1469 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1470 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1471 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1472 | IRQCHIP_SKIP_SET_WAKE | | |
1473 | IRQCHIP_MASK_ON_SUSPEND, | |
0b6a3da9 MZ |
1474 | }; |
1475 | ||
021f6537 MZ |
1476 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
1477 | irq_hw_number_t hw) | |
1478 | { | |
0b6a3da9 | 1479 | struct irq_chip *chip = &gic_chip; |
1b57d91b | 1480 | struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); |
0b6a3da9 | 1481 | |
d01d3274 | 1482 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1483 | chip = &gic_eoimode1_chip; |
1484 | ||
e91b036e | 1485 | switch (__get_intid_range(hw)) { |
70a29c32 | 1486 | case SGI_RANGE: |
e91b036e | 1487 | case PPI_RANGE: |
5f51f803 | 1488 | case EPPI_RANGE: |
021f6537 | 1489 | irq_set_percpu_devid(irq); |
0b6a3da9 | 1490 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1491 | handle_percpu_devid_irq, NULL, NULL); |
e91b036e MZ |
1492 | break; |
1493 | ||
1494 | case SPI_RANGE: | |
211bddd2 | 1495 | case ESPI_RANGE: |
0b6a3da9 | 1496 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1497 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 1498 | irq_set_probe(irq); |
1b57d91b | 1499 | irqd_set_single_target(irqd); |
e91b036e MZ |
1500 | break; |
1501 | ||
1502 | case LPI_RANGE: | |
da33f31d MZ |
1503 | if (!gic_dist_supports_lpis()) |
1504 | return -EPERM; | |
0b6a3da9 | 1505 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 1506 | handle_fasteoi_irq, NULL, NULL); |
e91b036e MZ |
1507 | break; |
1508 | ||
1509 | default: | |
1510 | return -EPERM; | |
da33f31d MZ |
1511 | } |
1512 | ||
1b57d91b VS |
1513 | /* Prevents SW retriggers which mess up the ACK/EOI ordering */ |
1514 | irqd_set_handle_enforce_irqctx(irqd); | |
021f6537 MZ |
1515 | return 0; |
1516 | } | |
1517 | ||
f833f57f MZ |
1518 | static int gic_irq_domain_translate(struct irq_domain *d, |
1519 | struct irq_fwspec *fwspec, | |
1520 | unsigned long *hwirq, | |
1521 | unsigned int *type) | |
021f6537 | 1522 | { |
64b499d8 MZ |
1523 | if (fwspec->param_count == 1 && fwspec->param[0] < 16) { |
1524 | *hwirq = fwspec->param[0]; | |
1525 | *type = IRQ_TYPE_EDGE_RISING; | |
1526 | return 0; | |
1527 | } | |
1528 | ||
f833f57f MZ |
1529 | if (is_of_node(fwspec->fwnode)) { |
1530 | if (fwspec->param_count < 3) | |
1531 | return -EINVAL; | |
021f6537 | 1532 | |
db8c70ec MZ |
1533 | switch (fwspec->param[0]) { |
1534 | case 0: /* SPI */ | |
1535 | *hwirq = fwspec->param[1] + 32; | |
1536 | break; | |
1537 | case 1: /* PPI */ | |
1538 | *hwirq = fwspec->param[1] + 16; | |
1539 | break; | |
211bddd2 MZ |
1540 | case 2: /* ESPI */ |
1541 | *hwirq = fwspec->param[1] + ESPI_BASE_INTID; | |
1542 | break; | |
5f51f803 MZ |
1543 | case 3: /* EPPI */ |
1544 | *hwirq = fwspec->param[1] + EPPI_BASE_INTID; | |
1545 | break; | |
db8c70ec MZ |
1546 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
1547 | *hwirq = fwspec->param[1]; | |
1548 | break; | |
5f51f803 MZ |
1549 | case GIC_IRQ_TYPE_PARTITION: |
1550 | *hwirq = fwspec->param[1]; | |
1551 | if (fwspec->param[1] >= 16) | |
1552 | *hwirq += EPPI_BASE_INTID - 16; | |
1553 | else | |
1554 | *hwirq += 16; | |
1555 | break; | |
db8c70ec MZ |
1556 | default: |
1557 | return -EINVAL; | |
1558 | } | |
f833f57f MZ |
1559 | |
1560 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
6ef6386e | 1561 | |
65da7d19 MZ |
1562 | /* |
1563 | * Make it clear that broken DTs are... broken. | |
a359f757 | 1564 | * Partitioned PPIs are an unfortunate exception. |
65da7d19 MZ |
1565 | */ |
1566 | WARN_ON(*type == IRQ_TYPE_NONE && | |
1567 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | |
f833f57f | 1568 | return 0; |
021f6537 MZ |
1569 | } |
1570 | ||
ffa7d616 TN |
1571 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
1572 | if(fwspec->param_count != 2) | |
1573 | return -EINVAL; | |
1574 | ||
544808f7 AP |
1575 | if (fwspec->param[0] < 16) { |
1576 | pr_err(FW_BUG "Illegal GSI%d translation request\n", | |
1577 | fwspec->param[0]); | |
1578 | return -EINVAL; | |
1579 | } | |
1580 | ||
ffa7d616 TN |
1581 | *hwirq = fwspec->param[0]; |
1582 | *type = fwspec->param[1]; | |
6ef6386e MZ |
1583 | |
1584 | WARN_ON(*type == IRQ_TYPE_NONE); | |
ffa7d616 TN |
1585 | return 0; |
1586 | } | |
1587 | ||
f833f57f | 1588 | return -EINVAL; |
021f6537 MZ |
1589 | } |
1590 | ||
443acc4f MZ |
1591 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1592 | unsigned int nr_irqs, void *arg) | |
1593 | { | |
1594 | int i, ret; | |
1595 | irq_hw_number_t hwirq; | |
1596 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1597 | struct irq_fwspec *fwspec = arg; |
443acc4f | 1598 | |
f833f57f | 1599 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
1600 | if (ret) |
1601 | return ret; | |
1602 | ||
63c16c6e SP |
1603 | for (i = 0; i < nr_irqs; i++) { |
1604 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1605 | if (ret) | |
1606 | return ret; | |
1607 | } | |
443acc4f MZ |
1608 | |
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
1613 | unsigned int nr_irqs) | |
1614 | { | |
1615 | int i; | |
1616 | ||
1617 | for (i = 0; i < nr_irqs; i++) { | |
1618 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
1619 | irq_set_handler(virq + i, NULL); | |
1620 | irq_domain_reset_irq_data(d); | |
1621 | } | |
1622 | } | |
1623 | ||
d753f849 JM |
1624 | static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, |
1625 | irq_hw_number_t hwirq) | |
1626 | { | |
1627 | enum gic_intid_range range; | |
1628 | ||
1629 | if (!gic_data.ppi_descs) | |
1630 | return false; | |
1631 | ||
1632 | if (!is_of_node(fwspec->fwnode)) | |
1633 | return false; | |
1634 | ||
1635 | if (fwspec->param_count < 4 || !fwspec->param[3]) | |
1636 | return false; | |
1637 | ||
1638 | range = __get_intid_range(hwirq); | |
1639 | if (range != PPI_RANGE && range != EPPI_RANGE) | |
1640 | return false; | |
1641 | ||
1642 | return true; | |
1643 | } | |
1644 | ||
e3825ba1 MZ |
1645 | static int gic_irq_domain_select(struct irq_domain *d, |
1646 | struct irq_fwspec *fwspec, | |
1647 | enum irq_domain_bus_token bus_token) | |
1648 | { | |
d753f849 JM |
1649 | unsigned int type, ret, ppi_idx; |
1650 | irq_hw_number_t hwirq; | |
1651 | ||
e3825ba1 MZ |
1652 | /* Not for us */ |
1653 | if (fwspec->fwnode != d->fwnode) | |
1654 | return 0; | |
1655 | ||
1656 | /* If this is not DT, then we have a single domain */ | |
1657 | if (!is_of_node(fwspec->fwnode)) | |
1658 | return 1; | |
1659 | ||
d753f849 JM |
1660 | ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type); |
1661 | if (WARN_ON_ONCE(ret)) | |
1662 | return 0; | |
1663 | ||
1664 | if (!fwspec_is_partitioned_ppi(fwspec, hwirq)) | |
1665 | return d == gic_data.domain; | |
1666 | ||
e3825ba1 MZ |
1667 | /* |
1668 | * If this is a PPI and we have a 4th (non-null) parameter, | |
1669 | * then we need to match the partition domain. | |
1670 | */ | |
d753f849 JM |
1671 | ppi_idx = __gic_get_ppi_index(hwirq); |
1672 | return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]); | |
e3825ba1 MZ |
1673 | } |
1674 | ||
021f6537 | 1675 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 1676 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
1677 | .alloc = gic_irq_domain_alloc, |
1678 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
1679 | .select = gic_irq_domain_select, |
1680 | }; | |
1681 | ||
1682 | static int partition_domain_translate(struct irq_domain *d, | |
1683 | struct irq_fwspec *fwspec, | |
1684 | unsigned long *hwirq, | |
1685 | unsigned int *type) | |
1686 | { | |
d753f849 | 1687 | unsigned long ppi_intid; |
e3825ba1 | 1688 | struct device_node *np; |
d753f849 | 1689 | unsigned int ppi_idx; |
e3825ba1 MZ |
1690 | int ret; |
1691 | ||
52085d3f MZ |
1692 | if (!gic_data.ppi_descs) |
1693 | return -ENOMEM; | |
1694 | ||
e3825ba1 MZ |
1695 | np = of_find_node_by_phandle(fwspec->param[3]); |
1696 | if (WARN_ON(!np)) | |
1697 | return -EINVAL; | |
1698 | ||
d753f849 JM |
1699 | ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type); |
1700 | if (WARN_ON_ONCE(ret)) | |
1701 | return 0; | |
1702 | ||
1703 | ppi_idx = __gic_get_ppi_index(ppi_intid); | |
1704 | ret = partition_translate_id(gic_data.ppi_descs[ppi_idx], | |
e3825ba1 MZ |
1705 | of_node_to_fwnode(np)); |
1706 | if (ret < 0) | |
1707 | return ret; | |
1708 | ||
1709 | *hwirq = ret; | |
1710 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1711 | ||
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | static const struct irq_domain_ops partition_domain_ops = { | |
1716 | .translate = partition_domain_translate, | |
1717 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1718 | }; |
1719 | ||
9c8114c2 SK |
1720 | static bool gic_enable_quirk_msm8996(void *data) |
1721 | { | |
1722 | struct gic_chip_data *d = data; | |
1723 | ||
1724 | d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; | |
1725 | ||
1726 | return true; | |
1727 | } | |
1728 | ||
44bd78dd DA |
1729 | static bool gic_enable_quirk_mtk_gicr(void *data) |
1730 | { | |
1731 | struct gic_chip_data *d = data; | |
1732 | ||
1733 | d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; | |
1734 | ||
1735 | return true; | |
1736 | } | |
1737 | ||
d01fd161 MZ |
1738 | static bool gic_enable_quirk_cavium_38539(void *data) |
1739 | { | |
1740 | struct gic_chip_data *d = data; | |
1741 | ||
1742 | d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; | |
1743 | ||
1744 | return true; | |
1745 | } | |
1746 | ||
7f2481b3 MZ |
1747 | static bool gic_enable_quirk_hip06_07(void *data) |
1748 | { | |
1749 | struct gic_chip_data *d = data; | |
1750 | ||
1751 | /* | |
1752 | * HIP06 GICD_IIDR clashes with GIC-600 product number (despite | |
1753 | * not being an actual ARM implementation). The saving grace is | |
1754 | * that GIC-600 doesn't have ESPI, so nothing to do in that case. | |
1755 | * HIP07 doesn't even have a proper IIDR, and still pretends to | |
1756 | * have ESPI. In both cases, put them right. | |
1757 | */ | |
1758 | if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { | |
1759 | /* Zero both ESPI and the RES0 field next to it... */ | |
1760 | d->rdists.gicd_typer &= ~GENMASK(9, 8); | |
1761 | return true; | |
1762 | } | |
1763 | ||
1764 | return false; | |
1765 | } | |
1766 | ||
35727af2 SD |
1767 | #define T241_CHIPN_MASK GENMASK_ULL(45, 44) |
1768 | #define T241_CHIP_GICDA_OFFSET 0x1580000 | |
1769 | #define SMCCC_SOC_ID_T241 0x036b0241 | |
1770 | ||
1771 | static bool gic_enable_quirk_nvidia_t241(void *data) | |
1772 | { | |
1773 | s32 soc_id = arm_smccc_get_soc_id_version(); | |
1774 | unsigned long chip_bmask = 0; | |
1775 | phys_addr_t phys; | |
1776 | u32 i; | |
1777 | ||
1778 | /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */ | |
1779 | if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241)) | |
1780 | return false; | |
1781 | ||
1782 | /* Find the chips based on GICR regions PHYS addr */ | |
1783 | for (i = 0; i < gic_data.nr_redist_regions; i++) { | |
1784 | chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK, | |
1785 | (u64)gic_data.redist_regions[i].phys_base)); | |
1786 | } | |
1787 | ||
1788 | if (hweight32(chip_bmask) < 3) | |
1789 | return false; | |
1790 | ||
1791 | /* Setup GICD alias regions */ | |
1792 | for (i = 0; i < ARRAY_SIZE(t241_dist_base_alias); i++) { | |
1793 | if (chip_bmask & BIT(i)) { | |
1794 | phys = gic_data.dist_phys_base + T241_CHIP_GICDA_OFFSET; | |
1795 | phys |= FIELD_PREP(T241_CHIPN_MASK, i); | |
1796 | t241_dist_base_alias[i] = ioremap(phys, SZ_64K); | |
1797 | WARN_ON_ONCE(!t241_dist_base_alias[i]); | |
1798 | } | |
1799 | } | |
1800 | static_branch_enable(&gic_nvidia_t241_erratum); | |
1801 | return true; | |
1802 | } | |
1803 | ||
7f2481b3 MZ |
1804 | static const struct gic_quirk gic_quirks[] = { |
1805 | { | |
1806 | .desc = "GICv3: Qualcomm MSM8996 broken firmware", | |
1807 | .compatible = "qcom,msm8996-gic-v3", | |
1808 | .init = gic_enable_quirk_msm8996, | |
1809 | }, | |
44bd78dd DA |
1810 | { |
1811 | .desc = "GICv3: Mediatek Chromebook GICR save problem", | |
1812 | .property = "mediatek,broken-save-restore-fw", | |
1813 | .init = gic_enable_quirk_mtk_gicr, | |
1814 | }, | |
7f2481b3 MZ |
1815 | { |
1816 | .desc = "GICv3: HIP06 erratum 161010803", | |
1817 | .iidr = 0x0204043b, | |
1818 | .mask = 0xffffffff, | |
1819 | .init = gic_enable_quirk_hip06_07, | |
1820 | }, | |
1821 | { | |
1822 | .desc = "GICv3: HIP07 erratum 161010803", | |
1823 | .iidr = 0x00000000, | |
1824 | .mask = 0xffffffff, | |
1825 | .init = gic_enable_quirk_hip06_07, | |
1826 | }, | |
d01fd161 MZ |
1827 | { |
1828 | /* | |
1829 | * Reserved register accesses generate a Synchronous | |
1830 | * External Abort. This erratum applies to: | |
1831 | * - ThunderX: CN88xx | |
1832 | * - OCTEON TX: CN83xx, CN81xx | |
1833 | * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* | |
1834 | */ | |
1835 | .desc = "GICv3: Cavium erratum 38539", | |
1836 | .iidr = 0xa000034c, | |
1837 | .mask = 0xe8f00fff, | |
1838 | .init = gic_enable_quirk_cavium_38539, | |
1839 | }, | |
35727af2 SD |
1840 | { |
1841 | .desc = "GICv3: NVIDIA erratum T241-FABRIC-4", | |
1842 | .iidr = 0x0402043b, | |
1843 | .mask = 0xffffffff, | |
1844 | .init = gic_enable_quirk_nvidia_t241, | |
1845 | }, | |
7f2481b3 MZ |
1846 | { |
1847 | } | |
1848 | }; | |
1849 | ||
d98d0a99 JT |
1850 | static void gic_enable_nmi_support(void) |
1851 | { | |
101b35f7 JT |
1852 | int i; |
1853 | ||
81a43273 MZ |
1854 | if (!gic_prio_masking_enabled()) |
1855 | return; | |
1856 | ||
44bd78dd DA |
1857 | if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) { |
1858 | pr_warn("Skipping NMI enable due to firmware issues\n"); | |
1859 | return; | |
1860 | } | |
1861 | ||
81a43273 MZ |
1862 | ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); |
1863 | if (!ppi_nmi_refs) | |
1864 | return; | |
1865 | ||
1866 | for (i = 0; i < gic_data.ppi_nr; i++) | |
101b35f7 JT |
1867 | refcount_set(&ppi_nmi_refs[i], 0); |
1868 | ||
4e594ad1 | 1869 | pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", |
8bf0a804 | 1870 | gic_has_relaxed_pmr_sync() ? "relaxed" : "forced"); |
f2266504 | 1871 | |
33678059 AE |
1872 | /* |
1873 | * How priority values are used by the GIC depends on two things: | |
1874 | * the security state of the GIC (controlled by the GICD_CTRL.DS bit) | |
1875 | * and if Group 0 interrupts can be delivered to Linux in the non-secure | |
1876 | * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the | |
29517170 | 1877 | * ICC_PMR_EL1 register and the priority that software assigns to |
33678059 AE |
1878 | * interrupts: |
1879 | * | |
1880 | * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority | |
1881 | * ----------------------------------------------------------- | |
1882 | * 1 | - | unchanged | unchanged | |
1883 | * ----------------------------------------------------------- | |
1884 | * 0 | 1 | non-secure | non-secure | |
1885 | * ----------------------------------------------------------- | |
1886 | * 0 | 0 | unchanged | non-secure | |
1887 | * | |
1888 | * where non-secure means that the value is right-shifted by one and the | |
1889 | * MSB bit set, to make it fit in the non-secure priority range. | |
1890 | * | |
1891 | * In the first two cases, where ICC_PMR_EL1 and the interrupt priority | |
1892 | * are both either modified or unchanged, we can use the same set of | |
1893 | * priorities. | |
1894 | * | |
1895 | * In the last case, where only the interrupt priorities are modified to | |
1896 | * be in the non-secure range, we use a different PMR value to mask IRQs | |
1897 | * and the rest of the values that we use remain unchanged. | |
1898 | */ | |
1899 | if (gic_has_group0() && !gic_dist_security_disabled()) | |
1900 | static_branch_enable(&gic_nonsecure_priorities); | |
1901 | ||
d98d0a99 | 1902 | static_branch_enable(&supports_pseudo_nmis); |
101b35f7 JT |
1903 | |
1904 | if (static_branch_likely(&supports_deactivate_key)) | |
1905 | gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
1906 | else | |
1907 | gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
d98d0a99 JT |
1908 | } |
1909 | ||
35727af2 SD |
1910 | static int __init gic_init_bases(phys_addr_t dist_phys_base, |
1911 | void __iomem *dist_base, | |
db57d746 TN |
1912 | struct redist_region *rdist_regs, |
1913 | u32 nr_redist_regions, | |
1914 | u64 redist_stride, | |
1915 | struct fwnode_handle *handle) | |
021f6537 | 1916 | { |
f5c1434c | 1917 | u32 typer; |
021f6537 | 1918 | int err; |
021f6537 | 1919 | |
0b6a3da9 | 1920 | if (!is_hyp_mode_available()) |
d01d3274 | 1921 | static_branch_disable(&supports_deactivate_key); |
0b6a3da9 | 1922 | |
d01d3274 | 1923 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1924 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
1925 | ||
e3825ba1 | 1926 | gic_data.fwnode = handle; |
35727af2 | 1927 | gic_data.dist_phys_base = dist_phys_base; |
021f6537 | 1928 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
1929 | gic_data.redist_regions = rdist_regs; |
1930 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
1931 | gic_data.redist_stride = redist_stride; |
1932 | ||
1933 | /* | |
1934 | * Find out how many interrupts are supported. | |
021f6537 | 1935 | */ |
f5c1434c | 1936 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
a4f9edb2 | 1937 | gic_data.rdists.gicd_typer = typer; |
7f2481b3 MZ |
1938 | |
1939 | gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), | |
1940 | gic_quirks, &gic_data); | |
1941 | ||
211bddd2 MZ |
1942 | pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); |
1943 | pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); | |
f2d83409 | 1944 | |
d01fd161 MZ |
1945 | /* |
1946 | * ThunderX1 explodes on reading GICD_TYPER2, in violation of the | |
1947 | * architecture spec (which says that reserved registers are RES0). | |
1948 | */ | |
1949 | if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) | |
1950 | gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); | |
f2d83409 | 1951 | |
db57d746 TN |
1952 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
1953 | &gic_data); | |
f5c1434c | 1954 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
35727af2 SD |
1955 | if (!static_branch_unlikely(&gic_nvidia_t241_erratum)) { |
1956 | /* Disable GICv4.x features for the erratum T241-FABRIC-4 */ | |
1957 | gic_data.rdists.has_rvpeid = true; | |
1958 | gic_data.rdists.has_vlpis = true; | |
1959 | gic_data.rdists.has_direct_lpi = true; | |
1960 | gic_data.rdists.has_vpend_valid_dirty = true; | |
1961 | } | |
021f6537 | 1962 | |
f5c1434c | 1963 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
1964 | err = -ENOMEM; |
1965 | goto out_free; | |
1966 | } | |
1967 | ||
eeaa4b24 | 1968 | irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); |
1969 | ||
eda0d04a | 1970 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
eda0d04a | 1971 | |
50528752 MZ |
1972 | if (typer & GICD_TYPER_MBIS) { |
1973 | err = mbi_init(handle, gic_data.domain); | |
1974 | if (err) | |
1975 | pr_err("Failed to initialize MBIs\n"); | |
1976 | } | |
1977 | ||
021f6537 MZ |
1978 | set_handle_irq(gic_handle_irq); |
1979 | ||
1a60e1e6 | 1980 | gic_update_rdist_properties(); |
0edc23ea | 1981 | |
021f6537 MZ |
1982 | gic_dist_init(); |
1983 | gic_cpu_init(); | |
64b499d8 | 1984 | gic_smp_init(); |
3708d52f | 1985 | gic_cpu_pm_init(); |
021f6537 | 1986 | |
d38a71c5 MZ |
1987 | if (gic_dist_supports_lpis()) { |
1988 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
1989 | its_cpu_init(); | |
d23bc2bc | 1990 | its_lpi_memreserve_init(); |
90b4c555 ZZ |
1991 | } else { |
1992 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1993 | gicv2m_init(handle, gic_data.domain); | |
d38a71c5 MZ |
1994 | } |
1995 | ||
81a43273 | 1996 | gic_enable_nmi_support(); |
d98d0a99 | 1997 | |
021f6537 MZ |
1998 | return 0; |
1999 | ||
2000 | out_free: | |
2001 | if (gic_data.domain) | |
2002 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 2003 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
2004 | return err; |
2005 | } | |
2006 | ||
2007 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
2008 | { | |
2009 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
2010 | ||
2011 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
2012 | return -ENODEV; | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
e3825ba1 | 2017 | /* Create all possible partitions at boot time */ |
7beaa24b | 2018 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
2019 | { |
2020 | struct device_node *parts_node, *child_part; | |
2021 | int part_idx = 0, i; | |
2022 | int nr_parts; | |
2023 | struct partition_affinity *parts; | |
2024 | ||
00ee9a1c | 2025 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
2026 | if (!parts_node) |
2027 | return; | |
2028 | ||
52085d3f MZ |
2029 | gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); |
2030 | if (!gic_data.ppi_descs) | |
ec8401a4 | 2031 | goto out_put_node; |
52085d3f | 2032 | |
e3825ba1 MZ |
2033 | nr_parts = of_get_child_count(parts_node); |
2034 | ||
2035 | if (!nr_parts) | |
00ee9a1c | 2036 | goto out_put_node; |
e3825ba1 | 2037 | |
6396bb22 | 2038 | parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); |
e3825ba1 | 2039 | if (WARN_ON(!parts)) |
00ee9a1c | 2040 | goto out_put_node; |
e3825ba1 MZ |
2041 | |
2042 | for_each_child_of_node(parts_node, child_part) { | |
2043 | struct partition_affinity *part; | |
2044 | int n; | |
2045 | ||
2046 | part = &parts[part_idx]; | |
2047 | ||
2048 | part->partition_id = of_node_to_fwnode(child_part); | |
2049 | ||
2ef790dc RH |
2050 | pr_info("GIC: PPI partition %pOFn[%d] { ", |
2051 | child_part, part_idx); | |
e3825ba1 MZ |
2052 | |
2053 | n = of_property_count_elems_of_size(child_part, "affinity", | |
2054 | sizeof(u32)); | |
2055 | WARN_ON(n <= 0); | |
2056 | ||
2057 | for (i = 0; i < n; i++) { | |
2058 | int err, cpu; | |
2059 | u32 cpu_phandle; | |
2060 | struct device_node *cpu_node; | |
2061 | ||
2062 | err = of_property_read_u32_index(child_part, "affinity", | |
2063 | i, &cpu_phandle); | |
2064 | if (WARN_ON(err)) | |
2065 | continue; | |
2066 | ||
2067 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
2068 | if (WARN_ON(!cpu_node)) | |
2069 | continue; | |
2070 | ||
c08ec7da | 2071 | cpu = of_cpu_node_to_id(cpu_node); |
fa1ad9d4 ML |
2072 | if (WARN_ON(cpu < 0)) { |
2073 | of_node_put(cpu_node); | |
e3825ba1 | 2074 | continue; |
fa1ad9d4 | 2075 | } |
e3825ba1 | 2076 | |
e81f54c6 | 2077 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
2078 | |
2079 | cpumask_set_cpu(cpu, &part->mask); | |
fa1ad9d4 | 2080 | of_node_put(cpu_node); |
e3825ba1 MZ |
2081 | } |
2082 | ||
2083 | pr_cont("}\n"); | |
2084 | part_idx++; | |
2085 | } | |
2086 | ||
52085d3f | 2087 | for (i = 0; i < gic_data.ppi_nr; i++) { |
e3825ba1 MZ |
2088 | unsigned int irq; |
2089 | struct partition_desc *desc; | |
2090 | struct irq_fwspec ppi_fwspec = { | |
2091 | .fwnode = gic_data.fwnode, | |
2092 | .param_count = 3, | |
2093 | .param = { | |
65da7d19 | 2094 | [0] = GIC_IRQ_TYPE_PARTITION, |
e3825ba1 MZ |
2095 | [1] = i, |
2096 | [2] = IRQ_TYPE_NONE, | |
2097 | }, | |
2098 | }; | |
2099 | ||
2100 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
2101 | if (WARN_ON(!irq)) | |
2102 | continue; | |
2103 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
2104 | irq, &partition_domain_ops); | |
2105 | if (WARN_ON(!desc)) | |
2106 | continue; | |
2107 | ||
2108 | gic_data.ppi_descs[i] = desc; | |
2109 | } | |
00ee9a1c JH |
2110 | |
2111 | out_put_node: | |
2112 | of_node_put(parts_node); | |
e3825ba1 MZ |
2113 | } |
2114 | ||
1839e576 JG |
2115 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
2116 | { | |
2117 | int ret; | |
2118 | struct resource r; | |
2119 | u32 gicv_idx; | |
2120 | ||
2121 | gic_v3_kvm_info.type = GIC_V3; | |
2122 | ||
2123 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
2124 | if (!gic_v3_kvm_info.maint_irq) | |
2125 | return; | |
2126 | ||
2127 | if (of_property_read_u32(node, "#redistributor-regions", | |
2128 | &gicv_idx)) | |
2129 | gicv_idx = 1; | |
2130 | ||
2131 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
2132 | ret = of_address_to_resource(node, gicv_idx, &r); | |
2133 | if (!ret) | |
2134 | gic_v3_kvm_info.vcpu = r; | |
2135 | ||
4bdf5025 | 2136 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 2137 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
0e5cb777 | 2138 | vgic_set_kvm_info(&gic_v3_kvm_info); |
1839e576 JG |
2139 | } |
2140 | ||
4deb96e3 RM |
2141 | static void gic_request_region(resource_size_t base, resource_size_t size, |
2142 | const char *name) | |
2143 | { | |
2144 | if (!request_mem_region(base, size, name)) | |
2145 | pr_warn_once(FW_BUG "%s region %pa has overlapping address\n", | |
2146 | name, &base); | |
2147 | } | |
2148 | ||
2149 | static void __iomem *gic_of_iomap(struct device_node *node, int idx, | |
2150 | const char *name, struct resource *res) | |
2151 | { | |
2152 | void __iomem *base; | |
2153 | int ret; | |
2154 | ||
2155 | ret = of_address_to_resource(node, idx, res); | |
2156 | if (ret) | |
2157 | return IOMEM_ERR_PTR(ret); | |
2158 | ||
2159 | gic_request_region(res->start, resource_size(res), name); | |
2160 | base = of_iomap(node, idx); | |
2161 | ||
2162 | return base ?: IOMEM_ERR_PTR(-ENOMEM); | |
2163 | } | |
2164 | ||
db57d746 TN |
2165 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
2166 | { | |
35727af2 | 2167 | phys_addr_t dist_phys_base; |
db57d746 TN |
2168 | void __iomem *dist_base; |
2169 | struct redist_region *rdist_regs; | |
4deb96e3 | 2170 | struct resource res; |
db57d746 TN |
2171 | u64 redist_stride; |
2172 | u32 nr_redist_regions; | |
2173 | int err, i; | |
2174 | ||
4deb96e3 | 2175 | dist_base = gic_of_iomap(node, 0, "GICD", &res); |
2b2cd74a | 2176 | if (IS_ERR(dist_base)) { |
e81f54c6 | 2177 | pr_err("%pOF: unable to map gic dist registers\n", node); |
2b2cd74a | 2178 | return PTR_ERR(dist_base); |
db57d746 TN |
2179 | } |
2180 | ||
35727af2 SD |
2181 | dist_phys_base = res.start; |
2182 | ||
db57d746 TN |
2183 | err = gic_validate_dist_version(dist_base); |
2184 | if (err) { | |
e81f54c6 | 2185 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
2186 | goto out_unmap_dist; |
2187 | } | |
2188 | ||
2189 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
2190 | nr_redist_regions = 1; | |
2191 | ||
6396bb22 KC |
2192 | rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), |
2193 | GFP_KERNEL); | |
db57d746 TN |
2194 | if (!rdist_regs) { |
2195 | err = -ENOMEM; | |
2196 | goto out_unmap_dist; | |
2197 | } | |
2198 | ||
2199 | for (i = 0; i < nr_redist_regions; i++) { | |
4deb96e3 RM |
2200 | rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res); |
2201 | if (IS_ERR(rdist_regs[i].redist_base)) { | |
e81f54c6 | 2202 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
2203 | err = -ENODEV; |
2204 | goto out_unmap_rdist; | |
2205 | } | |
2206 | rdist_regs[i].phys_base = res.start; | |
2207 | } | |
2208 | ||
2209 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
2210 | redist_stride = 0; | |
2211 | ||
f70fdb42 SK |
2212 | gic_enable_of_quirks(node, gic_quirks, &gic_data); |
2213 | ||
35727af2 SD |
2214 | err = gic_init_bases(dist_phys_base, dist_base, rdist_regs, |
2215 | nr_redist_regions, redist_stride, &node->fwnode); | |
e3825ba1 MZ |
2216 | if (err) |
2217 | goto out_unmap_rdist; | |
2218 | ||
2219 | gic_populate_ppi_partitions(node); | |
d33a3c8c | 2220 | |
d01d3274 | 2221 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 2222 | gic_of_setup_kvm_info(node); |
e3825ba1 | 2223 | return 0; |
db57d746 | 2224 | |
021f6537 | 2225 | out_unmap_rdist: |
f5c1434c | 2226 | for (i = 0; i < nr_redist_regions; i++) |
2b2cd74a | 2227 | if (rdist_regs[i].redist_base && !IS_ERR(rdist_regs[i].redist_base)) |
f5c1434c MZ |
2228 | iounmap(rdist_regs[i].redist_base); |
2229 | kfree(rdist_regs); | |
021f6537 MZ |
2230 | out_unmap_dist: |
2231 | iounmap(dist_base); | |
2232 | return err; | |
2233 | } | |
2234 | ||
2235 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
2236 | |
2237 | #ifdef CONFIG_ACPI | |
611f039f JG |
2238 | static struct |
2239 | { | |
2240 | void __iomem *dist_base; | |
2241 | struct redist_region *redist_regs; | |
2242 | u32 nr_redist_regions; | |
2243 | bool single_redist; | |
926b5dfa | 2244 | int enabled_rdists; |
1839e576 JG |
2245 | u32 maint_irq; |
2246 | int maint_irq_mode; | |
2247 | phys_addr_t vcpu_base; | |
611f039f | 2248 | } acpi_data __initdata; |
b70fb7af TN |
2249 | |
2250 | static void __init | |
2251 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
2252 | { | |
2253 | static int count = 0; | |
2254 | ||
611f039f JG |
2255 | acpi_data.redist_regs[count].phys_base = phys_base; |
2256 | acpi_data.redist_regs[count].redist_base = redist_base; | |
2257 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
2258 | count++; |
2259 | } | |
ffa7d616 TN |
2260 | |
2261 | static int __init | |
60574d1e | 2262 | gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, |
ffa7d616 TN |
2263 | const unsigned long end) |
2264 | { | |
2265 | struct acpi_madt_generic_redistributor *redist = | |
2266 | (struct acpi_madt_generic_redistributor *)header; | |
2267 | void __iomem *redist_base; | |
ffa7d616 TN |
2268 | |
2269 | redist_base = ioremap(redist->base_address, redist->length); | |
2270 | if (!redist_base) { | |
2271 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
2272 | return -ENOMEM; | |
2273 | } | |
4deb96e3 | 2274 | gic_request_region(redist->base_address, redist->length, "GICR"); |
ffa7d616 | 2275 | |
b70fb7af | 2276 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
2277 | return 0; |
2278 | } | |
2279 | ||
b70fb7af | 2280 | static int __init |
60574d1e | 2281 | gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
2282 | const unsigned long end) |
2283 | { | |
2284 | struct acpi_madt_generic_interrupt *gicc = | |
2285 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 2286 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
2287 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
2288 | void __iomem *redist_base; | |
2289 | ||
ebe2f871 SD |
2290 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
2291 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2292 | return 0; | |
2293 | ||
b70fb7af TN |
2294 | redist_base = ioremap(gicc->gicr_base_address, size); |
2295 | if (!redist_base) | |
2296 | return -ENOMEM; | |
4deb96e3 | 2297 | gic_request_region(gicc->gicr_base_address, size, "GICR"); |
b70fb7af TN |
2298 | |
2299 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | static int __init gic_acpi_collect_gicr_base(void) | |
2304 | { | |
2305 | acpi_tbl_entry_handler redist_parser; | |
2306 | enum acpi_madt_type type; | |
2307 | ||
611f039f | 2308 | if (acpi_data.single_redist) { |
b70fb7af TN |
2309 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
2310 | redist_parser = gic_acpi_parse_madt_gicc; | |
2311 | } else { | |
2312 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
2313 | redist_parser = gic_acpi_parse_madt_redist; | |
2314 | } | |
2315 | ||
2316 | /* Collect redistributor base addresses in GICR entries */ | |
2317 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
2318 | return 0; | |
2319 | ||
2320 | pr_info("No valid GICR entries exist\n"); | |
2321 | return -ENODEV; | |
2322 | } | |
2323 | ||
60574d1e | 2324 | static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, |
ffa7d616 TN |
2325 | const unsigned long end) |
2326 | { | |
2327 | /* Subtable presence means that redist exists, that's it */ | |
2328 | return 0; | |
2329 | } | |
2330 | ||
60574d1e | 2331 | static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
2332 | const unsigned long end) |
2333 | { | |
2334 | struct acpi_madt_generic_interrupt *gicc = | |
2335 | (struct acpi_madt_generic_interrupt *)header; | |
2336 | ||
2337 | /* | |
2338 | * If GICC is enabled and has valid gicr base address, then it means | |
2339 | * GICR base is presented via GICC | |
2340 | */ | |
926b5dfa MZ |
2341 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { |
2342 | acpi_data.enabled_rdists++; | |
b70fb7af | 2343 | return 0; |
926b5dfa | 2344 | } |
b70fb7af | 2345 | |
ebe2f871 SD |
2346 | /* |
2347 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
2348 | * should not treat as errors, skip the entry instead of probe fail. | |
2349 | */ | |
2350 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2351 | return 0; | |
2352 | ||
b70fb7af TN |
2353 | return -ENODEV; |
2354 | } | |
2355 | ||
2356 | static int __init gic_acpi_count_gicr_regions(void) | |
2357 | { | |
2358 | int count; | |
2359 | ||
2360 | /* | |
2361 | * Count how many redistributor regions we have. It is not allowed | |
2362 | * to mix redistributor description, GICR and GICC subtables have to be | |
2363 | * mutually exclusive. | |
2364 | */ | |
2365 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
2366 | gic_acpi_match_gicr, 0); | |
2367 | if (count > 0) { | |
611f039f | 2368 | acpi_data.single_redist = false; |
b70fb7af TN |
2369 | return count; |
2370 | } | |
2371 | ||
2372 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2373 | gic_acpi_match_gicc, 0); | |
926b5dfa | 2374 | if (count > 0) { |
611f039f | 2375 | acpi_data.single_redist = true; |
926b5dfa MZ |
2376 | count = acpi_data.enabled_rdists; |
2377 | } | |
b70fb7af TN |
2378 | |
2379 | return count; | |
2380 | } | |
2381 | ||
ffa7d616 TN |
2382 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
2383 | struct acpi_probe_entry *ape) | |
2384 | { | |
2385 | struct acpi_madt_generic_distributor *dist; | |
2386 | int count; | |
2387 | ||
2388 | dist = (struct acpi_madt_generic_distributor *)header; | |
2389 | if (dist->version != ape->driver_data) | |
2390 | return false; | |
2391 | ||
2392 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 2393 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
2394 | if (count <= 0) |
2395 | return false; | |
2396 | ||
611f039f | 2397 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
2398 | return true; |
2399 | } | |
2400 | ||
60574d1e | 2401 | static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, |
1839e576 JG |
2402 | const unsigned long end) |
2403 | { | |
2404 | struct acpi_madt_generic_interrupt *gicc = | |
2405 | (struct acpi_madt_generic_interrupt *)header; | |
2406 | int maint_irq_mode; | |
2407 | static int first_madt = true; | |
2408 | ||
2409 | /* Skip unusable CPUs */ | |
2410 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2411 | return 0; | |
2412 | ||
2413 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
2414 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
2415 | ||
2416 | if (first_madt) { | |
2417 | first_madt = false; | |
2418 | ||
2419 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
2420 | acpi_data.maint_irq_mode = maint_irq_mode; | |
2421 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
2422 | ||
2423 | return 0; | |
2424 | } | |
2425 | ||
2426 | /* | |
2427 | * The maintenance interrupt and GICV should be the same for every CPU | |
2428 | */ | |
2429 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
2430 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
2431 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
2432 | return -EINVAL; | |
2433 | ||
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | static bool __init gic_acpi_collect_virt_info(void) | |
2438 | { | |
2439 | int count; | |
2440 | ||
2441 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2442 | gic_acpi_parse_virt_madt_gicc, 0); | |
2443 | ||
2444 | return (count > 0); | |
2445 | } | |
2446 | ||
ffa7d616 | 2447 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
2448 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
2449 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
2450 | ||
2451 | static void __init gic_acpi_setup_kvm_info(void) | |
2452 | { | |
2453 | int irq; | |
2454 | ||
2455 | if (!gic_acpi_collect_virt_info()) { | |
2456 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
2457 | return; | |
2458 | } | |
2459 | ||
2460 | gic_v3_kvm_info.type = GIC_V3; | |
2461 | ||
2462 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
2463 | acpi_data.maint_irq_mode, | |
2464 | ACPI_ACTIVE_HIGH); | |
2465 | if (irq <= 0) | |
2466 | return; | |
2467 | ||
2468 | gic_v3_kvm_info.maint_irq = irq; | |
2469 | ||
2470 | if (acpi_data.vcpu_base) { | |
2471 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
2472 | ||
2473 | vcpu->flags = IORESOURCE_MEM; | |
2474 | vcpu->start = acpi_data.vcpu_base; | |
2475 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
2476 | } | |
2477 | ||
4bdf5025 | 2478 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 2479 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
0e5cb777 | 2480 | vgic_set_kvm_info(&gic_v3_kvm_info); |
1839e576 | 2481 | } |
ffa7d616 | 2482 | |
7327b16f MZ |
2483 | static struct fwnode_handle *gsi_domain_handle; |
2484 | ||
2485 | static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi) | |
2486 | { | |
2487 | return gsi_domain_handle; | |
2488 | } | |
2489 | ||
ffa7d616 | 2490 | static int __init |
aba3c7ed | 2491 | gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) |
ffa7d616 TN |
2492 | { |
2493 | struct acpi_madt_generic_distributor *dist; | |
611f039f | 2494 | size_t size; |
b70fb7af | 2495 | int i, err; |
ffa7d616 TN |
2496 | |
2497 | /* Get distributor base address */ | |
2498 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
2499 | acpi_data.dist_base = ioremap(dist->base_address, |
2500 | ACPI_GICV3_DIST_MEM_SIZE); | |
2501 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
2502 | pr_err("Unable to map GICD registers\n"); |
2503 | return -ENOMEM; | |
2504 | } | |
4deb96e3 | 2505 | gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); |
ffa7d616 | 2506 | |
611f039f | 2507 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 2508 | if (err) { |
71192a68 | 2509 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 2510 | acpi_data.dist_base); |
ffa7d616 TN |
2511 | goto out_dist_unmap; |
2512 | } | |
2513 | ||
611f039f JG |
2514 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
2515 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
2516 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
2517 | err = -ENOMEM; |
2518 | goto out_dist_unmap; | |
2519 | } | |
2520 | ||
b70fb7af TN |
2521 | err = gic_acpi_collect_gicr_base(); |
2522 | if (err) | |
ffa7d616 | 2523 | goto out_redist_unmap; |
ffa7d616 | 2524 | |
7327b16f MZ |
2525 | gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address); |
2526 | if (!gsi_domain_handle) { | |
ffa7d616 TN |
2527 | err = -ENOMEM; |
2528 | goto out_redist_unmap; | |
2529 | } | |
2530 | ||
35727af2 SD |
2531 | err = gic_init_bases(dist->base_address, acpi_data.dist_base, |
2532 | acpi_data.redist_regs, acpi_data.nr_redist_regions, | |
2533 | 0, gsi_domain_handle); | |
ffa7d616 TN |
2534 | if (err) |
2535 | goto out_fwhandle_free; | |
2536 | ||
7327b16f | 2537 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id); |
d33a3c8c | 2538 | |
d01d3274 | 2539 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 2540 | gic_acpi_setup_kvm_info(); |
1839e576 | 2541 | |
ffa7d616 TN |
2542 | return 0; |
2543 | ||
2544 | out_fwhandle_free: | |
7327b16f | 2545 | irq_domain_free_fwnode(gsi_domain_handle); |
ffa7d616 | 2546 | out_redist_unmap: |
611f039f JG |
2547 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
2548 | if (acpi_data.redist_regs[i].redist_base) | |
2549 | iounmap(acpi_data.redist_regs[i].redist_base); | |
2550 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 2551 | out_dist_unmap: |
611f039f | 2552 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
2553 | return err; |
2554 | } | |
2555 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2556 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
2557 | gic_acpi_init); | |
2558 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2559 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
2560 | gic_acpi_init); | |
2561 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2562 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
2563 | gic_acpi_init); | |
2564 | #endif |