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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/cpu.h> | |
3708d52f | 19 | #include <linux/cpu_pm.h> |
021f6537 MZ |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/percpu.h> | |
26 | #include <linux/slab.h> | |
27 | ||
41a83e06 | 28 | #include <linux/irqchip.h> |
021f6537 MZ |
29 | #include <linux/irqchip/arm-gic-v3.h> |
30 | ||
31 | #include <asm/cputype.h> | |
32 | #include <asm/exception.h> | |
33 | #include <asm/smp_plat.h> | |
0b6a3da9 | 34 | #include <asm/virt.h> |
021f6537 MZ |
35 | |
36 | #include "irq-gic-common.h" | |
021f6537 | 37 | |
f5c1434c MZ |
38 | struct redist_region { |
39 | void __iomem *redist_base; | |
40 | phys_addr_t phys_base; | |
41 | }; | |
42 | ||
021f6537 MZ |
43 | struct gic_chip_data { |
44 | void __iomem *dist_base; | |
f5c1434c MZ |
45 | struct redist_region *redist_regions; |
46 | struct rdists rdists; | |
021f6537 MZ |
47 | struct irq_domain *domain; |
48 | u64 redist_stride; | |
f5c1434c | 49 | u32 nr_redist_regions; |
021f6537 MZ |
50 | unsigned int irq_nr; |
51 | }; | |
52 | ||
53 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 54 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 55 | |
f5c1434c MZ |
56 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
57 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
58 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
59 | ||
60 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
61 | #define DEFAULT_PMR_VALUE 0xf0 | |
62 | ||
63 | static inline unsigned int gic_irq(struct irq_data *d) | |
64 | { | |
65 | return d->hwirq; | |
66 | } | |
67 | ||
68 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
69 | { | |
70 | return gic_irq(d) < 32; | |
71 | } | |
72 | ||
73 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
74 | { | |
75 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
76 | return gic_data_rdist_sgi_base(); | |
77 | ||
78 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
79 | return gic_data.dist_base; | |
80 | ||
021f6537 MZ |
81 | return NULL; |
82 | } | |
83 | ||
84 | static void gic_do_wait_for_rwp(void __iomem *base) | |
85 | { | |
86 | u32 count = 1000000; /* 1s! */ | |
87 | ||
88 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
89 | count--; | |
90 | if (!count) { | |
91 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
92 | return; | |
93 | } | |
94 | cpu_relax(); | |
95 | udelay(1); | |
96 | }; | |
97 | } | |
98 | ||
99 | /* Wait for completion of a distributor change */ | |
100 | static void gic_dist_wait_for_rwp(void) | |
101 | { | |
102 | gic_do_wait_for_rwp(gic_data.dist_base); | |
103 | } | |
104 | ||
105 | /* Wait for completion of a redistributor change */ | |
106 | static void gic_redist_wait_for_rwp(void) | |
107 | { | |
108 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
109 | } | |
110 | ||
111 | /* Low level accessors */ | |
c44e9d77 | 112 | static u64 __maybe_unused gic_read_iar(void) |
021f6537 MZ |
113 | { |
114 | u64 irqstat; | |
115 | ||
72c58395 | 116 | asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); |
021f6537 MZ |
117 | return irqstat; |
118 | } | |
119 | ||
c44e9d77 | 120 | static void __maybe_unused gic_write_pmr(u64 val) |
021f6537 | 121 | { |
72c58395 | 122 | asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
123 | } |
124 | ||
c44e9d77 | 125 | static void __maybe_unused gic_write_ctlr(u64 val) |
021f6537 | 126 | { |
72c58395 | 127 | asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
128 | isb(); |
129 | } | |
130 | ||
c44e9d77 | 131 | static void __maybe_unused gic_write_grpen1(u64 val) |
021f6537 | 132 | { |
72c58395 | 133 | asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
134 | isb(); |
135 | } | |
136 | ||
c44e9d77 | 137 | static void __maybe_unused gic_write_sgi1r(u64 val) |
021f6537 | 138 | { |
72c58395 | 139 | asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
140 | } |
141 | ||
142 | static void gic_enable_sre(void) | |
143 | { | |
144 | u64 val; | |
145 | ||
72c58395 | 146 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 | 147 | val |= ICC_SRE_EL1_SRE; |
72c58395 | 148 | asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
149 | isb(); |
150 | ||
151 | /* | |
152 | * Need to check that the SRE bit has actually been set. If | |
153 | * not, it means that SRE is disabled at EL2. We're going to | |
154 | * die painfully, and there is nothing we can do about it. | |
155 | * | |
156 | * Kindly inform the luser. | |
157 | */ | |
72c58395 | 158 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 MZ |
159 | if (!(val & ICC_SRE_EL1_SRE)) |
160 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
161 | } | |
162 | ||
a2c22510 | 163 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
164 | { |
165 | void __iomem *rbase; | |
166 | u32 count = 1000000; /* 1s! */ | |
167 | u32 val; | |
168 | ||
169 | rbase = gic_data_rdist_rd_base(); | |
170 | ||
021f6537 | 171 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
172 | if (enable) |
173 | /* Wake up this CPU redistributor */ | |
174 | val &= ~GICR_WAKER_ProcessorSleep; | |
175 | else | |
176 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
177 | writel_relaxed(val, rbase + GICR_WAKER); |
178 | ||
a2c22510 SH |
179 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
180 | val = readl_relaxed(rbase + GICR_WAKER); | |
181 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
182 | return; /* No PM support in this redistributor */ | |
183 | } | |
184 | ||
185 | while (count--) { | |
186 | val = readl_relaxed(rbase + GICR_WAKER); | |
187 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
188 | break; | |
021f6537 MZ |
189 | cpu_relax(); |
190 | udelay(1); | |
191 | }; | |
a2c22510 SH |
192 | if (!count) |
193 | pr_err_ratelimited("redistributor failed to %s...\n", | |
194 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
195 | } |
196 | ||
197 | /* | |
198 | * Routines to disable, enable, EOI and route interrupts | |
199 | */ | |
b594c6e2 MZ |
200 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
201 | { | |
202 | u32 mask = 1 << (gic_irq(d) % 32); | |
203 | void __iomem *base; | |
204 | ||
205 | if (gic_irq_in_rdist(d)) | |
206 | base = gic_data_rdist_sgi_base(); | |
207 | else | |
208 | base = gic_data.dist_base; | |
209 | ||
210 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
211 | } | |
212 | ||
021f6537 MZ |
213 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
214 | { | |
215 | u32 mask = 1 << (gic_irq(d) % 32); | |
216 | void (*rwp_wait)(void); | |
217 | void __iomem *base; | |
218 | ||
219 | if (gic_irq_in_rdist(d)) { | |
220 | base = gic_data_rdist_sgi_base(); | |
221 | rwp_wait = gic_redist_wait_for_rwp; | |
222 | } else { | |
223 | base = gic_data.dist_base; | |
224 | rwp_wait = gic_dist_wait_for_rwp; | |
225 | } | |
226 | ||
227 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
228 | rwp_wait(); | |
229 | } | |
230 | ||
021f6537 MZ |
231 | static void gic_mask_irq(struct irq_data *d) |
232 | { | |
233 | gic_poke_irq(d, GICD_ICENABLER); | |
234 | } | |
235 | ||
0b6a3da9 MZ |
236 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
237 | { | |
238 | gic_mask_irq(d); | |
239 | } | |
240 | ||
021f6537 MZ |
241 | static void gic_unmask_irq(struct irq_data *d) |
242 | { | |
243 | gic_poke_irq(d, GICD_ISENABLER); | |
244 | } | |
245 | ||
b594c6e2 MZ |
246 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
247 | enum irqchip_irq_state which, bool val) | |
248 | { | |
249 | u32 reg; | |
250 | ||
251 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
252 | return -EINVAL; | |
253 | ||
254 | switch (which) { | |
255 | case IRQCHIP_STATE_PENDING: | |
256 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
257 | break; | |
258 | ||
259 | case IRQCHIP_STATE_ACTIVE: | |
260 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
261 | break; | |
262 | ||
263 | case IRQCHIP_STATE_MASKED: | |
264 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
265 | break; | |
266 | ||
267 | default: | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | gic_poke_irq(d, reg); | |
272 | return 0; | |
273 | } | |
274 | ||
275 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
276 | enum irqchip_irq_state which, bool *val) | |
277 | { | |
278 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
279 | return -EINVAL; | |
280 | ||
281 | switch (which) { | |
282 | case IRQCHIP_STATE_PENDING: | |
283 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
284 | break; | |
285 | ||
286 | case IRQCHIP_STATE_ACTIVE: | |
287 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
288 | break; | |
289 | ||
290 | case IRQCHIP_STATE_MASKED: | |
291 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
292 | break; | |
293 | ||
294 | default: | |
295 | return -EINVAL; | |
296 | } | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
021f6537 MZ |
301 | static void gic_eoi_irq(struct irq_data *d) |
302 | { | |
303 | gic_write_eoir(gic_irq(d)); | |
304 | } | |
305 | ||
0b6a3da9 MZ |
306 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
307 | { | |
308 | /* | |
309 | * No need to deactivate an LPI. | |
310 | */ | |
311 | if (gic_irq(d) >= 8192) | |
312 | return; | |
313 | gic_write_dir(gic_irq(d)); | |
314 | } | |
315 | ||
021f6537 MZ |
316 | static int gic_set_type(struct irq_data *d, unsigned int type) |
317 | { | |
318 | unsigned int irq = gic_irq(d); | |
319 | void (*rwp_wait)(void); | |
320 | void __iomem *base; | |
321 | ||
322 | /* Interrupt configuration for SGIs can't be changed */ | |
323 | if (irq < 16) | |
324 | return -EINVAL; | |
325 | ||
fb7e7deb LD |
326 | /* SPIs have restrictions on the supported types */ |
327 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
328 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
329 | return -EINVAL; |
330 | ||
331 | if (gic_irq_in_rdist(d)) { | |
332 | base = gic_data_rdist_sgi_base(); | |
333 | rwp_wait = gic_redist_wait_for_rwp; | |
334 | } else { | |
335 | base = gic_data.dist_base; | |
336 | rwp_wait = gic_dist_wait_for_rwp; | |
337 | } | |
338 | ||
fb7e7deb | 339 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
340 | } |
341 | ||
342 | static u64 gic_mpidr_to_affinity(u64 mpidr) | |
343 | { | |
344 | u64 aff; | |
345 | ||
346 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | | |
347 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
348 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
349 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
350 | ||
351 | return aff; | |
352 | } | |
353 | ||
354 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
355 | { | |
356 | u64 irqnr; | |
357 | ||
358 | do { | |
359 | irqnr = gic_read_iar(); | |
360 | ||
da33f31d | 361 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 362 | int err; |
0b6a3da9 MZ |
363 | |
364 | if (static_key_true(&supports_deactivate)) | |
365 | gic_write_eoir(irqnr); | |
366 | ||
ebc6de00 MZ |
367 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
368 | if (err) { | |
da33f31d | 369 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
370 | if (static_key_true(&supports_deactivate)) { |
371 | if (irqnr < 8192) | |
372 | gic_write_dir(irqnr); | |
373 | } else { | |
374 | gic_write_eoir(irqnr); | |
375 | } | |
021f6537 | 376 | } |
ebc6de00 | 377 | continue; |
021f6537 MZ |
378 | } |
379 | if (irqnr < 16) { | |
380 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
381 | if (static_key_true(&supports_deactivate)) |
382 | gic_write_dir(irqnr); | |
021f6537 MZ |
383 | #ifdef CONFIG_SMP |
384 | handle_IPI(irqnr, regs); | |
385 | #else | |
386 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
387 | #endif | |
388 | continue; | |
389 | } | |
390 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
391 | } | |
392 | ||
393 | static void __init gic_dist_init(void) | |
394 | { | |
395 | unsigned int i; | |
396 | u64 affinity; | |
397 | void __iomem *base = gic_data.dist_base; | |
398 | ||
399 | /* Disable the distributor */ | |
400 | writel_relaxed(0, base + GICD_CTLR); | |
401 | gic_dist_wait_for_rwp(); | |
402 | ||
403 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
404 | ||
405 | /* Enable distributor with ARE, Group1 */ | |
406 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
407 | base + GICD_CTLR); | |
408 | ||
409 | /* | |
410 | * Set all global interrupts to the boot CPU only. ARE must be | |
411 | * enabled. | |
412 | */ | |
413 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
414 | for (i = 32; i < gic_data.irq_nr; i++) | |
415 | writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); | |
416 | } | |
417 | ||
418 | static int gic_populate_rdist(void) | |
419 | { | |
420 | u64 mpidr = cpu_logical_map(smp_processor_id()); | |
421 | u64 typer; | |
422 | u32 aff; | |
423 | int i; | |
424 | ||
425 | /* | |
426 | * Convert affinity to a 32bit value that can be matched to | |
427 | * GICR_TYPER bits [63:32]. | |
428 | */ | |
429 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
430 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
431 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
432 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
433 | ||
f5c1434c MZ |
434 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
435 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
436 | u32 reg; |
437 | ||
438 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
439 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
440 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
441 | pr_warn("No redistributor present @%p\n", ptr); | |
442 | break; | |
443 | } | |
444 | ||
445 | do { | |
446 | typer = readq_relaxed(ptr + GICR_TYPER); | |
447 | if ((typer >> 32) == aff) { | |
f5c1434c | 448 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 449 | gic_data_rdist_rd_base() = ptr; |
f5c1434c MZ |
450 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
451 | pr_info("CPU%d: found redistributor %llx region %d:%pa\n", | |
021f6537 | 452 | smp_processor_id(), |
f5c1434c MZ |
453 | (unsigned long long)mpidr, |
454 | i, &gic_data_rdist()->phys_base); | |
021f6537 MZ |
455 | return 0; |
456 | } | |
457 | ||
458 | if (gic_data.redist_stride) { | |
459 | ptr += gic_data.redist_stride; | |
460 | } else { | |
461 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
462 | if (typer & GICR_TYPER_VLPIS) | |
463 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
464 | } | |
465 | } while (!(typer & GICR_TYPER_LAST)); | |
466 | } | |
467 | ||
468 | /* We couldn't even deal with ourselves... */ | |
469 | WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", | |
470 | smp_processor_id(), (unsigned long long)mpidr); | |
471 | return -ENODEV; | |
472 | } | |
473 | ||
3708d52f SH |
474 | static void gic_cpu_sys_reg_init(void) |
475 | { | |
476 | /* Enable system registers */ | |
477 | gic_enable_sre(); | |
478 | ||
479 | /* Set priority mask register */ | |
480 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
481 | ||
0b6a3da9 MZ |
482 | if (static_key_true(&supports_deactivate)) { |
483 | /* EOI drops priority only (mode 1) */ | |
484 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
485 | } else { | |
486 | /* EOI deactivates interrupt too (mode 0) */ | |
487 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
488 | } | |
3708d52f SH |
489 | |
490 | /* ... and let's hit the road... */ | |
491 | gic_write_grpen1(1); | |
492 | } | |
493 | ||
da33f31d MZ |
494 | static int gic_dist_supports_lpis(void) |
495 | { | |
496 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
497 | } | |
498 | ||
021f6537 MZ |
499 | static void gic_cpu_init(void) |
500 | { | |
501 | void __iomem *rbase; | |
502 | ||
503 | /* Register ourselves with the rest of the world */ | |
504 | if (gic_populate_rdist()) | |
505 | return; | |
506 | ||
a2c22510 | 507 | gic_enable_redist(true); |
021f6537 MZ |
508 | |
509 | rbase = gic_data_rdist_sgi_base(); | |
510 | ||
511 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
512 | ||
da33f31d MZ |
513 | /* Give LPIs a spin */ |
514 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
515 | its_cpu_init(); | |
516 | ||
3708d52f SH |
517 | /* initialise system registers */ |
518 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
519 | } |
520 | ||
521 | #ifdef CONFIG_SMP | |
522 | static int gic_secondary_init(struct notifier_block *nfb, | |
523 | unsigned long action, void *hcpu) | |
524 | { | |
525 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
526 | gic_cpu_init(); | |
527 | return NOTIFY_OK; | |
528 | } | |
529 | ||
530 | /* | |
531 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
532 | * priority because the GIC needs to be up before the ARM generic timers. | |
533 | */ | |
534 | static struct notifier_block gic_cpu_notifier = { | |
535 | .notifier_call = gic_secondary_init, | |
536 | .priority = 100, | |
537 | }; | |
538 | ||
539 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
540 | u64 cluster_id) | |
541 | { | |
542 | int cpu = *base_cpu; | |
543 | u64 mpidr = cpu_logical_map(cpu); | |
544 | u16 tlist = 0; | |
545 | ||
546 | while (cpu < nr_cpu_ids) { | |
547 | /* | |
548 | * If we ever get a cluster of more than 16 CPUs, just | |
549 | * scream and skip that CPU. | |
550 | */ | |
551 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
552 | goto out; | |
553 | ||
554 | tlist |= 1 << (mpidr & 0xf); | |
555 | ||
556 | cpu = cpumask_next(cpu, mask); | |
614be385 | 557 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
558 | goto out; |
559 | ||
560 | mpidr = cpu_logical_map(cpu); | |
561 | ||
562 | if (cluster_id != (mpidr & ~0xffUL)) { | |
563 | cpu--; | |
564 | goto out; | |
565 | } | |
566 | } | |
567 | out: | |
568 | *base_cpu = cpu; | |
569 | return tlist; | |
570 | } | |
571 | ||
7e580278 AP |
572 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
573 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
574 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
575 | ||
021f6537 MZ |
576 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
577 | { | |
578 | u64 val; | |
579 | ||
7e580278 AP |
580 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
581 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
582 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
583 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
584 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
585 | |
586 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
587 | gic_write_sgi1r(val); | |
588 | } | |
589 | ||
590 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
591 | { | |
592 | int cpu; | |
593 | ||
594 | if (WARN_ON(irq >= 16)) | |
595 | return; | |
596 | ||
597 | /* | |
598 | * Ensure that stores to Normal memory are visible to the | |
599 | * other CPUs before issuing the IPI. | |
600 | */ | |
601 | smp_wmb(); | |
602 | ||
f9b531fe | 603 | for_each_cpu(cpu, mask) { |
021f6537 MZ |
604 | u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
605 | u16 tlist; | |
606 | ||
607 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
608 | gic_send_sgi(cluster_id, tlist, irq); | |
609 | } | |
610 | ||
611 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
612 | isb(); | |
613 | } | |
614 | ||
615 | static void gic_smp_init(void) | |
616 | { | |
617 | set_smp_cross_call(gic_raise_softirq); | |
618 | register_cpu_notifier(&gic_cpu_notifier); | |
619 | } | |
620 | ||
621 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
622 | bool force) | |
623 | { | |
624 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
625 | void __iomem *reg; | |
626 | int enabled; | |
627 | u64 val; | |
628 | ||
629 | if (gic_irq_in_rdist(d)) | |
630 | return -EINVAL; | |
631 | ||
632 | /* If interrupt was enabled, disable it first */ | |
633 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
634 | if (enabled) | |
635 | gic_mask_irq(d); | |
636 | ||
637 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
638 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
639 | ||
640 | writeq_relaxed(val, reg); | |
641 | ||
642 | /* | |
643 | * If the interrupt was enabled, enabled it again. Otherwise, | |
644 | * just wait for the distributor to have digested our changes. | |
645 | */ | |
646 | if (enabled) | |
647 | gic_unmask_irq(d); | |
648 | else | |
649 | gic_dist_wait_for_rwp(); | |
650 | ||
651 | return IRQ_SET_MASK_OK; | |
652 | } | |
653 | #else | |
654 | #define gic_set_affinity NULL | |
655 | #define gic_smp_init() do { } while(0) | |
656 | #endif | |
657 | ||
3708d52f SH |
658 | #ifdef CONFIG_CPU_PM |
659 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
660 | unsigned long cmd, void *v) | |
661 | { | |
662 | if (cmd == CPU_PM_EXIT) { | |
663 | gic_enable_redist(true); | |
664 | gic_cpu_sys_reg_init(); | |
665 | } else if (cmd == CPU_PM_ENTER) { | |
666 | gic_write_grpen1(0); | |
667 | gic_enable_redist(false); | |
668 | } | |
669 | return NOTIFY_OK; | |
670 | } | |
671 | ||
672 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
673 | .notifier_call = gic_cpu_pm_notifier, | |
674 | }; | |
675 | ||
676 | static void gic_cpu_pm_init(void) | |
677 | { | |
678 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
679 | } | |
680 | ||
681 | #else | |
682 | static inline void gic_cpu_pm_init(void) { } | |
683 | #endif /* CONFIG_CPU_PM */ | |
684 | ||
021f6537 MZ |
685 | static struct irq_chip gic_chip = { |
686 | .name = "GICv3", | |
687 | .irq_mask = gic_mask_irq, | |
688 | .irq_unmask = gic_unmask_irq, | |
689 | .irq_eoi = gic_eoi_irq, | |
690 | .irq_set_type = gic_set_type, | |
691 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
692 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
693 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 694 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
695 | }; |
696 | ||
0b6a3da9 MZ |
697 | static struct irq_chip gic_eoimode1_chip = { |
698 | .name = "GICv3", | |
699 | .irq_mask = gic_eoimode1_mask_irq, | |
700 | .irq_unmask = gic_unmask_irq, | |
701 | .irq_eoi = gic_eoimode1_eoi_irq, | |
702 | .irq_set_type = gic_set_type, | |
703 | .irq_set_affinity = gic_set_affinity, | |
704 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
705 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
706 | .flags = IRQCHIP_SET_TYPE_MASKED, | |
707 | }; | |
708 | ||
da33f31d MZ |
709 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
710 | ||
021f6537 MZ |
711 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
712 | irq_hw_number_t hw) | |
713 | { | |
0b6a3da9 MZ |
714 | struct irq_chip *chip = &gic_chip; |
715 | ||
716 | if (static_key_true(&supports_deactivate)) | |
717 | chip = &gic_eoimode1_chip; | |
718 | ||
021f6537 MZ |
719 | /* SGIs are private to the core kernel */ |
720 | if (hw < 16) | |
721 | return -EPERM; | |
da33f31d MZ |
722 | /* Nothing here */ |
723 | if (hw >= gic_data.irq_nr && hw < 8192) | |
724 | return -EPERM; | |
725 | /* Off limits */ | |
726 | if (hw >= GIC_ID_NR) | |
727 | return -EPERM; | |
728 | ||
021f6537 MZ |
729 | /* PPIs */ |
730 | if (hw < 32) { | |
731 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 732 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 733 | handle_percpu_devid_irq, NULL, NULL); |
021f6537 MZ |
734 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
735 | } | |
736 | /* SPIs */ | |
737 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 738 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 739 | handle_fasteoi_irq, NULL, NULL); |
021f6537 MZ |
740 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
741 | } | |
da33f31d MZ |
742 | /* LPIs */ |
743 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
744 | if (!gic_dist_supports_lpis()) | |
745 | return -EPERM; | |
0b6a3da9 | 746 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d MZ |
747 | handle_fasteoi_irq, NULL, NULL); |
748 | set_irq_flags(irq, IRQF_VALID); | |
749 | } | |
750 | ||
021f6537 MZ |
751 | return 0; |
752 | } | |
753 | ||
754 | static int gic_irq_domain_xlate(struct irq_domain *d, | |
755 | struct device_node *controller, | |
756 | const u32 *intspec, unsigned int intsize, | |
757 | unsigned long *out_hwirq, unsigned int *out_type) | |
758 | { | |
759 | if (d->of_node != controller) | |
760 | return -EINVAL; | |
761 | if (intsize < 3) | |
762 | return -EINVAL; | |
763 | ||
764 | switch(intspec[0]) { | |
765 | case 0: /* SPI */ | |
766 | *out_hwirq = intspec[1] + 32; | |
767 | break; | |
768 | case 1: /* PPI */ | |
769 | *out_hwirq = intspec[1] + 16; | |
770 | break; | |
da33f31d MZ |
771 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
772 | *out_hwirq = intspec[1]; | |
773 | break; | |
021f6537 MZ |
774 | default: |
775 | return -EINVAL; | |
776 | } | |
777 | ||
778 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
779 | return 0; | |
780 | } | |
781 | ||
443acc4f MZ |
782 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
783 | unsigned int nr_irqs, void *arg) | |
784 | { | |
785 | int i, ret; | |
786 | irq_hw_number_t hwirq; | |
787 | unsigned int type = IRQ_TYPE_NONE; | |
788 | struct of_phandle_args *irq_data = arg; | |
789 | ||
790 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, | |
791 | irq_data->args_count, &hwirq, &type); | |
792 | if (ret) | |
793 | return ret; | |
794 | ||
795 | for (i = 0; i < nr_irqs; i++) | |
796 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
802 | unsigned int nr_irqs) | |
803 | { | |
804 | int i; | |
805 | ||
806 | for (i = 0; i < nr_irqs; i++) { | |
807 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
808 | irq_set_handler(virq + i, NULL); | |
809 | irq_domain_reset_irq_data(d); | |
810 | } | |
811 | } | |
812 | ||
021f6537 | 813 | static const struct irq_domain_ops gic_irq_domain_ops = { |
021f6537 | 814 | .xlate = gic_irq_domain_xlate, |
443acc4f MZ |
815 | .alloc = gic_irq_domain_alloc, |
816 | .free = gic_irq_domain_free, | |
021f6537 MZ |
817 | }; |
818 | ||
819 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
820 | { | |
821 | void __iomem *dist_base; | |
f5c1434c | 822 | struct redist_region *rdist_regs; |
021f6537 | 823 | u64 redist_stride; |
f5c1434c MZ |
824 | u32 nr_redist_regions; |
825 | u32 typer; | |
021f6537 MZ |
826 | u32 reg; |
827 | int gic_irqs; | |
828 | int err; | |
829 | int i; | |
830 | ||
831 | dist_base = of_iomap(node, 0); | |
832 | if (!dist_base) { | |
833 | pr_err("%s: unable to map gic dist registers\n", | |
834 | node->full_name); | |
835 | return -ENXIO; | |
836 | } | |
837 | ||
838 | reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
839 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { | |
840 | pr_err("%s: no distributor detected, giving up\n", | |
841 | node->full_name); | |
842 | err = -ENODEV; | |
843 | goto out_unmap_dist; | |
844 | } | |
845 | ||
f5c1434c MZ |
846 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) |
847 | nr_redist_regions = 1; | |
021f6537 | 848 | |
f5c1434c MZ |
849 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); |
850 | if (!rdist_regs) { | |
021f6537 MZ |
851 | err = -ENOMEM; |
852 | goto out_unmap_dist; | |
853 | } | |
854 | ||
f5c1434c MZ |
855 | for (i = 0; i < nr_redist_regions; i++) { |
856 | struct resource res; | |
857 | int ret; | |
858 | ||
859 | ret = of_address_to_resource(node, 1 + i, &res); | |
860 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
861 | if (ret || !rdist_regs[i].redist_base) { | |
021f6537 MZ |
862 | pr_err("%s: couldn't map region %d\n", |
863 | node->full_name, i); | |
864 | err = -ENODEV; | |
865 | goto out_unmap_rdist; | |
866 | } | |
f5c1434c | 867 | rdist_regs[i].phys_base = res.start; |
021f6537 MZ |
868 | } |
869 | ||
870 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
871 | redist_stride = 0; | |
872 | ||
0b6a3da9 MZ |
873 | if (!is_hyp_mode_available()) |
874 | static_key_slow_dec(&supports_deactivate); | |
875 | ||
876 | if (static_key_true(&supports_deactivate)) | |
877 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
878 | ||
021f6537 | 879 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
880 | gic_data.redist_regions = rdist_regs; |
881 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
882 | gic_data.redist_stride = redist_stride; |
883 | ||
884 | /* | |
885 | * Find out how many interrupts are supported. | |
886 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
887 | */ | |
f5c1434c MZ |
888 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
889 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
890 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
891 | if (gic_irqs > 1020) |
892 | gic_irqs = 1020; | |
893 | gic_data.irq_nr = gic_irqs; | |
894 | ||
895 | gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, | |
896 | &gic_data); | |
f5c1434c | 897 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 898 | |
f5c1434c | 899 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
900 | err = -ENOMEM; |
901 | goto out_free; | |
902 | } | |
903 | ||
904 | set_handle_irq(gic_handle_irq); | |
905 | ||
da33f31d MZ |
906 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
907 | its_init(node, &gic_data.rdists, gic_data.domain); | |
908 | ||
021f6537 MZ |
909 | gic_smp_init(); |
910 | gic_dist_init(); | |
911 | gic_cpu_init(); | |
3708d52f | 912 | gic_cpu_pm_init(); |
021f6537 MZ |
913 | |
914 | return 0; | |
915 | ||
916 | out_free: | |
917 | if (gic_data.domain) | |
918 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 919 | free_percpu(gic_data.rdists.rdist); |
021f6537 | 920 | out_unmap_rdist: |
f5c1434c MZ |
921 | for (i = 0; i < nr_redist_regions; i++) |
922 | if (rdist_regs[i].redist_base) | |
923 | iounmap(rdist_regs[i].redist_base); | |
924 | kfree(rdist_regs); | |
021f6537 MZ |
925 | out_unmap_dist: |
926 | iounmap(dist_base); | |
927 | return err; | |
928 | } | |
929 | ||
930 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |