Commit | Line | Data |
---|---|---|
caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
021f6537 | 2 | /* |
0edc23ea | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
021f6537 MZ |
5 | */ |
6 | ||
68628bb8 JG |
7 | #define pr_fmt(fmt) "GICv3: " fmt |
8 | ||
ffa7d616 | 9 | #include <linux/acpi.h> |
021f6537 | 10 | #include <linux/cpu.h> |
3708d52f | 11 | #include <linux/cpu_pm.h> |
021f6537 MZ |
12 | #include <linux/delay.h> |
13 | #include <linux/interrupt.h> | |
ffa7d616 | 14 | #include <linux/irqdomain.h> |
021f6537 MZ |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | |
17 | #include <linux/of_irq.h> | |
18 | #include <linux/percpu.h> | |
101b35f7 | 19 | #include <linux/refcount.h> |
021f6537 MZ |
20 | #include <linux/slab.h> |
21 | ||
41a83e06 | 22 | #include <linux/irqchip.h> |
1839e576 | 23 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 24 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 25 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
26 | |
27 | #include <asm/cputype.h> | |
28 | #include <asm/exception.h> | |
29 | #include <asm/smp_plat.h> | |
0b6a3da9 | 30 | #include <asm/virt.h> |
021f6537 MZ |
31 | |
32 | #include "irq-gic-common.h" | |
021f6537 | 33 | |
f32c9266 JT |
34 | #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) |
35 | ||
9c8114c2 | 36 | #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) |
d01fd161 | 37 | #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) |
9c8114c2 | 38 | |
64b499d8 MZ |
39 | #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) |
40 | ||
f5c1434c MZ |
41 | struct redist_region { |
42 | void __iomem *redist_base; | |
43 | phys_addr_t phys_base; | |
b70fb7af | 44 | bool single_redist; |
f5c1434c MZ |
45 | }; |
46 | ||
021f6537 | 47 | struct gic_chip_data { |
e3825ba1 | 48 | struct fwnode_handle *fwnode; |
021f6537 | 49 | void __iomem *dist_base; |
f5c1434c MZ |
50 | struct redist_region *redist_regions; |
51 | struct rdists rdists; | |
021f6537 MZ |
52 | struct irq_domain *domain; |
53 | u64 redist_stride; | |
f5c1434c | 54 | u32 nr_redist_regions; |
9c8114c2 | 55 | u64 flags; |
eda0d04a | 56 | bool has_rss; |
1a60e1e6 | 57 | unsigned int ppi_nr; |
52085d3f | 58 | struct partition_desc **ppi_descs; |
021f6537 MZ |
59 | }; |
60 | ||
61 | static struct gic_chip_data gic_data __read_mostly; | |
d01d3274 | 62 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
021f6537 | 63 | |
211bddd2 | 64 | #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) |
c107d613 | 65 | #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) |
211bddd2 MZ |
66 | #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) |
67 | ||
d98d0a99 JT |
68 | /* |
69 | * The behaviours of RPR and PMR registers differ depending on the value of | |
70 | * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the | |
71 | * distributor and redistributors depends on whether security is enabled in the | |
72 | * GIC. | |
73 | * | |
74 | * When security is enabled, non-secure priority values from the (re)distributor | |
75 | * are presented to the GIC CPUIF as follow: | |
76 | * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; | |
77 | * | |
78 | * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure | |
79 | * EL1 are subject to a similar operation thus matching the priorities presented | |
33678059 AE |
80 | * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0, |
81 | * these values are unchanched by the GIC. | |
d98d0a99 JT |
82 | * |
83 | * see GICv3/GICv4 Architecture Specification (IHI0069D): | |
84 | * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt | |
85 | * priorities. | |
86 | * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 | |
87 | * interrupt. | |
d98d0a99 JT |
88 | */ |
89 | static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); | |
90 | ||
f2266504 MZ |
91 | /* |
92 | * Global static key controlling whether an update to PMR allowing more | |
93 | * interrupts requires to be propagated to the redistributor (DSB SY). | |
94 | * And this needs to be exported for modules to be able to enable | |
95 | * interrupts... | |
96 | */ | |
97 | DEFINE_STATIC_KEY_FALSE(gic_pmr_sync); | |
98 | EXPORT_SYMBOL(gic_pmr_sync); | |
99 | ||
33678059 AE |
100 | DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); |
101 | EXPORT_SYMBOL(gic_nonsecure_priorities); | |
102 | ||
101b35f7 | 103 | /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ |
81a43273 | 104 | static refcount_t *ppi_nmi_refs; |
101b35f7 | 105 | |
1839e576 | 106 | static struct gic_kvm_info gic_v3_kvm_info; |
eda0d04a | 107 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 108 | |
eda0d04a | 109 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
110 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
111 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
112 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
113 | ||
114 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
115 | #define DEFAULT_PMR_VALUE 0xf0 | |
116 | ||
e91b036e | 117 | enum gic_intid_range { |
70a29c32 | 118 | SGI_RANGE, |
e91b036e MZ |
119 | PPI_RANGE, |
120 | SPI_RANGE, | |
5f51f803 | 121 | EPPI_RANGE, |
211bddd2 | 122 | ESPI_RANGE, |
e91b036e MZ |
123 | LPI_RANGE, |
124 | __INVALID_RANGE__ | |
125 | }; | |
126 | ||
127 | static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) | |
128 | { | |
129 | switch (hwirq) { | |
70a29c32 MZ |
130 | case 0 ... 15: |
131 | return SGI_RANGE; | |
e91b036e MZ |
132 | case 16 ... 31: |
133 | return PPI_RANGE; | |
134 | case 32 ... 1019: | |
135 | return SPI_RANGE; | |
5f51f803 MZ |
136 | case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63): |
137 | return EPPI_RANGE; | |
211bddd2 MZ |
138 | case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023): |
139 | return ESPI_RANGE; | |
e91b036e MZ |
140 | case 8192 ... GENMASK(23, 0): |
141 | return LPI_RANGE; | |
142 | default: | |
143 | return __INVALID_RANGE__; | |
144 | } | |
145 | } | |
146 | ||
147 | static enum gic_intid_range get_intid_range(struct irq_data *d) | |
148 | { | |
149 | return __get_intid_range(d->hwirq); | |
150 | } | |
151 | ||
021f6537 MZ |
152 | static inline unsigned int gic_irq(struct irq_data *d) |
153 | { | |
154 | return d->hwirq; | |
155 | } | |
156 | ||
70a29c32 | 157 | static inline bool gic_irq_in_rdist(struct irq_data *d) |
021f6537 | 158 | { |
70a29c32 MZ |
159 | switch (get_intid_range(d)) { |
160 | case SGI_RANGE: | |
161 | case PPI_RANGE: | |
162 | case EPPI_RANGE: | |
163 | return true; | |
164 | default: | |
165 | return false; | |
166 | } | |
021f6537 MZ |
167 | } |
168 | ||
169 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
170 | { | |
e91b036e | 171 | switch (get_intid_range(d)) { |
70a29c32 | 172 | case SGI_RANGE: |
e91b036e | 173 | case PPI_RANGE: |
5f51f803 | 174 | case EPPI_RANGE: |
e91b036e | 175 | /* SGI+PPI -> SGI_base for this CPU */ |
021f6537 MZ |
176 | return gic_data_rdist_sgi_base(); |
177 | ||
e91b036e | 178 | case SPI_RANGE: |
211bddd2 | 179 | case ESPI_RANGE: |
e91b036e | 180 | /* SPI -> dist_base */ |
021f6537 MZ |
181 | return gic_data.dist_base; |
182 | ||
e91b036e MZ |
183 | default: |
184 | return NULL; | |
185 | } | |
021f6537 MZ |
186 | } |
187 | ||
188 | static void gic_do_wait_for_rwp(void __iomem *base) | |
189 | { | |
190 | u32 count = 1000000; /* 1s! */ | |
191 | ||
192 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
193 | count--; | |
194 | if (!count) { | |
195 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
196 | return; | |
197 | } | |
198 | cpu_relax(); | |
199 | udelay(1); | |
2c542426 | 200 | } |
021f6537 MZ |
201 | } |
202 | ||
203 | /* Wait for completion of a distributor change */ | |
204 | static void gic_dist_wait_for_rwp(void) | |
205 | { | |
206 | gic_do_wait_for_rwp(gic_data.dist_base); | |
207 | } | |
208 | ||
209 | /* Wait for completion of a redistributor change */ | |
210 | static void gic_redist_wait_for_rwp(void) | |
211 | { | |
212 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
213 | } | |
214 | ||
7936e914 | 215 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
216 | |
217 | static u64 __maybe_unused gic_read_iar(void) | |
218 | { | |
a4023f68 | 219 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
220 | return gic_read_iar_cavium_thunderx(); |
221 | else | |
222 | return gic_read_iar_common(); | |
223 | } | |
7936e914 | 224 | #endif |
021f6537 | 225 | |
a2c22510 | 226 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
227 | { |
228 | void __iomem *rbase; | |
229 | u32 count = 1000000; /* 1s! */ | |
230 | u32 val; | |
231 | ||
9c8114c2 SK |
232 | if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) |
233 | return; | |
234 | ||
021f6537 MZ |
235 | rbase = gic_data_rdist_rd_base(); |
236 | ||
021f6537 | 237 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
238 | if (enable) |
239 | /* Wake up this CPU redistributor */ | |
240 | val &= ~GICR_WAKER_ProcessorSleep; | |
241 | else | |
242 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
243 | writel_relaxed(val, rbase + GICR_WAKER); |
244 | ||
a2c22510 SH |
245 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
246 | val = readl_relaxed(rbase + GICR_WAKER); | |
247 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
248 | return; /* No PM support in this redistributor */ | |
249 | } | |
250 | ||
d102eb5c | 251 | while (--count) { |
a2c22510 | 252 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 253 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 254 | break; |
021f6537 MZ |
255 | cpu_relax(); |
256 | udelay(1); | |
2c542426 | 257 | } |
a2c22510 SH |
258 | if (!count) |
259 | pr_err_ratelimited("redistributor failed to %s...\n", | |
260 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
261 | } |
262 | ||
263 | /* | |
264 | * Routines to disable, enable, EOI and route interrupts | |
265 | */ | |
e91b036e MZ |
266 | static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index) |
267 | { | |
268 | switch (get_intid_range(d)) { | |
70a29c32 | 269 | case SGI_RANGE: |
e91b036e MZ |
270 | case PPI_RANGE: |
271 | case SPI_RANGE: | |
272 | *index = d->hwirq; | |
273 | return offset; | |
5f51f803 MZ |
274 | case EPPI_RANGE: |
275 | /* | |
276 | * Contrary to the ESPI range, the EPPI range is contiguous | |
277 | * to the PPI range in the registers, so let's adjust the | |
278 | * displacement accordingly. Consistency is overrated. | |
279 | */ | |
280 | *index = d->hwirq - EPPI_BASE_INTID + 32; | |
281 | return offset; | |
211bddd2 MZ |
282 | case ESPI_RANGE: |
283 | *index = d->hwirq - ESPI_BASE_INTID; | |
284 | switch (offset) { | |
285 | case GICD_ISENABLER: | |
286 | return GICD_ISENABLERnE; | |
287 | case GICD_ICENABLER: | |
288 | return GICD_ICENABLERnE; | |
289 | case GICD_ISPENDR: | |
290 | return GICD_ISPENDRnE; | |
291 | case GICD_ICPENDR: | |
292 | return GICD_ICPENDRnE; | |
293 | case GICD_ISACTIVER: | |
294 | return GICD_ISACTIVERnE; | |
295 | case GICD_ICACTIVER: | |
296 | return GICD_ICACTIVERnE; | |
297 | case GICD_IPRIORITYR: | |
298 | return GICD_IPRIORITYRnE; | |
299 | case GICD_ICFGR: | |
300 | return GICD_ICFGRnE; | |
301 | case GICD_IROUTER: | |
302 | return GICD_IROUTERnE; | |
303 | default: | |
304 | break; | |
305 | } | |
306 | break; | |
e91b036e MZ |
307 | default: |
308 | break; | |
309 | } | |
310 | ||
311 | WARN_ON(1); | |
312 | *index = d->hwirq; | |
313 | return offset; | |
314 | } | |
315 | ||
b594c6e2 MZ |
316 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
317 | { | |
b594c6e2 | 318 | void __iomem *base; |
e91b036e MZ |
319 | u32 index, mask; |
320 | ||
321 | offset = convert_offset_index(d, offset, &index); | |
322 | mask = 1 << (index % 32); | |
b594c6e2 MZ |
323 | |
324 | if (gic_irq_in_rdist(d)) | |
325 | base = gic_data_rdist_sgi_base(); | |
326 | else | |
327 | base = gic_data.dist_base; | |
328 | ||
e91b036e | 329 | return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); |
b594c6e2 MZ |
330 | } |
331 | ||
021f6537 MZ |
332 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
333 | { | |
021f6537 MZ |
334 | void (*rwp_wait)(void); |
335 | void __iomem *base; | |
e91b036e MZ |
336 | u32 index, mask; |
337 | ||
338 | offset = convert_offset_index(d, offset, &index); | |
339 | mask = 1 << (index % 32); | |
021f6537 MZ |
340 | |
341 | if (gic_irq_in_rdist(d)) { | |
342 | base = gic_data_rdist_sgi_base(); | |
343 | rwp_wait = gic_redist_wait_for_rwp; | |
344 | } else { | |
345 | base = gic_data.dist_base; | |
346 | rwp_wait = gic_dist_wait_for_rwp; | |
347 | } | |
348 | ||
e91b036e | 349 | writel_relaxed(mask, base + offset + (index / 32) * 4); |
021f6537 MZ |
350 | rwp_wait(); |
351 | } | |
352 | ||
021f6537 MZ |
353 | static void gic_mask_irq(struct irq_data *d) |
354 | { | |
355 | gic_poke_irq(d, GICD_ICENABLER); | |
356 | } | |
357 | ||
0b6a3da9 MZ |
358 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
359 | { | |
360 | gic_mask_irq(d); | |
530bf353 MZ |
361 | /* |
362 | * When masking a forwarded interrupt, make sure it is | |
363 | * deactivated as well. | |
364 | * | |
365 | * This ensures that an interrupt that is getting | |
366 | * disabled/masked will not get "stuck", because there is | |
367 | * noone to deactivate it (guest is being terminated). | |
368 | */ | |
4df7f54d | 369 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 370 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
371 | } |
372 | ||
021f6537 MZ |
373 | static void gic_unmask_irq(struct irq_data *d) |
374 | { | |
375 | gic_poke_irq(d, GICD_ISENABLER); | |
376 | } | |
377 | ||
d98d0a99 JT |
378 | static inline bool gic_supports_nmi(void) |
379 | { | |
380 | return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && | |
381 | static_branch_likely(&supports_pseudo_nmis); | |
382 | } | |
383 | ||
b594c6e2 MZ |
384 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
385 | enum irqchip_irq_state which, bool val) | |
386 | { | |
387 | u32 reg; | |
388 | ||
64b499d8 | 389 | if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ |
b594c6e2 MZ |
390 | return -EINVAL; |
391 | ||
392 | switch (which) { | |
393 | case IRQCHIP_STATE_PENDING: | |
394 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
395 | break; | |
396 | ||
397 | case IRQCHIP_STATE_ACTIVE: | |
398 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
399 | break; | |
400 | ||
401 | case IRQCHIP_STATE_MASKED: | |
402 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
403 | break; | |
404 | ||
405 | default: | |
406 | return -EINVAL; | |
407 | } | |
408 | ||
409 | gic_poke_irq(d, reg); | |
410 | return 0; | |
411 | } | |
412 | ||
413 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
414 | enum irqchip_irq_state which, bool *val) | |
415 | { | |
211bddd2 | 416 | if (d->hwirq >= 8192) /* PPI/SPI only */ |
b594c6e2 MZ |
417 | return -EINVAL; |
418 | ||
419 | switch (which) { | |
420 | case IRQCHIP_STATE_PENDING: | |
421 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
422 | break; | |
423 | ||
424 | case IRQCHIP_STATE_ACTIVE: | |
425 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
426 | break; | |
427 | ||
428 | case IRQCHIP_STATE_MASKED: | |
429 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
430 | break; | |
431 | ||
432 | default: | |
433 | return -EINVAL; | |
434 | } | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
101b35f7 JT |
439 | static void gic_irq_set_prio(struct irq_data *d, u8 prio) |
440 | { | |
441 | void __iomem *base = gic_dist_base(d); | |
e91b036e | 442 | u32 offset, index; |
101b35f7 | 443 | |
e91b036e MZ |
444 | offset = convert_offset_index(d, GICD_IPRIORITYR, &index); |
445 | ||
446 | writeb_relaxed(prio, base + offset + index); | |
101b35f7 JT |
447 | } |
448 | ||
81a43273 MZ |
449 | static u32 gic_get_ppi_index(struct irq_data *d) |
450 | { | |
451 | switch (get_intid_range(d)) { | |
452 | case PPI_RANGE: | |
453 | return d->hwirq - 16; | |
5f51f803 MZ |
454 | case EPPI_RANGE: |
455 | return d->hwirq - EPPI_BASE_INTID + 16; | |
81a43273 MZ |
456 | default: |
457 | unreachable(); | |
458 | } | |
459 | } | |
460 | ||
101b35f7 JT |
461 | static int gic_irq_nmi_setup(struct irq_data *d) |
462 | { | |
463 | struct irq_desc *desc = irq_to_desc(d->irq); | |
464 | ||
465 | if (!gic_supports_nmi()) | |
466 | return -EINVAL; | |
467 | ||
468 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
469 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
470 | return -EINVAL; | |
471 | } | |
472 | ||
473 | /* | |
474 | * A secondary irq_chip should be in charge of LPI request, | |
475 | * it should not be possible to get there | |
476 | */ | |
477 | if (WARN_ON(gic_irq(d) >= 8192)) | |
478 | return -EINVAL; | |
479 | ||
480 | /* desc lock should already be held */ | |
81a43273 MZ |
481 | if (gic_irq_in_rdist(d)) { |
482 | u32 idx = gic_get_ppi_index(d); | |
483 | ||
101b35f7 | 484 | /* Setting up PPI as NMI, only switch handler for first NMI */ |
81a43273 MZ |
485 | if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { |
486 | refcount_set(&ppi_nmi_refs[idx], 1); | |
101b35f7 JT |
487 | desc->handle_irq = handle_percpu_devid_fasteoi_nmi; |
488 | } | |
489 | } else { | |
490 | desc->handle_irq = handle_fasteoi_nmi; | |
491 | } | |
492 | ||
493 | gic_irq_set_prio(d, GICD_INT_NMI_PRI); | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static void gic_irq_nmi_teardown(struct irq_data *d) | |
499 | { | |
500 | struct irq_desc *desc = irq_to_desc(d->irq); | |
501 | ||
502 | if (WARN_ON(!gic_supports_nmi())) | |
503 | return; | |
504 | ||
505 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
506 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
507 | return; | |
508 | } | |
509 | ||
510 | /* | |
511 | * A secondary irq_chip should be in charge of LPI request, | |
512 | * it should not be possible to get there | |
513 | */ | |
514 | if (WARN_ON(gic_irq(d) >= 8192)) | |
515 | return; | |
516 | ||
517 | /* desc lock should already be held */ | |
81a43273 MZ |
518 | if (gic_irq_in_rdist(d)) { |
519 | u32 idx = gic_get_ppi_index(d); | |
520 | ||
101b35f7 | 521 | /* Tearing down NMI, only switch handler for last NMI */ |
81a43273 | 522 | if (refcount_dec_and_test(&ppi_nmi_refs[idx])) |
101b35f7 JT |
523 | desc->handle_irq = handle_percpu_devid_irq; |
524 | } else { | |
525 | desc->handle_irq = handle_fasteoi_irq; | |
526 | } | |
527 | ||
528 | gic_irq_set_prio(d, GICD_INT_DEF_PRI); | |
529 | } | |
530 | ||
021f6537 MZ |
531 | static void gic_eoi_irq(struct irq_data *d) |
532 | { | |
533 | gic_write_eoir(gic_irq(d)); | |
534 | } | |
535 | ||
0b6a3da9 MZ |
536 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
537 | { | |
538 | /* | |
530bf353 MZ |
539 | * No need to deactivate an LPI, or an interrupt that |
540 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 541 | */ |
4df7f54d | 542 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
543 | return; |
544 | gic_write_dir(gic_irq(d)); | |
545 | } | |
546 | ||
021f6537 MZ |
547 | static int gic_set_type(struct irq_data *d, unsigned int type) |
548 | { | |
5f51f803 | 549 | enum gic_intid_range range; |
021f6537 MZ |
550 | unsigned int irq = gic_irq(d); |
551 | void (*rwp_wait)(void); | |
552 | void __iomem *base; | |
e91b036e | 553 | u32 offset, index; |
13d22e2e | 554 | int ret; |
021f6537 | 555 | |
5f51f803 MZ |
556 | range = get_intid_range(d); |
557 | ||
64b499d8 MZ |
558 | /* Interrupt configuration for SGIs can't be changed */ |
559 | if (range == SGI_RANGE) | |
560 | return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; | |
561 | ||
fb7e7deb | 562 | /* SPIs have restrictions on the supported types */ |
5f51f803 MZ |
563 | if ((range == SPI_RANGE || range == ESPI_RANGE) && |
564 | type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
565 | return -EINVAL; |
566 | ||
567 | if (gic_irq_in_rdist(d)) { | |
568 | base = gic_data_rdist_sgi_base(); | |
569 | rwp_wait = gic_redist_wait_for_rwp; | |
570 | } else { | |
571 | base = gic_data.dist_base; | |
572 | rwp_wait = gic_dist_wait_for_rwp; | |
573 | } | |
574 | ||
e91b036e | 575 | offset = convert_offset_index(d, GICD_ICFGR, &index); |
13d22e2e | 576 | |
e91b036e | 577 | ret = gic_configure_irq(index, type, base + offset, rwp_wait); |
5f51f803 | 578 | if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) { |
13d22e2e | 579 | /* Misconfigured PPIs are usually not fatal */ |
5f51f803 | 580 | pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); |
13d22e2e MZ |
581 | ret = 0; |
582 | } | |
583 | ||
584 | return ret; | |
021f6537 MZ |
585 | } |
586 | ||
530bf353 MZ |
587 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
588 | { | |
64b499d8 MZ |
589 | if (get_intid_range(d) == SGI_RANGE) |
590 | return -EINVAL; | |
591 | ||
4df7f54d TG |
592 | if (vcpu) |
593 | irqd_set_forwarded_to_vcpu(d); | |
594 | else | |
595 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
596 | return 0; |
597 | } | |
598 | ||
f6c86a41 | 599 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
600 | { |
601 | u64 aff; | |
602 | ||
f6c86a41 | 603 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
604 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
605 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
606 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
607 | ||
608 | return aff; | |
609 | } | |
610 | ||
f32c9266 JT |
611 | static void gic_deactivate_unhandled(u32 irqnr) |
612 | { | |
613 | if (static_branch_likely(&supports_deactivate_key)) { | |
614 | if (irqnr < 8192) | |
615 | gic_write_dir(irqnr); | |
616 | } else { | |
617 | gic_write_eoir(irqnr); | |
618 | } | |
619 | } | |
620 | ||
621 | static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) | |
622 | { | |
17ce302f | 623 | bool irqs_enabled = interrupts_enabled(regs); |
f32c9266 JT |
624 | int err; |
625 | ||
17ce302f JT |
626 | if (irqs_enabled) |
627 | nmi_enter(); | |
628 | ||
f32c9266 JT |
629 | if (static_branch_likely(&supports_deactivate_key)) |
630 | gic_write_eoir(irqnr); | |
631 | /* | |
632 | * Leave the PSR.I bit set to prevent other NMIs to be | |
633 | * received while handling this one. | |
634 | * PSR.I will be restored when we ERET to the | |
635 | * interrupted context. | |
636 | */ | |
637 | err = handle_domain_nmi(gic_data.domain, irqnr, regs); | |
638 | if (err) | |
639 | gic_deactivate_unhandled(irqnr); | |
17ce302f JT |
640 | |
641 | if (irqs_enabled) | |
642 | nmi_exit(); | |
f32c9266 JT |
643 | } |
644 | ||
021f6537 MZ |
645 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
646 | { | |
f6c86a41 | 647 | u32 irqnr; |
021f6537 | 648 | |
342677d7 | 649 | irqnr = gic_read_iar(); |
021f6537 | 650 | |
f32c9266 JT |
651 | if (gic_supports_nmi() && |
652 | unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { | |
653 | gic_handle_nmi(irqnr, regs); | |
654 | return; | |
655 | } | |
656 | ||
3f1f3234 JT |
657 | if (gic_prio_masking_enabled()) { |
658 | gic_pmr_mask_irqs(); | |
659 | gic_arch_enable_irqs(); | |
660 | } | |
661 | ||
211bddd2 MZ |
662 | /* Check for special IDs first */ |
663 | if ((irqnr >= 1020 && irqnr <= 1023)) | |
664 | return; | |
665 | ||
64b499d8 | 666 | if (static_branch_likely(&supports_deactivate_key)) |
342677d7 | 667 | gic_write_eoir(irqnr); |
64b499d8 MZ |
668 | else |
669 | isb(); | |
670 | ||
671 | if (handle_domain_irq(gic_data.domain, irqnr, regs)) { | |
672 | WARN_ONCE(true, "Unexpected interrupt received!\n"); | |
673 | gic_deactivate_unhandled(irqnr); | |
342677d7 | 674 | } |
021f6537 MZ |
675 | } |
676 | ||
b5cf6073 JT |
677 | static u32 gic_get_pribits(void) |
678 | { | |
679 | u32 pribits; | |
680 | ||
681 | pribits = gic_read_ctlr(); | |
682 | pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
683 | pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
684 | pribits++; | |
685 | ||
686 | return pribits; | |
687 | } | |
688 | ||
689 | static bool gic_has_group0(void) | |
690 | { | |
691 | u32 val; | |
e7932188 JT |
692 | u32 old_pmr; |
693 | ||
694 | old_pmr = gic_read_pmr(); | |
b5cf6073 JT |
695 | |
696 | /* | |
697 | * Let's find out if Group0 is under control of EL3 or not by | |
698 | * setting the highest possible, non-zero priority in PMR. | |
699 | * | |
700 | * If SCR_EL3.FIQ is set, the priority gets shifted down in | |
701 | * order for the CPU interface to set bit 7, and keep the | |
702 | * actual priority in the non-secure range. In the process, it | |
703 | * looses the least significant bit and the actual priority | |
704 | * becomes 0x80. Reading it back returns 0, indicating that | |
705 | * we're don't have access to Group0. | |
706 | */ | |
707 | gic_write_pmr(BIT(8 - gic_get_pribits())); | |
708 | val = gic_read_pmr(); | |
709 | ||
e7932188 JT |
710 | gic_write_pmr(old_pmr); |
711 | ||
b5cf6073 JT |
712 | return val != 0; |
713 | } | |
714 | ||
021f6537 MZ |
715 | static void __init gic_dist_init(void) |
716 | { | |
717 | unsigned int i; | |
718 | u64 affinity; | |
719 | void __iomem *base = gic_data.dist_base; | |
0b04758b | 720 | u32 val; |
021f6537 MZ |
721 | |
722 | /* Disable the distributor */ | |
723 | writel_relaxed(0, base + GICD_CTLR); | |
724 | gic_dist_wait_for_rwp(); | |
725 | ||
7c9b9730 MZ |
726 | /* |
727 | * Configure SPIs as non-secure Group-1. This will only matter | |
728 | * if the GIC only has a single security state. This will not | |
729 | * do the right thing if the kernel is running in secure mode, | |
730 | * but that's not the intended use case anyway. | |
731 | */ | |
211bddd2 | 732 | for (i = 32; i < GIC_LINE_NR; i += 32) |
7c9b9730 MZ |
733 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); |
734 | ||
211bddd2 MZ |
735 | /* Extended SPI range, not handled by the GICv2/GICv3 common code */ |
736 | for (i = 0; i < GIC_ESPI_NR; i += 32) { | |
737 | writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); | |
738 | writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); | |
739 | } | |
740 | ||
741 | for (i = 0; i < GIC_ESPI_NR; i += 32) | |
742 | writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); | |
743 | ||
744 | for (i = 0; i < GIC_ESPI_NR; i += 16) | |
745 | writel_relaxed(0, base + GICD_ICFGRnE + i / 4); | |
746 | ||
747 | for (i = 0; i < GIC_ESPI_NR; i += 4) | |
748 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); | |
749 | ||
750 | /* Now do the common stuff, and wait for the distributor to drain */ | |
751 | gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); | |
021f6537 | 752 | |
0b04758b MZ |
753 | val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; |
754 | if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { | |
755 | pr_info("Enabling SGIs without active state\n"); | |
756 | val |= GICD_CTLR_nASSGIreq; | |
757 | } | |
758 | ||
021f6537 | 759 | /* Enable distributor with ARE, Group1 */ |
0b04758b | 760 | writel_relaxed(val, base + GICD_CTLR); |
021f6537 MZ |
761 | |
762 | /* | |
763 | * Set all global interrupts to the boot CPU only. ARE must be | |
764 | * enabled. | |
765 | */ | |
766 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
211bddd2 | 767 | for (i = 32; i < GIC_LINE_NR; i++) |
72c97126 | 768 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
211bddd2 MZ |
769 | |
770 | for (i = 0; i < GIC_ESPI_NR; i++) | |
771 | gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); | |
021f6537 MZ |
772 | } |
773 | ||
0d94ded2 | 774 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 775 | { |
0d94ded2 | 776 | int ret = -ENODEV; |
021f6537 MZ |
777 | int i; |
778 | ||
f5c1434c MZ |
779 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
780 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 781 | u64 typer; |
021f6537 MZ |
782 | u32 reg; |
783 | ||
784 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
785 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
786 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
787 | pr_warn("No redistributor present @%p\n", ptr); | |
788 | break; | |
789 | } | |
790 | ||
791 | do { | |
72c97126 | 792 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
793 | ret = fn(gic_data.redist_regions + i, ptr); |
794 | if (!ret) | |
021f6537 | 795 | return 0; |
021f6537 | 796 | |
b70fb7af TN |
797 | if (gic_data.redist_regions[i].single_redist) |
798 | break; | |
799 | ||
021f6537 MZ |
800 | if (gic_data.redist_stride) { |
801 | ptr += gic_data.redist_stride; | |
802 | } else { | |
803 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
804 | if (typer & GICR_TYPER_VLPIS) | |
805 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
806 | } | |
807 | } while (!(typer & GICR_TYPER_LAST)); | |
808 | } | |
809 | ||
0d94ded2 MZ |
810 | return ret ? -ENODEV : 0; |
811 | } | |
812 | ||
813 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
814 | { | |
815 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); | |
816 | u64 typer; | |
817 | u32 aff; | |
818 | ||
819 | /* | |
820 | * Convert affinity to a 32bit value that can be matched to | |
821 | * GICR_TYPER bits [63:32]. | |
822 | */ | |
823 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
824 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
825 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
826 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
827 | ||
828 | typer = gic_read_typer(ptr + GICR_TYPER); | |
829 | if ((typer >> 32) == aff) { | |
830 | u64 offset = ptr - region->redist_base; | |
9058a4e9 | 831 | raw_spin_lock_init(&gic_data_rdist()->rd_lock); |
0d94ded2 MZ |
832 | gic_data_rdist_rd_base() = ptr; |
833 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
834 | ||
835 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
836 | smp_processor_id(), mpidr, | |
837 | (int)(region - gic_data.redist_regions), | |
838 | &gic_data_rdist()->phys_base); | |
839 | return 0; | |
840 | } | |
841 | ||
842 | /* Try next one */ | |
843 | return 1; | |
844 | } | |
845 | ||
846 | static int gic_populate_rdist(void) | |
847 | { | |
848 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
849 | return 0; | |
850 | ||
021f6537 | 851 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 852 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
853 | smp_processor_id(), |
854 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
855 | return -ENODEV; |
856 | } | |
857 | ||
1a60e1e6 MZ |
858 | static int __gic_update_rdist_properties(struct redist_region *region, |
859 | void __iomem *ptr) | |
0edc23ea MZ |
860 | { |
861 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
b25319d2 | 862 | |
0edc23ea | 863 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); |
b25319d2 MZ |
864 | |
865 | /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ | |
866 | gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); | |
867 | gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | | |
868 | gic_data.rdists.has_rvpeid); | |
96806229 | 869 | gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); |
b25319d2 MZ |
870 | |
871 | /* Detect non-sensical configurations */ | |
872 | if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) { | |
873 | gic_data.rdists.has_direct_lpi = false; | |
874 | gic_data.rdists.has_vlpis = false; | |
875 | gic_data.rdists.has_rvpeid = false; | |
876 | } | |
877 | ||
5f51f803 | 878 | gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr); |
0edc23ea MZ |
879 | |
880 | return 1; | |
881 | } | |
882 | ||
1a60e1e6 | 883 | static void gic_update_rdist_properties(void) |
0edc23ea | 884 | { |
1a60e1e6 MZ |
885 | gic_data.ppi_nr = UINT_MAX; |
886 | gic_iterate_rdists(__gic_update_rdist_properties); | |
887 | if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) | |
888 | gic_data.ppi_nr = 0; | |
889 | pr_info("%d PPIs implemented\n", gic_data.ppi_nr); | |
96806229 MZ |
890 | if (gic_data.rdists.has_vlpis) |
891 | pr_info("GICv4 features: %s%s%s\n", | |
892 | gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", | |
893 | gic_data.rdists.has_rvpeid ? "RVPEID " : "", | |
894 | gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : ""); | |
0edc23ea MZ |
895 | } |
896 | ||
d98d0a99 JT |
897 | /* Check whether it's single security state view */ |
898 | static inline bool gic_dist_security_disabled(void) | |
899 | { | |
900 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
901 | } | |
902 | ||
3708d52f SH |
903 | static void gic_cpu_sys_reg_init(void) |
904 | { | |
eda0d04a SD |
905 | int i, cpu = smp_processor_id(); |
906 | u64 mpidr = cpu_logical_map(cpu); | |
907 | u64 need_rss = MPIDR_RS(mpidr); | |
33625282 | 908 | bool group0; |
b5cf6073 | 909 | u32 pribits; |
eda0d04a | 910 | |
7cabd008 MZ |
911 | /* |
912 | * Need to check that the SRE bit has actually been set. If | |
913 | * not, it means that SRE is disabled at EL2. We're going to | |
914 | * die painfully, and there is nothing we can do about it. | |
915 | * | |
916 | * Kindly inform the luser. | |
917 | */ | |
918 | if (!gic_enable_sre()) | |
919 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f | 920 | |
b5cf6073 | 921 | pribits = gic_get_pribits(); |
33625282 | 922 | |
b5cf6073 | 923 | group0 = gic_has_group0(); |
33625282 | 924 | |
3708d52f | 925 | /* Set priority mask register */ |
d98d0a99 | 926 | if (!gic_prio_masking_enabled()) { |
e7932188 | 927 | write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); |
33678059 | 928 | } else if (gic_supports_nmi()) { |
d98d0a99 JT |
929 | /* |
930 | * Mismatch configuration with boot CPU, the system is likely | |
931 | * to die as interrupt masking will not work properly on all | |
932 | * CPUs | |
33678059 AE |
933 | * |
934 | * The boot CPU calls this function before enabling NMI support, | |
935 | * and as a result we'll never see this warning in the boot path | |
936 | * for that CPU. | |
d98d0a99 | 937 | */ |
33678059 AE |
938 | if (static_branch_unlikely(&gic_nonsecure_priorities)) |
939 | WARN_ON(!group0 || gic_dist_security_disabled()); | |
940 | else | |
941 | WARN_ON(group0 && !gic_dist_security_disabled()); | |
d98d0a99 | 942 | } |
3708d52f | 943 | |
91ef8442 DT |
944 | /* |
945 | * Some firmwares hand over to the kernel with the BPR changed from | |
946 | * its reset value (and with a value large enough to prevent | |
947 | * any pre-emptive interrupts from working at all). Writing a zero | |
948 | * to BPR restores is reset value. | |
949 | */ | |
950 | gic_write_bpr1(0); | |
951 | ||
d01d3274 | 952 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
953 | /* EOI drops priority only (mode 1) */ |
954 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
955 | } else { | |
956 | /* EOI deactivates interrupt too (mode 0) */ | |
957 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
958 | } | |
3708d52f | 959 | |
33625282 MZ |
960 | /* Always whack Group0 before Group1 */ |
961 | if (group0) { | |
962 | switch(pribits) { | |
963 | case 8: | |
964 | case 7: | |
965 | write_gicreg(0, ICC_AP0R3_EL1); | |
966 | write_gicreg(0, ICC_AP0R2_EL1); | |
df561f66 | 967 | fallthrough; |
33625282 MZ |
968 | case 6: |
969 | write_gicreg(0, ICC_AP0R1_EL1); | |
df561f66 | 970 | fallthrough; |
33625282 MZ |
971 | case 5: |
972 | case 4: | |
973 | write_gicreg(0, ICC_AP0R0_EL1); | |
974 | } | |
975 | ||
976 | isb(); | |
977 | } | |
d6062a6d | 978 | |
33625282 | 979 | switch(pribits) { |
d6062a6d MZ |
980 | case 8: |
981 | case 7: | |
d6062a6d | 982 | write_gicreg(0, ICC_AP1R3_EL1); |
d6062a6d | 983 | write_gicreg(0, ICC_AP1R2_EL1); |
df561f66 | 984 | fallthrough; |
d6062a6d | 985 | case 6: |
d6062a6d | 986 | write_gicreg(0, ICC_AP1R1_EL1); |
df561f66 | 987 | fallthrough; |
d6062a6d MZ |
988 | case 5: |
989 | case 4: | |
d6062a6d MZ |
990 | write_gicreg(0, ICC_AP1R0_EL1); |
991 | } | |
992 | ||
993 | isb(); | |
994 | ||
3708d52f SH |
995 | /* ... and let's hit the road... */ |
996 | gic_write_grpen1(1); | |
eda0d04a SD |
997 | |
998 | /* Keep the RSS capability status in per_cpu variable */ | |
999 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
1000 | ||
1001 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
1002 | for_each_online_cpu(i) { | |
1003 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
1004 | ||
1005 | need_rss |= MPIDR_RS(cpu_logical_map(i)); | |
1006 | if (need_rss && (!have_rss)) | |
1007 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
1008 | cpu, (unsigned long)mpidr, | |
1009 | i, (unsigned long)cpu_logical_map(i)); | |
1010 | } | |
1011 | ||
1012 | /** | |
1013 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
1014 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
1015 | * UNPREDICTABLE choice of : | |
1016 | * - The write is ignored. | |
1017 | * - The RS field is treated as 0. | |
1018 | */ | |
1019 | if (need_rss && (!gic_data.has_rss)) | |
1020 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
1021 | } |
1022 | ||
f736d65d MZ |
1023 | static bool gicv3_nolpi; |
1024 | ||
1025 | static int __init gicv3_nolpi_cfg(char *buf) | |
1026 | { | |
1027 | return strtobool(buf, &gicv3_nolpi); | |
1028 | } | |
1029 | early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); | |
1030 | ||
da33f31d MZ |
1031 | static int gic_dist_supports_lpis(void) |
1032 | { | |
d38a71c5 MZ |
1033 | return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && |
1034 | !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && | |
1035 | !gicv3_nolpi); | |
da33f31d MZ |
1036 | } |
1037 | ||
021f6537 MZ |
1038 | static void gic_cpu_init(void) |
1039 | { | |
1040 | void __iomem *rbase; | |
1a60e1e6 | 1041 | int i; |
021f6537 MZ |
1042 | |
1043 | /* Register ourselves with the rest of the world */ | |
1044 | if (gic_populate_rdist()) | |
1045 | return; | |
1046 | ||
a2c22510 | 1047 | gic_enable_redist(true); |
021f6537 | 1048 | |
ad5a78d3 MZ |
1049 | WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) && |
1050 | !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange), | |
1051 | "Distributor has extended ranges, but CPU%d doesn't\n", | |
1052 | smp_processor_id()); | |
1053 | ||
021f6537 MZ |
1054 | rbase = gic_data_rdist_sgi_base(); |
1055 | ||
7c9b9730 | 1056 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
1a60e1e6 MZ |
1057 | for (i = 0; i < gic_data.ppi_nr + 16; i += 32) |
1058 | writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); | |
7c9b9730 | 1059 | |
1a60e1e6 | 1060 | gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); |
021f6537 | 1061 | |
3708d52f SH |
1062 | /* initialise system registers */ |
1063 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
1064 | } |
1065 | ||
1066 | #ifdef CONFIG_SMP | |
6670a6d8 | 1067 | |
eda0d04a SD |
1068 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
1069 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
1070 | ||
6670a6d8 | 1071 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 1072 | { |
6670a6d8 | 1073 | gic_cpu_init(); |
d38a71c5 MZ |
1074 | |
1075 | if (gic_dist_supports_lpis()) | |
1076 | its_cpu_init(); | |
1077 | ||
6670a6d8 | 1078 | return 0; |
021f6537 MZ |
1079 | } |
1080 | ||
021f6537 | 1081 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 1082 | unsigned long cluster_id) |
021f6537 | 1083 | { |
727653d6 | 1084 | int next_cpu, cpu = *base_cpu; |
f6c86a41 | 1085 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
1086 | u16 tlist = 0; |
1087 | ||
1088 | while (cpu < nr_cpu_ids) { | |
021f6537 MZ |
1089 | tlist |= 1 << (mpidr & 0xf); |
1090 | ||
727653d6 JM |
1091 | next_cpu = cpumask_next(cpu, mask); |
1092 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 1093 | goto out; |
727653d6 | 1094 | cpu = next_cpu; |
021f6537 MZ |
1095 | |
1096 | mpidr = cpu_logical_map(cpu); | |
1097 | ||
eda0d04a | 1098 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
1099 | cpu--; |
1100 | goto out; | |
1101 | } | |
1102 | } | |
1103 | out: | |
1104 | *base_cpu = cpu; | |
1105 | return tlist; | |
1106 | } | |
1107 | ||
7e580278 AP |
1108 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
1109 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
1110 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
1111 | ||
021f6537 MZ |
1112 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
1113 | { | |
1114 | u64 val; | |
1115 | ||
7e580278 AP |
1116 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
1117 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
1118 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
1119 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 1120 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 1121 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 1122 | |
b6dd4d83 | 1123 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
1124 | gic_write_sgi1r(val); |
1125 | } | |
1126 | ||
64b499d8 | 1127 | static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) |
021f6537 MZ |
1128 | { |
1129 | int cpu; | |
1130 | ||
64b499d8 | 1131 | if (WARN_ON(d->hwirq >= 16)) |
021f6537 MZ |
1132 | return; |
1133 | ||
1134 | /* | |
1135 | * Ensure that stores to Normal memory are visible to the | |
1136 | * other CPUs before issuing the IPI. | |
1137 | */ | |
21ec30c0 | 1138 | wmb(); |
021f6537 | 1139 | |
f9b531fe | 1140 | for_each_cpu(cpu, mask) { |
eda0d04a | 1141 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); |
021f6537 MZ |
1142 | u16 tlist; |
1143 | ||
1144 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
64b499d8 | 1145 | gic_send_sgi(cluster_id, tlist, d->hwirq); |
021f6537 MZ |
1146 | } |
1147 | ||
1148 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
1149 | isb(); | |
1150 | } | |
1151 | ||
8a94c1ab | 1152 | static void __init gic_smp_init(void) |
021f6537 | 1153 | { |
64b499d8 MZ |
1154 | struct irq_fwspec sgi_fwspec = { |
1155 | .fwnode = gic_data.fwnode, | |
1156 | .param_count = 1, | |
1157 | }; | |
1158 | int base_sgi; | |
1159 | ||
6896bcd1 | 1160 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
1161 | "irqchip/arm/gicv3:starting", |
1162 | gic_starting_cpu, NULL); | |
64b499d8 MZ |
1163 | |
1164 | /* Register all 8 non-secure SGIs */ | |
1165 | base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, | |
1166 | NUMA_NO_NODE, &sgi_fwspec, | |
1167 | false, NULL); | |
1168 | if (WARN_ON(base_sgi <= 0)) | |
1169 | return; | |
1170 | ||
1171 | set_smp_ipi_range(base_sgi, 8); | |
021f6537 MZ |
1172 | } |
1173 | ||
1174 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
1175 | bool force) | |
1176 | { | |
65a30f8b | 1177 | unsigned int cpu; |
e91b036e | 1178 | u32 offset, index; |
021f6537 MZ |
1179 | void __iomem *reg; |
1180 | int enabled; | |
1181 | u64 val; | |
1182 | ||
65a30f8b SP |
1183 | if (force) |
1184 | cpu = cpumask_first(mask_val); | |
1185 | else | |
1186 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
1187 | ||
866d7c1b SP |
1188 | if (cpu >= nr_cpu_ids) |
1189 | return -EINVAL; | |
1190 | ||
021f6537 MZ |
1191 | if (gic_irq_in_rdist(d)) |
1192 | return -EINVAL; | |
1193 | ||
1194 | /* If interrupt was enabled, disable it first */ | |
1195 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
1196 | if (enabled) | |
1197 | gic_mask_irq(d); | |
1198 | ||
e91b036e MZ |
1199 | offset = convert_offset_index(d, GICD_IROUTER, &index); |
1200 | reg = gic_dist_base(d) + offset + (index * 8); | |
021f6537 MZ |
1201 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); |
1202 | ||
72c97126 | 1203 | gic_write_irouter(val, reg); |
021f6537 MZ |
1204 | |
1205 | /* | |
1206 | * If the interrupt was enabled, enabled it again. Otherwise, | |
1207 | * just wait for the distributor to have digested our changes. | |
1208 | */ | |
1209 | if (enabled) | |
1210 | gic_unmask_irq(d); | |
1211 | else | |
1212 | gic_dist_wait_for_rwp(); | |
1213 | ||
956ae91a MZ |
1214 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
1215 | ||
0fc6fa29 | 1216 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
1217 | } |
1218 | #else | |
1219 | #define gic_set_affinity NULL | |
64b499d8 | 1220 | #define gic_ipi_send_mask NULL |
021f6537 MZ |
1221 | #define gic_smp_init() do { } while(0) |
1222 | #endif | |
1223 | ||
17f644e9 VS |
1224 | static int gic_retrigger(struct irq_data *data) |
1225 | { | |
1226 | return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); | |
1227 | } | |
1228 | ||
3708d52f SH |
1229 | #ifdef CONFIG_CPU_PM |
1230 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
1231 | unsigned long cmd, void *v) | |
1232 | { | |
1233 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
1234 | if (gic_dist_security_disabled()) |
1235 | gic_enable_redist(true); | |
3708d52f | 1236 | gic_cpu_sys_reg_init(); |
ccd9432a | 1237 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
1238 | gic_write_grpen1(0); |
1239 | gic_enable_redist(false); | |
1240 | } | |
1241 | return NOTIFY_OK; | |
1242 | } | |
1243 | ||
1244 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
1245 | .notifier_call = gic_cpu_pm_notifier, | |
1246 | }; | |
1247 | ||
1248 | static void gic_cpu_pm_init(void) | |
1249 | { | |
1250 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
1251 | } | |
1252 | ||
1253 | #else | |
1254 | static inline void gic_cpu_pm_init(void) { } | |
1255 | #endif /* CONFIG_CPU_PM */ | |
1256 | ||
021f6537 MZ |
1257 | static struct irq_chip gic_chip = { |
1258 | .name = "GICv3", | |
1259 | .irq_mask = gic_mask_irq, | |
1260 | .irq_unmask = gic_unmask_irq, | |
1261 | .irq_eoi = gic_eoi_irq, | |
1262 | .irq_set_type = gic_set_type, | |
1263 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1264 | .irq_retrigger = gic_retrigger, |
b594c6e2 MZ |
1265 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1266 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
101b35f7 JT |
1267 | .irq_nmi_setup = gic_irq_nmi_setup, |
1268 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1269 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1270 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1271 | IRQCHIP_SKIP_SET_WAKE | | |
1272 | IRQCHIP_MASK_ON_SUSPEND, | |
021f6537 MZ |
1273 | }; |
1274 | ||
0b6a3da9 MZ |
1275 | static struct irq_chip gic_eoimode1_chip = { |
1276 | .name = "GICv3", | |
1277 | .irq_mask = gic_eoimode1_mask_irq, | |
1278 | .irq_unmask = gic_unmask_irq, | |
1279 | .irq_eoi = gic_eoimode1_eoi_irq, | |
1280 | .irq_set_type = gic_set_type, | |
1281 | .irq_set_affinity = gic_set_affinity, | |
17f644e9 | 1282 | .irq_retrigger = gic_retrigger, |
0b6a3da9 MZ |
1283 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1284 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 1285 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
101b35f7 JT |
1286 | .irq_nmi_setup = gic_irq_nmi_setup, |
1287 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
64b499d8 | 1288 | .ipi_send_mask = gic_ipi_send_mask, |
4110b5cb MZ |
1289 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1290 | IRQCHIP_SKIP_SET_WAKE | | |
1291 | IRQCHIP_MASK_ON_SUSPEND, | |
0b6a3da9 MZ |
1292 | }; |
1293 | ||
021f6537 MZ |
1294 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
1295 | irq_hw_number_t hw) | |
1296 | { | |
0b6a3da9 | 1297 | struct irq_chip *chip = &gic_chip; |
1b57d91b | 1298 | struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); |
0b6a3da9 | 1299 | |
d01d3274 | 1300 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1301 | chip = &gic_eoimode1_chip; |
1302 | ||
e91b036e | 1303 | switch (__get_intid_range(hw)) { |
70a29c32 | 1304 | case SGI_RANGE: |
64b499d8 MZ |
1305 | irq_set_percpu_devid(irq); |
1306 | irq_domain_set_info(d, irq, hw, chip, d->host_data, | |
1307 | handle_percpu_devid_fasteoi_ipi, | |
1308 | NULL, NULL); | |
1309 | break; | |
1310 | ||
e91b036e | 1311 | case PPI_RANGE: |
5f51f803 | 1312 | case EPPI_RANGE: |
021f6537 | 1313 | irq_set_percpu_devid(irq); |
0b6a3da9 | 1314 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1315 | handle_percpu_devid_irq, NULL, NULL); |
e91b036e MZ |
1316 | break; |
1317 | ||
1318 | case SPI_RANGE: | |
211bddd2 | 1319 | case ESPI_RANGE: |
0b6a3da9 | 1320 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1321 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 1322 | irq_set_probe(irq); |
1b57d91b | 1323 | irqd_set_single_target(irqd); |
e91b036e MZ |
1324 | break; |
1325 | ||
1326 | case LPI_RANGE: | |
da33f31d MZ |
1327 | if (!gic_dist_supports_lpis()) |
1328 | return -EPERM; | |
0b6a3da9 | 1329 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 1330 | handle_fasteoi_irq, NULL, NULL); |
e91b036e MZ |
1331 | break; |
1332 | ||
1333 | default: | |
1334 | return -EPERM; | |
da33f31d MZ |
1335 | } |
1336 | ||
1b57d91b VS |
1337 | /* Prevents SW retriggers which mess up the ACK/EOI ordering */ |
1338 | irqd_set_handle_enforce_irqctx(irqd); | |
021f6537 MZ |
1339 | return 0; |
1340 | } | |
1341 | ||
f833f57f MZ |
1342 | static int gic_irq_domain_translate(struct irq_domain *d, |
1343 | struct irq_fwspec *fwspec, | |
1344 | unsigned long *hwirq, | |
1345 | unsigned int *type) | |
021f6537 | 1346 | { |
64b499d8 MZ |
1347 | if (fwspec->param_count == 1 && fwspec->param[0] < 16) { |
1348 | *hwirq = fwspec->param[0]; | |
1349 | *type = IRQ_TYPE_EDGE_RISING; | |
1350 | return 0; | |
1351 | } | |
1352 | ||
f833f57f MZ |
1353 | if (is_of_node(fwspec->fwnode)) { |
1354 | if (fwspec->param_count < 3) | |
1355 | return -EINVAL; | |
021f6537 | 1356 | |
db8c70ec MZ |
1357 | switch (fwspec->param[0]) { |
1358 | case 0: /* SPI */ | |
1359 | *hwirq = fwspec->param[1] + 32; | |
1360 | break; | |
1361 | case 1: /* PPI */ | |
1362 | *hwirq = fwspec->param[1] + 16; | |
1363 | break; | |
211bddd2 MZ |
1364 | case 2: /* ESPI */ |
1365 | *hwirq = fwspec->param[1] + ESPI_BASE_INTID; | |
1366 | break; | |
5f51f803 MZ |
1367 | case 3: /* EPPI */ |
1368 | *hwirq = fwspec->param[1] + EPPI_BASE_INTID; | |
1369 | break; | |
db8c70ec MZ |
1370 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
1371 | *hwirq = fwspec->param[1]; | |
1372 | break; | |
5f51f803 MZ |
1373 | case GIC_IRQ_TYPE_PARTITION: |
1374 | *hwirq = fwspec->param[1]; | |
1375 | if (fwspec->param[1] >= 16) | |
1376 | *hwirq += EPPI_BASE_INTID - 16; | |
1377 | else | |
1378 | *hwirq += 16; | |
1379 | break; | |
db8c70ec MZ |
1380 | default: |
1381 | return -EINVAL; | |
1382 | } | |
f833f57f MZ |
1383 | |
1384 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
6ef6386e | 1385 | |
65da7d19 MZ |
1386 | /* |
1387 | * Make it clear that broken DTs are... broken. | |
1388 | * Partitionned PPIs are an unfortunate exception. | |
1389 | */ | |
1390 | WARN_ON(*type == IRQ_TYPE_NONE && | |
1391 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | |
f833f57f | 1392 | return 0; |
021f6537 MZ |
1393 | } |
1394 | ||
ffa7d616 TN |
1395 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
1396 | if(fwspec->param_count != 2) | |
1397 | return -EINVAL; | |
1398 | ||
1399 | *hwirq = fwspec->param[0]; | |
1400 | *type = fwspec->param[1]; | |
6ef6386e MZ |
1401 | |
1402 | WARN_ON(*type == IRQ_TYPE_NONE); | |
ffa7d616 TN |
1403 | return 0; |
1404 | } | |
1405 | ||
f833f57f | 1406 | return -EINVAL; |
021f6537 MZ |
1407 | } |
1408 | ||
443acc4f MZ |
1409 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1410 | unsigned int nr_irqs, void *arg) | |
1411 | { | |
1412 | int i, ret; | |
1413 | irq_hw_number_t hwirq; | |
1414 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1415 | struct irq_fwspec *fwspec = arg; |
443acc4f | 1416 | |
f833f57f | 1417 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
1418 | if (ret) |
1419 | return ret; | |
1420 | ||
63c16c6e SP |
1421 | for (i = 0; i < nr_irqs; i++) { |
1422 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1423 | if (ret) | |
1424 | return ret; | |
1425 | } | |
443acc4f MZ |
1426 | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
1431 | unsigned int nr_irqs) | |
1432 | { | |
1433 | int i; | |
1434 | ||
1435 | for (i = 0; i < nr_irqs; i++) { | |
1436 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
1437 | irq_set_handler(virq + i, NULL); | |
1438 | irq_domain_reset_irq_data(d); | |
1439 | } | |
1440 | } | |
1441 | ||
e3825ba1 MZ |
1442 | static int gic_irq_domain_select(struct irq_domain *d, |
1443 | struct irq_fwspec *fwspec, | |
1444 | enum irq_domain_bus_token bus_token) | |
1445 | { | |
1446 | /* Not for us */ | |
1447 | if (fwspec->fwnode != d->fwnode) | |
1448 | return 0; | |
1449 | ||
1450 | /* If this is not DT, then we have a single domain */ | |
1451 | if (!is_of_node(fwspec->fwnode)) | |
1452 | return 1; | |
1453 | ||
1454 | /* | |
1455 | * If this is a PPI and we have a 4th (non-null) parameter, | |
1456 | * then we need to match the partition domain. | |
1457 | */ | |
1458 | if (fwspec->param_count >= 4 && | |
52085d3f MZ |
1459 | fwspec->param[0] == 1 && fwspec->param[3] != 0 && |
1460 | gic_data.ppi_descs) | |
e3825ba1 MZ |
1461 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); |
1462 | ||
1463 | return d == gic_data.domain; | |
1464 | } | |
1465 | ||
021f6537 | 1466 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 1467 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
1468 | .alloc = gic_irq_domain_alloc, |
1469 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
1470 | .select = gic_irq_domain_select, |
1471 | }; | |
1472 | ||
1473 | static int partition_domain_translate(struct irq_domain *d, | |
1474 | struct irq_fwspec *fwspec, | |
1475 | unsigned long *hwirq, | |
1476 | unsigned int *type) | |
1477 | { | |
1478 | struct device_node *np; | |
1479 | int ret; | |
1480 | ||
52085d3f MZ |
1481 | if (!gic_data.ppi_descs) |
1482 | return -ENOMEM; | |
1483 | ||
e3825ba1 MZ |
1484 | np = of_find_node_by_phandle(fwspec->param[3]); |
1485 | if (WARN_ON(!np)) | |
1486 | return -EINVAL; | |
1487 | ||
1488 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
1489 | of_node_to_fwnode(np)); | |
1490 | if (ret < 0) | |
1491 | return ret; | |
1492 | ||
1493 | *hwirq = ret; | |
1494 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | static const struct irq_domain_ops partition_domain_ops = { | |
1500 | .translate = partition_domain_translate, | |
1501 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1502 | }; |
1503 | ||
9c8114c2 SK |
1504 | static bool gic_enable_quirk_msm8996(void *data) |
1505 | { | |
1506 | struct gic_chip_data *d = data; | |
1507 | ||
1508 | d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; | |
1509 | ||
1510 | return true; | |
1511 | } | |
1512 | ||
d01fd161 MZ |
1513 | static bool gic_enable_quirk_cavium_38539(void *data) |
1514 | { | |
1515 | struct gic_chip_data *d = data; | |
1516 | ||
1517 | d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; | |
1518 | ||
1519 | return true; | |
1520 | } | |
1521 | ||
7f2481b3 MZ |
1522 | static bool gic_enable_quirk_hip06_07(void *data) |
1523 | { | |
1524 | struct gic_chip_data *d = data; | |
1525 | ||
1526 | /* | |
1527 | * HIP06 GICD_IIDR clashes with GIC-600 product number (despite | |
1528 | * not being an actual ARM implementation). The saving grace is | |
1529 | * that GIC-600 doesn't have ESPI, so nothing to do in that case. | |
1530 | * HIP07 doesn't even have a proper IIDR, and still pretends to | |
1531 | * have ESPI. In both cases, put them right. | |
1532 | */ | |
1533 | if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { | |
1534 | /* Zero both ESPI and the RES0 field next to it... */ | |
1535 | d->rdists.gicd_typer &= ~GENMASK(9, 8); | |
1536 | return true; | |
1537 | } | |
1538 | ||
1539 | return false; | |
1540 | } | |
1541 | ||
1542 | static const struct gic_quirk gic_quirks[] = { | |
1543 | { | |
1544 | .desc = "GICv3: Qualcomm MSM8996 broken firmware", | |
1545 | .compatible = "qcom,msm8996-gic-v3", | |
1546 | .init = gic_enable_quirk_msm8996, | |
1547 | }, | |
1548 | { | |
1549 | .desc = "GICv3: HIP06 erratum 161010803", | |
1550 | .iidr = 0x0204043b, | |
1551 | .mask = 0xffffffff, | |
1552 | .init = gic_enable_quirk_hip06_07, | |
1553 | }, | |
1554 | { | |
1555 | .desc = "GICv3: HIP07 erratum 161010803", | |
1556 | .iidr = 0x00000000, | |
1557 | .mask = 0xffffffff, | |
1558 | .init = gic_enable_quirk_hip06_07, | |
1559 | }, | |
d01fd161 MZ |
1560 | { |
1561 | /* | |
1562 | * Reserved register accesses generate a Synchronous | |
1563 | * External Abort. This erratum applies to: | |
1564 | * - ThunderX: CN88xx | |
1565 | * - OCTEON TX: CN83xx, CN81xx | |
1566 | * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* | |
1567 | */ | |
1568 | .desc = "GICv3: Cavium erratum 38539", | |
1569 | .iidr = 0xa000034c, | |
1570 | .mask = 0xe8f00fff, | |
1571 | .init = gic_enable_quirk_cavium_38539, | |
1572 | }, | |
7f2481b3 MZ |
1573 | { |
1574 | } | |
1575 | }; | |
1576 | ||
d98d0a99 JT |
1577 | static void gic_enable_nmi_support(void) |
1578 | { | |
101b35f7 JT |
1579 | int i; |
1580 | ||
81a43273 MZ |
1581 | if (!gic_prio_masking_enabled()) |
1582 | return; | |
1583 | ||
81a43273 MZ |
1584 | ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL); |
1585 | if (!ppi_nmi_refs) | |
1586 | return; | |
1587 | ||
1588 | for (i = 0; i < gic_data.ppi_nr; i++) | |
101b35f7 JT |
1589 | refcount_set(&ppi_nmi_refs[i], 0); |
1590 | ||
f2266504 MZ |
1591 | /* |
1592 | * Linux itself doesn't use 1:N distribution, so has no need to | |
1593 | * set PMHE. The only reason to have it set is if EL3 requires it | |
1594 | * (and we can't change it). | |
1595 | */ | |
1596 | if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) | |
1597 | static_branch_enable(&gic_pmr_sync); | |
1598 | ||
4e594ad1 AE |
1599 | pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", |
1600 | static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed"); | |
f2266504 | 1601 | |
33678059 AE |
1602 | /* |
1603 | * How priority values are used by the GIC depends on two things: | |
1604 | * the security state of the GIC (controlled by the GICD_CTRL.DS bit) | |
1605 | * and if Group 0 interrupts can be delivered to Linux in the non-secure | |
1606 | * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the | |
1607 | * the ICC_PMR_EL1 register and the priority that software assigns to | |
1608 | * interrupts: | |
1609 | * | |
1610 | * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority | |
1611 | * ----------------------------------------------------------- | |
1612 | * 1 | - | unchanged | unchanged | |
1613 | * ----------------------------------------------------------- | |
1614 | * 0 | 1 | non-secure | non-secure | |
1615 | * ----------------------------------------------------------- | |
1616 | * 0 | 0 | unchanged | non-secure | |
1617 | * | |
1618 | * where non-secure means that the value is right-shifted by one and the | |
1619 | * MSB bit set, to make it fit in the non-secure priority range. | |
1620 | * | |
1621 | * In the first two cases, where ICC_PMR_EL1 and the interrupt priority | |
1622 | * are both either modified or unchanged, we can use the same set of | |
1623 | * priorities. | |
1624 | * | |
1625 | * In the last case, where only the interrupt priorities are modified to | |
1626 | * be in the non-secure range, we use a different PMR value to mask IRQs | |
1627 | * and the rest of the values that we use remain unchanged. | |
1628 | */ | |
1629 | if (gic_has_group0() && !gic_dist_security_disabled()) | |
1630 | static_branch_enable(&gic_nonsecure_priorities); | |
1631 | ||
d98d0a99 | 1632 | static_branch_enable(&supports_pseudo_nmis); |
101b35f7 JT |
1633 | |
1634 | if (static_branch_likely(&supports_deactivate_key)) | |
1635 | gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
1636 | else | |
1637 | gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
d98d0a99 JT |
1638 | } |
1639 | ||
db57d746 TN |
1640 | static int __init gic_init_bases(void __iomem *dist_base, |
1641 | struct redist_region *rdist_regs, | |
1642 | u32 nr_redist_regions, | |
1643 | u64 redist_stride, | |
1644 | struct fwnode_handle *handle) | |
021f6537 | 1645 | { |
f5c1434c | 1646 | u32 typer; |
021f6537 | 1647 | int err; |
021f6537 | 1648 | |
0b6a3da9 | 1649 | if (!is_hyp_mode_available()) |
d01d3274 | 1650 | static_branch_disable(&supports_deactivate_key); |
0b6a3da9 | 1651 | |
d01d3274 | 1652 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1653 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
1654 | ||
e3825ba1 | 1655 | gic_data.fwnode = handle; |
021f6537 | 1656 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
1657 | gic_data.redist_regions = rdist_regs; |
1658 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
1659 | gic_data.redist_stride = redist_stride; |
1660 | ||
1661 | /* | |
1662 | * Find out how many interrupts are supported. | |
021f6537 | 1663 | */ |
f5c1434c | 1664 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
a4f9edb2 | 1665 | gic_data.rdists.gicd_typer = typer; |
7f2481b3 MZ |
1666 | |
1667 | gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR), | |
1668 | gic_quirks, &gic_data); | |
1669 | ||
211bddd2 MZ |
1670 | pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); |
1671 | pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR); | |
f2d83409 | 1672 | |
d01fd161 MZ |
1673 | /* |
1674 | * ThunderX1 explodes on reading GICD_TYPER2, in violation of the | |
1675 | * architecture spec (which says that reserved registers are RES0). | |
1676 | */ | |
1677 | if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539)) | |
1678 | gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2); | |
f2d83409 | 1679 | |
db57d746 TN |
1680 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
1681 | &gic_data); | |
f5c1434c | 1682 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
b25319d2 | 1683 | gic_data.rdists.has_rvpeid = true; |
0edc23ea MZ |
1684 | gic_data.rdists.has_vlpis = true; |
1685 | gic_data.rdists.has_direct_lpi = true; | |
96806229 | 1686 | gic_data.rdists.has_vpend_valid_dirty = true; |
021f6537 | 1687 | |
f5c1434c | 1688 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
1689 | err = -ENOMEM; |
1690 | goto out_free; | |
1691 | } | |
1692 | ||
eeaa4b24 | 1693 | irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); |
1694 | ||
eda0d04a SD |
1695 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
1696 | pr_info("Distributor has %sRange Selector support\n", | |
1697 | gic_data.has_rss ? "" : "no "); | |
1698 | ||
50528752 MZ |
1699 | if (typer & GICD_TYPER_MBIS) { |
1700 | err = mbi_init(handle, gic_data.domain); | |
1701 | if (err) | |
1702 | pr_err("Failed to initialize MBIs\n"); | |
1703 | } | |
1704 | ||
021f6537 MZ |
1705 | set_handle_irq(gic_handle_irq); |
1706 | ||
1a60e1e6 | 1707 | gic_update_rdist_properties(); |
0edc23ea | 1708 | |
021f6537 MZ |
1709 | gic_dist_init(); |
1710 | gic_cpu_init(); | |
64b499d8 | 1711 | gic_smp_init(); |
3708d52f | 1712 | gic_cpu_pm_init(); |
021f6537 | 1713 | |
d38a71c5 MZ |
1714 | if (gic_dist_supports_lpis()) { |
1715 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
1716 | its_cpu_init(); | |
90b4c555 ZZ |
1717 | } else { |
1718 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1719 | gicv2m_init(handle, gic_data.domain); | |
d38a71c5 MZ |
1720 | } |
1721 | ||
81a43273 | 1722 | gic_enable_nmi_support(); |
d98d0a99 | 1723 | |
021f6537 MZ |
1724 | return 0; |
1725 | ||
1726 | out_free: | |
1727 | if (gic_data.domain) | |
1728 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 1729 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
1730 | return err; |
1731 | } | |
1732 | ||
1733 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
1734 | { | |
1735 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1736 | ||
1737 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
1738 | return -ENODEV; | |
1739 | ||
1740 | return 0; | |
1741 | } | |
1742 | ||
e3825ba1 | 1743 | /* Create all possible partitions at boot time */ |
7beaa24b | 1744 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
1745 | { |
1746 | struct device_node *parts_node, *child_part; | |
1747 | int part_idx = 0, i; | |
1748 | int nr_parts; | |
1749 | struct partition_affinity *parts; | |
1750 | ||
00ee9a1c | 1751 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
1752 | if (!parts_node) |
1753 | return; | |
1754 | ||
52085d3f MZ |
1755 | gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL); |
1756 | if (!gic_data.ppi_descs) | |
1757 | return; | |
1758 | ||
e3825ba1 MZ |
1759 | nr_parts = of_get_child_count(parts_node); |
1760 | ||
1761 | if (!nr_parts) | |
00ee9a1c | 1762 | goto out_put_node; |
e3825ba1 | 1763 | |
6396bb22 | 1764 | parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); |
e3825ba1 | 1765 | if (WARN_ON(!parts)) |
00ee9a1c | 1766 | goto out_put_node; |
e3825ba1 MZ |
1767 | |
1768 | for_each_child_of_node(parts_node, child_part) { | |
1769 | struct partition_affinity *part; | |
1770 | int n; | |
1771 | ||
1772 | part = &parts[part_idx]; | |
1773 | ||
1774 | part->partition_id = of_node_to_fwnode(child_part); | |
1775 | ||
2ef790dc RH |
1776 | pr_info("GIC: PPI partition %pOFn[%d] { ", |
1777 | child_part, part_idx); | |
e3825ba1 MZ |
1778 | |
1779 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1780 | sizeof(u32)); | |
1781 | WARN_ON(n <= 0); | |
1782 | ||
1783 | for (i = 0; i < n; i++) { | |
1784 | int err, cpu; | |
1785 | u32 cpu_phandle; | |
1786 | struct device_node *cpu_node; | |
1787 | ||
1788 | err = of_property_read_u32_index(child_part, "affinity", | |
1789 | i, &cpu_phandle); | |
1790 | if (WARN_ON(err)) | |
1791 | continue; | |
1792 | ||
1793 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1794 | if (WARN_ON(!cpu_node)) | |
1795 | continue; | |
1796 | ||
c08ec7da SP |
1797 | cpu = of_cpu_node_to_id(cpu_node); |
1798 | if (WARN_ON(cpu < 0)) | |
e3825ba1 MZ |
1799 | continue; |
1800 | ||
e81f54c6 | 1801 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
1802 | |
1803 | cpumask_set_cpu(cpu, &part->mask); | |
1804 | } | |
1805 | ||
1806 | pr_cont("}\n"); | |
1807 | part_idx++; | |
1808 | } | |
1809 | ||
52085d3f | 1810 | for (i = 0; i < gic_data.ppi_nr; i++) { |
e3825ba1 MZ |
1811 | unsigned int irq; |
1812 | struct partition_desc *desc; | |
1813 | struct irq_fwspec ppi_fwspec = { | |
1814 | .fwnode = gic_data.fwnode, | |
1815 | .param_count = 3, | |
1816 | .param = { | |
65da7d19 | 1817 | [0] = GIC_IRQ_TYPE_PARTITION, |
e3825ba1 MZ |
1818 | [1] = i, |
1819 | [2] = IRQ_TYPE_NONE, | |
1820 | }, | |
1821 | }; | |
1822 | ||
1823 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1824 | if (WARN_ON(!irq)) | |
1825 | continue; | |
1826 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1827 | irq, &partition_domain_ops); | |
1828 | if (WARN_ON(!desc)) | |
1829 | continue; | |
1830 | ||
1831 | gic_data.ppi_descs[i] = desc; | |
1832 | } | |
00ee9a1c JH |
1833 | |
1834 | out_put_node: | |
1835 | of_node_put(parts_node); | |
e3825ba1 MZ |
1836 | } |
1837 | ||
1839e576 JG |
1838 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1839 | { | |
1840 | int ret; | |
1841 | struct resource r; | |
1842 | u32 gicv_idx; | |
1843 | ||
1844 | gic_v3_kvm_info.type = GIC_V3; | |
1845 | ||
1846 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1847 | if (!gic_v3_kvm_info.maint_irq) | |
1848 | return; | |
1849 | ||
1850 | if (of_property_read_u32(node, "#redistributor-regions", | |
1851 | &gicv_idx)) | |
1852 | gicv_idx = 1; | |
1853 | ||
1854 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
1855 | ret = of_address_to_resource(node, gicv_idx, &r); | |
1856 | if (!ret) | |
1857 | gic_v3_kvm_info.vcpu = r; | |
1858 | ||
4bdf5025 | 1859 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 1860 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
1839e576 JG |
1861 | gic_set_kvm_info(&gic_v3_kvm_info); |
1862 | } | |
1863 | ||
db57d746 TN |
1864 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1865 | { | |
1866 | void __iomem *dist_base; | |
1867 | struct redist_region *rdist_regs; | |
1868 | u64 redist_stride; | |
1869 | u32 nr_redist_regions; | |
1870 | int err, i; | |
1871 | ||
1872 | dist_base = of_iomap(node, 0); | |
1873 | if (!dist_base) { | |
e81f54c6 | 1874 | pr_err("%pOF: unable to map gic dist registers\n", node); |
db57d746 TN |
1875 | return -ENXIO; |
1876 | } | |
1877 | ||
1878 | err = gic_validate_dist_version(dist_base); | |
1879 | if (err) { | |
e81f54c6 | 1880 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
1881 | goto out_unmap_dist; |
1882 | } | |
1883 | ||
1884 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1885 | nr_redist_regions = 1; | |
1886 | ||
6396bb22 KC |
1887 | rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), |
1888 | GFP_KERNEL); | |
db57d746 TN |
1889 | if (!rdist_regs) { |
1890 | err = -ENOMEM; | |
1891 | goto out_unmap_dist; | |
1892 | } | |
1893 | ||
1894 | for (i = 0; i < nr_redist_regions; i++) { | |
1895 | struct resource res; | |
1896 | int ret; | |
1897 | ||
1898 | ret = of_address_to_resource(node, 1 + i, &res); | |
1899 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1900 | if (ret || !rdist_regs[i].redist_base) { | |
e81f54c6 | 1901 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
1902 | err = -ENODEV; |
1903 | goto out_unmap_rdist; | |
1904 | } | |
1905 | rdist_regs[i].phys_base = res.start; | |
1906 | } | |
1907 | ||
1908 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1909 | redist_stride = 0; | |
1910 | ||
f70fdb42 SK |
1911 | gic_enable_of_quirks(node, gic_quirks, &gic_data); |
1912 | ||
db57d746 TN |
1913 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, |
1914 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1915 | if (err) |
1916 | goto out_unmap_rdist; | |
1917 | ||
1918 | gic_populate_ppi_partitions(node); | |
d33a3c8c | 1919 | |
d01d3274 | 1920 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1921 | gic_of_setup_kvm_info(node); |
e3825ba1 | 1922 | return 0; |
db57d746 | 1923 | |
021f6537 | 1924 | out_unmap_rdist: |
f5c1434c MZ |
1925 | for (i = 0; i < nr_redist_regions; i++) |
1926 | if (rdist_regs[i].redist_base) | |
1927 | iounmap(rdist_regs[i].redist_base); | |
1928 | kfree(rdist_regs); | |
021f6537 MZ |
1929 | out_unmap_dist: |
1930 | iounmap(dist_base); | |
1931 | return err; | |
1932 | } | |
1933 | ||
1934 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1935 | |
1936 | #ifdef CONFIG_ACPI | |
611f039f JG |
1937 | static struct |
1938 | { | |
1939 | void __iomem *dist_base; | |
1940 | struct redist_region *redist_regs; | |
1941 | u32 nr_redist_regions; | |
1942 | bool single_redist; | |
926b5dfa | 1943 | int enabled_rdists; |
1839e576 JG |
1944 | u32 maint_irq; |
1945 | int maint_irq_mode; | |
1946 | phys_addr_t vcpu_base; | |
611f039f | 1947 | } acpi_data __initdata; |
b70fb7af TN |
1948 | |
1949 | static void __init | |
1950 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1951 | { | |
1952 | static int count = 0; | |
1953 | ||
611f039f JG |
1954 | acpi_data.redist_regs[count].phys_base = phys_base; |
1955 | acpi_data.redist_regs[count].redist_base = redist_base; | |
1956 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
1957 | count++; |
1958 | } | |
ffa7d616 TN |
1959 | |
1960 | static int __init | |
60574d1e | 1961 | gic_acpi_parse_madt_redist(union acpi_subtable_headers *header, |
ffa7d616 TN |
1962 | const unsigned long end) |
1963 | { | |
1964 | struct acpi_madt_generic_redistributor *redist = | |
1965 | (struct acpi_madt_generic_redistributor *)header; | |
1966 | void __iomem *redist_base; | |
ffa7d616 TN |
1967 | |
1968 | redist_base = ioremap(redist->base_address, redist->length); | |
1969 | if (!redist_base) { | |
1970 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1971 | return -ENOMEM; | |
1972 | } | |
1973 | ||
b70fb7af | 1974 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1975 | return 0; |
1976 | } | |
1977 | ||
b70fb7af | 1978 | static int __init |
60574d1e | 1979 | gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
1980 | const unsigned long end) |
1981 | { | |
1982 | struct acpi_madt_generic_interrupt *gicc = | |
1983 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 1984 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
1985 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
1986 | void __iomem *redist_base; | |
1987 | ||
ebe2f871 SD |
1988 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
1989 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1990 | return 0; | |
1991 | ||
b70fb7af TN |
1992 | redist_base = ioremap(gicc->gicr_base_address, size); |
1993 | if (!redist_base) | |
1994 | return -ENOMEM; | |
1995 | ||
1996 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1997 | return 0; | |
1998 | } | |
1999 | ||
2000 | static int __init gic_acpi_collect_gicr_base(void) | |
2001 | { | |
2002 | acpi_tbl_entry_handler redist_parser; | |
2003 | enum acpi_madt_type type; | |
2004 | ||
611f039f | 2005 | if (acpi_data.single_redist) { |
b70fb7af TN |
2006 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
2007 | redist_parser = gic_acpi_parse_madt_gicc; | |
2008 | } else { | |
2009 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
2010 | redist_parser = gic_acpi_parse_madt_redist; | |
2011 | } | |
2012 | ||
2013 | /* Collect redistributor base addresses in GICR entries */ | |
2014 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
2015 | return 0; | |
2016 | ||
2017 | pr_info("No valid GICR entries exist\n"); | |
2018 | return -ENODEV; | |
2019 | } | |
2020 | ||
60574d1e | 2021 | static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header, |
ffa7d616 TN |
2022 | const unsigned long end) |
2023 | { | |
2024 | /* Subtable presence means that redist exists, that's it */ | |
2025 | return 0; | |
2026 | } | |
2027 | ||
60574d1e | 2028 | static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, |
b70fb7af TN |
2029 | const unsigned long end) |
2030 | { | |
2031 | struct acpi_madt_generic_interrupt *gicc = | |
2032 | (struct acpi_madt_generic_interrupt *)header; | |
2033 | ||
2034 | /* | |
2035 | * If GICC is enabled and has valid gicr base address, then it means | |
2036 | * GICR base is presented via GICC | |
2037 | */ | |
926b5dfa MZ |
2038 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { |
2039 | acpi_data.enabled_rdists++; | |
b70fb7af | 2040 | return 0; |
926b5dfa | 2041 | } |
b70fb7af | 2042 | |
ebe2f871 SD |
2043 | /* |
2044 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
2045 | * should not treat as errors, skip the entry instead of probe fail. | |
2046 | */ | |
2047 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2048 | return 0; | |
2049 | ||
b70fb7af TN |
2050 | return -ENODEV; |
2051 | } | |
2052 | ||
2053 | static int __init gic_acpi_count_gicr_regions(void) | |
2054 | { | |
2055 | int count; | |
2056 | ||
2057 | /* | |
2058 | * Count how many redistributor regions we have. It is not allowed | |
2059 | * to mix redistributor description, GICR and GICC subtables have to be | |
2060 | * mutually exclusive. | |
2061 | */ | |
2062 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
2063 | gic_acpi_match_gicr, 0); | |
2064 | if (count > 0) { | |
611f039f | 2065 | acpi_data.single_redist = false; |
b70fb7af TN |
2066 | return count; |
2067 | } | |
2068 | ||
2069 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2070 | gic_acpi_match_gicc, 0); | |
926b5dfa | 2071 | if (count > 0) { |
611f039f | 2072 | acpi_data.single_redist = true; |
926b5dfa MZ |
2073 | count = acpi_data.enabled_rdists; |
2074 | } | |
b70fb7af TN |
2075 | |
2076 | return count; | |
2077 | } | |
2078 | ||
ffa7d616 TN |
2079 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
2080 | struct acpi_probe_entry *ape) | |
2081 | { | |
2082 | struct acpi_madt_generic_distributor *dist; | |
2083 | int count; | |
2084 | ||
2085 | dist = (struct acpi_madt_generic_distributor *)header; | |
2086 | if (dist->version != ape->driver_data) | |
2087 | return false; | |
2088 | ||
2089 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 2090 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
2091 | if (count <= 0) |
2092 | return false; | |
2093 | ||
611f039f | 2094 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
2095 | return true; |
2096 | } | |
2097 | ||
60574d1e | 2098 | static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, |
1839e576 JG |
2099 | const unsigned long end) |
2100 | { | |
2101 | struct acpi_madt_generic_interrupt *gicc = | |
2102 | (struct acpi_madt_generic_interrupt *)header; | |
2103 | int maint_irq_mode; | |
2104 | static int first_madt = true; | |
2105 | ||
2106 | /* Skip unusable CPUs */ | |
2107 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
2108 | return 0; | |
2109 | ||
2110 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
2111 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
2112 | ||
2113 | if (first_madt) { | |
2114 | first_madt = false; | |
2115 | ||
2116 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
2117 | acpi_data.maint_irq_mode = maint_irq_mode; | |
2118 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
2119 | ||
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | /* | |
2124 | * The maintenance interrupt and GICV should be the same for every CPU | |
2125 | */ | |
2126 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
2127 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
2128 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | return 0; | |
2132 | } | |
2133 | ||
2134 | static bool __init gic_acpi_collect_virt_info(void) | |
2135 | { | |
2136 | int count; | |
2137 | ||
2138 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
2139 | gic_acpi_parse_virt_madt_gicc, 0); | |
2140 | ||
2141 | return (count > 0); | |
2142 | } | |
2143 | ||
ffa7d616 | 2144 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
2145 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
2146 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
2147 | ||
2148 | static void __init gic_acpi_setup_kvm_info(void) | |
2149 | { | |
2150 | int irq; | |
2151 | ||
2152 | if (!gic_acpi_collect_virt_info()) { | |
2153 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
2154 | return; | |
2155 | } | |
2156 | ||
2157 | gic_v3_kvm_info.type = GIC_V3; | |
2158 | ||
2159 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
2160 | acpi_data.maint_irq_mode, | |
2161 | ACPI_ACTIVE_HIGH); | |
2162 | if (irq <= 0) | |
2163 | return; | |
2164 | ||
2165 | gic_v3_kvm_info.maint_irq = irq; | |
2166 | ||
2167 | if (acpi_data.vcpu_base) { | |
2168 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
2169 | ||
2170 | vcpu->flags = IORESOURCE_MEM; | |
2171 | vcpu->start = acpi_data.vcpu_base; | |
2172 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
2173 | } | |
2174 | ||
4bdf5025 | 2175 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
3c40706d | 2176 | gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; |
1839e576 JG |
2177 | gic_set_kvm_info(&gic_v3_kvm_info); |
2178 | } | |
ffa7d616 TN |
2179 | |
2180 | static int __init | |
aba3c7ed | 2181 | gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end) |
ffa7d616 TN |
2182 | { |
2183 | struct acpi_madt_generic_distributor *dist; | |
2184 | struct fwnode_handle *domain_handle; | |
611f039f | 2185 | size_t size; |
b70fb7af | 2186 | int i, err; |
ffa7d616 TN |
2187 | |
2188 | /* Get distributor base address */ | |
2189 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
2190 | acpi_data.dist_base = ioremap(dist->base_address, |
2191 | ACPI_GICV3_DIST_MEM_SIZE); | |
2192 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
2193 | pr_err("Unable to map GICD registers\n"); |
2194 | return -ENOMEM; | |
2195 | } | |
2196 | ||
611f039f | 2197 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 2198 | if (err) { |
71192a68 | 2199 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 2200 | acpi_data.dist_base); |
ffa7d616 TN |
2201 | goto out_dist_unmap; |
2202 | } | |
2203 | ||
611f039f JG |
2204 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
2205 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
2206 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
2207 | err = -ENOMEM; |
2208 | goto out_dist_unmap; | |
2209 | } | |
2210 | ||
b70fb7af TN |
2211 | err = gic_acpi_collect_gicr_base(); |
2212 | if (err) | |
ffa7d616 | 2213 | goto out_redist_unmap; |
ffa7d616 | 2214 | |
eeee0d09 | 2215 | domain_handle = irq_domain_alloc_fwnode(&dist->base_address); |
ffa7d616 TN |
2216 | if (!domain_handle) { |
2217 | err = -ENOMEM; | |
2218 | goto out_redist_unmap; | |
2219 | } | |
2220 | ||
611f039f JG |
2221 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
2222 | acpi_data.nr_redist_regions, 0, domain_handle); | |
ffa7d616 TN |
2223 | if (err) |
2224 | goto out_fwhandle_free; | |
2225 | ||
2226 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
d33a3c8c | 2227 | |
d01d3274 | 2228 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 2229 | gic_acpi_setup_kvm_info(); |
1839e576 | 2230 | |
ffa7d616 TN |
2231 | return 0; |
2232 | ||
2233 | out_fwhandle_free: | |
2234 | irq_domain_free_fwnode(domain_handle); | |
2235 | out_redist_unmap: | |
611f039f JG |
2236 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
2237 | if (acpi_data.redist_regs[i].redist_base) | |
2238 | iounmap(acpi_data.redist_regs[i].redist_base); | |
2239 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 2240 | out_dist_unmap: |
611f039f | 2241 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
2242 | return err; |
2243 | } | |
2244 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2245 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
2246 | gic_acpi_init); | |
2247 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2248 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
2249 | gic_acpi_init); | |
2250 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
2251 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
2252 | gic_acpi_init); | |
2253 | #endif |