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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/delay.h> | |
44bb7e24 | 23 | #include <linux/dma-iommu.h> |
cc2d3216 | 24 | #include <linux/interrupt.h> |
3f010cf1 | 25 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 MZ |
38 | #include <linux/irqchip/arm-gic-v3.h> |
39 | ||
cc2d3216 MZ |
40 | #include <asm/cputype.h> |
41 | #include <asm/exception.h> | |
42 | ||
67510cca RR |
43 | #include "irq-gic-common.h" |
44 | ||
94100970 RR |
45 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
46 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 48 | |
c48ed51c MZ |
49 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
50 | ||
cc2d3216 MZ |
51 | /* |
52 | * Collection structure - just an ID, and a redistributor address to | |
53 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
54 | * CPU. | |
55 | */ | |
56 | struct its_collection { | |
57 | u64 target_address; | |
58 | u16 col_id; | |
59 | }; | |
60 | ||
466b7d16 | 61 | /* |
9347359a SD |
62 | * The ITS_BASER structure - contains memory information, cached |
63 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
64 | */ |
65 | struct its_baser { | |
66 | void *base; | |
67 | u64 val; | |
68 | u32 order; | |
9347359a | 69 | u32 psz; |
466b7d16 SD |
70 | }; |
71 | ||
cc2d3216 MZ |
72 | /* |
73 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
74 | * top-level MSI domain, the command queue, the collections, and the |
75 | * list of devices writing to it. | |
cc2d3216 MZ |
76 | */ |
77 | struct its_node { | |
78 | raw_spinlock_t lock; | |
79 | struct list_head entry; | |
cc2d3216 | 80 | void __iomem *base; |
db40f0a7 | 81 | phys_addr_t phys_base; |
cc2d3216 MZ |
82 | struct its_cmd_block *cmd_base; |
83 | struct its_cmd_block *cmd_write; | |
466b7d16 | 84 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
85 | struct its_collection *collections; |
86 | struct list_head its_device_list; | |
87 | u64 flags; | |
88 | u32 ite_size; | |
466b7d16 | 89 | u32 device_ids; |
fbf8f40e | 90 | int numa_node; |
cc2d3216 MZ |
91 | }; |
92 | ||
93 | #define ITS_ITT_ALIGN SZ_256 | |
94 | ||
2eca0d6c SD |
95 | /* Convert page order to size in bytes */ |
96 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
97 | ||
591e5bec MZ |
98 | struct event_lpi_map { |
99 | unsigned long *lpi_map; | |
100 | u16 *col_map; | |
101 | irq_hw_number_t lpi_base; | |
102 | int nr_lpis; | |
103 | }; | |
104 | ||
cc2d3216 MZ |
105 | /* |
106 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
107 | * interrupt translation table, and a list of interrupts. | |
108 | */ | |
109 | struct its_device { | |
110 | struct list_head entry; | |
111 | struct its_node *its; | |
591e5bec | 112 | struct event_lpi_map event_map; |
cc2d3216 | 113 | void *itt; |
cc2d3216 MZ |
114 | u32 nr_ites; |
115 | u32 device_id; | |
116 | }; | |
117 | ||
1ac19ca6 MZ |
118 | static LIST_HEAD(its_nodes); |
119 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 120 | static struct rdists *gic_rdists; |
db40f0a7 | 121 | static struct irq_domain *its_parent; |
1ac19ca6 MZ |
122 | |
123 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) | |
124 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
125 | ||
591e5bec MZ |
126 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
127 | u32 event) | |
128 | { | |
129 | struct its_node *its = its_dev->its; | |
130 | ||
131 | return its->collections + its_dev->event_map.col_map[event]; | |
132 | } | |
133 | ||
cc2d3216 MZ |
134 | /* |
135 | * ITS command descriptors - parameters to be encoded in a command | |
136 | * block. | |
137 | */ | |
138 | struct its_cmd_desc { | |
139 | union { | |
140 | struct { | |
141 | struct its_device *dev; | |
142 | u32 event_id; | |
143 | } its_inv_cmd; | |
144 | ||
145 | struct { | |
146 | struct its_device *dev; | |
147 | u32 event_id; | |
148 | } its_int_cmd; | |
149 | ||
150 | struct { | |
151 | struct its_device *dev; | |
152 | int valid; | |
153 | } its_mapd_cmd; | |
154 | ||
155 | struct { | |
156 | struct its_collection *col; | |
157 | int valid; | |
158 | } its_mapc_cmd; | |
159 | ||
160 | struct { | |
161 | struct its_device *dev; | |
162 | u32 phys_id; | |
163 | u32 event_id; | |
6a25ad3a | 164 | } its_mapti_cmd; |
cc2d3216 MZ |
165 | |
166 | struct { | |
167 | struct its_device *dev; | |
168 | struct its_collection *col; | |
591e5bec | 169 | u32 event_id; |
cc2d3216 MZ |
170 | } its_movi_cmd; |
171 | ||
172 | struct { | |
173 | struct its_device *dev; | |
174 | u32 event_id; | |
175 | } its_discard_cmd; | |
176 | ||
177 | struct { | |
178 | struct its_collection *col; | |
179 | } its_invall_cmd; | |
180 | }; | |
181 | }; | |
182 | ||
183 | /* | |
184 | * The ITS command block, which is what the ITS actually parses. | |
185 | */ | |
186 | struct its_cmd_block { | |
187 | u64 raw_cmd[4]; | |
188 | }; | |
189 | ||
190 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
191 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
192 | ||
193 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
194 | struct its_cmd_desc *); | |
195 | ||
4d36f136 MZ |
196 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
197 | { | |
198 | u64 mask = GENMASK_ULL(h, l); | |
199 | *raw_cmd &= ~mask; | |
200 | *raw_cmd |= (val << l) & mask; | |
201 | } | |
202 | ||
cc2d3216 MZ |
203 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
204 | { | |
4d36f136 | 205 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
206 | } |
207 | ||
208 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
209 | { | |
4d36f136 | 210 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
211 | } |
212 | ||
213 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
214 | { | |
4d36f136 | 215 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
216 | } |
217 | ||
218 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
219 | { | |
4d36f136 | 220 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
221 | } |
222 | ||
223 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
224 | { | |
4d36f136 | 225 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
226 | } |
227 | ||
228 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
229 | { | |
4d36f136 | 230 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); |
cc2d3216 MZ |
231 | } |
232 | ||
233 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
234 | { | |
4d36f136 | 235 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
236 | } |
237 | ||
238 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
239 | { | |
4d36f136 | 240 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); |
cc2d3216 MZ |
241 | } |
242 | ||
243 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
244 | { | |
4d36f136 | 245 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
246 | } |
247 | ||
248 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
249 | { | |
250 | /* Let's fixup BE commands */ | |
251 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
252 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
253 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
254 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
255 | } | |
256 | ||
257 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
258 | struct its_cmd_desc *desc) | |
259 | { | |
260 | unsigned long itt_addr; | |
c8481267 | 261 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
262 | |
263 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
264 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
265 | ||
266 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
267 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
268 | its_encode_size(cmd, size - 1); | |
269 | its_encode_itt(cmd, itt_addr); | |
270 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
271 | ||
272 | its_fixup_cmd(cmd); | |
273 | ||
591e5bec | 274 | return NULL; |
cc2d3216 MZ |
275 | } |
276 | ||
277 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
278 | struct its_cmd_desc *desc) | |
279 | { | |
280 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
281 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
282 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
283 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
284 | ||
285 | its_fixup_cmd(cmd); | |
286 | ||
287 | return desc->its_mapc_cmd.col; | |
288 | } | |
289 | ||
6a25ad3a | 290 | static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd, |
cc2d3216 MZ |
291 | struct its_cmd_desc *desc) |
292 | { | |
591e5bec MZ |
293 | struct its_collection *col; |
294 | ||
6a25ad3a MZ |
295 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
296 | desc->its_mapti_cmd.event_id); | |
591e5bec | 297 | |
6a25ad3a MZ |
298 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
299 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
300 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
301 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 302 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
303 | |
304 | its_fixup_cmd(cmd); | |
305 | ||
591e5bec | 306 | return col; |
cc2d3216 MZ |
307 | } |
308 | ||
309 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
310 | struct its_cmd_desc *desc) | |
311 | { | |
591e5bec MZ |
312 | struct its_collection *col; |
313 | ||
314 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
315 | desc->its_movi_cmd.event_id); | |
316 | ||
cc2d3216 MZ |
317 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
318 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 319 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
320 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
321 | ||
322 | its_fixup_cmd(cmd); | |
323 | ||
591e5bec | 324 | return col; |
cc2d3216 MZ |
325 | } |
326 | ||
327 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
328 | struct its_cmd_desc *desc) | |
329 | { | |
591e5bec MZ |
330 | struct its_collection *col; |
331 | ||
332 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
333 | desc->its_discard_cmd.event_id); | |
334 | ||
cc2d3216 MZ |
335 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
336 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
337 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
338 | ||
339 | its_fixup_cmd(cmd); | |
340 | ||
591e5bec | 341 | return col; |
cc2d3216 MZ |
342 | } |
343 | ||
344 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
345 | struct its_cmd_desc *desc) | |
346 | { | |
591e5bec MZ |
347 | struct its_collection *col; |
348 | ||
349 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
350 | desc->its_inv_cmd.event_id); | |
351 | ||
cc2d3216 MZ |
352 | its_encode_cmd(cmd, GITS_CMD_INV); |
353 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
354 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
355 | ||
356 | its_fixup_cmd(cmd); | |
357 | ||
591e5bec | 358 | return col; |
cc2d3216 MZ |
359 | } |
360 | ||
361 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, | |
362 | struct its_cmd_desc *desc) | |
363 | { | |
364 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
365 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
366 | ||
367 | its_fixup_cmd(cmd); | |
368 | ||
369 | return NULL; | |
370 | } | |
371 | ||
372 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
373 | struct its_cmd_block *ptr) | |
374 | { | |
375 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
376 | } | |
377 | ||
378 | static int its_queue_full(struct its_node *its) | |
379 | { | |
380 | int widx; | |
381 | int ridx; | |
382 | ||
383 | widx = its->cmd_write - its->cmd_base; | |
384 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
385 | ||
386 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
387 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
388 | return 1; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
394 | { | |
395 | struct its_cmd_block *cmd; | |
396 | u32 count = 1000000; /* 1s! */ | |
397 | ||
398 | while (its_queue_full(its)) { | |
399 | count--; | |
400 | if (!count) { | |
401 | pr_err_ratelimited("ITS queue not draining\n"); | |
402 | return NULL; | |
403 | } | |
404 | cpu_relax(); | |
405 | udelay(1); | |
406 | } | |
407 | ||
408 | cmd = its->cmd_write++; | |
409 | ||
410 | /* Handle queue wrapping */ | |
411 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
412 | its->cmd_write = its->cmd_base; | |
413 | ||
34d677a9 MZ |
414 | /* Clear command */ |
415 | cmd->raw_cmd[0] = 0; | |
416 | cmd->raw_cmd[1] = 0; | |
417 | cmd->raw_cmd[2] = 0; | |
418 | cmd->raw_cmd[3] = 0; | |
419 | ||
cc2d3216 MZ |
420 | return cmd; |
421 | } | |
422 | ||
423 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
424 | { | |
425 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
426 | ||
427 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
428 | ||
429 | return its->cmd_write; | |
430 | } | |
431 | ||
432 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
433 | { | |
434 | /* | |
435 | * Make sure the commands written to memory are observable by | |
436 | * the ITS. | |
437 | */ | |
438 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 439 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
440 | else |
441 | dsb(ishst); | |
442 | } | |
443 | ||
444 | static void its_wait_for_range_completion(struct its_node *its, | |
445 | struct its_cmd_block *from, | |
446 | struct its_cmd_block *to) | |
447 | { | |
448 | u64 rd_idx, from_idx, to_idx; | |
449 | u32 count = 1000000; /* 1s! */ | |
450 | ||
451 | from_idx = its_cmd_ptr_to_offset(its, from); | |
452 | to_idx = its_cmd_ptr_to_offset(its, to); | |
453 | ||
454 | while (1) { | |
455 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
456 | if (rd_idx >= to_idx || rd_idx < from_idx) | |
457 | break; | |
458 | ||
459 | count--; | |
460 | if (!count) { | |
461 | pr_err_ratelimited("ITS queue timeout\n"); | |
462 | return; | |
463 | } | |
464 | cpu_relax(); | |
465 | udelay(1); | |
466 | } | |
467 | } | |
468 | ||
469 | static void its_send_single_command(struct its_node *its, | |
470 | its_cmd_builder_t builder, | |
471 | struct its_cmd_desc *desc) | |
472 | { | |
473 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; | |
474 | struct its_collection *sync_col; | |
3e39e8f5 | 475 | unsigned long flags; |
cc2d3216 | 476 | |
3e39e8f5 | 477 | raw_spin_lock_irqsave(&its->lock, flags); |
cc2d3216 MZ |
478 | |
479 | cmd = its_allocate_entry(its); | |
480 | if (!cmd) { /* We're soooooo screewed... */ | |
481 | pr_err_ratelimited("ITS can't allocate, dropping command\n"); | |
3e39e8f5 | 482 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
483 | return; |
484 | } | |
485 | sync_col = builder(cmd, desc); | |
486 | its_flush_cmd(its, cmd); | |
487 | ||
488 | if (sync_col) { | |
489 | sync_cmd = its_allocate_entry(its); | |
490 | if (!sync_cmd) { | |
491 | pr_err_ratelimited("ITS can't SYNC, skipping\n"); | |
492 | goto post; | |
493 | } | |
494 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
495 | its_encode_target(sync_cmd, sync_col->target_address); | |
496 | its_fixup_cmd(sync_cmd); | |
497 | its_flush_cmd(its, sync_cmd); | |
498 | } | |
499 | ||
500 | post: | |
501 | next_cmd = its_post_commands(its); | |
3e39e8f5 | 502 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
503 | |
504 | its_wait_for_range_completion(its, cmd, next_cmd); | |
505 | } | |
506 | ||
507 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
508 | { | |
509 | struct its_cmd_desc desc; | |
510 | ||
511 | desc.its_inv_cmd.dev = dev; | |
512 | desc.its_inv_cmd.event_id = event_id; | |
513 | ||
514 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
515 | } | |
516 | ||
517 | static void its_send_mapd(struct its_device *dev, int valid) | |
518 | { | |
519 | struct its_cmd_desc desc; | |
520 | ||
521 | desc.its_mapd_cmd.dev = dev; | |
522 | desc.its_mapd_cmd.valid = !!valid; | |
523 | ||
524 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
525 | } | |
526 | ||
527 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
528 | int valid) | |
529 | { | |
530 | struct its_cmd_desc desc; | |
531 | ||
532 | desc.its_mapc_cmd.col = col; | |
533 | desc.its_mapc_cmd.valid = !!valid; | |
534 | ||
535 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
536 | } | |
537 | ||
6a25ad3a | 538 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
539 | { |
540 | struct its_cmd_desc desc; | |
541 | ||
6a25ad3a MZ |
542 | desc.its_mapti_cmd.dev = dev; |
543 | desc.its_mapti_cmd.phys_id = irq_id; | |
544 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 545 | |
6a25ad3a | 546 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
547 | } |
548 | ||
549 | static void its_send_movi(struct its_device *dev, | |
550 | struct its_collection *col, u32 id) | |
551 | { | |
552 | struct its_cmd_desc desc; | |
553 | ||
554 | desc.its_movi_cmd.dev = dev; | |
555 | desc.its_movi_cmd.col = col; | |
591e5bec | 556 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
557 | |
558 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
559 | } | |
560 | ||
561 | static void its_send_discard(struct its_device *dev, u32 id) | |
562 | { | |
563 | struct its_cmd_desc desc; | |
564 | ||
565 | desc.its_discard_cmd.dev = dev; | |
566 | desc.its_discard_cmd.event_id = id; | |
567 | ||
568 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
569 | } | |
570 | ||
571 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
572 | { | |
573 | struct its_cmd_desc desc; | |
574 | ||
575 | desc.its_invall_cmd.col = col; | |
576 | ||
577 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
578 | } | |
c48ed51c MZ |
579 | |
580 | /* | |
581 | * irqchip functions - assumes MSI, mostly. | |
582 | */ | |
583 | ||
584 | static inline u32 its_get_event_id(struct irq_data *d) | |
585 | { | |
586 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 587 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
588 | } |
589 | ||
590 | static void lpi_set_config(struct irq_data *d, bool enable) | |
591 | { | |
592 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
593 | irq_hw_number_t hwirq = d->hwirq; | |
594 | u32 id = its_get_event_id(d); | |
595 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
596 | ||
597 | if (enable) | |
598 | *cfg |= LPI_PROP_ENABLED; | |
599 | else | |
600 | *cfg &= ~LPI_PROP_ENABLED; | |
601 | ||
602 | /* | |
603 | * Make the above write visible to the redistributors. | |
604 | * And yes, we're flushing exactly: One. Single. Byte. | |
605 | * Humpf... | |
606 | */ | |
607 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 608 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
609 | else |
610 | dsb(ishst); | |
611 | its_send_inv(its_dev, id); | |
612 | } | |
613 | ||
614 | static void its_mask_irq(struct irq_data *d) | |
615 | { | |
616 | lpi_set_config(d, false); | |
617 | } | |
618 | ||
619 | static void its_unmask_irq(struct irq_data *d) | |
620 | { | |
621 | lpi_set_config(d, true); | |
622 | } | |
623 | ||
c48ed51c MZ |
624 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
625 | bool force) | |
626 | { | |
fbf8f40e GK |
627 | unsigned int cpu; |
628 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
629 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
630 | struct its_collection *target_col; | |
631 | u32 id = its_get_event_id(d); | |
632 | ||
fbf8f40e GK |
633 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
634 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
635 | if (its_dev->its->numa_node >= 0) { | |
636 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
637 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
638 | return -EINVAL; | |
639 | } | |
640 | } | |
641 | ||
642 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
643 | ||
c48ed51c MZ |
644 | if (cpu >= nr_cpu_ids) |
645 | return -EINVAL; | |
646 | ||
8b8d94a7 M |
647 | /* don't set the affinity when the target cpu is same as current one */ |
648 | if (cpu != its_dev->event_map.col_map[id]) { | |
649 | target_col = &its_dev->its->collections[cpu]; | |
650 | its_send_movi(its_dev, target_col, id); | |
651 | its_dev->event_map.col_map[id] = cpu; | |
652 | } | |
c48ed51c MZ |
653 | |
654 | return IRQ_SET_MASK_OK_DONE; | |
655 | } | |
656 | ||
b48ac83d MZ |
657 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
658 | { | |
659 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
660 | struct its_node *its; | |
661 | u64 addr; | |
662 | ||
663 | its = its_dev->its; | |
664 | addr = its->phys_base + GITS_TRANSLATER; | |
665 | ||
b11283eb VM |
666 | msg->address_lo = lower_32_bits(addr); |
667 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 668 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
669 | |
670 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
671 | } |
672 | ||
c48ed51c MZ |
673 | static struct irq_chip its_irq_chip = { |
674 | .name = "ITS", | |
675 | .irq_mask = its_mask_irq, | |
676 | .irq_unmask = its_unmask_irq, | |
004fa08d | 677 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 678 | .irq_set_affinity = its_set_affinity, |
b48ac83d MZ |
679 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
680 | }; | |
681 | ||
bf9529f8 MZ |
682 | /* |
683 | * How we allocate LPIs: | |
684 | * | |
685 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
686 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
687 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
688 | * bits to the right. | |
689 | * | |
690 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
691 | */ | |
692 | #define IRQS_PER_CHUNK_SHIFT 5 | |
693 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
694 | ||
695 | static unsigned long *lpi_bitmap; | |
696 | static u32 lpi_chunks; | |
697 | static DEFINE_SPINLOCK(lpi_lock); | |
698 | ||
699 | static int its_lpi_to_chunk(int lpi) | |
700 | { | |
701 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
702 | } | |
703 | ||
704 | static int its_chunk_to_lpi(int chunk) | |
705 | { | |
706 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
707 | } | |
708 | ||
04a0e4de | 709 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
710 | { |
711 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
712 | ||
713 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
714 | GFP_KERNEL); | |
715 | if (!lpi_bitmap) { | |
716 | lpi_chunks = 0; | |
717 | return -ENOMEM; | |
718 | } | |
719 | ||
720 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
721 | return 0; | |
722 | } | |
723 | ||
724 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
725 | { | |
726 | unsigned long *bitmap = NULL; | |
727 | int chunk_id; | |
728 | int nr_chunks; | |
729 | int i; | |
730 | ||
731 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
732 | ||
733 | spin_lock(&lpi_lock); | |
734 | ||
735 | do { | |
736 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
737 | 0, nr_chunks, 0); | |
738 | if (chunk_id < lpi_chunks) | |
739 | break; | |
740 | ||
741 | nr_chunks--; | |
742 | } while (nr_chunks > 0); | |
743 | ||
744 | if (!nr_chunks) | |
745 | goto out; | |
746 | ||
747 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
748 | GFP_ATOMIC); | |
749 | if (!bitmap) | |
750 | goto out; | |
751 | ||
752 | for (i = 0; i < nr_chunks; i++) | |
753 | set_bit(chunk_id + i, lpi_bitmap); | |
754 | ||
755 | *base = its_chunk_to_lpi(chunk_id); | |
756 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
757 | ||
758 | out: | |
759 | spin_unlock(&lpi_lock); | |
760 | ||
c8415b94 MZ |
761 | if (!bitmap) |
762 | *base = *nr_ids = 0; | |
763 | ||
bf9529f8 MZ |
764 | return bitmap; |
765 | } | |
766 | ||
591e5bec | 767 | static void its_lpi_free(struct event_lpi_map *map) |
bf9529f8 | 768 | { |
591e5bec MZ |
769 | int base = map->lpi_base; |
770 | int nr_ids = map->nr_lpis; | |
bf9529f8 MZ |
771 | int lpi; |
772 | ||
773 | spin_lock(&lpi_lock); | |
774 | ||
775 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
776 | int chunk = its_lpi_to_chunk(lpi); | |
777 | BUG_ON(chunk > lpi_chunks); | |
778 | if (test_bit(chunk, lpi_bitmap)) { | |
779 | clear_bit(chunk, lpi_bitmap); | |
780 | } else { | |
781 | pr_err("Bad LPI chunk %d\n", chunk); | |
782 | } | |
783 | } | |
784 | ||
785 | spin_unlock(&lpi_lock); | |
786 | ||
591e5bec MZ |
787 | kfree(map->lpi_map); |
788 | kfree(map->col_map); | |
bf9529f8 | 789 | } |
1ac19ca6 MZ |
790 | |
791 | /* | |
792 | * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to | |
793 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
794 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
795 | */ | |
796 | #define LPI_PROPBASE_SZ SZ_64K | |
797 | #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) | |
798 | ||
799 | /* | |
800 | * This is how many bits of ID we need, including the useless ones. | |
801 | */ | |
802 | #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) | |
803 | ||
804 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
805 | ||
806 | static int __init its_alloc_lpi_tables(void) | |
807 | { | |
808 | phys_addr_t paddr; | |
809 | ||
810 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, | |
811 | get_order(LPI_PROPBASE_SZ)); | |
812 | if (!gic_rdists->prop_page) { | |
813 | pr_err("Failed to allocate PROPBASE\n"); | |
814 | return -ENOMEM; | |
815 | } | |
816 | ||
817 | paddr = page_to_phys(gic_rdists->prop_page); | |
818 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
819 | ||
820 | /* Priority 0xa0, Group-1, disabled */ | |
821 | memset(page_address(gic_rdists->prop_page), | |
822 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
823 | LPI_PROPBASE_SZ); | |
824 | ||
825 | /* Make sure the GIC will observe the written configuration */ | |
328191c0 | 826 | gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); |
1ac19ca6 MZ |
827 | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static const char *its_base_type_string[] = { | |
832 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
833 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 834 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
835 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
836 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
837 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
838 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
839 | }; | |
840 | ||
2d81d425 SD |
841 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
842 | { | |
843 | u32 idx = baser - its->tables; | |
844 | ||
0968a619 | 845 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
846 | } |
847 | ||
848 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
849 | u64 val) | |
850 | { | |
851 | u32 idx = baser - its->tables; | |
852 | ||
0968a619 | 853 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
854 | baser->val = its_read_baser(its, baser); |
855 | } | |
856 | ||
9347359a | 857 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
858 | u64 cache, u64 shr, u32 psz, u32 order, |
859 | bool indirect) | |
9347359a SD |
860 | { |
861 | u64 val = its_read_baser(its, baser); | |
862 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
863 | u64 type = GITS_BASER_TYPE(val); | |
864 | u32 alloc_pages; | |
865 | void *base; | |
866 | u64 tmp; | |
867 | ||
868 | retry_alloc_baser: | |
869 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
870 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
871 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
872 | &its->phys_base, its_base_type_string[type], | |
873 | alloc_pages, GITS_BASER_PAGES_MAX); | |
874 | alloc_pages = GITS_BASER_PAGES_MAX; | |
875 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
876 | } | |
877 | ||
878 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
879 | if (!base) | |
880 | return -ENOMEM; | |
881 | ||
882 | retry_baser: | |
883 | val = (virt_to_phys(base) | | |
884 | (type << GITS_BASER_TYPE_SHIFT) | | |
885 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
886 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
887 | cache | | |
888 | shr | | |
889 | GITS_BASER_VALID); | |
890 | ||
3faf24ea SD |
891 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
892 | ||
9347359a SD |
893 | switch (psz) { |
894 | case SZ_4K: | |
895 | val |= GITS_BASER_PAGE_SIZE_4K; | |
896 | break; | |
897 | case SZ_16K: | |
898 | val |= GITS_BASER_PAGE_SIZE_16K; | |
899 | break; | |
900 | case SZ_64K: | |
901 | val |= GITS_BASER_PAGE_SIZE_64K; | |
902 | break; | |
903 | } | |
904 | ||
905 | its_write_baser(its, baser, val); | |
906 | tmp = baser->val; | |
907 | ||
908 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
909 | /* | |
910 | * Shareability didn't stick. Just use | |
911 | * whatever the read reported, which is likely | |
912 | * to be the only thing this redistributor | |
913 | * supports. If that's zero, make it | |
914 | * non-cacheable as well. | |
915 | */ | |
916 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
917 | if (!shr) { | |
918 | cache = GITS_BASER_nC; | |
328191c0 | 919 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
920 | } |
921 | goto retry_baser; | |
922 | } | |
923 | ||
924 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
925 | /* | |
926 | * Page size didn't stick. Let's try a smaller | |
927 | * size and retry. If we reach 4K, then | |
928 | * something is horribly wrong... | |
929 | */ | |
930 | free_pages((unsigned long)base, order); | |
931 | baser->base = NULL; | |
932 | ||
933 | switch (psz) { | |
934 | case SZ_16K: | |
935 | psz = SZ_4K; | |
936 | goto retry_alloc_baser; | |
937 | case SZ_64K: | |
938 | psz = SZ_16K; | |
939 | goto retry_alloc_baser; | |
940 | } | |
941 | } | |
942 | ||
943 | if (val != tmp) { | |
b11283eb | 944 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 945 | &its->phys_base, its_base_type_string[type], |
b11283eb | 946 | val, tmp); |
9347359a SD |
947 | free_pages((unsigned long)base, order); |
948 | return -ENXIO; | |
949 | } | |
950 | ||
951 | baser->order = order; | |
952 | baser->base = base; | |
953 | baser->psz = psz; | |
3faf24ea | 954 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 955 | |
3faf24ea | 956 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 957 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
958 | its_base_type_string[type], |
959 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 960 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
961 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
3faf24ea SD |
966 | static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, |
967 | u32 psz, u32 *order) | |
4b75c459 SD |
968 | { |
969 | u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); | |
2fd632a0 | 970 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
971 | u32 ids = its->device_ids; |
972 | u32 new_order = *order; | |
3faf24ea SD |
973 | bool indirect = false; |
974 | ||
975 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
976 | if ((esz << ids) > (psz * 2)) { | |
977 | /* | |
978 | * Find out whether hw supports a single or two-level table by | |
979 | * table by reading bit at offset '62' after writing '1' to it. | |
980 | */ | |
981 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
982 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
983 | ||
984 | if (indirect) { | |
985 | /* | |
986 | * The size of the lvl2 table is equal to ITS page size | |
987 | * which is 'psz'. For computing lvl1 table size, | |
988 | * subtract ID bits that sparse lvl2 table from 'ids' | |
989 | * which is reported by ITS hardware times lvl1 table | |
990 | * entry size. | |
991 | */ | |
d524eaa2 | 992 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
993 | esz = GITS_LVL1_ENTRY_SIZE; |
994 | } | |
995 | } | |
4b75c459 SD |
996 | |
997 | /* | |
998 | * Allocate as many entries as required to fit the | |
999 | * range of device IDs that the ITS can grok... The ID | |
1000 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1001 | * massive waste of memory if two-level device table |
1002 | * feature is not supported by hardware. | |
4b75c459 SD |
1003 | */ |
1004 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1005 | if (new_order >= MAX_ORDER) { | |
1006 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1007 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4b75c459 SD |
1008 | pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", |
1009 | &its->phys_base, its->device_ids, ids); | |
1010 | } | |
1011 | ||
1012 | *order = new_order; | |
3faf24ea SD |
1013 | |
1014 | return indirect; | |
4b75c459 SD |
1015 | } |
1016 | ||
1ac19ca6 MZ |
1017 | static void its_free_tables(struct its_node *its) |
1018 | { | |
1019 | int i; | |
1020 | ||
1021 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1022 | if (its->tables[i].base) { |
1023 | free_pages((unsigned long)its->tables[i].base, | |
1024 | its->tables[i].order); | |
1025 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1026 | } |
1027 | } | |
1028 | } | |
1029 | ||
0e0b0f69 | 1030 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1031 | { |
589ce5f4 | 1032 | u64 typer = gic_read_typer(its->base + GITS_TYPER); |
9347359a | 1033 | u32 ids = GITS_TYPER_DEVBITS(typer); |
1ac19ca6 | 1034 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1035 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1036 | u32 psz = SZ_64K; |
1037 | int err, i; | |
94100970 RR |
1038 | |
1039 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1040 | /* | |
9347359a SD |
1041 | * erratum 22375: only alloc 8MB table size |
1042 | * erratum 24313: ignore memory access type | |
1043 | */ | |
1044 | cache = GITS_BASER_nCnB; | |
1045 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1046 | } |
1ac19ca6 | 1047 | |
466b7d16 SD |
1048 | its->device_ids = ids; |
1049 | ||
1ac19ca6 | 1050 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1051 | struct its_baser *baser = its->tables + i; |
1052 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1053 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1054 | u32 order = get_order(psz); |
3faf24ea | 1055 | bool indirect = false; |
1ac19ca6 MZ |
1056 | |
1057 | if (type == GITS_BASER_TYPE_NONE) | |
1058 | continue; | |
1059 | ||
4b75c459 | 1060 | if (type == GITS_BASER_TYPE_DEVICE) |
3faf24ea | 1061 | indirect = its_parse_baser_device(its, baser, psz, &order); |
f54b97ed | 1062 | |
3faf24ea | 1063 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1064 | if (err < 0) { |
1065 | its_free_tables(its); | |
1066 | return err; | |
1ac19ca6 MZ |
1067 | } |
1068 | ||
9347359a SD |
1069 | /* Update settings which will be used for next BASERn */ |
1070 | psz = baser->psz; | |
1071 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1072 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1073 | } |
1074 | ||
1075 | return 0; | |
1ac19ca6 MZ |
1076 | } |
1077 | ||
1078 | static int its_alloc_collections(struct its_node *its) | |
1079 | { | |
1080 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1081 | GFP_KERNEL); | |
1082 | if (!its->collections) | |
1083 | return -ENOMEM; | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static void its_cpu_init_lpis(void) | |
1089 | { | |
1090 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1091 | struct page *pend_page; | |
1092 | u64 val, tmp; | |
1093 | ||
1094 | /* If we didn't allocate the pending table yet, do it now */ | |
1095 | pend_page = gic_data_rdist()->pend_page; | |
1096 | if (!pend_page) { | |
1097 | phys_addr_t paddr; | |
1098 | /* | |
1099 | * The pending pages have to be at least 64kB aligned, | |
1100 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1101 | */ | |
1102 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
1103 | get_order(max(LPI_PENDBASE_SZ, SZ_64K))); | |
1104 | if (!pend_page) { | |
1105 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1106 | smp_processor_id()); | |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | /* Make sure the GIC will observe the zero-ed page */ | |
328191c0 | 1111 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); |
1ac19ca6 MZ |
1112 | |
1113 | paddr = page_to_phys(pend_page); | |
1114 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1115 | smp_processor_id(), &paddr); | |
1116 | gic_data_rdist()->pend_page = pend_page; | |
1117 | } | |
1118 | ||
1119 | /* Disable LPIs */ | |
1120 | val = readl_relaxed(rbase + GICR_CTLR); | |
1121 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1122 | writel_relaxed(val, rbase + GICR_CTLR); | |
1123 | ||
1124 | /* | |
1125 | * Make sure any change to the table is observable by the GIC. | |
1126 | */ | |
1127 | dsb(sy); | |
1128 | ||
1129 | /* set PROPBASE */ | |
1130 | val = (page_to_phys(gic_rdists->prop_page) | | |
1131 | GICR_PROPBASER_InnerShareable | | |
2fd632a0 | 1132 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1133 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1134 | ||
0968a619 VM |
1135 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1136 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1137 | |
1138 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1139 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1140 | /* | |
1141 | * The HW reports non-shareable, we must | |
1142 | * remove the cacheability attributes as | |
1143 | * well. | |
1144 | */ | |
1145 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1146 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1147 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1148 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1149 | } |
1ac19ca6 MZ |
1150 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1151 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1152 | } | |
1153 | ||
1154 | /* set PENDBASE */ | |
1155 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1156 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 1157 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1158 | |
0968a619 VM |
1159 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1160 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1161 | |
1162 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1163 | /* | |
1164 | * The HW reports non-shareable, we must remove the | |
1165 | * cacheability attributes as well. | |
1166 | */ | |
1167 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1168 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1169 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1170 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1171 | } |
1ac19ca6 MZ |
1172 | |
1173 | /* Enable LPIs */ | |
1174 | val = readl_relaxed(rbase + GICR_CTLR); | |
1175 | val |= GICR_CTLR_ENABLE_LPIS; | |
1176 | writel_relaxed(val, rbase + GICR_CTLR); | |
1177 | ||
1178 | /* Make sure the GIC has seen the above */ | |
1179 | dsb(sy); | |
1180 | } | |
1181 | ||
1182 | static void its_cpu_init_collection(void) | |
1183 | { | |
1184 | struct its_node *its; | |
1185 | int cpu; | |
1186 | ||
1187 | spin_lock(&its_lock); | |
1188 | cpu = smp_processor_id(); | |
1189 | ||
1190 | list_for_each_entry(its, &its_nodes, entry) { | |
1191 | u64 target; | |
1192 | ||
fbf8f40e GK |
1193 | /* avoid cross node collections and its mapping */ |
1194 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1195 | struct device_node *cpu_node; | |
1196 | ||
1197 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1198 | if (its->numa_node != NUMA_NO_NODE && | |
1199 | its->numa_node != of_node_to_nid(cpu_node)) | |
1200 | continue; | |
1201 | } | |
1202 | ||
1ac19ca6 MZ |
1203 | /* |
1204 | * We now have to bind each collection to its target | |
1205 | * redistributor. | |
1206 | */ | |
589ce5f4 | 1207 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1208 | /* |
1209 | * This ITS wants the physical address of the | |
1210 | * redistributor. | |
1211 | */ | |
1212 | target = gic_data_rdist()->phys_base; | |
1213 | } else { | |
1214 | /* | |
1215 | * This ITS wants a linear CPU number. | |
1216 | */ | |
589ce5f4 | 1217 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1218 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1219 | } |
1220 | ||
1221 | /* Perform collection mapping */ | |
1222 | its->collections[cpu].target_address = target; | |
1223 | its->collections[cpu].col_id = cpu; | |
1224 | ||
1225 | its_send_mapc(its, &its->collections[cpu], 1); | |
1226 | its_send_invall(its, &its->collections[cpu]); | |
1227 | } | |
1228 | ||
1229 | spin_unlock(&its_lock); | |
1230 | } | |
84a6a2e7 MZ |
1231 | |
1232 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1233 | { | |
1234 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1235 | unsigned long flags; |
84a6a2e7 | 1236 | |
3e39e8f5 | 1237 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1238 | |
1239 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1240 | if (tmp->device_id == dev_id) { | |
1241 | its_dev = tmp; | |
1242 | break; | |
1243 | } | |
1244 | } | |
1245 | ||
3e39e8f5 | 1246 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1247 | |
1248 | return its_dev; | |
1249 | } | |
1250 | ||
466b7d16 SD |
1251 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1252 | { | |
1253 | int i; | |
1254 | ||
1255 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1256 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1257 | return &its->tables[i]; | |
1258 | } | |
1259 | ||
1260 | return NULL; | |
1261 | } | |
1262 | ||
3faf24ea SD |
1263 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1264 | { | |
1265 | struct its_baser *baser; | |
1266 | struct page *page; | |
1267 | u32 esz, idx; | |
1268 | __le64 *table; | |
1269 | ||
1270 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1271 | ||
1272 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1273 | if (!baser) | |
1274 | return (ilog2(dev_id) < its->device_ids); | |
1275 | ||
1276 | /* Don't allow device id that exceeds single, flat table limit */ | |
1277 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1278 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
1279 | return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); | |
1280 | ||
1281 | /* Compute 1st level table index & check if that exceeds table limit */ | |
1282 | idx = dev_id >> ilog2(baser->psz / esz); | |
1283 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) | |
1284 | return false; | |
1285 | ||
1286 | table = baser->base; | |
1287 | ||
1288 | /* Allocate memory for 2nd level table */ | |
1289 | if (!table[idx]) { | |
1290 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1291 | if (!page) | |
1292 | return false; | |
1293 | ||
1294 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1295 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1296 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1297 | |
1298 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1299 | ||
1300 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1301 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1302 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1303 | |
1304 | /* Ensure updated table contents are visible to ITS hardware */ | |
1305 | dsb(sy); | |
1306 | } | |
1307 | ||
1308 | return true; | |
1309 | } | |
1310 | ||
84a6a2e7 MZ |
1311 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1312 | int nvecs) | |
1313 | { | |
1314 | struct its_device *dev; | |
1315 | unsigned long *lpi_map; | |
3e39e8f5 | 1316 | unsigned long flags; |
591e5bec | 1317 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1318 | void *itt; |
1319 | int lpi_base; | |
1320 | int nr_lpis; | |
c8481267 | 1321 | int nr_ites; |
84a6a2e7 MZ |
1322 | int sz; |
1323 | ||
3faf24ea | 1324 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1325 | return NULL; |
1326 | ||
84a6a2e7 | 1327 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1328 | /* |
1329 | * At least one bit of EventID is being used, hence a minimum | |
1330 | * of two entries. No, the architecture doesn't let you | |
1331 | * express an ITT with a single entry. | |
1332 | */ | |
96555c47 | 1333 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1334 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1335 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1336 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1337 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1338 | if (lpi_map) |
1339 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1340 | |
591e5bec | 1341 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1342 | kfree(dev); |
1343 | kfree(itt); | |
1344 | kfree(lpi_map); | |
591e5bec | 1345 | kfree(col_map); |
84a6a2e7 MZ |
1346 | return NULL; |
1347 | } | |
1348 | ||
328191c0 | 1349 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 1350 | |
84a6a2e7 MZ |
1351 | dev->its = its; |
1352 | dev->itt = itt; | |
c8481267 | 1353 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1354 | dev->event_map.lpi_map = lpi_map; |
1355 | dev->event_map.col_map = col_map; | |
1356 | dev->event_map.lpi_base = lpi_base; | |
1357 | dev->event_map.nr_lpis = nr_lpis; | |
84a6a2e7 MZ |
1358 | dev->device_id = dev_id; |
1359 | INIT_LIST_HEAD(&dev->entry); | |
1360 | ||
3e39e8f5 | 1361 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1362 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1363 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1364 | |
84a6a2e7 MZ |
1365 | /* Map device to its ITT */ |
1366 | its_send_mapd(dev, 1); | |
1367 | ||
1368 | return dev; | |
1369 | } | |
1370 | ||
1371 | static void its_free_device(struct its_device *its_dev) | |
1372 | { | |
3e39e8f5 MZ |
1373 | unsigned long flags; |
1374 | ||
1375 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1376 | list_del(&its_dev->entry); |
3e39e8f5 | 1377 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1378 | kfree(its_dev->itt); |
1379 | kfree(its_dev); | |
1380 | } | |
b48ac83d MZ |
1381 | |
1382 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1383 | { | |
1384 | int idx; | |
1385 | ||
591e5bec MZ |
1386 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1387 | dev->event_map.nr_lpis); | |
1388 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1389 | return -ENOSPC; |
1390 | ||
591e5bec MZ |
1391 | *hwirq = dev->event_map.lpi_base + idx; |
1392 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1393 | |
b48ac83d MZ |
1394 | return 0; |
1395 | } | |
1396 | ||
54456db9 MZ |
1397 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1398 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1399 | { |
b48ac83d | 1400 | struct its_node *its; |
b48ac83d | 1401 | struct its_device *its_dev; |
54456db9 MZ |
1402 | struct msi_domain_info *msi_info; |
1403 | u32 dev_id; | |
1404 | ||
1405 | /* | |
1406 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1407 | * been passed via the scratchpad. This limits this domain's | |
1408 | * usefulness to upper layers that definitely know that they | |
1409 | * are built on top of the ITS. | |
1410 | */ | |
1411 | dev_id = info->scratchpad[0].ul; | |
1412 | ||
1413 | msi_info = msi_get_domain_info(domain); | |
1414 | its = msi_info->data; | |
e8137f4f | 1415 | |
f130420e | 1416 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1417 | if (its_dev) { |
1418 | /* | |
1419 | * We already have seen this ID, probably through | |
1420 | * another alias (PCI bridge of some sort). No need to | |
1421 | * create the device. | |
1422 | */ | |
f130420e | 1423 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1424 | goto out; |
1425 | } | |
b48ac83d | 1426 | |
f130420e | 1427 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1428 | if (!its_dev) |
1429 | return -ENOMEM; | |
1430 | ||
f130420e | 1431 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1432 | out: |
b48ac83d | 1433 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1434 | return 0; |
1435 | } | |
1436 | ||
54456db9 MZ |
1437 | static struct msi_domain_ops its_msi_domain_ops = { |
1438 | .msi_prepare = its_msi_prepare, | |
1439 | }; | |
1440 | ||
b48ac83d MZ |
1441 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1442 | unsigned int virq, | |
1443 | irq_hw_number_t hwirq) | |
1444 | { | |
f833f57f MZ |
1445 | struct irq_fwspec fwspec; |
1446 | ||
1447 | if (irq_domain_get_of_node(domain->parent)) { | |
1448 | fwspec.fwnode = domain->parent->fwnode; | |
1449 | fwspec.param_count = 3; | |
1450 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1451 | fwspec.param[1] = hwirq; | |
1452 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
1453 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
1454 | fwspec.fwnode = domain->parent->fwnode; | |
1455 | fwspec.param_count = 2; | |
1456 | fwspec.param[0] = hwirq; | |
1457 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
1458 | } else { |
1459 | return -EINVAL; | |
1460 | } | |
b48ac83d | 1461 | |
f833f57f | 1462 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1463 | } |
1464 | ||
1465 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1466 | unsigned int nr_irqs, void *args) | |
1467 | { | |
1468 | msi_alloc_info_t *info = args; | |
1469 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1470 | irq_hw_number_t hwirq; | |
1471 | int err; | |
1472 | int i; | |
1473 | ||
1474 | for (i = 0; i < nr_irqs; i++) { | |
1475 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1476 | if (err) | |
1477 | return err; | |
1478 | ||
1479 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1480 | if (err) | |
1481 | return err; | |
1482 | ||
1483 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1484 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1485 | pr_debug("ID:%d pID:%d vID:%d\n", |
1486 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1487 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1488 | } |
1489 | ||
1490 | return 0; | |
1491 | } | |
1492 | ||
aca268df MZ |
1493 | static void its_irq_domain_activate(struct irq_domain *domain, |
1494 | struct irq_data *d) | |
1495 | { | |
1496 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1497 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1498 | const struct cpumask *cpu_mask = cpu_online_mask; |
1499 | ||
1500 | /* get the cpu_mask of local node */ | |
1501 | if (its_dev->its->numa_node >= 0) | |
1502 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1503 | |
591e5bec | 1504 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1505 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1506 | |
aca268df | 1507 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 1508 | its_send_mapti(its_dev, d->hwirq, event); |
aca268df MZ |
1509 | } |
1510 | ||
1511 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1512 | struct irq_data *d) | |
1513 | { | |
1514 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1515 | u32 event = its_get_event_id(d); | |
1516 | ||
1517 | /* Stop the delivery of interrupts */ | |
1518 | its_send_discard(its_dev, event); | |
1519 | } | |
1520 | ||
b48ac83d MZ |
1521 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1522 | unsigned int nr_irqs) | |
1523 | { | |
1524 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1525 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1526 | int i; | |
1527 | ||
1528 | for (i = 0; i < nr_irqs; i++) { | |
1529 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1530 | virq + i); | |
aca268df | 1531 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
1532 | |
1533 | /* Mark interrupt index as unused */ | |
591e5bec | 1534 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
1535 | |
1536 | /* Nuke the entry in the domain */ | |
2da39949 | 1537 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
1538 | } |
1539 | ||
1540 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
1541 | if (bitmap_empty(its_dev->event_map.lpi_map, |
1542 | its_dev->event_map.nr_lpis)) { | |
1543 | its_lpi_free(&its_dev->event_map); | |
b48ac83d MZ |
1544 | |
1545 | /* Unmap device/itt */ | |
1546 | its_send_mapd(its_dev, 0); | |
1547 | its_free_device(its_dev); | |
1548 | } | |
1549 | ||
1550 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1551 | } | |
1552 | ||
1553 | static const struct irq_domain_ops its_domain_ops = { | |
1554 | .alloc = its_irq_domain_alloc, | |
1555 | .free = its_irq_domain_free, | |
aca268df MZ |
1556 | .activate = its_irq_domain_activate, |
1557 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 1558 | }; |
4c21f3c2 | 1559 | |
4559fbb3 YW |
1560 | static int its_force_quiescent(void __iomem *base) |
1561 | { | |
1562 | u32 count = 1000000; /* 1s */ | |
1563 | u32 val; | |
1564 | ||
1565 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
1566 | /* |
1567 | * GIC architecture specification requires the ITS to be both | |
1568 | * disabled and quiescent for writes to GITS_BASER<n> or | |
1569 | * GITS_CBASER to not have UNPREDICTABLE results. | |
1570 | */ | |
1571 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
1572 | return 0; |
1573 | ||
1574 | /* Disable the generation of all interrupts to this ITS */ | |
1575 | val &= ~GITS_CTLR_ENABLE; | |
1576 | writel_relaxed(val, base + GITS_CTLR); | |
1577 | ||
1578 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
1579 | while (1) { | |
1580 | val = readl_relaxed(base + GITS_CTLR); | |
1581 | if (val & GITS_CTLR_QUIESCENT) | |
1582 | return 0; | |
1583 | ||
1584 | count--; | |
1585 | if (!count) | |
1586 | return -EBUSY; | |
1587 | ||
1588 | cpu_relax(); | |
1589 | udelay(1); | |
1590 | } | |
1591 | } | |
1592 | ||
94100970 RR |
1593 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
1594 | { | |
1595 | struct its_node *its = data; | |
1596 | ||
1597 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
1598 | } | |
1599 | ||
fbf8f40e GK |
1600 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
1601 | { | |
1602 | struct its_node *its = data; | |
1603 | ||
1604 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
1605 | } | |
1606 | ||
90922a2d SD |
1607 | static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
1608 | { | |
1609 | struct its_node *its = data; | |
1610 | ||
1611 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
1612 | its->ite_size = 16; | |
1613 | } | |
1614 | ||
67510cca | 1615 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
1616 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
1617 | { | |
1618 | .desc = "ITS: Cavium errata 22375, 24313", | |
1619 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1620 | .mask = 0xffff0fff, | |
1621 | .init = its_enable_quirk_cavium_22375, | |
1622 | }, | |
fbf8f40e GK |
1623 | #endif |
1624 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
1625 | { | |
1626 | .desc = "ITS: Cavium erratum 23144", | |
1627 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1628 | .mask = 0xffff0fff, | |
1629 | .init = its_enable_quirk_cavium_23144, | |
1630 | }, | |
90922a2d SD |
1631 | #endif |
1632 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
1633 | { | |
1634 | .desc = "ITS: QDF2400 erratum 0065", | |
1635 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
1636 | .mask = 0xffffffff, | |
1637 | .init = its_enable_quirk_qdf2400_e0065, | |
1638 | }, | |
94100970 | 1639 | #endif |
67510cca RR |
1640 | { |
1641 | } | |
1642 | }; | |
1643 | ||
1644 | static void its_enable_quirks(struct its_node *its) | |
1645 | { | |
1646 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
1647 | ||
1648 | gic_enable_quirks(iidr, its_quirks, its); | |
1649 | } | |
1650 | ||
db40f0a7 | 1651 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
1652 | { |
1653 | struct irq_domain *inner_domain; | |
1654 | struct msi_domain_info *info; | |
1655 | ||
1656 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
1657 | if (!info) | |
1658 | return -ENOMEM; | |
1659 | ||
db40f0a7 | 1660 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
1661 | if (!inner_domain) { |
1662 | kfree(info); | |
1663 | return -ENOMEM; | |
1664 | } | |
1665 | ||
db40f0a7 | 1666 | inner_domain->parent = its_parent; |
d14ae5e6 | 1667 | inner_domain->bus_token = DOMAIN_BUS_NEXUS; |
59768527 | 1668 | inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; |
d14ae5e6 TN |
1669 | info->ops = &its_msi_domain_ops; |
1670 | info->data = its; | |
1671 | inner_domain->host_data = info; | |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
db40f0a7 TN |
1676 | static int __init its_probe_one(struct resource *res, |
1677 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 1678 | { |
4c21f3c2 MZ |
1679 | struct its_node *its; |
1680 | void __iomem *its_base; | |
1681 | u32 val; | |
1682 | u64 baser, tmp; | |
1683 | int err; | |
1684 | ||
db40f0a7 | 1685 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 1686 | if (!its_base) { |
db40f0a7 | 1687 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
1688 | return -ENOMEM; |
1689 | } | |
1690 | ||
1691 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1692 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 1693 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
1694 | err = -ENODEV; |
1695 | goto out_unmap; | |
1696 | } | |
1697 | ||
4559fbb3 YW |
1698 | err = its_force_quiescent(its_base); |
1699 | if (err) { | |
db40f0a7 | 1700 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
1701 | goto out_unmap; |
1702 | } | |
1703 | ||
db40f0a7 | 1704 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
1705 | |
1706 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1707 | if (!its) { | |
1708 | err = -ENOMEM; | |
1709 | goto out_unmap; | |
1710 | } | |
1711 | ||
1712 | raw_spin_lock_init(&its->lock); | |
1713 | INIT_LIST_HEAD(&its->entry); | |
1714 | INIT_LIST_HEAD(&its->its_device_list); | |
1715 | its->base = its_base; | |
db40f0a7 | 1716 | its->phys_base = res->start; |
589ce5f4 | 1717 | its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; |
db40f0a7 | 1718 | its->numa_node = numa_node; |
4c21f3c2 | 1719 | |
5bc13c2c RR |
1720 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
1721 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
1722 | if (!its->cmd_base) { |
1723 | err = -ENOMEM; | |
1724 | goto out_free_its; | |
1725 | } | |
1726 | its->cmd_write = its->cmd_base; | |
1727 | ||
67510cca RR |
1728 | its_enable_quirks(its); |
1729 | ||
0e0b0f69 | 1730 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
1731 | if (err) |
1732 | goto out_free_cmd; | |
1733 | ||
1734 | err = its_alloc_collections(its); | |
1735 | if (err) | |
1736 | goto out_free_tables; | |
1737 | ||
1738 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 1739 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
1740 | GITS_CBASER_InnerShareable | |
1741 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1742 | GITS_CBASER_VALID); | |
1743 | ||
0968a619 VM |
1744 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
1745 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 1746 | |
4ad3e363 | 1747 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
1748 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
1749 | /* | |
1750 | * The HW reports non-shareable, we must | |
1751 | * remove the cacheability attributes as | |
1752 | * well. | |
1753 | */ | |
1754 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
1755 | GITS_CBASER_CACHEABILITY_MASK); | |
1756 | baser |= GITS_CBASER_nC; | |
0968a619 | 1757 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 1758 | } |
4c21f3c2 MZ |
1759 | pr_info("ITS: using cache flushing for cmd queue\n"); |
1760 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1761 | } | |
1762 | ||
0968a619 | 1763 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
241a386c MZ |
1764 | writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); |
1765 | ||
db40f0a7 | 1766 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
1767 | if (err) |
1768 | goto out_free_tables; | |
4c21f3c2 MZ |
1769 | |
1770 | spin_lock(&its_lock); | |
1771 | list_add(&its->entry, &its_nodes); | |
1772 | spin_unlock(&its_lock); | |
1773 | ||
1774 | return 0; | |
1775 | ||
4c21f3c2 MZ |
1776 | out_free_tables: |
1777 | its_free_tables(its); | |
1778 | out_free_cmd: | |
5bc13c2c | 1779 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
1780 | out_free_its: |
1781 | kfree(its); | |
1782 | out_unmap: | |
1783 | iounmap(its_base); | |
db40f0a7 | 1784 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
1785 | return err; |
1786 | } | |
1787 | ||
1788 | static bool gic_rdists_supports_plpis(void) | |
1789 | { | |
589ce5f4 | 1790 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
1791 | } |
1792 | ||
1793 | int its_cpu_init(void) | |
1794 | { | |
4c21f3c2 | 1795 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
1796 | if (!gic_rdists_supports_plpis()) { |
1797 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1798 | return -ENXIO; | |
1799 | } | |
4c21f3c2 MZ |
1800 | its_cpu_init_lpis(); |
1801 | its_cpu_init_collection(); | |
1802 | } | |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
1807 | static struct of_device_id its_device_id[] = { | |
1808 | { .compatible = "arm,gic-v3-its", }, | |
1809 | {}, | |
1810 | }; | |
1811 | ||
db40f0a7 | 1812 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
1813 | { |
1814 | struct device_node *np; | |
db40f0a7 | 1815 | struct resource res; |
4c21f3c2 MZ |
1816 | |
1817 | for (np = of_find_matching_node(node, its_device_id); np; | |
1818 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 TN |
1819 | if (!of_property_read_bool(np, "msi-controller")) { |
1820 | pr_warn("%s: no msi-controller property, ITS ignored\n", | |
1821 | np->full_name); | |
1822 | continue; | |
1823 | } | |
1824 | ||
db40f0a7 TN |
1825 | if (of_address_to_resource(np, 0, &res)) { |
1826 | pr_warn("%s: no regs?\n", np->full_name); | |
1827 | continue; | |
1828 | } | |
1829 | ||
1830 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 1831 | } |
db40f0a7 TN |
1832 | return 0; |
1833 | } | |
1834 | ||
3f010cf1 TN |
1835 | #ifdef CONFIG_ACPI |
1836 | ||
1837 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
1838 | ||
1839 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, | |
1840 | const unsigned long end) | |
1841 | { | |
1842 | struct acpi_madt_generic_translator *its_entry; | |
1843 | struct fwnode_handle *dom_handle; | |
1844 | struct resource res; | |
1845 | int err; | |
1846 | ||
1847 | its_entry = (struct acpi_madt_generic_translator *)header; | |
1848 | memset(&res, 0, sizeof(res)); | |
1849 | res.start = its_entry->base_address; | |
1850 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
1851 | res.flags = IORESOURCE_MEM; | |
1852 | ||
1853 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
1854 | if (!dom_handle) { | |
1855 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
1856 | &res.start); | |
1857 | return -ENOMEM; | |
1858 | } | |
1859 | ||
1860 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
1861 | if (err) { | |
1862 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
1863 | &res.start, its_entry->translation_id); | |
1864 | goto dom_err; | |
1865 | } | |
1866 | ||
1867 | err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); | |
1868 | if (!err) | |
1869 | return 0; | |
1870 | ||
1871 | iort_deregister_domain_token(its_entry->translation_id); | |
1872 | dom_err: | |
1873 | irq_domain_free_fwnode(dom_handle); | |
1874 | return err; | |
1875 | } | |
1876 | ||
1877 | static void __init its_acpi_probe(void) | |
1878 | { | |
1879 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, | |
1880 | gic_acpi_parse_madt_its, 0); | |
1881 | } | |
1882 | #else | |
1883 | static void __init its_acpi_probe(void) { } | |
1884 | #endif | |
1885 | ||
db40f0a7 TN |
1886 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
1887 | struct irq_domain *parent_domain) | |
1888 | { | |
1889 | struct device_node *of_node; | |
1890 | ||
1891 | its_parent = parent_domain; | |
1892 | of_node = to_of_node(handle); | |
1893 | if (of_node) | |
1894 | its_of_probe(of_node); | |
1895 | else | |
3f010cf1 | 1896 | its_acpi_probe(); |
4c21f3c2 MZ |
1897 | |
1898 | if (list_empty(&its_nodes)) { | |
1899 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
1900 | return -ENXIO; | |
1901 | } | |
1902 | ||
1903 | gic_rdists = rdists; | |
4c21f3c2 MZ |
1904 | its_alloc_lpi_tables(); |
1905 | its_lpi_init(rdists->id_bits); | |
1906 | ||
1907 | return 0; | |
1908 | } |