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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/bitmap.h> | |
19 | #include <linux/cpu.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/log2.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/msi.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/percpu.h> | |
31 | #include <linux/slab.h> | |
32 | ||
33 | #include <linux/irqchip/arm-gic-v3.h> | |
34 | ||
35 | #include <asm/cacheflush.h> | |
36 | #include <asm/cputype.h> | |
37 | #include <asm/exception.h> | |
38 | ||
39 | #include "irqchip.h" | |
40 | ||
41 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0) | |
42 | ||
c48ed51c MZ |
43 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
44 | ||
cc2d3216 MZ |
45 | /* |
46 | * Collection structure - just an ID, and a redistributor address to | |
47 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
48 | * CPU. | |
49 | */ | |
50 | struct its_collection { | |
51 | u64 target_address; | |
52 | u16 col_id; | |
53 | }; | |
54 | ||
55 | /* | |
56 | * The ITS structure - contains most of the infrastructure, with the | |
57 | * msi_controller, the command queue, the collections, and the list of | |
58 | * devices writing to it. | |
59 | */ | |
60 | struct its_node { | |
61 | raw_spinlock_t lock; | |
62 | struct list_head entry; | |
63 | struct msi_controller msi_chip; | |
64 | struct irq_domain *domain; | |
65 | void __iomem *base; | |
66 | unsigned long phys_base; | |
67 | struct its_cmd_block *cmd_base; | |
68 | struct its_cmd_block *cmd_write; | |
69 | void *tables[GITS_BASER_NR_REGS]; | |
70 | struct its_collection *collections; | |
71 | struct list_head its_device_list; | |
72 | u64 flags; | |
73 | u32 ite_size; | |
74 | }; | |
75 | ||
76 | #define ITS_ITT_ALIGN SZ_256 | |
77 | ||
78 | /* | |
79 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
80 | * interrupt translation table, and a list of interrupts. | |
81 | */ | |
82 | struct its_device { | |
83 | struct list_head entry; | |
84 | struct its_node *its; | |
85 | struct its_collection *collection; | |
86 | void *itt; | |
87 | unsigned long *lpi_map; | |
88 | irq_hw_number_t lpi_base; | |
89 | int nr_lpis; | |
90 | u32 nr_ites; | |
91 | u32 device_id; | |
92 | }; | |
93 | ||
1ac19ca6 MZ |
94 | static LIST_HEAD(its_nodes); |
95 | static DEFINE_SPINLOCK(its_lock); | |
96 | static struct device_node *gic_root_node; | |
97 | static struct rdists *gic_rdists; | |
98 | ||
99 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) | |
100 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
101 | ||
cc2d3216 MZ |
102 | /* |
103 | * ITS command descriptors - parameters to be encoded in a command | |
104 | * block. | |
105 | */ | |
106 | struct its_cmd_desc { | |
107 | union { | |
108 | struct { | |
109 | struct its_device *dev; | |
110 | u32 event_id; | |
111 | } its_inv_cmd; | |
112 | ||
113 | struct { | |
114 | struct its_device *dev; | |
115 | u32 event_id; | |
116 | } its_int_cmd; | |
117 | ||
118 | struct { | |
119 | struct its_device *dev; | |
120 | int valid; | |
121 | } its_mapd_cmd; | |
122 | ||
123 | struct { | |
124 | struct its_collection *col; | |
125 | int valid; | |
126 | } its_mapc_cmd; | |
127 | ||
128 | struct { | |
129 | struct its_device *dev; | |
130 | u32 phys_id; | |
131 | u32 event_id; | |
132 | } its_mapvi_cmd; | |
133 | ||
134 | struct { | |
135 | struct its_device *dev; | |
136 | struct its_collection *col; | |
137 | u32 id; | |
138 | } its_movi_cmd; | |
139 | ||
140 | struct { | |
141 | struct its_device *dev; | |
142 | u32 event_id; | |
143 | } its_discard_cmd; | |
144 | ||
145 | struct { | |
146 | struct its_collection *col; | |
147 | } its_invall_cmd; | |
148 | }; | |
149 | }; | |
150 | ||
151 | /* | |
152 | * The ITS command block, which is what the ITS actually parses. | |
153 | */ | |
154 | struct its_cmd_block { | |
155 | u64 raw_cmd[4]; | |
156 | }; | |
157 | ||
158 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
159 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
160 | ||
161 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
162 | struct its_cmd_desc *); | |
163 | ||
164 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) | |
165 | { | |
166 | cmd->raw_cmd[0] &= ~0xffUL; | |
167 | cmd->raw_cmd[0] |= cmd_nr; | |
168 | } | |
169 | ||
170 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
171 | { | |
172 | cmd->raw_cmd[0] &= ~(0xffffUL << 32); | |
173 | cmd->raw_cmd[0] |= ((u64)devid) << 32; | |
174 | } | |
175 | ||
176 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
177 | { | |
178 | cmd->raw_cmd[1] &= ~0xffffffffUL; | |
179 | cmd->raw_cmd[1] |= id; | |
180 | } | |
181 | ||
182 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
183 | { | |
184 | cmd->raw_cmd[1] &= 0xffffffffUL; | |
185 | cmd->raw_cmd[1] |= ((u64)phys_id) << 32; | |
186 | } | |
187 | ||
188 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
189 | { | |
190 | cmd->raw_cmd[1] &= ~0x1fUL; | |
191 | cmd->raw_cmd[1] |= size & 0x1f; | |
192 | } | |
193 | ||
194 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
195 | { | |
196 | cmd->raw_cmd[2] &= ~0xffffffffffffUL; | |
197 | cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL; | |
198 | } | |
199 | ||
200 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
201 | { | |
202 | cmd->raw_cmd[2] &= ~(1UL << 63); | |
203 | cmd->raw_cmd[2] |= ((u64)!!valid) << 63; | |
204 | } | |
205 | ||
206 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
207 | { | |
208 | cmd->raw_cmd[2] &= ~(0xffffffffUL << 16); | |
209 | cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16)); | |
210 | } | |
211 | ||
212 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
213 | { | |
214 | cmd->raw_cmd[2] &= ~0xffffUL; | |
215 | cmd->raw_cmd[2] |= col; | |
216 | } | |
217 | ||
218 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
219 | { | |
220 | /* Let's fixup BE commands */ | |
221 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
222 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
223 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
224 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
225 | } | |
226 | ||
227 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
228 | struct its_cmd_desc *desc) | |
229 | { | |
230 | unsigned long itt_addr; | |
231 | u8 size = order_base_2(desc->its_mapd_cmd.dev->nr_ites); | |
232 | ||
233 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
234 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
235 | ||
236 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
237 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
238 | its_encode_size(cmd, size - 1); | |
239 | its_encode_itt(cmd, itt_addr); | |
240 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
241 | ||
242 | its_fixup_cmd(cmd); | |
243 | ||
244 | return desc->its_mapd_cmd.dev->collection; | |
245 | } | |
246 | ||
247 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
248 | struct its_cmd_desc *desc) | |
249 | { | |
250 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
251 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
252 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
253 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
254 | ||
255 | its_fixup_cmd(cmd); | |
256 | ||
257 | return desc->its_mapc_cmd.col; | |
258 | } | |
259 | ||
260 | static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, | |
261 | struct its_cmd_desc *desc) | |
262 | { | |
263 | its_encode_cmd(cmd, GITS_CMD_MAPVI); | |
264 | its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); | |
265 | its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); | |
266 | its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); | |
267 | its_encode_collection(cmd, desc->its_mapvi_cmd.dev->collection->col_id); | |
268 | ||
269 | its_fixup_cmd(cmd); | |
270 | ||
271 | return desc->its_mapvi_cmd.dev->collection; | |
272 | } | |
273 | ||
274 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
275 | struct its_cmd_desc *desc) | |
276 | { | |
277 | its_encode_cmd(cmd, GITS_CMD_MOVI); | |
278 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
279 | its_encode_event_id(cmd, desc->its_movi_cmd.id); | |
280 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); | |
281 | ||
282 | its_fixup_cmd(cmd); | |
283 | ||
284 | return desc->its_movi_cmd.dev->collection; | |
285 | } | |
286 | ||
287 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
288 | struct its_cmd_desc *desc) | |
289 | { | |
290 | its_encode_cmd(cmd, GITS_CMD_DISCARD); | |
291 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
292 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
293 | ||
294 | its_fixup_cmd(cmd); | |
295 | ||
296 | return desc->its_discard_cmd.dev->collection; | |
297 | } | |
298 | ||
299 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
300 | struct its_cmd_desc *desc) | |
301 | { | |
302 | its_encode_cmd(cmd, GITS_CMD_INV); | |
303 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
304 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
305 | ||
306 | its_fixup_cmd(cmd); | |
307 | ||
308 | return desc->its_inv_cmd.dev->collection; | |
309 | } | |
310 | ||
311 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, | |
312 | struct its_cmd_desc *desc) | |
313 | { | |
314 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
315 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
316 | ||
317 | its_fixup_cmd(cmd); | |
318 | ||
319 | return NULL; | |
320 | } | |
321 | ||
322 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
323 | struct its_cmd_block *ptr) | |
324 | { | |
325 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
326 | } | |
327 | ||
328 | static int its_queue_full(struct its_node *its) | |
329 | { | |
330 | int widx; | |
331 | int ridx; | |
332 | ||
333 | widx = its->cmd_write - its->cmd_base; | |
334 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
335 | ||
336 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
337 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
338 | return 1; | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
344 | { | |
345 | struct its_cmd_block *cmd; | |
346 | u32 count = 1000000; /* 1s! */ | |
347 | ||
348 | while (its_queue_full(its)) { | |
349 | count--; | |
350 | if (!count) { | |
351 | pr_err_ratelimited("ITS queue not draining\n"); | |
352 | return NULL; | |
353 | } | |
354 | cpu_relax(); | |
355 | udelay(1); | |
356 | } | |
357 | ||
358 | cmd = its->cmd_write++; | |
359 | ||
360 | /* Handle queue wrapping */ | |
361 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
362 | its->cmd_write = its->cmd_base; | |
363 | ||
364 | return cmd; | |
365 | } | |
366 | ||
367 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
368 | { | |
369 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
370 | ||
371 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
372 | ||
373 | return its->cmd_write; | |
374 | } | |
375 | ||
376 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
377 | { | |
378 | /* | |
379 | * Make sure the commands written to memory are observable by | |
380 | * the ITS. | |
381 | */ | |
382 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
383 | __flush_dcache_area(cmd, sizeof(*cmd)); | |
384 | else | |
385 | dsb(ishst); | |
386 | } | |
387 | ||
388 | static void its_wait_for_range_completion(struct its_node *its, | |
389 | struct its_cmd_block *from, | |
390 | struct its_cmd_block *to) | |
391 | { | |
392 | u64 rd_idx, from_idx, to_idx; | |
393 | u32 count = 1000000; /* 1s! */ | |
394 | ||
395 | from_idx = its_cmd_ptr_to_offset(its, from); | |
396 | to_idx = its_cmd_ptr_to_offset(its, to); | |
397 | ||
398 | while (1) { | |
399 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
400 | if (rd_idx >= to_idx || rd_idx < from_idx) | |
401 | break; | |
402 | ||
403 | count--; | |
404 | if (!count) { | |
405 | pr_err_ratelimited("ITS queue timeout\n"); | |
406 | return; | |
407 | } | |
408 | cpu_relax(); | |
409 | udelay(1); | |
410 | } | |
411 | } | |
412 | ||
413 | static void its_send_single_command(struct its_node *its, | |
414 | its_cmd_builder_t builder, | |
415 | struct its_cmd_desc *desc) | |
416 | { | |
417 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; | |
418 | struct its_collection *sync_col; | |
419 | ||
420 | raw_spin_lock(&its->lock); | |
421 | ||
422 | cmd = its_allocate_entry(its); | |
423 | if (!cmd) { /* We're soooooo screewed... */ | |
424 | pr_err_ratelimited("ITS can't allocate, dropping command\n"); | |
425 | raw_spin_unlock(&its->lock); | |
426 | return; | |
427 | } | |
428 | sync_col = builder(cmd, desc); | |
429 | its_flush_cmd(its, cmd); | |
430 | ||
431 | if (sync_col) { | |
432 | sync_cmd = its_allocate_entry(its); | |
433 | if (!sync_cmd) { | |
434 | pr_err_ratelimited("ITS can't SYNC, skipping\n"); | |
435 | goto post; | |
436 | } | |
437 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
438 | its_encode_target(sync_cmd, sync_col->target_address); | |
439 | its_fixup_cmd(sync_cmd); | |
440 | its_flush_cmd(its, sync_cmd); | |
441 | } | |
442 | ||
443 | post: | |
444 | next_cmd = its_post_commands(its); | |
445 | raw_spin_unlock(&its->lock); | |
446 | ||
447 | its_wait_for_range_completion(its, cmd, next_cmd); | |
448 | } | |
449 | ||
450 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
451 | { | |
452 | struct its_cmd_desc desc; | |
453 | ||
454 | desc.its_inv_cmd.dev = dev; | |
455 | desc.its_inv_cmd.event_id = event_id; | |
456 | ||
457 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
458 | } | |
459 | ||
460 | static void its_send_mapd(struct its_device *dev, int valid) | |
461 | { | |
462 | struct its_cmd_desc desc; | |
463 | ||
464 | desc.its_mapd_cmd.dev = dev; | |
465 | desc.its_mapd_cmd.valid = !!valid; | |
466 | ||
467 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
468 | } | |
469 | ||
470 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
471 | int valid) | |
472 | { | |
473 | struct its_cmd_desc desc; | |
474 | ||
475 | desc.its_mapc_cmd.col = col; | |
476 | desc.its_mapc_cmd.valid = !!valid; | |
477 | ||
478 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
479 | } | |
480 | ||
481 | static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) | |
482 | { | |
483 | struct its_cmd_desc desc; | |
484 | ||
485 | desc.its_mapvi_cmd.dev = dev; | |
486 | desc.its_mapvi_cmd.phys_id = irq_id; | |
487 | desc.its_mapvi_cmd.event_id = id; | |
488 | ||
489 | its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); | |
490 | } | |
491 | ||
492 | static void its_send_movi(struct its_device *dev, | |
493 | struct its_collection *col, u32 id) | |
494 | { | |
495 | struct its_cmd_desc desc; | |
496 | ||
497 | desc.its_movi_cmd.dev = dev; | |
498 | desc.its_movi_cmd.col = col; | |
499 | desc.its_movi_cmd.id = id; | |
500 | ||
501 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
502 | } | |
503 | ||
504 | static void its_send_discard(struct its_device *dev, u32 id) | |
505 | { | |
506 | struct its_cmd_desc desc; | |
507 | ||
508 | desc.its_discard_cmd.dev = dev; | |
509 | desc.its_discard_cmd.event_id = id; | |
510 | ||
511 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
512 | } | |
513 | ||
514 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
515 | { | |
516 | struct its_cmd_desc desc; | |
517 | ||
518 | desc.its_invall_cmd.col = col; | |
519 | ||
520 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
521 | } | |
c48ed51c MZ |
522 | |
523 | /* | |
524 | * irqchip functions - assumes MSI, mostly. | |
525 | */ | |
526 | ||
527 | static inline u32 its_get_event_id(struct irq_data *d) | |
528 | { | |
529 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
530 | return d->hwirq - its_dev->lpi_base; | |
531 | } | |
532 | ||
533 | static void lpi_set_config(struct irq_data *d, bool enable) | |
534 | { | |
535 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
536 | irq_hw_number_t hwirq = d->hwirq; | |
537 | u32 id = its_get_event_id(d); | |
538 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
539 | ||
540 | if (enable) | |
541 | *cfg |= LPI_PROP_ENABLED; | |
542 | else | |
543 | *cfg &= ~LPI_PROP_ENABLED; | |
544 | ||
545 | /* | |
546 | * Make the above write visible to the redistributors. | |
547 | * And yes, we're flushing exactly: One. Single. Byte. | |
548 | * Humpf... | |
549 | */ | |
550 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
551 | __flush_dcache_area(cfg, sizeof(*cfg)); | |
552 | else | |
553 | dsb(ishst); | |
554 | its_send_inv(its_dev, id); | |
555 | } | |
556 | ||
557 | static void its_mask_irq(struct irq_data *d) | |
558 | { | |
559 | lpi_set_config(d, false); | |
560 | } | |
561 | ||
562 | static void its_unmask_irq(struct irq_data *d) | |
563 | { | |
564 | lpi_set_config(d, true); | |
565 | } | |
566 | ||
567 | static void its_eoi_irq(struct irq_data *d) | |
568 | { | |
569 | gic_write_eoir(d->hwirq); | |
570 | } | |
571 | ||
572 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
573 | bool force) | |
574 | { | |
575 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
576 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
577 | struct its_collection *target_col; | |
578 | u32 id = its_get_event_id(d); | |
579 | ||
580 | if (cpu >= nr_cpu_ids) | |
581 | return -EINVAL; | |
582 | ||
583 | target_col = &its_dev->its->collections[cpu]; | |
584 | its_send_movi(its_dev, target_col, id); | |
585 | its_dev->collection = target_col; | |
586 | ||
587 | return IRQ_SET_MASK_OK_DONE; | |
588 | } | |
589 | ||
b48ac83d MZ |
590 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
591 | { | |
592 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
593 | struct its_node *its; | |
594 | u64 addr; | |
595 | ||
596 | its = its_dev->its; | |
597 | addr = its->phys_base + GITS_TRANSLATER; | |
598 | ||
599 | msg->address_lo = addr & ((1UL << 32) - 1); | |
600 | msg->address_hi = addr >> 32; | |
601 | msg->data = its_get_event_id(d); | |
602 | } | |
603 | ||
c48ed51c MZ |
604 | static struct irq_chip its_irq_chip = { |
605 | .name = "ITS", | |
606 | .irq_mask = its_mask_irq, | |
607 | .irq_unmask = its_unmask_irq, | |
608 | .irq_eoi = its_eoi_irq, | |
609 | .irq_set_affinity = its_set_affinity, | |
b48ac83d MZ |
610 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
611 | }; | |
612 | ||
613 | static void its_mask_msi_irq(struct irq_data *d) | |
614 | { | |
615 | pci_msi_mask_irq(d); | |
616 | irq_chip_mask_parent(d); | |
617 | } | |
618 | ||
619 | static void its_unmask_msi_irq(struct irq_data *d) | |
620 | { | |
621 | pci_msi_unmask_irq(d); | |
622 | irq_chip_unmask_parent(d); | |
623 | } | |
624 | ||
625 | static struct irq_chip its_msi_irq_chip = { | |
626 | .name = "ITS-MSI", | |
627 | .irq_unmask = its_unmask_msi_irq, | |
628 | .irq_mask = its_mask_msi_irq, | |
629 | .irq_eoi = irq_chip_eoi_parent, | |
630 | .irq_write_msi_msg = pci_msi_domain_write_msg, | |
c48ed51c | 631 | }; |
bf9529f8 MZ |
632 | |
633 | /* | |
634 | * How we allocate LPIs: | |
635 | * | |
636 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
637 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
638 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
639 | * bits to the right. | |
640 | * | |
641 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
642 | */ | |
643 | #define IRQS_PER_CHUNK_SHIFT 5 | |
644 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
645 | ||
646 | static unsigned long *lpi_bitmap; | |
647 | static u32 lpi_chunks; | |
648 | static DEFINE_SPINLOCK(lpi_lock); | |
649 | ||
650 | static int its_lpi_to_chunk(int lpi) | |
651 | { | |
652 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
653 | } | |
654 | ||
655 | static int its_chunk_to_lpi(int chunk) | |
656 | { | |
657 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
658 | } | |
659 | ||
660 | static int its_lpi_init(u32 id_bits) | |
661 | { | |
662 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
663 | ||
664 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
665 | GFP_KERNEL); | |
666 | if (!lpi_bitmap) { | |
667 | lpi_chunks = 0; | |
668 | return -ENOMEM; | |
669 | } | |
670 | ||
671 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
672 | return 0; | |
673 | } | |
674 | ||
675 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
676 | { | |
677 | unsigned long *bitmap = NULL; | |
678 | int chunk_id; | |
679 | int nr_chunks; | |
680 | int i; | |
681 | ||
682 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
683 | ||
684 | spin_lock(&lpi_lock); | |
685 | ||
686 | do { | |
687 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
688 | 0, nr_chunks, 0); | |
689 | if (chunk_id < lpi_chunks) | |
690 | break; | |
691 | ||
692 | nr_chunks--; | |
693 | } while (nr_chunks > 0); | |
694 | ||
695 | if (!nr_chunks) | |
696 | goto out; | |
697 | ||
698 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
699 | GFP_ATOMIC); | |
700 | if (!bitmap) | |
701 | goto out; | |
702 | ||
703 | for (i = 0; i < nr_chunks; i++) | |
704 | set_bit(chunk_id + i, lpi_bitmap); | |
705 | ||
706 | *base = its_chunk_to_lpi(chunk_id); | |
707 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
708 | ||
709 | out: | |
710 | spin_unlock(&lpi_lock); | |
711 | ||
712 | return bitmap; | |
713 | } | |
714 | ||
715 | static void its_lpi_free(unsigned long *bitmap, int base, int nr_ids) | |
716 | { | |
717 | int lpi; | |
718 | ||
719 | spin_lock(&lpi_lock); | |
720 | ||
721 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
722 | int chunk = its_lpi_to_chunk(lpi); | |
723 | BUG_ON(chunk > lpi_chunks); | |
724 | if (test_bit(chunk, lpi_bitmap)) { | |
725 | clear_bit(chunk, lpi_bitmap); | |
726 | } else { | |
727 | pr_err("Bad LPI chunk %d\n", chunk); | |
728 | } | |
729 | } | |
730 | ||
731 | spin_unlock(&lpi_lock); | |
732 | ||
733 | kfree(bitmap); | |
734 | } | |
1ac19ca6 MZ |
735 | |
736 | /* | |
737 | * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to | |
738 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
739 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
740 | */ | |
741 | #define LPI_PROPBASE_SZ SZ_64K | |
742 | #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) | |
743 | ||
744 | /* | |
745 | * This is how many bits of ID we need, including the useless ones. | |
746 | */ | |
747 | #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) | |
748 | ||
749 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
750 | ||
751 | static int __init its_alloc_lpi_tables(void) | |
752 | { | |
753 | phys_addr_t paddr; | |
754 | ||
755 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, | |
756 | get_order(LPI_PROPBASE_SZ)); | |
757 | if (!gic_rdists->prop_page) { | |
758 | pr_err("Failed to allocate PROPBASE\n"); | |
759 | return -ENOMEM; | |
760 | } | |
761 | ||
762 | paddr = page_to_phys(gic_rdists->prop_page); | |
763 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
764 | ||
765 | /* Priority 0xa0, Group-1, disabled */ | |
766 | memset(page_address(gic_rdists->prop_page), | |
767 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
768 | LPI_PROPBASE_SZ); | |
769 | ||
770 | /* Make sure the GIC will observe the written configuration */ | |
771 | __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static const char *its_base_type_string[] = { | |
777 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
778 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
779 | [GITS_BASER_TYPE_CPU] = "Physical CPUs", | |
780 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", | |
781 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
782 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
783 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
784 | }; | |
785 | ||
786 | static void its_free_tables(struct its_node *its) | |
787 | { | |
788 | int i; | |
789 | ||
790 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
791 | if (its->tables[i]) { | |
792 | free_page((unsigned long)its->tables[i]); | |
793 | its->tables[i] = NULL; | |
794 | } | |
795 | } | |
796 | } | |
797 | ||
798 | static int its_alloc_tables(struct its_node *its) | |
799 | { | |
800 | int err; | |
801 | int i; | |
802 | int psz = PAGE_SIZE; | |
803 | u64 shr = GITS_BASER_InnerShareable; | |
804 | ||
805 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
806 | u64 val = readq_relaxed(its->base + GITS_BASER + i * 8); | |
807 | u64 type = GITS_BASER_TYPE(val); | |
808 | u64 entry_size = GITS_BASER_ENTRY_SIZE(val); | |
809 | u64 tmp; | |
810 | void *base; | |
811 | ||
812 | if (type == GITS_BASER_TYPE_NONE) | |
813 | continue; | |
814 | ||
815 | /* We're lazy and only allocate a single page for now */ | |
816 | base = (void *)get_zeroed_page(GFP_KERNEL); | |
817 | if (!base) { | |
818 | err = -ENOMEM; | |
819 | goto out_free; | |
820 | } | |
821 | ||
822 | its->tables[i] = base; | |
823 | ||
824 | retry_baser: | |
825 | val = (virt_to_phys(base) | | |
826 | (type << GITS_BASER_TYPE_SHIFT) | | |
827 | ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
828 | GITS_BASER_WaWb | | |
829 | shr | | |
830 | GITS_BASER_VALID); | |
831 | ||
832 | switch (psz) { | |
833 | case SZ_4K: | |
834 | val |= GITS_BASER_PAGE_SIZE_4K; | |
835 | break; | |
836 | case SZ_16K: | |
837 | val |= GITS_BASER_PAGE_SIZE_16K; | |
838 | break; | |
839 | case SZ_64K: | |
840 | val |= GITS_BASER_PAGE_SIZE_64K; | |
841 | break; | |
842 | } | |
843 | ||
844 | val |= (PAGE_SIZE / psz) - 1; | |
845 | ||
846 | writeq_relaxed(val, its->base + GITS_BASER + i * 8); | |
847 | tmp = readq_relaxed(its->base + GITS_BASER + i * 8); | |
848 | ||
849 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
850 | /* | |
851 | * Shareability didn't stick. Just use | |
852 | * whatever the read reported, which is likely | |
853 | * to be the only thing this redistributor | |
854 | * supports. | |
855 | */ | |
856 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
857 | goto retry_baser; | |
858 | } | |
859 | ||
860 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
861 | /* | |
862 | * Page size didn't stick. Let's try a smaller | |
863 | * size and retry. If we reach 4K, then | |
864 | * something is horribly wrong... | |
865 | */ | |
866 | switch (psz) { | |
867 | case SZ_16K: | |
868 | psz = SZ_4K; | |
869 | goto retry_baser; | |
870 | case SZ_64K: | |
871 | psz = SZ_16K; | |
872 | goto retry_baser; | |
873 | } | |
874 | } | |
875 | ||
876 | if (val != tmp) { | |
877 | pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n", | |
878 | its->msi_chip.of_node->full_name, i, | |
879 | (unsigned long) val, (unsigned long) tmp); | |
880 | err = -ENXIO; | |
881 | goto out_free; | |
882 | } | |
883 | ||
884 | pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n", | |
885 | (int)(PAGE_SIZE / entry_size), | |
886 | its_base_type_string[type], | |
887 | (unsigned long)virt_to_phys(base), | |
888 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); | |
889 | } | |
890 | ||
891 | return 0; | |
892 | ||
893 | out_free: | |
894 | its_free_tables(its); | |
895 | ||
896 | return err; | |
897 | } | |
898 | ||
899 | static int its_alloc_collections(struct its_node *its) | |
900 | { | |
901 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
902 | GFP_KERNEL); | |
903 | if (!its->collections) | |
904 | return -ENOMEM; | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | static void its_cpu_init_lpis(void) | |
910 | { | |
911 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
912 | struct page *pend_page; | |
913 | u64 val, tmp; | |
914 | ||
915 | /* If we didn't allocate the pending table yet, do it now */ | |
916 | pend_page = gic_data_rdist()->pend_page; | |
917 | if (!pend_page) { | |
918 | phys_addr_t paddr; | |
919 | /* | |
920 | * The pending pages have to be at least 64kB aligned, | |
921 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
922 | */ | |
923 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
924 | get_order(max(LPI_PENDBASE_SZ, SZ_64K))); | |
925 | if (!pend_page) { | |
926 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
927 | smp_processor_id()); | |
928 | return; | |
929 | } | |
930 | ||
931 | /* Make sure the GIC will observe the zero-ed page */ | |
932 | __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ); | |
933 | ||
934 | paddr = page_to_phys(pend_page); | |
935 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
936 | smp_processor_id(), &paddr); | |
937 | gic_data_rdist()->pend_page = pend_page; | |
938 | } | |
939 | ||
940 | /* Disable LPIs */ | |
941 | val = readl_relaxed(rbase + GICR_CTLR); | |
942 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
943 | writel_relaxed(val, rbase + GICR_CTLR); | |
944 | ||
945 | /* | |
946 | * Make sure any change to the table is observable by the GIC. | |
947 | */ | |
948 | dsb(sy); | |
949 | ||
950 | /* set PROPBASE */ | |
951 | val = (page_to_phys(gic_rdists->prop_page) | | |
952 | GICR_PROPBASER_InnerShareable | | |
953 | GICR_PROPBASER_WaWb | | |
954 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); | |
955 | ||
956 | writeq_relaxed(val, rbase + GICR_PROPBASER); | |
957 | tmp = readq_relaxed(rbase + GICR_PROPBASER); | |
958 | ||
959 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
960 | pr_info_once("GIC: using cache flushing for LPI property table\n"); | |
961 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
962 | } | |
963 | ||
964 | /* set PENDBASE */ | |
965 | val = (page_to_phys(pend_page) | | |
966 | GICR_PROPBASER_InnerShareable | | |
967 | GICR_PROPBASER_WaWb); | |
968 | ||
969 | writeq_relaxed(val, rbase + GICR_PENDBASER); | |
970 | ||
971 | /* Enable LPIs */ | |
972 | val = readl_relaxed(rbase + GICR_CTLR); | |
973 | val |= GICR_CTLR_ENABLE_LPIS; | |
974 | writel_relaxed(val, rbase + GICR_CTLR); | |
975 | ||
976 | /* Make sure the GIC has seen the above */ | |
977 | dsb(sy); | |
978 | } | |
979 | ||
980 | static void its_cpu_init_collection(void) | |
981 | { | |
982 | struct its_node *its; | |
983 | int cpu; | |
984 | ||
985 | spin_lock(&its_lock); | |
986 | cpu = smp_processor_id(); | |
987 | ||
988 | list_for_each_entry(its, &its_nodes, entry) { | |
989 | u64 target; | |
990 | ||
991 | /* | |
992 | * We now have to bind each collection to its target | |
993 | * redistributor. | |
994 | */ | |
995 | if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
996 | /* | |
997 | * This ITS wants the physical address of the | |
998 | * redistributor. | |
999 | */ | |
1000 | target = gic_data_rdist()->phys_base; | |
1001 | } else { | |
1002 | /* | |
1003 | * This ITS wants a linear CPU number. | |
1004 | */ | |
1005 | target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); | |
1006 | target = GICR_TYPER_CPU_NUMBER(target); | |
1007 | } | |
1008 | ||
1009 | /* Perform collection mapping */ | |
1010 | its->collections[cpu].target_address = target; | |
1011 | its->collections[cpu].col_id = cpu; | |
1012 | ||
1013 | its_send_mapc(its, &its->collections[cpu], 1); | |
1014 | its_send_invall(its, &its->collections[cpu]); | |
1015 | } | |
1016 | ||
1017 | spin_unlock(&its_lock); | |
1018 | } | |
84a6a2e7 MZ |
1019 | |
1020 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1021 | { | |
1022 | struct its_device *its_dev = NULL, *tmp; | |
1023 | ||
1024 | raw_spin_lock(&its->lock); | |
1025 | ||
1026 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1027 | if (tmp->device_id == dev_id) { | |
1028 | its_dev = tmp; | |
1029 | break; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | raw_spin_unlock(&its->lock); | |
1034 | ||
1035 | return its_dev; | |
1036 | } | |
1037 | ||
1038 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, | |
1039 | int nvecs) | |
1040 | { | |
1041 | struct its_device *dev; | |
1042 | unsigned long *lpi_map; | |
1043 | void *itt; | |
1044 | int lpi_base; | |
1045 | int nr_lpis; | |
1046 | int cpu; | |
1047 | int sz; | |
1048 | ||
1049 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1050 | sz = nvecs * its->ite_size; | |
1051 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; | |
1052 | itt = kmalloc(sz, GFP_KERNEL); | |
1053 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); | |
1054 | ||
1055 | if (!dev || !itt || !lpi_map) { | |
1056 | kfree(dev); | |
1057 | kfree(itt); | |
1058 | kfree(lpi_map); | |
1059 | return NULL; | |
1060 | } | |
1061 | ||
1062 | dev->its = its; | |
1063 | dev->itt = itt; | |
1064 | dev->nr_ites = nvecs; | |
1065 | dev->lpi_map = lpi_map; | |
1066 | dev->lpi_base = lpi_base; | |
1067 | dev->nr_lpis = nr_lpis; | |
1068 | dev->device_id = dev_id; | |
1069 | INIT_LIST_HEAD(&dev->entry); | |
1070 | ||
1071 | raw_spin_lock(&its->lock); | |
1072 | list_add(&dev->entry, &its->its_device_list); | |
1073 | raw_spin_unlock(&its->lock); | |
1074 | ||
1075 | /* Bind the device to the first possible CPU */ | |
1076 | cpu = cpumask_first(cpu_online_mask); | |
1077 | dev->collection = &its->collections[cpu]; | |
1078 | ||
1079 | /* Map device to its ITT */ | |
1080 | its_send_mapd(dev, 1); | |
1081 | ||
1082 | return dev; | |
1083 | } | |
1084 | ||
1085 | static void its_free_device(struct its_device *its_dev) | |
1086 | { | |
1087 | raw_spin_lock(&its_dev->its->lock); | |
1088 | list_del(&its_dev->entry); | |
1089 | raw_spin_unlock(&its_dev->its->lock); | |
1090 | kfree(its_dev->itt); | |
1091 | kfree(its_dev); | |
1092 | } | |
b48ac83d MZ |
1093 | |
1094 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1095 | { | |
1096 | int idx; | |
1097 | ||
1098 | idx = find_first_zero_bit(dev->lpi_map, dev->nr_lpis); | |
1099 | if (idx == dev->nr_lpis) | |
1100 | return -ENOSPC; | |
1101 | ||
1102 | *hwirq = dev->lpi_base + idx; | |
1103 | set_bit(idx, dev->lpi_map); | |
1104 | ||
1105 | /* Map the GIC irq ID to the device */ | |
1106 | its_send_mapvi(dev, *hwirq, idx); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, | |
1112 | int nvec, msi_alloc_info_t *info) | |
1113 | { | |
1114 | struct pci_dev *pdev; | |
1115 | struct its_node *its; | |
1116 | u32 dev_id; | |
1117 | struct its_device *its_dev; | |
1118 | ||
1119 | if (!dev_is_pci(dev)) | |
1120 | return -EINVAL; | |
1121 | ||
1122 | pdev = to_pci_dev(dev); | |
1123 | dev_id = PCI_DEVID(pdev->bus->number, pdev->devfn); | |
1124 | its = domain->parent->host_data; | |
1125 | ||
1126 | its_dev = its_find_device(its, dev_id); | |
1127 | if (WARN_ON(its_dev)) | |
1128 | return -EINVAL; | |
1129 | ||
1130 | its_dev = its_create_device(its, dev_id, nvec); | |
1131 | if (!its_dev) | |
1132 | return -ENOMEM; | |
1133 | ||
1134 | dev_dbg(&pdev->dev, "ITT %d entries, %d bits\n", nvec, ilog2(nvec)); | |
1135 | ||
1136 | info->scratchpad[0].ptr = its_dev; | |
1137 | info->scratchpad[1].ptr = dev; | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static struct msi_domain_ops its_pci_msi_ops = { | |
1142 | .msi_prepare = its_msi_prepare, | |
1143 | }; | |
1144 | ||
1145 | static struct msi_domain_info its_pci_msi_domain_info = { | |
1146 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
1147 | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), | |
1148 | .ops = &its_pci_msi_ops, | |
1149 | .chip = &its_msi_irq_chip, | |
1150 | }; | |
1151 | ||
1152 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, | |
1153 | unsigned int virq, | |
1154 | irq_hw_number_t hwirq) | |
1155 | { | |
1156 | struct of_phandle_args args; | |
1157 | ||
1158 | args.np = domain->parent->of_node; | |
1159 | args.args_count = 3; | |
1160 | args.args[0] = GIC_IRQ_TYPE_LPI; | |
1161 | args.args[1] = hwirq; | |
1162 | args.args[2] = IRQ_TYPE_EDGE_RISING; | |
1163 | ||
1164 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &args); | |
1165 | } | |
1166 | ||
1167 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1168 | unsigned int nr_irqs, void *args) | |
1169 | { | |
1170 | msi_alloc_info_t *info = args; | |
1171 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1172 | irq_hw_number_t hwirq; | |
1173 | int err; | |
1174 | int i; | |
1175 | ||
1176 | for (i = 0; i < nr_irqs; i++) { | |
1177 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1178 | if (err) | |
1179 | return err; | |
1180 | ||
1181 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1182 | if (err) | |
1183 | return err; | |
1184 | ||
1185 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1186 | hwirq, &its_irq_chip, its_dev); | |
1187 | dev_dbg(info->scratchpad[1].ptr, "ID:%d pID:%d vID:%d\n", | |
1188 | (int)(hwirq - its_dev->lpi_base), (int)hwirq, virq + i); | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
1195 | unsigned int nr_irqs) | |
1196 | { | |
1197 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1198 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1199 | int i; | |
1200 | ||
1201 | for (i = 0; i < nr_irqs; i++) { | |
1202 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1203 | virq + i); | |
1204 | int event = its_get_event_id(data); | |
1205 | ||
1206 | /* Stop the delivery of interrupts */ | |
1207 | its_send_discard(its_dev, event); | |
1208 | ||
1209 | /* Mark interrupt index as unused */ | |
1210 | clear_bit(event, its_dev->lpi_map); | |
1211 | ||
1212 | /* Nuke the entry in the domain */ | |
1213 | irq_domain_reset_irq_data(d); | |
1214 | } | |
1215 | ||
1216 | /* If all interrupts have been freed, start mopping the floor */ | |
1217 | if (bitmap_empty(its_dev->lpi_map, its_dev->nr_lpis)) { | |
1218 | its_lpi_free(its_dev->lpi_map, | |
1219 | its_dev->lpi_base, | |
1220 | its_dev->nr_lpis); | |
1221 | ||
1222 | /* Unmap device/itt */ | |
1223 | its_send_mapd(its_dev, 0); | |
1224 | its_free_device(its_dev); | |
1225 | } | |
1226 | ||
1227 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1228 | } | |
1229 | ||
1230 | static const struct irq_domain_ops its_domain_ops = { | |
1231 | .alloc = its_irq_domain_alloc, | |
1232 | .free = its_irq_domain_free, | |
1233 | }; | |
4c21f3c2 MZ |
1234 | |
1235 | static int its_probe(struct device_node *node, struct irq_domain *parent) | |
1236 | { | |
1237 | struct resource res; | |
1238 | struct its_node *its; | |
1239 | void __iomem *its_base; | |
1240 | u32 val; | |
1241 | u64 baser, tmp; | |
1242 | int err; | |
1243 | ||
1244 | err = of_address_to_resource(node, 0, &res); | |
1245 | if (err) { | |
1246 | pr_warn("%s: no regs?\n", node->full_name); | |
1247 | return -ENXIO; | |
1248 | } | |
1249 | ||
1250 | its_base = ioremap(res.start, resource_size(&res)); | |
1251 | if (!its_base) { | |
1252 | pr_warn("%s: unable to map registers\n", node->full_name); | |
1253 | return -ENOMEM; | |
1254 | } | |
1255 | ||
1256 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1257 | if (val != 0x30 && val != 0x40) { | |
1258 | pr_warn("%s: no ITS detected, giving up\n", node->full_name); | |
1259 | err = -ENODEV; | |
1260 | goto out_unmap; | |
1261 | } | |
1262 | ||
1263 | pr_info("ITS: %s\n", node->full_name); | |
1264 | ||
1265 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1266 | if (!its) { | |
1267 | err = -ENOMEM; | |
1268 | goto out_unmap; | |
1269 | } | |
1270 | ||
1271 | raw_spin_lock_init(&its->lock); | |
1272 | INIT_LIST_HEAD(&its->entry); | |
1273 | INIT_LIST_HEAD(&its->its_device_list); | |
1274 | its->base = its_base; | |
1275 | its->phys_base = res.start; | |
1276 | its->msi_chip.of_node = node; | |
1277 | its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; | |
1278 | ||
1279 | its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); | |
1280 | if (!its->cmd_base) { | |
1281 | err = -ENOMEM; | |
1282 | goto out_free_its; | |
1283 | } | |
1284 | its->cmd_write = its->cmd_base; | |
1285 | ||
1286 | err = its_alloc_tables(its); | |
1287 | if (err) | |
1288 | goto out_free_cmd; | |
1289 | ||
1290 | err = its_alloc_collections(its); | |
1291 | if (err) | |
1292 | goto out_free_tables; | |
1293 | ||
1294 | baser = (virt_to_phys(its->cmd_base) | | |
1295 | GITS_CBASER_WaWb | | |
1296 | GITS_CBASER_InnerShareable | | |
1297 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1298 | GITS_CBASER_VALID); | |
1299 | ||
1300 | writeq_relaxed(baser, its->base + GITS_CBASER); | |
1301 | tmp = readq_relaxed(its->base + GITS_CBASER); | |
1302 | writeq_relaxed(0, its->base + GITS_CWRITER); | |
1303 | writel_relaxed(1, its->base + GITS_CTLR); | |
1304 | ||
1305 | if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) { | |
1306 | pr_info("ITS: using cache flushing for cmd queue\n"); | |
1307 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1308 | } | |
1309 | ||
1310 | if (of_property_read_bool(its->msi_chip.of_node, "msi-controller")) { | |
1311 | its->domain = irq_domain_add_tree(NULL, &its_domain_ops, its); | |
1312 | if (!its->domain) { | |
1313 | err = -ENOMEM; | |
1314 | goto out_free_tables; | |
1315 | } | |
1316 | ||
1317 | its->domain->parent = parent; | |
1318 | ||
1319 | its->msi_chip.domain = pci_msi_create_irq_domain(node, | |
1320 | &its_pci_msi_domain_info, | |
1321 | its->domain); | |
1322 | if (!its->msi_chip.domain) { | |
1323 | err = -ENOMEM; | |
1324 | goto out_free_domains; | |
1325 | } | |
1326 | ||
1327 | err = of_pci_msi_chip_add(&its->msi_chip); | |
1328 | if (err) | |
1329 | goto out_free_domains; | |
1330 | } | |
1331 | ||
1332 | spin_lock(&its_lock); | |
1333 | list_add(&its->entry, &its_nodes); | |
1334 | spin_unlock(&its_lock); | |
1335 | ||
1336 | return 0; | |
1337 | ||
1338 | out_free_domains: | |
1339 | if (its->msi_chip.domain) | |
1340 | irq_domain_remove(its->msi_chip.domain); | |
1341 | if (its->domain) | |
1342 | irq_domain_remove(its->domain); | |
1343 | out_free_tables: | |
1344 | its_free_tables(its); | |
1345 | out_free_cmd: | |
1346 | kfree(its->cmd_base); | |
1347 | out_free_its: | |
1348 | kfree(its); | |
1349 | out_unmap: | |
1350 | iounmap(its_base); | |
1351 | pr_err("ITS: failed probing %s (%d)\n", node->full_name, err); | |
1352 | return err; | |
1353 | } | |
1354 | ||
1355 | static bool gic_rdists_supports_plpis(void) | |
1356 | { | |
1357 | return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); | |
1358 | } | |
1359 | ||
1360 | int its_cpu_init(void) | |
1361 | { | |
1362 | if (!gic_rdists_supports_plpis()) { | |
1363 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1364 | return -ENXIO; | |
1365 | } | |
1366 | ||
1367 | if (!list_empty(&its_nodes)) { | |
1368 | its_cpu_init_lpis(); | |
1369 | its_cpu_init_collection(); | |
1370 | } | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | static struct of_device_id its_device_id[] = { | |
1376 | { .compatible = "arm,gic-v3-its", }, | |
1377 | {}, | |
1378 | }; | |
1379 | ||
1380 | int its_init(struct device_node *node, struct rdists *rdists, | |
1381 | struct irq_domain *parent_domain) | |
1382 | { | |
1383 | struct device_node *np; | |
1384 | ||
1385 | for (np = of_find_matching_node(node, its_device_id); np; | |
1386 | np = of_find_matching_node(np, its_device_id)) { | |
1387 | its_probe(np, parent_domain); | |
1388 | } | |
1389 | ||
1390 | if (list_empty(&its_nodes)) { | |
1391 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
1392 | return -ENXIO; | |
1393 | } | |
1394 | ||
1395 | gic_rdists = rdists; | |
1396 | gic_root_node = node; | |
1397 | ||
1398 | its_alloc_lpi_tables(); | |
1399 | its_lpi_init(rdists->id_bits); | |
1400 | ||
1401 | return 0; | |
1402 | } |