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cc2d3216 | 1 | /* |
d7276b80 | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/delay.h> | |
44bb7e24 | 23 | #include <linux/dma-iommu.h> |
cc2d3216 | 24 | #include <linux/interrupt.h> |
3f010cf1 | 25 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 | 38 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 39 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 40 | |
cc2d3216 MZ |
41 | #include <asm/cputype.h> |
42 | #include <asm/exception.h> | |
43 | ||
67510cca RR |
44 | #include "irq-gic-common.h" |
45 | ||
94100970 RR |
46 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 48 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 49 | |
c48ed51c MZ |
50 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
51 | ||
a13b0404 MZ |
52 | static u32 lpi_id_bits; |
53 | ||
54 | /* | |
55 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
56 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
57 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
58 | */ | |
59 | #define LPI_NRBITS lpi_id_bits | |
60 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
61 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
62 | ||
63 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
64 | ||
cc2d3216 MZ |
65 | /* |
66 | * Collection structure - just an ID, and a redistributor address to | |
67 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
68 | * CPU. | |
69 | */ | |
70 | struct its_collection { | |
71 | u64 target_address; | |
72 | u16 col_id; | |
73 | }; | |
74 | ||
466b7d16 | 75 | /* |
9347359a SD |
76 | * The ITS_BASER structure - contains memory information, cached |
77 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
78 | */ |
79 | struct its_baser { | |
80 | void *base; | |
81 | u64 val; | |
82 | u32 order; | |
9347359a | 83 | u32 psz; |
466b7d16 SD |
84 | }; |
85 | ||
558b0165 AB |
86 | struct its_device; |
87 | ||
cc2d3216 MZ |
88 | /* |
89 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
90 | * top-level MSI domain, the command queue, the collections, and the |
91 | * list of devices writing to it. | |
cc2d3216 MZ |
92 | */ |
93 | struct its_node { | |
94 | raw_spinlock_t lock; | |
95 | struct list_head entry; | |
cc2d3216 | 96 | void __iomem *base; |
db40f0a7 | 97 | phys_addr_t phys_base; |
cc2d3216 MZ |
98 | struct its_cmd_block *cmd_base; |
99 | struct its_cmd_block *cmd_write; | |
466b7d16 | 100 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 101 | struct its_collection *collections; |
558b0165 AB |
102 | struct fwnode_handle *fwnode_handle; |
103 | u64 (*get_msi_base)(struct its_device *its_dev); | |
cc2d3216 MZ |
104 | struct list_head its_device_list; |
105 | u64 flags; | |
debf6d02 | 106 | unsigned long list_nr; |
cc2d3216 | 107 | u32 ite_size; |
466b7d16 | 108 | u32 device_ids; |
fbf8f40e | 109 | int numa_node; |
558b0165 AB |
110 | unsigned int msi_domain_flags; |
111 | u32 pre_its_base; /* for Socionext Synquacer */ | |
3dfa576b | 112 | bool is_v4; |
5c9a882e | 113 | int vlpi_redist_offset; |
cc2d3216 MZ |
114 | }; |
115 | ||
116 | #define ITS_ITT_ALIGN SZ_256 | |
117 | ||
2eca0d6c SD |
118 | /* Convert page order to size in bytes */ |
119 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
120 | ||
591e5bec MZ |
121 | struct event_lpi_map { |
122 | unsigned long *lpi_map; | |
123 | u16 *col_map; | |
124 | irq_hw_number_t lpi_base; | |
125 | int nr_lpis; | |
d011e4e6 MZ |
126 | struct mutex vlpi_lock; |
127 | struct its_vm *vm; | |
128 | struct its_vlpi_map *vlpi_maps; | |
129 | int nr_vlpis; | |
591e5bec MZ |
130 | }; |
131 | ||
cc2d3216 | 132 | /* |
d011e4e6 MZ |
133 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
134 | * translation table, and a list of interrupts. If it some of its | |
135 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
136 | * indicates which one. | |
cc2d3216 MZ |
137 | */ |
138 | struct its_device { | |
139 | struct list_head entry; | |
140 | struct its_node *its; | |
591e5bec | 141 | struct event_lpi_map event_map; |
cc2d3216 | 142 | void *itt; |
cc2d3216 MZ |
143 | u32 nr_ites; |
144 | u32 device_id; | |
145 | }; | |
146 | ||
20b3d54e MZ |
147 | static struct { |
148 | raw_spinlock_t lock; | |
149 | struct its_device *dev; | |
150 | struct its_vpe **vpes; | |
151 | int next_victim; | |
152 | } vpe_proxy; | |
153 | ||
1ac19ca6 MZ |
154 | static LIST_HEAD(its_nodes); |
155 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 156 | static struct rdists *gic_rdists; |
db40f0a7 | 157 | static struct irq_domain *its_parent; |
1ac19ca6 | 158 | |
3dfa576b MZ |
159 | /* |
160 | * We have a maximum number of 16 ITSs in the whole system if we're | |
161 | * using the ITSList mechanism | |
162 | */ | |
163 | #define ITS_LIST_MAX 16 | |
164 | ||
165 | static unsigned long its_list_map; | |
3171a47a MZ |
166 | static u16 vmovp_seq_num; |
167 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
168 | ||
7d75bbb4 | 169 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 170 | |
1ac19ca6 MZ |
171 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
172 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
e643d803 | 173 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 174 | |
591e5bec MZ |
175 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
176 | u32 event) | |
177 | { | |
178 | struct its_node *its = its_dev->its; | |
179 | ||
180 | return its->collections + its_dev->event_map.col_map[event]; | |
181 | } | |
182 | ||
cc2d3216 MZ |
183 | /* |
184 | * ITS command descriptors - parameters to be encoded in a command | |
185 | * block. | |
186 | */ | |
187 | struct its_cmd_desc { | |
188 | union { | |
189 | struct { | |
190 | struct its_device *dev; | |
191 | u32 event_id; | |
192 | } its_inv_cmd; | |
193 | ||
8d85dced MZ |
194 | struct { |
195 | struct its_device *dev; | |
196 | u32 event_id; | |
197 | } its_clear_cmd; | |
198 | ||
cc2d3216 MZ |
199 | struct { |
200 | struct its_device *dev; | |
201 | u32 event_id; | |
202 | } its_int_cmd; | |
203 | ||
204 | struct { | |
205 | struct its_device *dev; | |
206 | int valid; | |
207 | } its_mapd_cmd; | |
208 | ||
209 | struct { | |
210 | struct its_collection *col; | |
211 | int valid; | |
212 | } its_mapc_cmd; | |
213 | ||
214 | struct { | |
215 | struct its_device *dev; | |
216 | u32 phys_id; | |
217 | u32 event_id; | |
6a25ad3a | 218 | } its_mapti_cmd; |
cc2d3216 MZ |
219 | |
220 | struct { | |
221 | struct its_device *dev; | |
222 | struct its_collection *col; | |
591e5bec | 223 | u32 event_id; |
cc2d3216 MZ |
224 | } its_movi_cmd; |
225 | ||
226 | struct { | |
227 | struct its_device *dev; | |
228 | u32 event_id; | |
229 | } its_discard_cmd; | |
230 | ||
231 | struct { | |
232 | struct its_collection *col; | |
233 | } its_invall_cmd; | |
d011e4e6 | 234 | |
eb78192b MZ |
235 | struct { |
236 | struct its_vpe *vpe; | |
237 | } its_vinvall_cmd; | |
238 | ||
239 | struct { | |
240 | struct its_vpe *vpe; | |
241 | struct its_collection *col; | |
242 | bool valid; | |
243 | } its_vmapp_cmd; | |
244 | ||
d011e4e6 MZ |
245 | struct { |
246 | struct its_vpe *vpe; | |
247 | struct its_device *dev; | |
248 | u32 virt_id; | |
249 | u32 event_id; | |
250 | bool db_enabled; | |
251 | } its_vmapti_cmd; | |
252 | ||
253 | struct { | |
254 | struct its_vpe *vpe; | |
255 | struct its_device *dev; | |
256 | u32 event_id; | |
257 | bool db_enabled; | |
258 | } its_vmovi_cmd; | |
3171a47a MZ |
259 | |
260 | struct { | |
261 | struct its_vpe *vpe; | |
262 | struct its_collection *col; | |
263 | u16 seq_num; | |
264 | u16 its_list; | |
265 | } its_vmovp_cmd; | |
cc2d3216 MZ |
266 | }; |
267 | }; | |
268 | ||
269 | /* | |
270 | * The ITS command block, which is what the ITS actually parses. | |
271 | */ | |
272 | struct its_cmd_block { | |
273 | u64 raw_cmd[4]; | |
274 | }; | |
275 | ||
276 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
277 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
278 | ||
67047f90 MZ |
279 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *, |
280 | struct its_cmd_block *, | |
cc2d3216 MZ |
281 | struct its_cmd_desc *); |
282 | ||
67047f90 MZ |
283 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *, |
284 | struct its_cmd_block *, | |
d011e4e6 MZ |
285 | struct its_cmd_desc *); |
286 | ||
4d36f136 MZ |
287 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
288 | { | |
289 | u64 mask = GENMASK_ULL(h, l); | |
290 | *raw_cmd &= ~mask; | |
291 | *raw_cmd |= (val << l) & mask; | |
292 | } | |
293 | ||
cc2d3216 MZ |
294 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
295 | { | |
4d36f136 | 296 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
297 | } |
298 | ||
299 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
300 | { | |
4d36f136 | 301 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
302 | } |
303 | ||
304 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
305 | { | |
4d36f136 | 306 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
307 | } |
308 | ||
309 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
310 | { | |
4d36f136 | 311 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
312 | } |
313 | ||
314 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
315 | { | |
4d36f136 | 316 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
317 | } |
318 | ||
319 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
320 | { | |
4d36f136 | 321 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); |
cc2d3216 MZ |
322 | } |
323 | ||
324 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
325 | { | |
4d36f136 | 326 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
327 | } |
328 | ||
329 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
330 | { | |
4d36f136 | 331 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); |
cc2d3216 MZ |
332 | } |
333 | ||
334 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
335 | { | |
4d36f136 | 336 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
337 | } |
338 | ||
d011e4e6 MZ |
339 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
340 | { | |
341 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
342 | } | |
343 | ||
344 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
345 | { | |
346 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
347 | } | |
348 | ||
349 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
350 | { | |
351 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
352 | } | |
353 | ||
354 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
355 | { | |
356 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
357 | } | |
358 | ||
3171a47a MZ |
359 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
360 | { | |
361 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
362 | } | |
363 | ||
364 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
365 | { | |
366 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
367 | } | |
368 | ||
eb78192b MZ |
369 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
370 | { | |
371 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 50, 16); | |
372 | } | |
373 | ||
374 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
375 | { | |
376 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
377 | } | |
378 | ||
cc2d3216 MZ |
379 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
380 | { | |
381 | /* Let's fixup BE commands */ | |
382 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
383 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
384 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
385 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
386 | } | |
387 | ||
67047f90 MZ |
388 | static struct its_collection *its_build_mapd_cmd(struct its_node *its, |
389 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
390 | struct its_cmd_desc *desc) |
391 | { | |
392 | unsigned long itt_addr; | |
c8481267 | 393 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
394 | |
395 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
396 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
397 | ||
398 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
399 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
400 | its_encode_size(cmd, size - 1); | |
401 | its_encode_itt(cmd, itt_addr); | |
402 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
403 | ||
404 | its_fixup_cmd(cmd); | |
405 | ||
591e5bec | 406 | return NULL; |
cc2d3216 MZ |
407 | } |
408 | ||
67047f90 MZ |
409 | static struct its_collection *its_build_mapc_cmd(struct its_node *its, |
410 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
411 | struct its_cmd_desc *desc) |
412 | { | |
413 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
414 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
415 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
416 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
417 | ||
418 | its_fixup_cmd(cmd); | |
419 | ||
420 | return desc->its_mapc_cmd.col; | |
421 | } | |
422 | ||
67047f90 MZ |
423 | static struct its_collection *its_build_mapti_cmd(struct its_node *its, |
424 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
425 | struct its_cmd_desc *desc) |
426 | { | |
591e5bec MZ |
427 | struct its_collection *col; |
428 | ||
6a25ad3a MZ |
429 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
430 | desc->its_mapti_cmd.event_id); | |
591e5bec | 431 | |
6a25ad3a MZ |
432 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
433 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
434 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
435 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 436 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
437 | |
438 | its_fixup_cmd(cmd); | |
439 | ||
591e5bec | 440 | return col; |
cc2d3216 MZ |
441 | } |
442 | ||
67047f90 MZ |
443 | static struct its_collection *its_build_movi_cmd(struct its_node *its, |
444 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
445 | struct its_cmd_desc *desc) |
446 | { | |
591e5bec MZ |
447 | struct its_collection *col; |
448 | ||
449 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
450 | desc->its_movi_cmd.event_id); | |
451 | ||
cc2d3216 MZ |
452 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
453 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 454 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
455 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
456 | ||
457 | its_fixup_cmd(cmd); | |
458 | ||
591e5bec | 459 | return col; |
cc2d3216 MZ |
460 | } |
461 | ||
67047f90 MZ |
462 | static struct its_collection *its_build_discard_cmd(struct its_node *its, |
463 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
464 | struct its_cmd_desc *desc) |
465 | { | |
591e5bec MZ |
466 | struct its_collection *col; |
467 | ||
468 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
469 | desc->its_discard_cmd.event_id); | |
470 | ||
cc2d3216 MZ |
471 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
472 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
473 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
474 | ||
475 | its_fixup_cmd(cmd); | |
476 | ||
591e5bec | 477 | return col; |
cc2d3216 MZ |
478 | } |
479 | ||
67047f90 MZ |
480 | static struct its_collection *its_build_inv_cmd(struct its_node *its, |
481 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
482 | struct its_cmd_desc *desc) |
483 | { | |
591e5bec MZ |
484 | struct its_collection *col; |
485 | ||
486 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
487 | desc->its_inv_cmd.event_id); | |
488 | ||
cc2d3216 MZ |
489 | its_encode_cmd(cmd, GITS_CMD_INV); |
490 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
491 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
492 | ||
493 | its_fixup_cmd(cmd); | |
494 | ||
591e5bec | 495 | return col; |
cc2d3216 MZ |
496 | } |
497 | ||
67047f90 MZ |
498 | static struct its_collection *its_build_int_cmd(struct its_node *its, |
499 | struct its_cmd_block *cmd, | |
8d85dced MZ |
500 | struct its_cmd_desc *desc) |
501 | { | |
502 | struct its_collection *col; | |
503 | ||
504 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
505 | desc->its_int_cmd.event_id); | |
506 | ||
507 | its_encode_cmd(cmd, GITS_CMD_INT); | |
508 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
509 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
510 | ||
511 | its_fixup_cmd(cmd); | |
512 | ||
513 | return col; | |
514 | } | |
515 | ||
67047f90 MZ |
516 | static struct its_collection *its_build_clear_cmd(struct its_node *its, |
517 | struct its_cmd_block *cmd, | |
8d85dced MZ |
518 | struct its_cmd_desc *desc) |
519 | { | |
520 | struct its_collection *col; | |
521 | ||
522 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
523 | desc->its_clear_cmd.event_id); | |
524 | ||
525 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
526 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
527 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
528 | ||
529 | its_fixup_cmd(cmd); | |
530 | ||
531 | return col; | |
532 | } | |
533 | ||
67047f90 MZ |
534 | static struct its_collection *its_build_invall_cmd(struct its_node *its, |
535 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
536 | struct its_cmd_desc *desc) |
537 | { | |
538 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
539 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
540 | ||
541 | its_fixup_cmd(cmd); | |
542 | ||
543 | return NULL; | |
544 | } | |
545 | ||
67047f90 MZ |
546 | static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, |
547 | struct its_cmd_block *cmd, | |
eb78192b MZ |
548 | struct its_cmd_desc *desc) |
549 | { | |
550 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
551 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
552 | ||
553 | its_fixup_cmd(cmd); | |
554 | ||
555 | return desc->its_vinvall_cmd.vpe; | |
556 | } | |
557 | ||
67047f90 MZ |
558 | static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, |
559 | struct its_cmd_block *cmd, | |
eb78192b MZ |
560 | struct its_cmd_desc *desc) |
561 | { | |
562 | unsigned long vpt_addr; | |
5c9a882e | 563 | u64 target; |
eb78192b MZ |
564 | |
565 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
5c9a882e | 566 | target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; |
eb78192b MZ |
567 | |
568 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
569 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
570 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
5c9a882e | 571 | its_encode_target(cmd, target); |
eb78192b MZ |
572 | its_encode_vpt_addr(cmd, vpt_addr); |
573 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
574 | ||
575 | its_fixup_cmd(cmd); | |
576 | ||
577 | return desc->its_vmapp_cmd.vpe; | |
578 | } | |
579 | ||
67047f90 MZ |
580 | static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, |
581 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
582 | struct its_cmd_desc *desc) |
583 | { | |
584 | u32 db; | |
585 | ||
586 | if (desc->its_vmapti_cmd.db_enabled) | |
587 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; | |
588 | else | |
589 | db = 1023; | |
590 | ||
591 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
592 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
593 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
594 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
595 | its_encode_db_phys_id(cmd, db); | |
596 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
597 | ||
598 | its_fixup_cmd(cmd); | |
599 | ||
600 | return desc->its_vmapti_cmd.vpe; | |
601 | } | |
602 | ||
67047f90 MZ |
603 | static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, |
604 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
605 | struct its_cmd_desc *desc) |
606 | { | |
607 | u32 db; | |
608 | ||
609 | if (desc->its_vmovi_cmd.db_enabled) | |
610 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; | |
611 | else | |
612 | db = 1023; | |
613 | ||
614 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
615 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
616 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
617 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
618 | its_encode_db_phys_id(cmd, db); | |
619 | its_encode_db_valid(cmd, true); | |
620 | ||
621 | its_fixup_cmd(cmd); | |
622 | ||
623 | return desc->its_vmovi_cmd.vpe; | |
624 | } | |
625 | ||
67047f90 MZ |
626 | static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, |
627 | struct its_cmd_block *cmd, | |
3171a47a MZ |
628 | struct its_cmd_desc *desc) |
629 | { | |
5c9a882e MZ |
630 | u64 target; |
631 | ||
632 | target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; | |
3171a47a MZ |
633 | its_encode_cmd(cmd, GITS_CMD_VMOVP); |
634 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
635 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
636 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
5c9a882e | 637 | its_encode_target(cmd, target); |
3171a47a MZ |
638 | |
639 | its_fixup_cmd(cmd); | |
640 | ||
641 | return desc->its_vmovp_cmd.vpe; | |
642 | } | |
643 | ||
cc2d3216 MZ |
644 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
645 | struct its_cmd_block *ptr) | |
646 | { | |
647 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
648 | } | |
649 | ||
650 | static int its_queue_full(struct its_node *its) | |
651 | { | |
652 | int widx; | |
653 | int ridx; | |
654 | ||
655 | widx = its->cmd_write - its->cmd_base; | |
656 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
657 | ||
658 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
659 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
660 | return 1; | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
666 | { | |
667 | struct its_cmd_block *cmd; | |
668 | u32 count = 1000000; /* 1s! */ | |
669 | ||
670 | while (its_queue_full(its)) { | |
671 | count--; | |
672 | if (!count) { | |
673 | pr_err_ratelimited("ITS queue not draining\n"); | |
674 | return NULL; | |
675 | } | |
676 | cpu_relax(); | |
677 | udelay(1); | |
678 | } | |
679 | ||
680 | cmd = its->cmd_write++; | |
681 | ||
682 | /* Handle queue wrapping */ | |
683 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
684 | its->cmd_write = its->cmd_base; | |
685 | ||
34d677a9 MZ |
686 | /* Clear command */ |
687 | cmd->raw_cmd[0] = 0; | |
688 | cmd->raw_cmd[1] = 0; | |
689 | cmd->raw_cmd[2] = 0; | |
690 | cmd->raw_cmd[3] = 0; | |
691 | ||
cc2d3216 MZ |
692 | return cmd; |
693 | } | |
694 | ||
695 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
696 | { | |
697 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
698 | ||
699 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
700 | ||
701 | return its->cmd_write; | |
702 | } | |
703 | ||
704 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
705 | { | |
706 | /* | |
707 | * Make sure the commands written to memory are observable by | |
708 | * the ITS. | |
709 | */ | |
710 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 711 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
712 | else |
713 | dsb(ishst); | |
714 | } | |
715 | ||
a19b462f MZ |
716 | static int its_wait_for_range_completion(struct its_node *its, |
717 | struct its_cmd_block *from, | |
718 | struct its_cmd_block *to) | |
cc2d3216 MZ |
719 | { |
720 | u64 rd_idx, from_idx, to_idx; | |
721 | u32 count = 1000000; /* 1s! */ | |
722 | ||
723 | from_idx = its_cmd_ptr_to_offset(its, from); | |
724 | to_idx = its_cmd_ptr_to_offset(its, to); | |
725 | ||
726 | while (1) { | |
727 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
9bdd8b1c MZ |
728 | |
729 | /* Direct case */ | |
730 | if (from_idx < to_idx && rd_idx >= to_idx) | |
731 | break; | |
732 | ||
733 | /* Wrapped case */ | |
734 | if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx) | |
cc2d3216 MZ |
735 | break; |
736 | ||
737 | count--; | |
738 | if (!count) { | |
a19b462f MZ |
739 | pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n", |
740 | from_idx, to_idx, rd_idx); | |
741 | return -1; | |
cc2d3216 MZ |
742 | } |
743 | cpu_relax(); | |
744 | udelay(1); | |
745 | } | |
a19b462f MZ |
746 | |
747 | return 0; | |
cc2d3216 MZ |
748 | } |
749 | ||
e4f9094b MZ |
750 | /* Warning, macro hell follows */ |
751 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
752 | void name(struct its_node *its, \ | |
753 | buildtype builder, \ | |
754 | struct its_cmd_desc *desc) \ | |
755 | { \ | |
756 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
757 | synctype *sync_obj; \ | |
758 | unsigned long flags; \ | |
759 | \ | |
760 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
761 | \ | |
762 | cmd = its_allocate_entry(its); \ | |
763 | if (!cmd) { /* We're soooooo screewed... */ \ | |
764 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
765 | return; \ | |
766 | } \ | |
67047f90 | 767 | sync_obj = builder(its, cmd, desc); \ |
e4f9094b MZ |
768 | its_flush_cmd(its, cmd); \ |
769 | \ | |
770 | if (sync_obj) { \ | |
771 | sync_cmd = its_allocate_entry(its); \ | |
772 | if (!sync_cmd) \ | |
773 | goto post; \ | |
774 | \ | |
67047f90 | 775 | buildfn(its, sync_cmd, sync_obj); \ |
e4f9094b MZ |
776 | its_flush_cmd(its, sync_cmd); \ |
777 | } \ | |
778 | \ | |
779 | post: \ | |
780 | next_cmd = its_post_commands(its); \ | |
781 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
782 | \ | |
a19b462f MZ |
783 | if (its_wait_for_range_completion(its, cmd, next_cmd)) \ |
784 | pr_err_ratelimited("ITS cmd %ps failed\n", builder); \ | |
e4f9094b | 785 | } |
cc2d3216 | 786 | |
67047f90 MZ |
787 | static void its_build_sync_cmd(struct its_node *its, |
788 | struct its_cmd_block *sync_cmd, | |
e4f9094b MZ |
789 | struct its_collection *sync_col) |
790 | { | |
791 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
792 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 793 | |
e4f9094b | 794 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
795 | } |
796 | ||
e4f9094b MZ |
797 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
798 | struct its_collection, its_build_sync_cmd) | |
799 | ||
67047f90 MZ |
800 | static void its_build_vsync_cmd(struct its_node *its, |
801 | struct its_cmd_block *sync_cmd, | |
d011e4e6 MZ |
802 | struct its_vpe *sync_vpe) |
803 | { | |
804 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
805 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
806 | ||
807 | its_fixup_cmd(sync_cmd); | |
808 | } | |
809 | ||
810 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
811 | struct its_vpe, its_build_vsync_cmd) | |
812 | ||
8d85dced | 813 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 814 | { |
8d85dced | 815 | struct its_cmd_desc desc; |
cc2d3216 | 816 | |
8d85dced MZ |
817 | desc.its_int_cmd.dev = dev; |
818 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 819 | |
8d85dced MZ |
820 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
821 | } | |
cc2d3216 | 822 | |
8d85dced MZ |
823 | static void its_send_clear(struct its_device *dev, u32 event_id) |
824 | { | |
825 | struct its_cmd_desc desc; | |
cc2d3216 | 826 | |
8d85dced MZ |
827 | desc.its_clear_cmd.dev = dev; |
828 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 829 | |
8d85dced | 830 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
831 | } |
832 | ||
833 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
834 | { | |
835 | struct its_cmd_desc desc; | |
836 | ||
837 | desc.its_inv_cmd.dev = dev; | |
838 | desc.its_inv_cmd.event_id = event_id; | |
839 | ||
840 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
841 | } | |
842 | ||
843 | static void its_send_mapd(struct its_device *dev, int valid) | |
844 | { | |
845 | struct its_cmd_desc desc; | |
846 | ||
847 | desc.its_mapd_cmd.dev = dev; | |
848 | desc.its_mapd_cmd.valid = !!valid; | |
849 | ||
850 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
851 | } | |
852 | ||
853 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
854 | int valid) | |
855 | { | |
856 | struct its_cmd_desc desc; | |
857 | ||
858 | desc.its_mapc_cmd.col = col; | |
859 | desc.its_mapc_cmd.valid = !!valid; | |
860 | ||
861 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
862 | } | |
863 | ||
6a25ad3a | 864 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
865 | { |
866 | struct its_cmd_desc desc; | |
867 | ||
6a25ad3a MZ |
868 | desc.its_mapti_cmd.dev = dev; |
869 | desc.its_mapti_cmd.phys_id = irq_id; | |
870 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 871 | |
6a25ad3a | 872 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
873 | } |
874 | ||
875 | static void its_send_movi(struct its_device *dev, | |
876 | struct its_collection *col, u32 id) | |
877 | { | |
878 | struct its_cmd_desc desc; | |
879 | ||
880 | desc.its_movi_cmd.dev = dev; | |
881 | desc.its_movi_cmd.col = col; | |
591e5bec | 882 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
883 | |
884 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
885 | } | |
886 | ||
887 | static void its_send_discard(struct its_device *dev, u32 id) | |
888 | { | |
889 | struct its_cmd_desc desc; | |
890 | ||
891 | desc.its_discard_cmd.dev = dev; | |
892 | desc.its_discard_cmd.event_id = id; | |
893 | ||
894 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
895 | } | |
896 | ||
897 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
898 | { | |
899 | struct its_cmd_desc desc; | |
900 | ||
901 | desc.its_invall_cmd.col = col; | |
902 | ||
903 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
904 | } | |
c48ed51c | 905 | |
d011e4e6 MZ |
906 | static void its_send_vmapti(struct its_device *dev, u32 id) |
907 | { | |
908 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
909 | struct its_cmd_desc desc; | |
910 | ||
911 | desc.its_vmapti_cmd.vpe = map->vpe; | |
912 | desc.its_vmapti_cmd.dev = dev; | |
913 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
914 | desc.its_vmapti_cmd.event_id = id; | |
915 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
916 | ||
917 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
918 | } | |
919 | ||
920 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
921 | { | |
922 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
923 | struct its_cmd_desc desc; | |
924 | ||
925 | desc.its_vmovi_cmd.vpe = map->vpe; | |
926 | desc.its_vmovi_cmd.dev = dev; | |
927 | desc.its_vmovi_cmd.event_id = id; | |
928 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
929 | ||
930 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
931 | } | |
932 | ||
eb78192b MZ |
933 | static void its_send_vmapp(struct its_vpe *vpe, bool valid) |
934 | { | |
935 | struct its_cmd_desc desc; | |
936 | struct its_node *its; | |
937 | ||
938 | desc.its_vmapp_cmd.vpe = vpe; | |
939 | desc.its_vmapp_cmd.valid = valid; | |
940 | ||
941 | list_for_each_entry(its, &its_nodes, entry) { | |
942 | if (!its->is_v4) | |
943 | continue; | |
944 | ||
945 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; | |
946 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); | |
947 | } | |
948 | } | |
949 | ||
3171a47a MZ |
950 | static void its_send_vmovp(struct its_vpe *vpe) |
951 | { | |
952 | struct its_cmd_desc desc; | |
953 | struct its_node *its; | |
954 | unsigned long flags; | |
955 | int col_id = vpe->col_idx; | |
956 | ||
957 | desc.its_vmovp_cmd.vpe = vpe; | |
958 | desc.its_vmovp_cmd.its_list = (u16)its_list_map; | |
959 | ||
960 | if (!its_list_map) { | |
961 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
962 | desc.its_vmovp_cmd.seq_num = 0; | |
963 | desc.its_vmovp_cmd.col = &its->collections[col_id]; | |
964 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
965 | return; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Yet another marvel of the architecture. If using the | |
970 | * its_list "feature", we need to make sure that all ITSs | |
971 | * receive all VMOVP commands in the same order. The only way | |
972 | * to guarantee this is to make vmovp a serialization point. | |
973 | * | |
974 | * Wall <-- Head. | |
975 | */ | |
976 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
977 | ||
978 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
979 | ||
980 | /* Emit VMOVPs */ | |
981 | list_for_each_entry(its, &its_nodes, entry) { | |
982 | if (!its->is_v4) | |
983 | continue; | |
984 | ||
985 | desc.its_vmovp_cmd.col = &its->collections[col_id]; | |
986 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
987 | } | |
988 | ||
989 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
990 | } | |
991 | ||
eb78192b MZ |
992 | static void its_send_vinvall(struct its_vpe *vpe) |
993 | { | |
994 | struct its_cmd_desc desc; | |
995 | struct its_node *its; | |
996 | ||
997 | desc.its_vinvall_cmd.vpe = vpe; | |
998 | ||
999 | list_for_each_entry(its, &its_nodes, entry) { | |
1000 | if (!its->is_v4) | |
1001 | continue; | |
1002 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); | |
1003 | } | |
1004 | } | |
1005 | ||
c48ed51c MZ |
1006 | /* |
1007 | * irqchip functions - assumes MSI, mostly. | |
1008 | */ | |
1009 | ||
1010 | static inline u32 its_get_event_id(struct irq_data *d) | |
1011 | { | |
1012 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 1013 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
1014 | } |
1015 | ||
015ec038 | 1016 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 1017 | { |
015ec038 | 1018 | irq_hw_number_t hwirq; |
adcdb94e MZ |
1019 | struct page *prop_page; |
1020 | u8 *cfg; | |
c48ed51c | 1021 | |
015ec038 MZ |
1022 | if (irqd_is_forwarded_to_vcpu(d)) { |
1023 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1024 | u32 event = its_get_event_id(d); | |
1025 | ||
1026 | prop_page = its_dev->event_map.vm->vprop_page; | |
1027 | hwirq = its_dev->event_map.vlpi_maps[event].vintid; | |
1028 | } else { | |
1029 | prop_page = gic_rdists->prop_page; | |
1030 | hwirq = d->hwirq; | |
1031 | } | |
adcdb94e MZ |
1032 | |
1033 | cfg = page_address(prop_page) + hwirq - 8192; | |
1034 | *cfg &= ~clr; | |
015ec038 | 1035 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1036 | |
1037 | /* | |
1038 | * Make the above write visible to the redistributors. | |
1039 | * And yes, we're flushing exactly: One. Single. Byte. | |
1040 | * Humpf... | |
1041 | */ | |
1042 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1043 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1044 | else |
1045 | dsb(ishst); | |
015ec038 MZ |
1046 | } |
1047 | ||
1048 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) | |
1049 | { | |
1050 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1051 | ||
1052 | lpi_write_config(d, clr, set); | |
adcdb94e | 1053 | its_send_inv(its_dev, its_get_event_id(d)); |
c48ed51c MZ |
1054 | } |
1055 | ||
015ec038 MZ |
1056 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1057 | { | |
1058 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1059 | u32 event = its_get_event_id(d); | |
1060 | ||
1061 | if (its_dev->event_map.vlpi_maps[event].db_enabled == enable) | |
1062 | return; | |
1063 | ||
1064 | its_dev->event_map.vlpi_maps[event].db_enabled = enable; | |
1065 | ||
1066 | /* | |
1067 | * More fun with the architecture: | |
1068 | * | |
1069 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1070 | * value or to 1023, depending on the enable bit. But that | |
1071 | * would be issueing a mapping for an /existing/ DevID+EventID | |
1072 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
1073 | * to the /same/ vPE, using this opportunity to adjust the | |
1074 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1075 | */ | |
1076 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1077 | } |
1078 | ||
1079 | static void its_mask_irq(struct irq_data *d) | |
1080 | { | |
015ec038 MZ |
1081 | if (irqd_is_forwarded_to_vcpu(d)) |
1082 | its_vlpi_set_doorbell(d, false); | |
1083 | ||
adcdb94e | 1084 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1085 | } |
1086 | ||
1087 | static void its_unmask_irq(struct irq_data *d) | |
1088 | { | |
015ec038 MZ |
1089 | if (irqd_is_forwarded_to_vcpu(d)) |
1090 | its_vlpi_set_doorbell(d, true); | |
1091 | ||
adcdb94e | 1092 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1093 | } |
1094 | ||
c48ed51c MZ |
1095 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1096 | bool force) | |
1097 | { | |
fbf8f40e GK |
1098 | unsigned int cpu; |
1099 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
1100 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1101 | struct its_collection *target_col; | |
1102 | u32 id = its_get_event_id(d); | |
1103 | ||
015ec038 MZ |
1104 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1105 | if (irqd_is_forwarded_to_vcpu(d)) | |
1106 | return -EINVAL; | |
1107 | ||
fbf8f40e GK |
1108 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
1109 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1110 | if (its_dev->its->numa_node >= 0) { | |
1111 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
1112 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
1113 | return -EINVAL; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
1118 | ||
c48ed51c MZ |
1119 | if (cpu >= nr_cpu_ids) |
1120 | return -EINVAL; | |
1121 | ||
8b8d94a7 M |
1122 | /* don't set the affinity when the target cpu is same as current one */ |
1123 | if (cpu != its_dev->event_map.col_map[id]) { | |
1124 | target_col = &its_dev->its->collections[cpu]; | |
1125 | its_send_movi(its_dev, target_col, id); | |
1126 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1127 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1128 | } |
c48ed51c MZ |
1129 | |
1130 | return IRQ_SET_MASK_OK_DONE; | |
1131 | } | |
1132 | ||
558b0165 AB |
1133 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1134 | { | |
1135 | struct its_node *its = its_dev->its; | |
1136 | ||
1137 | return its->phys_base + GITS_TRANSLATER; | |
1138 | } | |
1139 | ||
b48ac83d MZ |
1140 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1141 | { | |
1142 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1143 | struct its_node *its; | |
1144 | u64 addr; | |
1145 | ||
1146 | its = its_dev->its; | |
558b0165 | 1147 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1148 | |
b11283eb VM |
1149 | msg->address_lo = lower_32_bits(addr); |
1150 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1151 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
1152 | |
1153 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
1154 | } |
1155 | ||
8d85dced MZ |
1156 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1157 | enum irqchip_irq_state which, | |
1158 | bool state) | |
1159 | { | |
1160 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1161 | u32 event = its_get_event_id(d); | |
1162 | ||
1163 | if (which != IRQCHIP_STATE_PENDING) | |
1164 | return -EINVAL; | |
1165 | ||
1166 | if (state) | |
1167 | its_send_int(its_dev, event); | |
1168 | else | |
1169 | its_send_clear(its_dev, event); | |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
d011e4e6 MZ |
1174 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1175 | { | |
1176 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1177 | u32 event = its_get_event_id(d); | |
1178 | int ret = 0; | |
1179 | ||
1180 | if (!info->map) | |
1181 | return -EINVAL; | |
1182 | ||
1183 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1184 | ||
1185 | if (!its_dev->event_map.vm) { | |
1186 | struct its_vlpi_map *maps; | |
1187 | ||
1188 | maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis, | |
1189 | GFP_KERNEL); | |
1190 | if (!maps) { | |
1191 | ret = -ENOMEM; | |
1192 | goto out; | |
1193 | } | |
1194 | ||
1195 | its_dev->event_map.vm = info->map->vm; | |
1196 | its_dev->event_map.vlpi_maps = maps; | |
1197 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1198 | ret = -EINVAL; | |
1199 | goto out; | |
1200 | } | |
1201 | ||
1202 | /* Get our private copy of the mapping information */ | |
1203 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1204 | ||
1205 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1206 | /* Already mapped, move it around */ | |
1207 | its_send_vmovi(its_dev, event); | |
1208 | } else { | |
1209 | /* Drop the physical mapping */ | |
1210 | its_send_discard(its_dev, event); | |
1211 | ||
1212 | /* and install the virtual one */ | |
1213 | its_send_vmapti(its_dev, event); | |
1214 | irqd_set_forwarded_to_vcpu(d); | |
1215 | ||
1216 | /* Increment the number of VLPIs */ | |
1217 | its_dev->event_map.nr_vlpis++; | |
1218 | } | |
1219 | ||
1220 | out: | |
1221 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1222 | return ret; | |
1223 | } | |
1224 | ||
1225 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1226 | { | |
1227 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1228 | u32 event = its_get_event_id(d); | |
1229 | int ret = 0; | |
1230 | ||
1231 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1232 | ||
1233 | if (!its_dev->event_map.vm || | |
1234 | !its_dev->event_map.vlpi_maps[event].vm) { | |
1235 | ret = -EINVAL; | |
1236 | goto out; | |
1237 | } | |
1238 | ||
1239 | /* Copy our mapping information to the incoming request */ | |
1240 | *info->map = its_dev->event_map.vlpi_maps[event]; | |
1241 | ||
1242 | out: | |
1243 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1244 | return ret; | |
1245 | } | |
1246 | ||
1247 | static int its_vlpi_unmap(struct irq_data *d) | |
1248 | { | |
1249 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1250 | u32 event = its_get_event_id(d); | |
1251 | int ret = 0; | |
1252 | ||
1253 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1254 | ||
1255 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1256 | ret = -EINVAL; | |
1257 | goto out; | |
1258 | } | |
1259 | ||
1260 | /* Drop the virtual mapping */ | |
1261 | its_send_discard(its_dev, event); | |
1262 | ||
1263 | /* and restore the physical one */ | |
1264 | irqd_clr_forwarded_to_vcpu(d); | |
1265 | its_send_mapti(its_dev, d->hwirq, event); | |
1266 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1267 | LPI_PROP_ENABLED | | |
1268 | LPI_PROP_GROUP1)); | |
1269 | ||
1270 | /* | |
1271 | * Drop the refcount and make the device available again if | |
1272 | * this was the last VLPI. | |
1273 | */ | |
1274 | if (!--its_dev->event_map.nr_vlpis) { | |
1275 | its_dev->event_map.vm = NULL; | |
1276 | kfree(its_dev->event_map.vlpi_maps); | |
1277 | } | |
1278 | ||
1279 | out: | |
1280 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1281 | return ret; | |
1282 | } | |
1283 | ||
015ec038 MZ |
1284 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1285 | { | |
1286 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1287 | ||
1288 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1289 | return -EINVAL; | |
1290 | ||
1291 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1292 | lpi_update_config(d, 0xff, info->config); | |
1293 | else | |
1294 | lpi_write_config(d, 0xff, info->config); | |
1295 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
c808eea8 MZ |
1300 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1301 | { | |
1302 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1303 | struct its_cmd_info *info = vcpu_info; | |
1304 | ||
1305 | /* Need a v4 ITS */ | |
d011e4e6 | 1306 | if (!its_dev->its->is_v4) |
c808eea8 MZ |
1307 | return -EINVAL; |
1308 | ||
d011e4e6 MZ |
1309 | /* Unmap request? */ |
1310 | if (!info) | |
1311 | return its_vlpi_unmap(d); | |
1312 | ||
c808eea8 MZ |
1313 | switch (info->cmd_type) { |
1314 | case MAP_VLPI: | |
d011e4e6 | 1315 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1316 | |
1317 | case GET_VLPI: | |
d011e4e6 | 1318 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1319 | |
1320 | case PROP_UPDATE_VLPI: | |
1321 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1322 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1323 | |
1324 | default: | |
1325 | return -EINVAL; | |
1326 | } | |
1327 | } | |
1328 | ||
c48ed51c MZ |
1329 | static struct irq_chip its_irq_chip = { |
1330 | .name = "ITS", | |
1331 | .irq_mask = its_mask_irq, | |
1332 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1333 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1334 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1335 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1336 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1337 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1338 | }; |
1339 | ||
bf9529f8 MZ |
1340 | /* |
1341 | * How we allocate LPIs: | |
1342 | * | |
1343 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
1344 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
1345 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
1346 | * bits to the right. | |
1347 | * | |
1348 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
1349 | */ | |
1350 | #define IRQS_PER_CHUNK_SHIFT 5 | |
1351 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
6c31e123 | 1352 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
bf9529f8 MZ |
1353 | |
1354 | static unsigned long *lpi_bitmap; | |
1355 | static u32 lpi_chunks; | |
1356 | static DEFINE_SPINLOCK(lpi_lock); | |
1357 | ||
1358 | static int its_lpi_to_chunk(int lpi) | |
1359 | { | |
1360 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
1361 | } | |
1362 | ||
1363 | static int its_chunk_to_lpi(int chunk) | |
1364 | { | |
1365 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
1366 | } | |
1367 | ||
04a0e4de | 1368 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
1369 | { |
1370 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
1371 | ||
1372 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
1373 | GFP_KERNEL); | |
1374 | if (!lpi_bitmap) { | |
1375 | lpi_chunks = 0; | |
1376 | return -ENOMEM; | |
1377 | } | |
1378 | ||
1379 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
1384 | { | |
1385 | unsigned long *bitmap = NULL; | |
1386 | int chunk_id; | |
1387 | int nr_chunks; | |
1388 | int i; | |
1389 | ||
1390 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
1391 | ||
1392 | spin_lock(&lpi_lock); | |
1393 | ||
1394 | do { | |
1395 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
1396 | 0, nr_chunks, 0); | |
1397 | if (chunk_id < lpi_chunks) | |
1398 | break; | |
1399 | ||
1400 | nr_chunks--; | |
1401 | } while (nr_chunks > 0); | |
1402 | ||
1403 | if (!nr_chunks) | |
1404 | goto out; | |
1405 | ||
1406 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
1407 | GFP_ATOMIC); | |
1408 | if (!bitmap) | |
1409 | goto out; | |
1410 | ||
1411 | for (i = 0; i < nr_chunks; i++) | |
1412 | set_bit(chunk_id + i, lpi_bitmap); | |
1413 | ||
1414 | *base = its_chunk_to_lpi(chunk_id); | |
1415 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
1416 | ||
1417 | out: | |
1418 | spin_unlock(&lpi_lock); | |
1419 | ||
c8415b94 MZ |
1420 | if (!bitmap) |
1421 | *base = *nr_ids = 0; | |
1422 | ||
bf9529f8 MZ |
1423 | return bitmap; |
1424 | } | |
1425 | ||
cf2be8ba | 1426 | static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids) |
bf9529f8 MZ |
1427 | { |
1428 | int lpi; | |
1429 | ||
1430 | spin_lock(&lpi_lock); | |
1431 | ||
1432 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
1433 | int chunk = its_lpi_to_chunk(lpi); | |
cf2be8ba | 1434 | |
bf9529f8 MZ |
1435 | BUG_ON(chunk > lpi_chunks); |
1436 | if (test_bit(chunk, lpi_bitmap)) { | |
1437 | clear_bit(chunk, lpi_bitmap); | |
1438 | } else { | |
1439 | pr_err("Bad LPI chunk %d\n", chunk); | |
1440 | } | |
1441 | } | |
1442 | ||
1443 | spin_unlock(&lpi_lock); | |
1444 | ||
cf2be8ba | 1445 | kfree(bitmap); |
bf9529f8 | 1446 | } |
1ac19ca6 | 1447 | |
0e5ccf91 MZ |
1448 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
1449 | { | |
1450 | struct page *prop_page; | |
1ac19ca6 | 1451 | |
0e5ccf91 MZ |
1452 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
1453 | if (!prop_page) | |
1454 | return NULL; | |
1455 | ||
1456 | /* Priority 0xa0, Group-1, disabled */ | |
1457 | memset(page_address(prop_page), | |
1458 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
1459 | LPI_PROPBASE_SZ); | |
1460 | ||
1461 | /* Make sure the GIC will observe the written configuration */ | |
1462 | gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ); | |
1463 | ||
1464 | return prop_page; | |
1465 | } | |
1466 | ||
7d75bbb4 MZ |
1467 | static void its_free_prop_table(struct page *prop_page) |
1468 | { | |
1469 | free_pages((unsigned long)page_address(prop_page), | |
1470 | get_order(LPI_PROPBASE_SZ)); | |
1471 | } | |
1ac19ca6 MZ |
1472 | |
1473 | static int __init its_alloc_lpi_tables(void) | |
1474 | { | |
1475 | phys_addr_t paddr; | |
1476 | ||
6c31e123 | 1477 | lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS); |
0e5ccf91 | 1478 | gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT); |
1ac19ca6 MZ |
1479 | if (!gic_rdists->prop_page) { |
1480 | pr_err("Failed to allocate PROPBASE\n"); | |
1481 | return -ENOMEM; | |
1482 | } | |
1483 | ||
1484 | paddr = page_to_phys(gic_rdists->prop_page); | |
1485 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
1486 | ||
6c31e123 | 1487 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
1488 | } |
1489 | ||
1490 | static const char *its_base_type_string[] = { | |
1491 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
1492 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 1493 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
1494 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
1495 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
1496 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
1497 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
1498 | }; | |
1499 | ||
2d81d425 SD |
1500 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
1501 | { | |
1502 | u32 idx = baser - its->tables; | |
1503 | ||
0968a619 | 1504 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1505 | } |
1506 | ||
1507 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
1508 | u64 val) | |
1509 | { | |
1510 | u32 idx = baser - its->tables; | |
1511 | ||
0968a619 | 1512 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1513 | baser->val = its_read_baser(its, baser); |
1514 | } | |
1515 | ||
9347359a | 1516 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
1517 | u64 cache, u64 shr, u32 psz, u32 order, |
1518 | bool indirect) | |
9347359a SD |
1519 | { |
1520 | u64 val = its_read_baser(its, baser); | |
1521 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
1522 | u64 type = GITS_BASER_TYPE(val); | |
1523 | u32 alloc_pages; | |
1524 | void *base; | |
1525 | u64 tmp; | |
1526 | ||
1527 | retry_alloc_baser: | |
1528 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
1529 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
1530 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
1531 | &its->phys_base, its_base_type_string[type], | |
1532 | alloc_pages, GITS_BASER_PAGES_MAX); | |
1533 | alloc_pages = GITS_BASER_PAGES_MAX; | |
1534 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
1535 | } | |
1536 | ||
1537 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
1538 | if (!base) | |
1539 | return -ENOMEM; | |
1540 | ||
1541 | retry_baser: | |
1542 | val = (virt_to_phys(base) | | |
1543 | (type << GITS_BASER_TYPE_SHIFT) | | |
1544 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
1545 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
1546 | cache | | |
1547 | shr | | |
1548 | GITS_BASER_VALID); | |
1549 | ||
3faf24ea SD |
1550 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
1551 | ||
9347359a SD |
1552 | switch (psz) { |
1553 | case SZ_4K: | |
1554 | val |= GITS_BASER_PAGE_SIZE_4K; | |
1555 | break; | |
1556 | case SZ_16K: | |
1557 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1558 | break; | |
1559 | case SZ_64K: | |
1560 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1561 | break; | |
1562 | } | |
1563 | ||
1564 | its_write_baser(its, baser, val); | |
1565 | tmp = baser->val; | |
1566 | ||
1567 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1568 | /* | |
1569 | * Shareability didn't stick. Just use | |
1570 | * whatever the read reported, which is likely | |
1571 | * to be the only thing this redistributor | |
1572 | * supports. If that's zero, make it | |
1573 | * non-cacheable as well. | |
1574 | */ | |
1575 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
1576 | if (!shr) { | |
1577 | cache = GITS_BASER_nC; | |
328191c0 | 1578 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
1579 | } |
1580 | goto retry_baser; | |
1581 | } | |
1582 | ||
1583 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
1584 | /* | |
1585 | * Page size didn't stick. Let's try a smaller | |
1586 | * size and retry. If we reach 4K, then | |
1587 | * something is horribly wrong... | |
1588 | */ | |
1589 | free_pages((unsigned long)base, order); | |
1590 | baser->base = NULL; | |
1591 | ||
1592 | switch (psz) { | |
1593 | case SZ_16K: | |
1594 | psz = SZ_4K; | |
1595 | goto retry_alloc_baser; | |
1596 | case SZ_64K: | |
1597 | psz = SZ_16K; | |
1598 | goto retry_alloc_baser; | |
1599 | } | |
1600 | } | |
1601 | ||
1602 | if (val != tmp) { | |
b11283eb | 1603 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 1604 | &its->phys_base, its_base_type_string[type], |
b11283eb | 1605 | val, tmp); |
9347359a SD |
1606 | free_pages((unsigned long)base, order); |
1607 | return -ENXIO; | |
1608 | } | |
1609 | ||
1610 | baser->order = order; | |
1611 | baser->base = base; | |
1612 | baser->psz = psz; | |
3faf24ea | 1613 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 1614 | |
3faf24ea | 1615 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 1616 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
1617 | its_base_type_string[type], |
1618 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 1619 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
1620 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
4cacac57 MZ |
1625 | static bool its_parse_indirect_baser(struct its_node *its, |
1626 | struct its_baser *baser, | |
1627 | u32 psz, u32 *order) | |
4b75c459 | 1628 | { |
4cacac57 MZ |
1629 | u64 tmp = its_read_baser(its, baser); |
1630 | u64 type = GITS_BASER_TYPE(tmp); | |
1631 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 1632 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
1633 | u32 ids = its->device_ids; |
1634 | u32 new_order = *order; | |
3faf24ea SD |
1635 | bool indirect = false; |
1636 | ||
1637 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
1638 | if ((esz << ids) > (psz * 2)) { | |
1639 | /* | |
1640 | * Find out whether hw supports a single or two-level table by | |
1641 | * table by reading bit at offset '62' after writing '1' to it. | |
1642 | */ | |
1643 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
1644 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
1645 | ||
1646 | if (indirect) { | |
1647 | /* | |
1648 | * The size of the lvl2 table is equal to ITS page size | |
1649 | * which is 'psz'. For computing lvl1 table size, | |
1650 | * subtract ID bits that sparse lvl2 table from 'ids' | |
1651 | * which is reported by ITS hardware times lvl1 table | |
1652 | * entry size. | |
1653 | */ | |
d524eaa2 | 1654 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
1655 | esz = GITS_LVL1_ENTRY_SIZE; |
1656 | } | |
1657 | } | |
4b75c459 SD |
1658 | |
1659 | /* | |
1660 | * Allocate as many entries as required to fit the | |
1661 | * range of device IDs that the ITS can grok... The ID | |
1662 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1663 | * massive waste of memory if two-level device table |
1664 | * feature is not supported by hardware. | |
4b75c459 SD |
1665 | */ |
1666 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1667 | if (new_order >= MAX_ORDER) { | |
1668 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1669 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4cacac57 MZ |
1670 | pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n", |
1671 | &its->phys_base, its_base_type_string[type], | |
1672 | its->device_ids, ids); | |
4b75c459 SD |
1673 | } |
1674 | ||
1675 | *order = new_order; | |
3faf24ea SD |
1676 | |
1677 | return indirect; | |
4b75c459 SD |
1678 | } |
1679 | ||
1ac19ca6 MZ |
1680 | static void its_free_tables(struct its_node *its) |
1681 | { | |
1682 | int i; | |
1683 | ||
1684 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1685 | if (its->tables[i].base) { |
1686 | free_pages((unsigned long)its->tables[i].base, | |
1687 | its->tables[i].order); | |
1688 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1689 | } |
1690 | } | |
1691 | } | |
1692 | ||
0e0b0f69 | 1693 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1694 | { |
1ac19ca6 | 1695 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1696 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1697 | u32 psz = SZ_64K; |
1698 | int err, i; | |
94100970 | 1699 | |
fa150019 AB |
1700 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
1701 | /* erratum 24313: ignore memory access type */ | |
1702 | cache = GITS_BASER_nCnB; | |
466b7d16 | 1703 | |
1ac19ca6 | 1704 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1705 | struct its_baser *baser = its->tables + i; |
1706 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1707 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1708 | u32 order = get_order(psz); |
3faf24ea | 1709 | bool indirect = false; |
1ac19ca6 | 1710 | |
4cacac57 MZ |
1711 | switch (type) { |
1712 | case GITS_BASER_TYPE_NONE: | |
1ac19ca6 MZ |
1713 | continue; |
1714 | ||
4cacac57 MZ |
1715 | case GITS_BASER_TYPE_DEVICE: |
1716 | case GITS_BASER_TYPE_VCPU: | |
1717 | indirect = its_parse_indirect_baser(its, baser, | |
1718 | psz, &order); | |
1719 | break; | |
1720 | } | |
f54b97ed | 1721 | |
3faf24ea | 1722 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1723 | if (err < 0) { |
1724 | its_free_tables(its); | |
1725 | return err; | |
1ac19ca6 MZ |
1726 | } |
1727 | ||
9347359a SD |
1728 | /* Update settings which will be used for next BASERn */ |
1729 | psz = baser->psz; | |
1730 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1731 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1732 | } |
1733 | ||
1734 | return 0; | |
1ac19ca6 MZ |
1735 | } |
1736 | ||
1737 | static int its_alloc_collections(struct its_node *its) | |
1738 | { | |
1739 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1740 | GFP_KERNEL); | |
1741 | if (!its->collections) | |
1742 | return -ENOMEM; | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | ||
7c297a2d MZ |
1747 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
1748 | { | |
1749 | struct page *pend_page; | |
1750 | /* | |
1751 | * The pending pages have to be at least 64kB aligned, | |
1752 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1753 | */ | |
1754 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, | |
1755 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); | |
1756 | if (!pend_page) | |
1757 | return NULL; | |
1758 | ||
1759 | /* Make sure the GIC will observe the zero-ed page */ | |
1760 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
1761 | ||
1762 | return pend_page; | |
1763 | } | |
1764 | ||
7d75bbb4 MZ |
1765 | static void its_free_pending_table(struct page *pt) |
1766 | { | |
1767 | free_pages((unsigned long)page_address(pt), | |
1768 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); | |
1769 | } | |
1770 | ||
1ac19ca6 MZ |
1771 | static void its_cpu_init_lpis(void) |
1772 | { | |
1773 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1774 | struct page *pend_page; | |
1775 | u64 val, tmp; | |
1776 | ||
1777 | /* If we didn't allocate the pending table yet, do it now */ | |
1778 | pend_page = gic_data_rdist()->pend_page; | |
1779 | if (!pend_page) { | |
1780 | phys_addr_t paddr; | |
7c297a2d MZ |
1781 | |
1782 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 MZ |
1783 | if (!pend_page) { |
1784 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1785 | smp_processor_id()); | |
1786 | return; | |
1787 | } | |
1788 | ||
1ac19ca6 MZ |
1789 | paddr = page_to_phys(pend_page); |
1790 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1791 | smp_processor_id(), &paddr); | |
1792 | gic_data_rdist()->pend_page = pend_page; | |
1793 | } | |
1794 | ||
1795 | /* Disable LPIs */ | |
1796 | val = readl_relaxed(rbase + GICR_CTLR); | |
1797 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1798 | writel_relaxed(val, rbase + GICR_CTLR); | |
1799 | ||
1800 | /* | |
1801 | * Make sure any change to the table is observable by the GIC. | |
1802 | */ | |
1803 | dsb(sy); | |
1804 | ||
1805 | /* set PROPBASE */ | |
1806 | val = (page_to_phys(gic_rdists->prop_page) | | |
1807 | GICR_PROPBASER_InnerShareable | | |
2fd632a0 | 1808 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1809 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1810 | ||
0968a619 VM |
1811 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1812 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1813 | |
1814 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1815 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1816 | /* | |
1817 | * The HW reports non-shareable, we must | |
1818 | * remove the cacheability attributes as | |
1819 | * well. | |
1820 | */ | |
1821 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1822 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1823 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1824 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1825 | } |
1ac19ca6 MZ |
1826 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1827 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1828 | } | |
1829 | ||
1830 | /* set PENDBASE */ | |
1831 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1832 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 1833 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1834 | |
0968a619 VM |
1835 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1836 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1837 | |
1838 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1839 | /* | |
1840 | * The HW reports non-shareable, we must remove the | |
1841 | * cacheability attributes as well. | |
1842 | */ | |
1843 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1844 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1845 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1846 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1847 | } |
1ac19ca6 MZ |
1848 | |
1849 | /* Enable LPIs */ | |
1850 | val = readl_relaxed(rbase + GICR_CTLR); | |
1851 | val |= GICR_CTLR_ENABLE_LPIS; | |
1852 | writel_relaxed(val, rbase + GICR_CTLR); | |
1853 | ||
1854 | /* Make sure the GIC has seen the above */ | |
1855 | dsb(sy); | |
1856 | } | |
1857 | ||
1858 | static void its_cpu_init_collection(void) | |
1859 | { | |
1860 | struct its_node *its; | |
1861 | int cpu; | |
1862 | ||
1863 | spin_lock(&its_lock); | |
1864 | cpu = smp_processor_id(); | |
1865 | ||
1866 | list_for_each_entry(its, &its_nodes, entry) { | |
1867 | u64 target; | |
1868 | ||
fbf8f40e GK |
1869 | /* avoid cross node collections and its mapping */ |
1870 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1871 | struct device_node *cpu_node; | |
1872 | ||
1873 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1874 | if (its->numa_node != NUMA_NO_NODE && | |
1875 | its->numa_node != of_node_to_nid(cpu_node)) | |
1876 | continue; | |
1877 | } | |
1878 | ||
1ac19ca6 MZ |
1879 | /* |
1880 | * We now have to bind each collection to its target | |
1881 | * redistributor. | |
1882 | */ | |
589ce5f4 | 1883 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1884 | /* |
1885 | * This ITS wants the physical address of the | |
1886 | * redistributor. | |
1887 | */ | |
1888 | target = gic_data_rdist()->phys_base; | |
1889 | } else { | |
1890 | /* | |
1891 | * This ITS wants a linear CPU number. | |
1892 | */ | |
589ce5f4 | 1893 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1894 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1895 | } |
1896 | ||
1897 | /* Perform collection mapping */ | |
1898 | its->collections[cpu].target_address = target; | |
1899 | its->collections[cpu].col_id = cpu; | |
1900 | ||
1901 | its_send_mapc(its, &its->collections[cpu], 1); | |
1902 | its_send_invall(its, &its->collections[cpu]); | |
1903 | } | |
1904 | ||
1905 | spin_unlock(&its_lock); | |
1906 | } | |
84a6a2e7 MZ |
1907 | |
1908 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1909 | { | |
1910 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1911 | unsigned long flags; |
84a6a2e7 | 1912 | |
3e39e8f5 | 1913 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1914 | |
1915 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1916 | if (tmp->device_id == dev_id) { | |
1917 | its_dev = tmp; | |
1918 | break; | |
1919 | } | |
1920 | } | |
1921 | ||
3e39e8f5 | 1922 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1923 | |
1924 | return its_dev; | |
1925 | } | |
1926 | ||
466b7d16 SD |
1927 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1928 | { | |
1929 | int i; | |
1930 | ||
1931 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1932 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1933 | return &its->tables[i]; | |
1934 | } | |
1935 | ||
1936 | return NULL; | |
1937 | } | |
1938 | ||
70cc81ed | 1939 | static bool its_alloc_table_entry(struct its_baser *baser, u32 id) |
3faf24ea | 1940 | { |
3faf24ea SD |
1941 | struct page *page; |
1942 | u32 esz, idx; | |
1943 | __le64 *table; | |
1944 | ||
3faf24ea SD |
1945 | /* Don't allow device id that exceeds single, flat table limit */ |
1946 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1947 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 1948 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
1949 | |
1950 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 1951 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
1952 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
1953 | return false; | |
1954 | ||
1955 | table = baser->base; | |
1956 | ||
1957 | /* Allocate memory for 2nd level table */ | |
1958 | if (!table[idx]) { | |
1959 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1960 | if (!page) | |
1961 | return false; | |
1962 | ||
1963 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1964 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1965 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1966 | |
1967 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1968 | ||
1969 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1970 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1971 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1972 | |
1973 | /* Ensure updated table contents are visible to ITS hardware */ | |
1974 | dsb(sy); | |
1975 | } | |
1976 | ||
1977 | return true; | |
1978 | } | |
1979 | ||
70cc81ed MZ |
1980 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1981 | { | |
1982 | struct its_baser *baser; | |
1983 | ||
1984 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1985 | ||
1986 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1987 | if (!baser) | |
1988 | return (ilog2(dev_id) < its->device_ids); | |
1989 | ||
1990 | return its_alloc_table_entry(baser, dev_id); | |
1991 | } | |
1992 | ||
7d75bbb4 MZ |
1993 | static bool its_alloc_vpe_table(u32 vpe_id) |
1994 | { | |
1995 | struct its_node *its; | |
1996 | ||
1997 | /* | |
1998 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
1999 | * could try and only do it on ITSs corresponding to devices | |
2000 | * that have interrupts targeted at this VPE, but the | |
2001 | * complexity becomes crazy (and you have tons of memory | |
2002 | * anyway, right?). | |
2003 | */ | |
2004 | list_for_each_entry(its, &its_nodes, entry) { | |
2005 | struct its_baser *baser; | |
2006 | ||
2007 | if (!its->is_v4) | |
2008 | continue; | |
3faf24ea | 2009 | |
7d75bbb4 MZ |
2010 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
2011 | if (!baser) | |
2012 | return false; | |
3faf24ea | 2013 | |
7d75bbb4 MZ |
2014 | if (!its_alloc_table_entry(baser, vpe_id)) |
2015 | return false; | |
3faf24ea SD |
2016 | } |
2017 | ||
2018 | return true; | |
2019 | } | |
2020 | ||
84a6a2e7 | 2021 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 2022 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
2023 | { |
2024 | struct its_device *dev; | |
93f94ea0 | 2025 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 2026 | unsigned long flags; |
591e5bec | 2027 | u16 *col_map = NULL; |
84a6a2e7 MZ |
2028 | void *itt; |
2029 | int lpi_base; | |
2030 | int nr_lpis; | |
c8481267 | 2031 | int nr_ites; |
84a6a2e7 MZ |
2032 | int sz; |
2033 | ||
3faf24ea | 2034 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
2035 | return NULL; |
2036 | ||
84a6a2e7 | 2037 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
2038 | /* |
2039 | * At least one bit of EventID is being used, hence a minimum | |
2040 | * of two entries. No, the architecture doesn't let you | |
2041 | * express an ITT with a single entry. | |
2042 | */ | |
96555c47 | 2043 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 2044 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 2045 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 2046 | itt = kzalloc(sz, GFP_KERNEL); |
93f94ea0 MZ |
2047 | if (alloc_lpis) { |
2048 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); | |
2049 | if (lpi_map) | |
2050 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, | |
2051 | GFP_KERNEL); | |
2052 | } else { | |
2053 | col_map = kzalloc(sizeof(*col_map) * nr_ites, GFP_KERNEL); | |
2054 | nr_lpis = 0; | |
2055 | lpi_base = 0; | |
2056 | } | |
84a6a2e7 | 2057 | |
93f94ea0 | 2058 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
2059 | kfree(dev); |
2060 | kfree(itt); | |
2061 | kfree(lpi_map); | |
591e5bec | 2062 | kfree(col_map); |
84a6a2e7 MZ |
2063 | return NULL; |
2064 | } | |
2065 | ||
328191c0 | 2066 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 2067 | |
84a6a2e7 MZ |
2068 | dev->its = its; |
2069 | dev->itt = itt; | |
c8481267 | 2070 | dev->nr_ites = nr_ites; |
591e5bec MZ |
2071 | dev->event_map.lpi_map = lpi_map; |
2072 | dev->event_map.col_map = col_map; | |
2073 | dev->event_map.lpi_base = lpi_base; | |
2074 | dev->event_map.nr_lpis = nr_lpis; | |
d011e4e6 | 2075 | mutex_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
2076 | dev->device_id = dev_id; |
2077 | INIT_LIST_HEAD(&dev->entry); | |
2078 | ||
3e39e8f5 | 2079 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 2080 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 2081 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 2082 | |
84a6a2e7 MZ |
2083 | /* Map device to its ITT */ |
2084 | its_send_mapd(dev, 1); | |
2085 | ||
2086 | return dev; | |
2087 | } | |
2088 | ||
2089 | static void its_free_device(struct its_device *its_dev) | |
2090 | { | |
3e39e8f5 MZ |
2091 | unsigned long flags; |
2092 | ||
2093 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 2094 | list_del(&its_dev->entry); |
3e39e8f5 | 2095 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
2096 | kfree(its_dev->itt); |
2097 | kfree(its_dev); | |
2098 | } | |
b48ac83d MZ |
2099 | |
2100 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
2101 | { | |
2102 | int idx; | |
2103 | ||
591e5bec MZ |
2104 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
2105 | dev->event_map.nr_lpis); | |
2106 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
2107 | return -ENOSPC; |
2108 | ||
591e5bec MZ |
2109 | *hwirq = dev->event_map.lpi_base + idx; |
2110 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 2111 | |
b48ac83d MZ |
2112 | return 0; |
2113 | } | |
2114 | ||
54456db9 MZ |
2115 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
2116 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 2117 | { |
b48ac83d | 2118 | struct its_node *its; |
b48ac83d | 2119 | struct its_device *its_dev; |
54456db9 MZ |
2120 | struct msi_domain_info *msi_info; |
2121 | u32 dev_id; | |
2122 | ||
2123 | /* | |
2124 | * We ignore "dev" entierely, and rely on the dev_id that has | |
2125 | * been passed via the scratchpad. This limits this domain's | |
2126 | * usefulness to upper layers that definitely know that they | |
2127 | * are built on top of the ITS. | |
2128 | */ | |
2129 | dev_id = info->scratchpad[0].ul; | |
2130 | ||
2131 | msi_info = msi_get_domain_info(domain); | |
2132 | its = msi_info->data; | |
e8137f4f | 2133 | |
20b3d54e MZ |
2134 | if (!gic_rdists->has_direct_lpi && |
2135 | vpe_proxy.dev && | |
2136 | vpe_proxy.dev->its == its && | |
2137 | dev_id == vpe_proxy.dev->device_id) { | |
2138 | /* Bad luck. Get yourself a better implementation */ | |
2139 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
2140 | dev_id); | |
2141 | return -EINVAL; | |
2142 | } | |
2143 | ||
f130420e | 2144 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
2145 | if (its_dev) { |
2146 | /* | |
2147 | * We already have seen this ID, probably through | |
2148 | * another alias (PCI bridge of some sort). No need to | |
2149 | * create the device. | |
2150 | */ | |
f130420e | 2151 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
2152 | goto out; |
2153 | } | |
b48ac83d | 2154 | |
93f94ea0 | 2155 | its_dev = its_create_device(its, dev_id, nvec, true); |
b48ac83d MZ |
2156 | if (!its_dev) |
2157 | return -ENOMEM; | |
2158 | ||
f130420e | 2159 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 2160 | out: |
b48ac83d | 2161 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
2162 | return 0; |
2163 | } | |
2164 | ||
54456db9 MZ |
2165 | static struct msi_domain_ops its_msi_domain_ops = { |
2166 | .msi_prepare = its_msi_prepare, | |
2167 | }; | |
2168 | ||
b48ac83d MZ |
2169 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
2170 | unsigned int virq, | |
2171 | irq_hw_number_t hwirq) | |
2172 | { | |
f833f57f MZ |
2173 | struct irq_fwspec fwspec; |
2174 | ||
2175 | if (irq_domain_get_of_node(domain->parent)) { | |
2176 | fwspec.fwnode = domain->parent->fwnode; | |
2177 | fwspec.param_count = 3; | |
2178 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
2179 | fwspec.param[1] = hwirq; | |
2180 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
2181 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
2182 | fwspec.fwnode = domain->parent->fwnode; | |
2183 | fwspec.param_count = 2; | |
2184 | fwspec.param[0] = hwirq; | |
2185 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
2186 | } else { |
2187 | return -EINVAL; | |
2188 | } | |
b48ac83d | 2189 | |
f833f57f | 2190 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
2191 | } |
2192 | ||
2193 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
2194 | unsigned int nr_irqs, void *args) | |
2195 | { | |
2196 | msi_alloc_info_t *info = args; | |
2197 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
2198 | irq_hw_number_t hwirq; | |
2199 | int err; | |
2200 | int i; | |
2201 | ||
2202 | for (i = 0; i < nr_irqs; i++) { | |
2203 | err = its_alloc_device_irq(its_dev, &hwirq); | |
2204 | if (err) | |
2205 | return err; | |
2206 | ||
2207 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
2208 | if (err) | |
2209 | return err; | |
2210 | ||
2211 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
2212 | hwirq, &its_irq_chip, its_dev); | |
0d224d35 | 2213 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); |
f130420e MZ |
2214 | pr_debug("ID:%d pID:%d vID:%d\n", |
2215 | (int)(hwirq - its_dev->event_map.lpi_base), | |
2216 | (int) hwirq, virq + i); | |
b48ac83d MZ |
2217 | } |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
72491643 TG |
2222 | static int its_irq_domain_activate(struct irq_domain *domain, |
2223 | struct irq_data *d, bool early) | |
aca268df MZ |
2224 | { |
2225 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2226 | u32 event = its_get_event_id(d); | |
fbf8f40e | 2227 | const struct cpumask *cpu_mask = cpu_online_mask; |
0d224d35 | 2228 | int cpu; |
fbf8f40e GK |
2229 | |
2230 | /* get the cpu_mask of local node */ | |
2231 | if (its_dev->its->numa_node >= 0) | |
2232 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 2233 | |
591e5bec | 2234 | /* Bind the LPI to the first possible CPU */ |
0d224d35 MZ |
2235 | cpu = cpumask_first(cpu_mask); |
2236 | its_dev->event_map.col_map[event] = cpu; | |
2237 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 2238 | |
aca268df | 2239 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 2240 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 2241 | return 0; |
aca268df MZ |
2242 | } |
2243 | ||
2244 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
2245 | struct irq_data *d) | |
2246 | { | |
2247 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2248 | u32 event = its_get_event_id(d); | |
2249 | ||
2250 | /* Stop the delivery of interrupts */ | |
2251 | its_send_discard(its_dev, event); | |
2252 | } | |
2253 | ||
b48ac83d MZ |
2254 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
2255 | unsigned int nr_irqs) | |
2256 | { | |
2257 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
2258 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2259 | int i; | |
2260 | ||
2261 | for (i = 0; i < nr_irqs; i++) { | |
2262 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2263 | virq + i); | |
aca268df | 2264 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
2265 | |
2266 | /* Mark interrupt index as unused */ | |
591e5bec | 2267 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
2268 | |
2269 | /* Nuke the entry in the domain */ | |
2da39949 | 2270 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
2271 | } |
2272 | ||
2273 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
2274 | if (bitmap_empty(its_dev->event_map.lpi_map, |
2275 | its_dev->event_map.nr_lpis)) { | |
cf2be8ba MZ |
2276 | its_lpi_free_chunks(its_dev->event_map.lpi_map, |
2277 | its_dev->event_map.lpi_base, | |
2278 | its_dev->event_map.nr_lpis); | |
2279 | kfree(its_dev->event_map.col_map); | |
b48ac83d MZ |
2280 | |
2281 | /* Unmap device/itt */ | |
2282 | its_send_mapd(its_dev, 0); | |
2283 | its_free_device(its_dev); | |
2284 | } | |
2285 | ||
2286 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
2287 | } | |
2288 | ||
2289 | static const struct irq_domain_ops its_domain_ops = { | |
2290 | .alloc = its_irq_domain_alloc, | |
2291 | .free = its_irq_domain_free, | |
aca268df MZ |
2292 | .activate = its_irq_domain_activate, |
2293 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 2294 | }; |
4c21f3c2 | 2295 | |
20b3d54e MZ |
2296 | /* |
2297 | * This is insane. | |
2298 | * | |
2299 | * If a GICv4 doesn't implement Direct LPIs (which is extremely | |
2300 | * likely), the only way to perform an invalidate is to use a fake | |
2301 | * device to issue an INV command, implying that the LPI has first | |
2302 | * been mapped to some event on that device. Since this is not exactly | |
2303 | * cheap, we try to keep that mapping around as long as possible, and | |
2304 | * only issue an UNMAP if we're short on available slots. | |
2305 | * | |
2306 | * Broken by design(tm). | |
2307 | */ | |
2308 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
2309 | { | |
2310 | /* Already unmapped? */ | |
2311 | if (vpe->vpe_proxy_event == -1) | |
2312 | return; | |
2313 | ||
2314 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2315 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
2316 | ||
2317 | /* | |
2318 | * We don't track empty slots at all, so let's move the | |
2319 | * next_victim pointer if we can quickly reuse that slot | |
2320 | * instead of nuking an existing entry. Not clear that this is | |
2321 | * always a win though, and this might just generate a ripple | |
2322 | * effect... Let's just hope VPEs don't migrate too often. | |
2323 | */ | |
2324 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2325 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
2326 | ||
2327 | vpe->vpe_proxy_event = -1; | |
2328 | } | |
2329 | ||
2330 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
2331 | { | |
2332 | if (!gic_rdists->has_direct_lpi) { | |
2333 | unsigned long flags; | |
2334 | ||
2335 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2336 | its_vpe_db_proxy_unmap_locked(vpe); | |
2337 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2338 | } | |
2339 | } | |
2340 | ||
2341 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
2342 | { | |
2343 | /* Already mapped? */ | |
2344 | if (vpe->vpe_proxy_event != -1) | |
2345 | return; | |
2346 | ||
2347 | /* This slot was already allocated. Kick the other VPE out. */ | |
2348 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2349 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
2350 | ||
2351 | /* Map the new VPE instead */ | |
2352 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
2353 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
2354 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
2355 | ||
2356 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
2357 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
2358 | } | |
2359 | ||
958b90d1 MZ |
2360 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
2361 | { | |
2362 | unsigned long flags; | |
2363 | struct its_collection *target_col; | |
2364 | ||
2365 | if (gic_rdists->has_direct_lpi) { | |
2366 | void __iomem *rdbase; | |
2367 | ||
2368 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
2369 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2370 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2371 | cpu_relax(); | |
2372 | ||
2373 | return; | |
2374 | } | |
2375 | ||
2376 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2377 | ||
2378 | its_vpe_db_proxy_map_locked(vpe); | |
2379 | ||
2380 | target_col = &vpe_proxy.dev->its->collections[to]; | |
2381 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
2382 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
2383 | ||
2384 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2385 | } | |
2386 | ||
3171a47a MZ |
2387 | static int its_vpe_set_affinity(struct irq_data *d, |
2388 | const struct cpumask *mask_val, | |
2389 | bool force) | |
2390 | { | |
2391 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2392 | int cpu = cpumask_first(mask_val); | |
2393 | ||
2394 | /* | |
2395 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 2396 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
2397 | * into the proxy device, we need to move the doorbell |
2398 | * interrupt to its new location. | |
3171a47a MZ |
2399 | */ |
2400 | if (vpe->col_idx != cpu) { | |
958b90d1 MZ |
2401 | int from = vpe->col_idx; |
2402 | ||
3171a47a MZ |
2403 | vpe->col_idx = cpu; |
2404 | its_send_vmovp(vpe); | |
958b90d1 | 2405 | its_vpe_db_proxy_move(vpe, from, cpu); |
3171a47a MZ |
2406 | } |
2407 | ||
2408 | return IRQ_SET_MASK_OK_DONE; | |
2409 | } | |
2410 | ||
e643d803 MZ |
2411 | static void its_vpe_schedule(struct its_vpe *vpe) |
2412 | { | |
2413 | void * __iomem vlpi_base = gic_data_rdist_vlpi_base(); | |
2414 | u64 val; | |
2415 | ||
2416 | /* Schedule the VPE */ | |
2417 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
2418 | GENMASK_ULL(51, 12); | |
2419 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
2420 | val |= GICR_VPROPBASER_RaWb; | |
2421 | val |= GICR_VPROPBASER_InnerShareable; | |
2422 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2423 | ||
2424 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
2425 | GENMASK_ULL(51, 16); | |
2426 | val |= GICR_VPENDBASER_RaWaWb; | |
2427 | val |= GICR_VPENDBASER_NonShareable; | |
2428 | /* | |
2429 | * There is no good way of finding out if the pending table is | |
2430 | * empty as we can race against the doorbell interrupt very | |
2431 | * easily. So in the end, vpe->pending_last is only an | |
2432 | * indication that the vcpu has something pending, not one | |
2433 | * that the pending table is empty. A good implementation | |
2434 | * would be able to read its coarse map pretty quickly anyway, | |
2435 | * making this a tolerable issue. | |
2436 | */ | |
2437 | val |= GICR_VPENDBASER_PendingLast; | |
2438 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
2439 | val |= GICR_VPENDBASER_Valid; | |
2440 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2441 | } | |
2442 | ||
2443 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
2444 | { | |
2445 | void * __iomem vlpi_base = gic_data_rdist_vlpi_base(); | |
2446 | u32 count = 1000000; /* 1s! */ | |
2447 | bool clean; | |
2448 | u64 val; | |
2449 | ||
2450 | /* We're being scheduled out */ | |
2451 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2452 | val &= ~GICR_VPENDBASER_Valid; | |
2453 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2454 | ||
2455 | do { | |
2456 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2457 | clean = !(val & GICR_VPENDBASER_Dirty); | |
2458 | if (!clean) { | |
2459 | count--; | |
2460 | cpu_relax(); | |
2461 | udelay(1); | |
2462 | } | |
2463 | } while (!clean && count); | |
2464 | ||
2465 | if (unlikely(!clean && !count)) { | |
2466 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); | |
2467 | vpe->idai = false; | |
2468 | vpe->pending_last = true; | |
2469 | } else { | |
2470 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); | |
2471 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
2472 | } | |
2473 | } | |
2474 | ||
2475 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) | |
2476 | { | |
2477 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2478 | struct its_cmd_info *info = vcpu_info; | |
2479 | ||
2480 | switch (info->cmd_type) { | |
2481 | case SCHEDULE_VPE: | |
2482 | its_vpe_schedule(vpe); | |
2483 | return 0; | |
2484 | ||
2485 | case DESCHEDULE_VPE: | |
2486 | its_vpe_deschedule(vpe); | |
2487 | return 0; | |
2488 | ||
5e2f7642 MZ |
2489 | case INVALL_VPE: |
2490 | its_send_vinvall(vpe); | |
2491 | return 0; | |
2492 | ||
e643d803 MZ |
2493 | default: |
2494 | return -EINVAL; | |
2495 | } | |
2496 | } | |
2497 | ||
20b3d54e MZ |
2498 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
2499 | void (*cmd)(struct its_device *, u32)) | |
2500 | { | |
2501 | unsigned long flags; | |
2502 | ||
2503 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2504 | ||
2505 | its_vpe_db_proxy_map_locked(vpe); | |
2506 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2507 | ||
2508 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2509 | } | |
2510 | ||
f6a91da7 MZ |
2511 | static void its_vpe_send_inv(struct irq_data *d) |
2512 | { | |
2513 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 2514 | |
20b3d54e MZ |
2515 | if (gic_rdists->has_direct_lpi) { |
2516 | void __iomem *rdbase; | |
2517 | ||
2518 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2519 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR); | |
2520 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2521 | cpu_relax(); | |
2522 | } else { | |
2523 | its_vpe_send_cmd(vpe, its_send_inv); | |
2524 | } | |
f6a91da7 MZ |
2525 | } |
2526 | ||
2527 | static void its_vpe_mask_irq(struct irq_data *d) | |
2528 | { | |
2529 | /* | |
2530 | * We need to unmask the LPI, which is described by the parent | |
2531 | * irq_data. Instead of calling into the parent (which won't | |
2532 | * exactly do the right thing, let's simply use the | |
2533 | * parent_data pointer. Yes, I'm naughty. | |
2534 | */ | |
2535 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
2536 | its_vpe_send_inv(d); | |
2537 | } | |
2538 | ||
2539 | static void its_vpe_unmask_irq(struct irq_data *d) | |
2540 | { | |
2541 | /* Same hack as above... */ | |
2542 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
2543 | its_vpe_send_inv(d); | |
2544 | } | |
2545 | ||
e57a3e28 MZ |
2546 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
2547 | enum irqchip_irq_state which, | |
2548 | bool state) | |
2549 | { | |
2550 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2551 | ||
2552 | if (which != IRQCHIP_STATE_PENDING) | |
2553 | return -EINVAL; | |
2554 | ||
2555 | if (gic_rdists->has_direct_lpi) { | |
2556 | void __iomem *rdbase; | |
2557 | ||
2558 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2559 | if (state) { | |
2560 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
2561 | } else { | |
2562 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2563 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2564 | cpu_relax(); | |
2565 | } | |
2566 | } else { | |
2567 | if (state) | |
2568 | its_vpe_send_cmd(vpe, its_send_int); | |
2569 | else | |
2570 | its_vpe_send_cmd(vpe, its_send_clear); | |
2571 | } | |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
8fff27ae MZ |
2576 | static struct irq_chip its_vpe_irq_chip = { |
2577 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
2578 | .irq_mask = its_vpe_mask_irq, |
2579 | .irq_unmask = its_vpe_unmask_irq, | |
2580 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 2581 | .irq_set_affinity = its_vpe_set_affinity, |
e57a3e28 | 2582 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 2583 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
2584 | }; |
2585 | ||
7d75bbb4 MZ |
2586 | static int its_vpe_id_alloc(void) |
2587 | { | |
2588 | return ida_simple_get(&its_vpeid_ida, 0, 1 << 16, GFP_KERNEL); | |
2589 | } | |
2590 | ||
2591 | static void its_vpe_id_free(u16 id) | |
2592 | { | |
2593 | ida_simple_remove(&its_vpeid_ida, id); | |
2594 | } | |
2595 | ||
2596 | static int its_vpe_init(struct its_vpe *vpe) | |
2597 | { | |
2598 | struct page *vpt_page; | |
2599 | int vpe_id; | |
2600 | ||
2601 | /* Allocate vpe_id */ | |
2602 | vpe_id = its_vpe_id_alloc(); | |
2603 | if (vpe_id < 0) | |
2604 | return vpe_id; | |
2605 | ||
2606 | /* Allocate VPT */ | |
2607 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
2608 | if (!vpt_page) { | |
2609 | its_vpe_id_free(vpe_id); | |
2610 | return -ENOMEM; | |
2611 | } | |
2612 | ||
2613 | if (!its_alloc_vpe_table(vpe_id)) { | |
2614 | its_vpe_id_free(vpe_id); | |
2615 | its_free_pending_table(vpe->vpt_page); | |
2616 | return -ENOMEM; | |
2617 | } | |
2618 | ||
2619 | vpe->vpe_id = vpe_id; | |
2620 | vpe->vpt_page = vpt_page; | |
20b3d54e | 2621 | vpe->vpe_proxy_event = -1; |
7d75bbb4 MZ |
2622 | |
2623 | return 0; | |
2624 | } | |
2625 | ||
2626 | static void its_vpe_teardown(struct its_vpe *vpe) | |
2627 | { | |
20b3d54e | 2628 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
2629 | its_vpe_id_free(vpe->vpe_id); |
2630 | its_free_pending_table(vpe->vpt_page); | |
2631 | } | |
2632 | ||
2633 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
2634 | unsigned int virq, | |
2635 | unsigned int nr_irqs) | |
2636 | { | |
2637 | struct its_vm *vm = domain->host_data; | |
2638 | int i; | |
2639 | ||
2640 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
2641 | ||
2642 | for (i = 0; i < nr_irqs; i++) { | |
2643 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2644 | virq + i); | |
2645 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
2646 | ||
2647 | BUG_ON(vm != vpe->its_vm); | |
2648 | ||
2649 | clear_bit(data->hwirq, vm->db_bitmap); | |
2650 | its_vpe_teardown(vpe); | |
2651 | irq_domain_reset_irq_data(data); | |
2652 | } | |
2653 | ||
2654 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
2655 | its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); | |
2656 | its_free_prop_table(vm->vprop_page); | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
2661 | unsigned int nr_irqs, void *args) | |
2662 | { | |
2663 | struct its_vm *vm = args; | |
2664 | unsigned long *bitmap; | |
2665 | struct page *vprop_page; | |
2666 | int base, nr_ids, i, err = 0; | |
2667 | ||
2668 | BUG_ON(!vm); | |
2669 | ||
2670 | bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids); | |
2671 | if (!bitmap) | |
2672 | return -ENOMEM; | |
2673 | ||
2674 | if (nr_ids < nr_irqs) { | |
2675 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2676 | return -ENOMEM; | |
2677 | } | |
2678 | ||
2679 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
2680 | if (!vprop_page) { | |
2681 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2682 | return -ENOMEM; | |
2683 | } | |
2684 | ||
2685 | vm->db_bitmap = bitmap; | |
2686 | vm->db_lpi_base = base; | |
2687 | vm->nr_db_lpis = nr_ids; | |
2688 | vm->vprop_page = vprop_page; | |
2689 | ||
2690 | for (i = 0; i < nr_irqs; i++) { | |
2691 | vm->vpes[i]->vpe_db_lpi = base + i; | |
2692 | err = its_vpe_init(vm->vpes[i]); | |
2693 | if (err) | |
2694 | break; | |
2695 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
2696 | vm->vpes[i]->vpe_db_lpi); | |
2697 | if (err) | |
2698 | break; | |
2699 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
2700 | &its_vpe_irq_chip, vm->vpes[i]); | |
2701 | set_bit(i, bitmap); | |
2702 | } | |
2703 | ||
2704 | if (err) { | |
2705 | if (i > 0) | |
2706 | its_vpe_irq_domain_free(domain, virq, i - 1); | |
2707 | ||
2708 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2709 | its_free_prop_table(vprop_page); | |
2710 | } | |
2711 | ||
2712 | return err; | |
2713 | } | |
2714 | ||
72491643 TG |
2715 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
2716 | struct irq_data *d, bool early) | |
eb78192b MZ |
2717 | { |
2718 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2719 | ||
2720 | /* Map the VPE to the first possible CPU */ | |
2721 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
2722 | its_send_vmapp(vpe, true); | |
2723 | its_send_vinvall(vpe); | |
72491643 | 2724 | return 0; |
eb78192b MZ |
2725 | } |
2726 | ||
2727 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
2728 | struct irq_data *d) | |
2729 | { | |
2730 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2731 | ||
2732 | its_send_vmapp(vpe, false); | |
2733 | } | |
2734 | ||
8fff27ae | 2735 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
2736 | .alloc = its_vpe_irq_domain_alloc, |
2737 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
2738 | .activate = its_vpe_irq_domain_activate, |
2739 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
2740 | }; |
2741 | ||
4559fbb3 YW |
2742 | static int its_force_quiescent(void __iomem *base) |
2743 | { | |
2744 | u32 count = 1000000; /* 1s */ | |
2745 | u32 val; | |
2746 | ||
2747 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
2748 | /* |
2749 | * GIC architecture specification requires the ITS to be both | |
2750 | * disabled and quiescent for writes to GITS_BASER<n> or | |
2751 | * GITS_CBASER to not have UNPREDICTABLE results. | |
2752 | */ | |
2753 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
2754 | return 0; |
2755 | ||
2756 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 2757 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
2758 | writel_relaxed(val, base + GITS_CTLR); |
2759 | ||
2760 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
2761 | while (1) { | |
2762 | val = readl_relaxed(base + GITS_CTLR); | |
2763 | if (val & GITS_CTLR_QUIESCENT) | |
2764 | return 0; | |
2765 | ||
2766 | count--; | |
2767 | if (!count) | |
2768 | return -EBUSY; | |
2769 | ||
2770 | cpu_relax(); | |
2771 | udelay(1); | |
2772 | } | |
2773 | } | |
2774 | ||
9d111d49 | 2775 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
2776 | { |
2777 | struct its_node *its = data; | |
2778 | ||
fa150019 AB |
2779 | /* erratum 22375: only alloc 8MB table size */ |
2780 | its->device_ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 2781 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
2782 | |
2783 | return true; | |
94100970 RR |
2784 | } |
2785 | ||
9d111d49 | 2786 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
2787 | { |
2788 | struct its_node *its = data; | |
2789 | ||
2790 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
2791 | |
2792 | return true; | |
fbf8f40e GK |
2793 | } |
2794 | ||
9d111d49 | 2795 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
2796 | { |
2797 | struct its_node *its = data; | |
2798 | ||
2799 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
2800 | its->ite_size = 16; | |
9d111d49 AB |
2801 | |
2802 | return true; | |
90922a2d SD |
2803 | } |
2804 | ||
558b0165 AB |
2805 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
2806 | { | |
2807 | struct its_node *its = its_dev->its; | |
2808 | ||
2809 | /* | |
2810 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
2811 | * which maps 32-bit writes targeted at a separate window of | |
2812 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
2813 | * with device ID taken from bits [device_id_bits + 1:2] of | |
2814 | * the window offset. | |
2815 | */ | |
2816 | return its->pre_its_base + (its_dev->device_id << 2); | |
2817 | } | |
2818 | ||
2819 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
2820 | { | |
2821 | struct its_node *its = data; | |
2822 | u32 pre_its_window[2]; | |
2823 | u32 ids; | |
2824 | ||
2825 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
2826 | "socionext,synquacer-pre-its", | |
2827 | pre_its_window, | |
2828 | ARRAY_SIZE(pre_its_window))) { | |
2829 | ||
2830 | its->pre_its_base = pre_its_window[0]; | |
2831 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
2832 | ||
2833 | ids = ilog2(pre_its_window[1]) - 2; | |
2834 | if (its->device_ids > ids) | |
2835 | its->device_ids = ids; | |
2836 | ||
2837 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
2838 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; | |
2839 | return true; | |
2840 | } | |
2841 | return false; | |
2842 | } | |
2843 | ||
5c9a882e MZ |
2844 | static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) |
2845 | { | |
2846 | struct its_node *its = data; | |
2847 | ||
2848 | /* | |
2849 | * Hip07 insists on using the wrong address for the VLPI | |
2850 | * page. Trick it into doing the right thing... | |
2851 | */ | |
2852 | its->vlpi_redist_offset = SZ_128K; | |
2853 | return true; | |
2854 | } | |
2855 | ||
67510cca | 2856 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
2857 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
2858 | { | |
2859 | .desc = "ITS: Cavium errata 22375, 24313", | |
2860 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2861 | .mask = 0xffff0fff, | |
2862 | .init = its_enable_quirk_cavium_22375, | |
2863 | }, | |
fbf8f40e GK |
2864 | #endif |
2865 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
2866 | { | |
2867 | .desc = "ITS: Cavium erratum 23144", | |
2868 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2869 | .mask = 0xffff0fff, | |
2870 | .init = its_enable_quirk_cavium_23144, | |
2871 | }, | |
90922a2d SD |
2872 | #endif |
2873 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
2874 | { | |
2875 | .desc = "ITS: QDF2400 erratum 0065", | |
2876 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
2877 | .mask = 0xffffffff, | |
2878 | .init = its_enable_quirk_qdf2400_e0065, | |
2879 | }, | |
558b0165 AB |
2880 | #endif |
2881 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
2882 | { | |
2883 | /* | |
2884 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
2885 | * implementation, but with a 'pre-ITS' added that requires | |
2886 | * special handling in software. | |
2887 | */ | |
2888 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
2889 | .iidr = 0x0001143b, | |
2890 | .mask = 0xffffffff, | |
2891 | .init = its_enable_quirk_socionext_synquacer, | |
2892 | }, | |
5c9a882e MZ |
2893 | #endif |
2894 | #ifdef CONFIG_HISILICON_ERRATUM_161600802 | |
2895 | { | |
2896 | .desc = "ITS: Hip07 erratum 161600802", | |
2897 | .iidr = 0x00000004, | |
2898 | .mask = 0xffffffff, | |
2899 | .init = its_enable_quirk_hip07_161600802, | |
2900 | }, | |
94100970 | 2901 | #endif |
67510cca RR |
2902 | { |
2903 | } | |
2904 | }; | |
2905 | ||
2906 | static void its_enable_quirks(struct its_node *its) | |
2907 | { | |
2908 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
2909 | ||
2910 | gic_enable_quirks(iidr, its_quirks, its); | |
2911 | } | |
2912 | ||
db40f0a7 | 2913 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
2914 | { |
2915 | struct irq_domain *inner_domain; | |
2916 | struct msi_domain_info *info; | |
2917 | ||
2918 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
2919 | if (!info) | |
2920 | return -ENOMEM; | |
2921 | ||
db40f0a7 | 2922 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
2923 | if (!inner_domain) { |
2924 | kfree(info); | |
2925 | return -ENOMEM; | |
2926 | } | |
2927 | ||
db40f0a7 | 2928 | inner_domain->parent = its_parent; |
96f0d93a | 2929 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
558b0165 | 2930 | inner_domain->flags |= its->msi_domain_flags; |
d14ae5e6 TN |
2931 | info->ops = &its_msi_domain_ops; |
2932 | info->data = its; | |
2933 | inner_domain->host_data = info; | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
8fff27ae MZ |
2938 | static int its_init_vpe_domain(void) |
2939 | { | |
20b3d54e MZ |
2940 | struct its_node *its; |
2941 | u32 devid; | |
2942 | int entries; | |
2943 | ||
2944 | if (gic_rdists->has_direct_lpi) { | |
2945 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
2946 | return 0; | |
2947 | } | |
2948 | ||
2949 | /* Any ITS will do, even if not v4 */ | |
2950 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
2951 | ||
2952 | entries = roundup_pow_of_two(nr_cpu_ids); | |
2953 | vpe_proxy.vpes = kzalloc(sizeof(*vpe_proxy.vpes) * entries, | |
2954 | GFP_KERNEL); | |
2955 | if (!vpe_proxy.vpes) { | |
2956 | pr_err("ITS: Can't allocate GICv4 proxy device array\n"); | |
2957 | return -ENOMEM; | |
2958 | } | |
2959 | ||
2960 | /* Use the last possible DevID */ | |
2961 | devid = GENMASK(its->device_ids - 1, 0); | |
2962 | vpe_proxy.dev = its_create_device(its, devid, entries, false); | |
2963 | if (!vpe_proxy.dev) { | |
2964 | kfree(vpe_proxy.vpes); | |
2965 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
2966 | return -ENOMEM; | |
2967 | } | |
2968 | ||
2969 | BUG_ON(entries != vpe_proxy.dev->nr_ites); | |
2970 | ||
2971 | raw_spin_lock_init(&vpe_proxy.lock); | |
2972 | vpe_proxy.next_victim = 0; | |
2973 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
2974 | devid, vpe_proxy.dev->nr_ites); | |
2975 | ||
8fff27ae MZ |
2976 | return 0; |
2977 | } | |
2978 | ||
3dfa576b MZ |
2979 | static int __init its_compute_its_list_map(struct resource *res, |
2980 | void __iomem *its_base) | |
2981 | { | |
2982 | int its_number; | |
2983 | u32 ctlr; | |
2984 | ||
2985 | /* | |
2986 | * This is assumed to be done early enough that we're | |
2987 | * guaranteed to be single-threaded, hence no | |
2988 | * locking. Should this change, we should address | |
2989 | * this. | |
2990 | */ | |
2991 | its_number = find_first_zero_bit(&its_list_map, ITS_LIST_MAX); | |
2992 | if (its_number >= ITS_LIST_MAX) { | |
2993 | pr_err("ITS@%pa: No ITSList entry available!\n", | |
2994 | &res->start); | |
2995 | return -EINVAL; | |
2996 | } | |
2997 | ||
2998 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
2999 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
3000 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
3001 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
3002 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
3003 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
3004 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
3005 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
3006 | } | |
3007 | ||
3008 | if (test_and_set_bit(its_number, &its_list_map)) { | |
3009 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
3010 | &res->start, its_number); | |
3011 | return -EINVAL; | |
3012 | } | |
3013 | ||
3014 | return its_number; | |
3015 | } | |
3016 | ||
db40f0a7 TN |
3017 | static int __init its_probe_one(struct resource *res, |
3018 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 3019 | { |
4c21f3c2 MZ |
3020 | struct its_node *its; |
3021 | void __iomem *its_base; | |
3dfa576b MZ |
3022 | u32 val, ctlr; |
3023 | u64 baser, tmp, typer; | |
4c21f3c2 MZ |
3024 | int err; |
3025 | ||
db40f0a7 | 3026 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 3027 | if (!its_base) { |
db40f0a7 | 3028 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
3029 | return -ENOMEM; |
3030 | } | |
3031 | ||
3032 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
3033 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 3034 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
3035 | err = -ENODEV; |
3036 | goto out_unmap; | |
3037 | } | |
3038 | ||
4559fbb3 YW |
3039 | err = its_force_quiescent(its_base); |
3040 | if (err) { | |
db40f0a7 | 3041 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
3042 | goto out_unmap; |
3043 | } | |
3044 | ||
db40f0a7 | 3045 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
3046 | |
3047 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
3048 | if (!its) { | |
3049 | err = -ENOMEM; | |
3050 | goto out_unmap; | |
3051 | } | |
3052 | ||
3053 | raw_spin_lock_init(&its->lock); | |
3054 | INIT_LIST_HEAD(&its->entry); | |
3055 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 3056 | typer = gic_read_typer(its_base + GITS_TYPER); |
4c21f3c2 | 3057 | its->base = its_base; |
db40f0a7 | 3058 | its->phys_base = res->start; |
3dfa576b | 3059 | its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); |
fa150019 | 3060 | its->device_ids = GITS_TYPER_DEVBITS(typer); |
3dfa576b MZ |
3061 | its->is_v4 = !!(typer & GITS_TYPER_VLPIS); |
3062 | if (its->is_v4) { | |
3063 | if (!(typer & GITS_TYPER_VMOVP)) { | |
3064 | err = its_compute_its_list_map(res, its_base); | |
3065 | if (err < 0) | |
3066 | goto out_free_its; | |
3067 | ||
debf6d02 MZ |
3068 | its->list_nr = err; |
3069 | ||
3dfa576b MZ |
3070 | pr_info("ITS@%pa: Using ITS number %d\n", |
3071 | &res->start, err); | |
3072 | } else { | |
3073 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
3074 | } | |
3075 | } | |
3076 | ||
db40f0a7 | 3077 | its->numa_node = numa_node; |
4c21f3c2 | 3078 | |
5bc13c2c RR |
3079 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
3080 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
3081 | if (!its->cmd_base) { |
3082 | err = -ENOMEM; | |
3083 | goto out_free_its; | |
3084 | } | |
3085 | its->cmd_write = its->cmd_base; | |
558b0165 AB |
3086 | its->fwnode_handle = handle; |
3087 | its->get_msi_base = its_irq_get_msi_base; | |
3088 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4c21f3c2 | 3089 | |
67510cca RR |
3090 | its_enable_quirks(its); |
3091 | ||
0e0b0f69 | 3092 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
3093 | if (err) |
3094 | goto out_free_cmd; | |
3095 | ||
3096 | err = its_alloc_collections(its); | |
3097 | if (err) | |
3098 | goto out_free_tables; | |
3099 | ||
3100 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 3101 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
3102 | GITS_CBASER_InnerShareable | |
3103 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
3104 | GITS_CBASER_VALID); | |
3105 | ||
0968a619 VM |
3106 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
3107 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 3108 | |
4ad3e363 | 3109 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
3110 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
3111 | /* | |
3112 | * The HW reports non-shareable, we must | |
3113 | * remove the cacheability attributes as | |
3114 | * well. | |
3115 | */ | |
3116 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
3117 | GITS_CBASER_CACHEABILITY_MASK); | |
3118 | baser |= GITS_CBASER_nC; | |
0968a619 | 3119 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 3120 | } |
4c21f3c2 MZ |
3121 | pr_info("ITS: using cache flushing for cmd queue\n"); |
3122 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
3123 | } | |
3124 | ||
0968a619 | 3125 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 3126 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d MZ |
3127 | ctlr |= GITS_CTLR_ENABLE; |
3128 | if (its->is_v4) | |
3129 | ctlr |= GITS_CTLR_ImDe; | |
3130 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 3131 | |
db40f0a7 | 3132 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
3133 | if (err) |
3134 | goto out_free_tables; | |
4c21f3c2 MZ |
3135 | |
3136 | spin_lock(&its_lock); | |
3137 | list_add(&its->entry, &its_nodes); | |
3138 | spin_unlock(&its_lock); | |
3139 | ||
3140 | return 0; | |
3141 | ||
4c21f3c2 MZ |
3142 | out_free_tables: |
3143 | its_free_tables(its); | |
3144 | out_free_cmd: | |
5bc13c2c | 3145 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
3146 | out_free_its: |
3147 | kfree(its); | |
3148 | out_unmap: | |
3149 | iounmap(its_base); | |
db40f0a7 | 3150 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
3151 | return err; |
3152 | } | |
3153 | ||
3154 | static bool gic_rdists_supports_plpis(void) | |
3155 | { | |
589ce5f4 | 3156 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
3157 | } |
3158 | ||
3159 | int its_cpu_init(void) | |
3160 | { | |
4c21f3c2 | 3161 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
3162 | if (!gic_rdists_supports_plpis()) { |
3163 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
3164 | return -ENXIO; | |
3165 | } | |
4c21f3c2 MZ |
3166 | its_cpu_init_lpis(); |
3167 | its_cpu_init_collection(); | |
3168 | } | |
3169 | ||
3170 | return 0; | |
3171 | } | |
3172 | ||
935bba7c | 3173 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
3174 | { .compatible = "arm,gic-v3-its", }, |
3175 | {}, | |
3176 | }; | |
3177 | ||
db40f0a7 | 3178 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
3179 | { |
3180 | struct device_node *np; | |
db40f0a7 | 3181 | struct resource res; |
4c21f3c2 MZ |
3182 | |
3183 | for (np = of_find_matching_node(node, its_device_id); np; | |
3184 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 | 3185 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
3186 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
3187 | np); | |
d14ae5e6 TN |
3188 | continue; |
3189 | } | |
3190 | ||
db40f0a7 | 3191 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 3192 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
3193 | continue; |
3194 | } | |
3195 | ||
3196 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 3197 | } |
db40f0a7 TN |
3198 | return 0; |
3199 | } | |
3200 | ||
3f010cf1 TN |
3201 | #ifdef CONFIG_ACPI |
3202 | ||
3203 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
3204 | ||
d1ce263f | 3205 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
3206 | struct its_srat_map { |
3207 | /* numa node id */ | |
3208 | u32 numa_node; | |
3209 | /* GIC ITS ID */ | |
3210 | u32 its_id; | |
3211 | }; | |
3212 | ||
fdf6e7a8 | 3213 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
3214 | static int its_in_srat __initdata; |
3215 | ||
3216 | static int __init acpi_get_its_numa_node(u32 its_id) | |
3217 | { | |
3218 | int i; | |
3219 | ||
3220 | for (i = 0; i < its_in_srat; i++) { | |
3221 | if (its_id == its_srat_maps[i].its_id) | |
3222 | return its_srat_maps[i].numa_node; | |
3223 | } | |
3224 | return NUMA_NO_NODE; | |
3225 | } | |
3226 | ||
fdf6e7a8 HG |
3227 | static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header, |
3228 | const unsigned long end) | |
3229 | { | |
3230 | return 0; | |
3231 | } | |
3232 | ||
dbd2b826 GK |
3233 | static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, |
3234 | const unsigned long end) | |
3235 | { | |
3236 | int node; | |
3237 | struct acpi_srat_gic_its_affinity *its_affinity; | |
3238 | ||
3239 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
3240 | if (!its_affinity) | |
3241 | return -EINVAL; | |
3242 | ||
3243 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
3244 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
3245 | its_affinity->header.length); | |
3246 | return -EINVAL; | |
3247 | } | |
3248 | ||
dbd2b826 GK |
3249 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); |
3250 | ||
3251 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
3252 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
3253 | return 0; | |
3254 | } | |
3255 | ||
3256 | its_srat_maps[its_in_srat].numa_node = node; | |
3257 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
3258 | its_in_srat++; | |
3259 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
3260 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
3261 | ||
3262 | return 0; | |
3263 | } | |
3264 | ||
3265 | static void __init acpi_table_parse_srat_its(void) | |
3266 | { | |
fdf6e7a8 HG |
3267 | int count; |
3268 | ||
3269 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
3270 | sizeof(struct acpi_table_srat), | |
3271 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3272 | gic_acpi_match_srat_its, 0); | |
3273 | if (count <= 0) | |
3274 | return; | |
3275 | ||
3276 | its_srat_maps = kmalloc(count * sizeof(struct its_srat_map), | |
3277 | GFP_KERNEL); | |
3278 | if (!its_srat_maps) { | |
3279 | pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n"); | |
3280 | return; | |
3281 | } | |
3282 | ||
dbd2b826 GK |
3283 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
3284 | sizeof(struct acpi_table_srat), | |
3285 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3286 | gic_acpi_parse_srat_its, 0); | |
3287 | } | |
fdf6e7a8 HG |
3288 | |
3289 | /* free the its_srat_maps after ITS probing */ | |
3290 | static void __init acpi_its_srat_maps_free(void) | |
3291 | { | |
3292 | kfree(its_srat_maps); | |
3293 | } | |
dbd2b826 GK |
3294 | #else |
3295 | static void __init acpi_table_parse_srat_its(void) { } | |
3296 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 3297 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
3298 | #endif |
3299 | ||
3f010cf1 TN |
3300 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, |
3301 | const unsigned long end) | |
3302 | { | |
3303 | struct acpi_madt_generic_translator *its_entry; | |
3304 | struct fwnode_handle *dom_handle; | |
3305 | struct resource res; | |
3306 | int err; | |
3307 | ||
3308 | its_entry = (struct acpi_madt_generic_translator *)header; | |
3309 | memset(&res, 0, sizeof(res)); | |
3310 | res.start = its_entry->base_address; | |
3311 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
3312 | res.flags = IORESOURCE_MEM; | |
3313 | ||
3314 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
3315 | if (!dom_handle) { | |
3316 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
3317 | &res.start); | |
3318 | return -ENOMEM; | |
3319 | } | |
3320 | ||
3321 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
3322 | if (err) { | |
3323 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
3324 | &res.start, its_entry->translation_id); | |
3325 | goto dom_err; | |
3326 | } | |
3327 | ||
dbd2b826 GK |
3328 | err = its_probe_one(&res, dom_handle, |
3329 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
3330 | if (!err) |
3331 | return 0; | |
3332 | ||
3333 | iort_deregister_domain_token(its_entry->translation_id); | |
3334 | dom_err: | |
3335 | irq_domain_free_fwnode(dom_handle); | |
3336 | return err; | |
3337 | } | |
3338 | ||
3339 | static void __init its_acpi_probe(void) | |
3340 | { | |
dbd2b826 | 3341 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
3342 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
3343 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 3344 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
3345 | } |
3346 | #else | |
3347 | static void __init its_acpi_probe(void) { } | |
3348 | #endif | |
3349 | ||
db40f0a7 TN |
3350 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
3351 | struct irq_domain *parent_domain) | |
3352 | { | |
3353 | struct device_node *of_node; | |
8fff27ae MZ |
3354 | struct its_node *its; |
3355 | bool has_v4 = false; | |
3356 | int err; | |
db40f0a7 TN |
3357 | |
3358 | its_parent = parent_domain; | |
3359 | of_node = to_of_node(handle); | |
3360 | if (of_node) | |
3361 | its_of_probe(of_node); | |
3362 | else | |
3f010cf1 | 3363 | its_acpi_probe(); |
4c21f3c2 MZ |
3364 | |
3365 | if (list_empty(&its_nodes)) { | |
3366 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
3367 | return -ENXIO; | |
3368 | } | |
3369 | ||
3370 | gic_rdists = rdists; | |
8fff27ae MZ |
3371 | err = its_alloc_lpi_tables(); |
3372 | if (err) | |
3373 | return err; | |
3374 | ||
3375 | list_for_each_entry(its, &its_nodes, entry) | |
3376 | has_v4 |= its->is_v4; | |
3377 | ||
3378 | if (has_v4 & rdists->has_vlpis) { | |
3d63cb53 MZ |
3379 | if (its_init_vpe_domain() || |
3380 | its_init_v4(parent_domain, &its_vpe_domain_ops)) { | |
8fff27ae MZ |
3381 | rdists->has_vlpis = false; |
3382 | pr_err("ITS: Disabling GICv4 support\n"); | |
3383 | } | |
3384 | } | |
3385 | ||
3386 | return 0; | |
4c21f3c2 | 3387 | } |