Commit | Line | Data |
---|---|---|
caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cc2d3216 | 2 | /* |
d7276b80 | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
cc2d3216 MZ |
5 | */ |
6 | ||
3f010cf1 | 7 | #include <linux/acpi.h> |
8d3554b8 | 8 | #include <linux/acpi_iort.h> |
ffedbf0c | 9 | #include <linux/bitfield.h> |
cc2d3216 MZ |
10 | #include <linux/bitmap.h> |
11 | #include <linux/cpu.h> | |
c6e2ccb6 | 12 | #include <linux/crash_dump.h> |
cc2d3216 | 13 | #include <linux/delay.h> |
44bb7e24 | 14 | #include <linux/dma-iommu.h> |
3fb68fae | 15 | #include <linux/efi.h> |
cc2d3216 | 16 | #include <linux/interrupt.h> |
96806229 | 17 | #include <linux/iopoll.h> |
3f010cf1 | 18 | #include <linux/irqdomain.h> |
880cb3cd | 19 | #include <linux/list.h> |
cc2d3216 | 20 | #include <linux/log2.h> |
5e2c9f9a | 21 | #include <linux/memblock.h> |
cc2d3216 MZ |
22 | #include <linux/mm.h> |
23 | #include <linux/msi.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
dba0bc7b | 31 | #include <linux/syscore_ops.h> |
cc2d3216 | 32 | |
41a83e06 | 33 | #include <linux/irqchip.h> |
cc2d3216 | 34 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 35 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 36 | |
cc2d3216 MZ |
37 | #include <asm/cputype.h> |
38 | #include <asm/exception.h> | |
39 | ||
67510cca RR |
40 | #include "irq-gic-common.h" |
41 | ||
94100970 RR |
42 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
43 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 44 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
dba0bc7b | 45 | #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) |
cc2d3216 | 46 | |
c48ed51c | 47 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
c440a9d9 | 48 | #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) |
c48ed51c | 49 | |
a13b0404 MZ |
50 | static u32 lpi_id_bits; |
51 | ||
52 | /* | |
53 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
54 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
55 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
56 | */ | |
57 | #define LPI_NRBITS lpi_id_bits | |
58 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
59 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
60 | ||
2130b789 | 61 | #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI |
a13b0404 | 62 | |
cc2d3216 MZ |
63 | /* |
64 | * Collection structure - just an ID, and a redistributor address to | |
65 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
66 | * CPU. | |
67 | */ | |
68 | struct its_collection { | |
69 | u64 target_address; | |
70 | u16 col_id; | |
71 | }; | |
72 | ||
466b7d16 | 73 | /* |
9347359a SD |
74 | * The ITS_BASER structure - contains memory information, cached |
75 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
76 | */ |
77 | struct its_baser { | |
78 | void *base; | |
79 | u64 val; | |
80 | u32 order; | |
9347359a | 81 | u32 psz; |
466b7d16 SD |
82 | }; |
83 | ||
558b0165 AB |
84 | struct its_device; |
85 | ||
cc2d3216 MZ |
86 | /* |
87 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
88 | * top-level MSI domain, the command queue, the collections, and the |
89 | * list of devices writing to it. | |
9791ec7d MZ |
90 | * |
91 | * dev_alloc_lock has to be taken for device allocations, while the | |
92 | * spinlock must be taken to parse data structures such as the device | |
93 | * list. | |
cc2d3216 MZ |
94 | */ |
95 | struct its_node { | |
96 | raw_spinlock_t lock; | |
9791ec7d | 97 | struct mutex dev_alloc_lock; |
cc2d3216 | 98 | struct list_head entry; |
cc2d3216 | 99 | void __iomem *base; |
5e46a484 | 100 | void __iomem *sgir_base; |
db40f0a7 | 101 | phys_addr_t phys_base; |
cc2d3216 MZ |
102 | struct its_cmd_block *cmd_base; |
103 | struct its_cmd_block *cmd_write; | |
466b7d16 | 104 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 105 | struct its_collection *collections; |
558b0165 AB |
106 | struct fwnode_handle *fwnode_handle; |
107 | u64 (*get_msi_base)(struct its_device *its_dev); | |
0dd57fed | 108 | u64 typer; |
dba0bc7b DB |
109 | u64 cbaser_save; |
110 | u32 ctlr_save; | |
5e516846 | 111 | u32 mpidr; |
cc2d3216 MZ |
112 | struct list_head its_device_list; |
113 | u64 flags; | |
debf6d02 | 114 | unsigned long list_nr; |
fbf8f40e | 115 | int numa_node; |
558b0165 AB |
116 | unsigned int msi_domain_flags; |
117 | u32 pre_its_base; /* for Socionext Synquacer */ | |
5c9a882e | 118 | int vlpi_redist_offset; |
cc2d3216 MZ |
119 | }; |
120 | ||
0dd57fed | 121 | #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) |
5e516846 | 122 | #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) |
576a8342 | 123 | #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) |
0dd57fed | 124 | |
cc2d3216 MZ |
125 | #define ITS_ITT_ALIGN SZ_256 |
126 | ||
32bd44dc | 127 | /* The maximum number of VPEID bits supported by VLPI commands */ |
f2d83409 MZ |
128 | #define ITS_MAX_VPEID_BITS \ |
129 | ({ \ | |
130 | int nvpeid = 16; \ | |
131 | if (gic_rdists->has_rvpeid && \ | |
132 | gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ | |
133 | nvpeid = 1 + (gic_rdists->gicd_typer2 & \ | |
134 | GICD_TYPER2_VID); \ | |
135 | \ | |
136 | nvpeid; \ | |
137 | }) | |
32bd44dc SD |
138 | #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) |
139 | ||
2eca0d6c SD |
140 | /* Convert page order to size in bytes */ |
141 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
142 | ||
591e5bec MZ |
143 | struct event_lpi_map { |
144 | unsigned long *lpi_map; | |
145 | u16 *col_map; | |
146 | irq_hw_number_t lpi_base; | |
147 | int nr_lpis; | |
11635fa2 | 148 | raw_spinlock_t vlpi_lock; |
d011e4e6 MZ |
149 | struct its_vm *vm; |
150 | struct its_vlpi_map *vlpi_maps; | |
151 | int nr_vlpis; | |
591e5bec MZ |
152 | }; |
153 | ||
cc2d3216 | 154 | /* |
d011e4e6 MZ |
155 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
156 | * translation table, and a list of interrupts. If it some of its | |
157 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
158 | * indicates which one. | |
cc2d3216 MZ |
159 | */ |
160 | struct its_device { | |
161 | struct list_head entry; | |
162 | struct its_node *its; | |
591e5bec | 163 | struct event_lpi_map event_map; |
cc2d3216 | 164 | void *itt; |
cc2d3216 MZ |
165 | u32 nr_ites; |
166 | u32 device_id; | |
9791ec7d | 167 | bool shared; |
cc2d3216 MZ |
168 | }; |
169 | ||
20b3d54e MZ |
170 | static struct { |
171 | raw_spinlock_t lock; | |
172 | struct its_device *dev; | |
173 | struct its_vpe **vpes; | |
174 | int next_victim; | |
175 | } vpe_proxy; | |
176 | ||
2f13ff1d MZ |
177 | struct cpu_lpi_count { |
178 | atomic_t managed; | |
179 | atomic_t unmanaged; | |
180 | }; | |
181 | ||
182 | static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count); | |
183 | ||
1ac19ca6 | 184 | static LIST_HEAD(its_nodes); |
a8db7456 | 185 | static DEFINE_RAW_SPINLOCK(its_lock); |
1ac19ca6 | 186 | static struct rdists *gic_rdists; |
db40f0a7 | 187 | static struct irq_domain *its_parent; |
1ac19ca6 | 188 | |
3dfa576b | 189 | static unsigned long its_list_map; |
3171a47a MZ |
190 | static u16 vmovp_seq_num; |
191 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
192 | ||
7d75bbb4 | 193 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 194 | |
1ac19ca6 | 195 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
11e37d35 | 196 | #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu)) |
1ac19ca6 | 197 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
e643d803 | 198 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 199 | |
009384b3 MZ |
200 | /* |
201 | * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we | |
202 | * always have vSGIs mapped. | |
203 | */ | |
204 | static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) | |
205 | { | |
206 | return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); | |
207 | } | |
208 | ||
84243125 ZY |
209 | static u16 get_its_list(struct its_vm *vm) |
210 | { | |
211 | struct its_node *its; | |
212 | unsigned long its_list = 0; | |
213 | ||
214 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 215 | if (!is_v4(its)) |
84243125 ZY |
216 | continue; |
217 | ||
009384b3 | 218 | if (require_its_list_vmovp(vm, its)) |
84243125 ZY |
219 | __set_bit(its->list_nr, &its_list); |
220 | } | |
221 | ||
222 | return (u16)its_list; | |
223 | } | |
224 | ||
425c09be MZ |
225 | static inline u32 its_get_event_id(struct irq_data *d) |
226 | { | |
227 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
228 | return d->hwirq - its_dev->event_map.lpi_base; | |
229 | } | |
230 | ||
591e5bec MZ |
231 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
232 | u32 event) | |
233 | { | |
234 | struct its_node *its = its_dev->its; | |
235 | ||
236 | return its->collections + its_dev->event_map.col_map[event]; | |
237 | } | |
238 | ||
c1d4d5cd MZ |
239 | static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev, |
240 | u32 event) | |
241 | { | |
242 | if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) | |
243 | return NULL; | |
244 | ||
245 | return &its_dev->event_map.vlpi_maps[event]; | |
246 | } | |
247 | ||
f4a81f5a MZ |
248 | static struct its_vlpi_map *get_vlpi_map(struct irq_data *d) |
249 | { | |
250 | if (irqd_is_forwarded_to_vcpu(d)) { | |
251 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
252 | u32 event = its_get_event_id(d); | |
253 | ||
254 | return dev_event_to_vlpi_map(its_dev, event); | |
255 | } | |
256 | ||
257 | return NULL; | |
258 | } | |
259 | ||
f3a05921 MZ |
260 | static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags) |
261 | { | |
262 | raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); | |
263 | return vpe->col_idx; | |
264 | } | |
265 | ||
266 | static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags) | |
267 | { | |
268 | raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); | |
269 | } | |
270 | ||
271 | static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags) | |
425c09be | 272 | { |
f4a81f5a | 273 | struct its_vlpi_map *map = get_vlpi_map(d); |
f3a05921 | 274 | int cpu; |
f4a81f5a | 275 | |
f3a05921 MZ |
276 | if (map) { |
277 | cpu = vpe_to_cpuid_lock(map->vpe, flags); | |
278 | } else { | |
279 | /* Physical LPIs are already locked via the irq_desc lock */ | |
280 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
281 | cpu = its_dev->event_map.col_map[its_get_event_id(d)]; | |
282 | /* Keep GCC quiet... */ | |
283 | *flags = 0; | |
284 | } | |
425c09be | 285 | |
f3a05921 MZ |
286 | return cpu; |
287 | } | |
288 | ||
289 | static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags) | |
425c09be | 290 | { |
f4a81f5a MZ |
291 | struct its_vlpi_map *map = get_vlpi_map(d); |
292 | ||
293 | if (map) | |
f3a05921 | 294 | vpe_to_cpuid_unlock(map->vpe, flags); |
425c09be MZ |
295 | } |
296 | ||
83559b47 MZ |
297 | static struct its_collection *valid_col(struct its_collection *col) |
298 | { | |
20faba84 | 299 | if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) |
83559b47 MZ |
300 | return NULL; |
301 | ||
302 | return col; | |
303 | } | |
304 | ||
205e065d MZ |
305 | static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) |
306 | { | |
307 | if (valid_col(its->collections + vpe->col_idx)) | |
308 | return vpe; | |
309 | ||
310 | return NULL; | |
311 | } | |
312 | ||
cc2d3216 MZ |
313 | /* |
314 | * ITS command descriptors - parameters to be encoded in a command | |
315 | * block. | |
316 | */ | |
317 | struct its_cmd_desc { | |
318 | union { | |
319 | struct { | |
320 | struct its_device *dev; | |
321 | u32 event_id; | |
322 | } its_inv_cmd; | |
323 | ||
8d85dced MZ |
324 | struct { |
325 | struct its_device *dev; | |
326 | u32 event_id; | |
327 | } its_clear_cmd; | |
328 | ||
cc2d3216 MZ |
329 | struct { |
330 | struct its_device *dev; | |
331 | u32 event_id; | |
332 | } its_int_cmd; | |
333 | ||
334 | struct { | |
335 | struct its_device *dev; | |
336 | int valid; | |
337 | } its_mapd_cmd; | |
338 | ||
339 | struct { | |
340 | struct its_collection *col; | |
341 | int valid; | |
342 | } its_mapc_cmd; | |
343 | ||
344 | struct { | |
345 | struct its_device *dev; | |
346 | u32 phys_id; | |
347 | u32 event_id; | |
6a25ad3a | 348 | } its_mapti_cmd; |
cc2d3216 MZ |
349 | |
350 | struct { | |
351 | struct its_device *dev; | |
352 | struct its_collection *col; | |
591e5bec | 353 | u32 event_id; |
cc2d3216 MZ |
354 | } its_movi_cmd; |
355 | ||
356 | struct { | |
357 | struct its_device *dev; | |
358 | u32 event_id; | |
359 | } its_discard_cmd; | |
360 | ||
361 | struct { | |
362 | struct its_collection *col; | |
363 | } its_invall_cmd; | |
d011e4e6 | 364 | |
eb78192b MZ |
365 | struct { |
366 | struct its_vpe *vpe; | |
367 | } its_vinvall_cmd; | |
368 | ||
369 | struct { | |
370 | struct its_vpe *vpe; | |
371 | struct its_collection *col; | |
372 | bool valid; | |
373 | } its_vmapp_cmd; | |
374 | ||
d011e4e6 MZ |
375 | struct { |
376 | struct its_vpe *vpe; | |
377 | struct its_device *dev; | |
378 | u32 virt_id; | |
379 | u32 event_id; | |
380 | bool db_enabled; | |
381 | } its_vmapti_cmd; | |
382 | ||
383 | struct { | |
384 | struct its_vpe *vpe; | |
385 | struct its_device *dev; | |
386 | u32 event_id; | |
387 | bool db_enabled; | |
388 | } its_vmovi_cmd; | |
3171a47a MZ |
389 | |
390 | struct { | |
391 | struct its_vpe *vpe; | |
392 | struct its_collection *col; | |
393 | u16 seq_num; | |
394 | u16 its_list; | |
395 | } its_vmovp_cmd; | |
d97c97ba MZ |
396 | |
397 | struct { | |
398 | struct its_vpe *vpe; | |
399 | } its_invdb_cmd; | |
e252cf8a MZ |
400 | |
401 | struct { | |
402 | struct its_vpe *vpe; | |
403 | u8 sgi; | |
404 | u8 priority; | |
405 | bool enable; | |
406 | bool group; | |
407 | bool clear; | |
408 | } its_vsgi_cmd; | |
cc2d3216 MZ |
409 | }; |
410 | }; | |
411 | ||
412 | /* | |
413 | * The ITS command block, which is what the ITS actually parses. | |
414 | */ | |
415 | struct its_cmd_block { | |
2bbdfcc5 BDC |
416 | union { |
417 | u64 raw_cmd[4]; | |
418 | __le64 raw_cmd_le[4]; | |
419 | }; | |
cc2d3216 MZ |
420 | }; |
421 | ||
422 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
423 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
424 | ||
67047f90 MZ |
425 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *, |
426 | struct its_cmd_block *, | |
cc2d3216 MZ |
427 | struct its_cmd_desc *); |
428 | ||
67047f90 MZ |
429 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *, |
430 | struct its_cmd_block *, | |
d011e4e6 MZ |
431 | struct its_cmd_desc *); |
432 | ||
4d36f136 MZ |
433 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
434 | { | |
435 | u64 mask = GENMASK_ULL(h, l); | |
436 | *raw_cmd &= ~mask; | |
437 | *raw_cmd |= (val << l) & mask; | |
438 | } | |
439 | ||
cc2d3216 MZ |
440 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
441 | { | |
4d36f136 | 442 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
443 | } |
444 | ||
445 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
446 | { | |
4d36f136 | 447 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
448 | } |
449 | ||
450 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
451 | { | |
4d36f136 | 452 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
453 | } |
454 | ||
455 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
456 | { | |
4d36f136 | 457 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
458 | } |
459 | ||
460 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
461 | { | |
4d36f136 | 462 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
463 | } |
464 | ||
465 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
466 | { | |
30ae9610 | 467 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); |
cc2d3216 MZ |
468 | } |
469 | ||
470 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
471 | { | |
4d36f136 | 472 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
473 | } |
474 | ||
475 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
476 | { | |
30ae9610 | 477 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); |
cc2d3216 MZ |
478 | } |
479 | ||
480 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
481 | { | |
4d36f136 | 482 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
483 | } |
484 | ||
d011e4e6 MZ |
485 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
486 | { | |
487 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
488 | } | |
489 | ||
490 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
491 | { | |
492 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
493 | } | |
494 | ||
495 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
496 | { | |
497 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
498 | } | |
499 | ||
500 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
501 | { | |
502 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
503 | } | |
504 | ||
3171a47a MZ |
505 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
506 | { | |
507 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
508 | } | |
509 | ||
510 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
511 | { | |
512 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
513 | } | |
514 | ||
eb78192b MZ |
515 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
516 | { | |
30ae9610 | 517 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); |
eb78192b MZ |
518 | } |
519 | ||
520 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
521 | { | |
522 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
523 | } | |
524 | ||
64edfaa9 MZ |
525 | static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa) |
526 | { | |
527 | its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); | |
528 | } | |
529 | ||
530 | static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc) | |
531 | { | |
532 | its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); | |
533 | } | |
534 | ||
535 | static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz) | |
536 | { | |
537 | its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); | |
538 | } | |
539 | ||
540 | static void its_encode_vmapp_default_db(struct its_cmd_block *cmd, | |
541 | u32 vpe_db_lpi) | |
542 | { | |
543 | its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); | |
544 | } | |
545 | ||
dd3f050a MZ |
546 | static void its_encode_vmovp_default_db(struct its_cmd_block *cmd, |
547 | u32 vpe_db_lpi) | |
548 | { | |
549 | its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); | |
550 | } | |
551 | ||
552 | static void its_encode_db(struct its_cmd_block *cmd, bool db) | |
553 | { | |
554 | its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); | |
555 | } | |
556 | ||
e252cf8a MZ |
557 | static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi) |
558 | { | |
559 | its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); | |
560 | } | |
561 | ||
562 | static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio) | |
563 | { | |
564 | its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); | |
565 | } | |
566 | ||
567 | static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp) | |
568 | { | |
569 | its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); | |
570 | } | |
571 | ||
572 | static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr) | |
573 | { | |
574 | its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); | |
575 | } | |
576 | ||
577 | static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en) | |
578 | { | |
579 | its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); | |
580 | } | |
581 | ||
cc2d3216 MZ |
582 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
583 | { | |
584 | /* Let's fixup BE commands */ | |
2bbdfcc5 BDC |
585 | cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); |
586 | cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
587 | cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
588 | cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
cc2d3216 MZ |
589 | } |
590 | ||
67047f90 MZ |
591 | static struct its_collection *its_build_mapd_cmd(struct its_node *its, |
592 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
593 | struct its_cmd_desc *desc) |
594 | { | |
595 | unsigned long itt_addr; | |
c8481267 | 596 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
597 | |
598 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
599 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
600 | ||
601 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
602 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
603 | its_encode_size(cmd, size - 1); | |
604 | its_encode_itt(cmd, itt_addr); | |
605 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
606 | ||
607 | its_fixup_cmd(cmd); | |
608 | ||
591e5bec | 609 | return NULL; |
cc2d3216 MZ |
610 | } |
611 | ||
67047f90 MZ |
612 | static struct its_collection *its_build_mapc_cmd(struct its_node *its, |
613 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
614 | struct its_cmd_desc *desc) |
615 | { | |
616 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
617 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
618 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
619 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
620 | ||
621 | its_fixup_cmd(cmd); | |
622 | ||
623 | return desc->its_mapc_cmd.col; | |
624 | } | |
625 | ||
67047f90 MZ |
626 | static struct its_collection *its_build_mapti_cmd(struct its_node *its, |
627 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
628 | struct its_cmd_desc *desc) |
629 | { | |
591e5bec MZ |
630 | struct its_collection *col; |
631 | ||
6a25ad3a MZ |
632 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
633 | desc->its_mapti_cmd.event_id); | |
591e5bec | 634 | |
6a25ad3a MZ |
635 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
636 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
637 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
638 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 639 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
640 | |
641 | its_fixup_cmd(cmd); | |
642 | ||
83559b47 | 643 | return valid_col(col); |
cc2d3216 MZ |
644 | } |
645 | ||
67047f90 MZ |
646 | static struct its_collection *its_build_movi_cmd(struct its_node *its, |
647 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
648 | struct its_cmd_desc *desc) |
649 | { | |
591e5bec MZ |
650 | struct its_collection *col; |
651 | ||
652 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
653 | desc->its_movi_cmd.event_id); | |
654 | ||
cc2d3216 MZ |
655 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
656 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 657 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
658 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
659 | ||
660 | its_fixup_cmd(cmd); | |
661 | ||
83559b47 | 662 | return valid_col(col); |
cc2d3216 MZ |
663 | } |
664 | ||
67047f90 MZ |
665 | static struct its_collection *its_build_discard_cmd(struct its_node *its, |
666 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
667 | struct its_cmd_desc *desc) |
668 | { | |
591e5bec MZ |
669 | struct its_collection *col; |
670 | ||
671 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
672 | desc->its_discard_cmd.event_id); | |
673 | ||
cc2d3216 MZ |
674 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
675 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
676 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
677 | ||
678 | its_fixup_cmd(cmd); | |
679 | ||
83559b47 | 680 | return valid_col(col); |
cc2d3216 MZ |
681 | } |
682 | ||
67047f90 MZ |
683 | static struct its_collection *its_build_inv_cmd(struct its_node *its, |
684 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
685 | struct its_cmd_desc *desc) |
686 | { | |
591e5bec MZ |
687 | struct its_collection *col; |
688 | ||
689 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
690 | desc->its_inv_cmd.event_id); | |
691 | ||
cc2d3216 MZ |
692 | its_encode_cmd(cmd, GITS_CMD_INV); |
693 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
694 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
695 | ||
696 | its_fixup_cmd(cmd); | |
697 | ||
83559b47 | 698 | return valid_col(col); |
cc2d3216 MZ |
699 | } |
700 | ||
67047f90 MZ |
701 | static struct its_collection *its_build_int_cmd(struct its_node *its, |
702 | struct its_cmd_block *cmd, | |
8d85dced MZ |
703 | struct its_cmd_desc *desc) |
704 | { | |
705 | struct its_collection *col; | |
706 | ||
707 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
708 | desc->its_int_cmd.event_id); | |
709 | ||
710 | its_encode_cmd(cmd, GITS_CMD_INT); | |
711 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
712 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
713 | ||
714 | its_fixup_cmd(cmd); | |
715 | ||
83559b47 | 716 | return valid_col(col); |
8d85dced MZ |
717 | } |
718 | ||
67047f90 MZ |
719 | static struct its_collection *its_build_clear_cmd(struct its_node *its, |
720 | struct its_cmd_block *cmd, | |
8d85dced MZ |
721 | struct its_cmd_desc *desc) |
722 | { | |
723 | struct its_collection *col; | |
724 | ||
725 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
726 | desc->its_clear_cmd.event_id); | |
727 | ||
728 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
729 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
730 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
731 | ||
732 | its_fixup_cmd(cmd); | |
733 | ||
83559b47 | 734 | return valid_col(col); |
8d85dced MZ |
735 | } |
736 | ||
67047f90 MZ |
737 | static struct its_collection *its_build_invall_cmd(struct its_node *its, |
738 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
739 | struct its_cmd_desc *desc) |
740 | { | |
741 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
10794522 | 742 | its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); |
cc2d3216 MZ |
743 | |
744 | its_fixup_cmd(cmd); | |
745 | ||
746 | return NULL; | |
747 | } | |
748 | ||
67047f90 MZ |
749 | static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, |
750 | struct its_cmd_block *cmd, | |
eb78192b MZ |
751 | struct its_cmd_desc *desc) |
752 | { | |
753 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
754 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
755 | ||
756 | its_fixup_cmd(cmd); | |
757 | ||
205e065d | 758 | return valid_vpe(its, desc->its_vinvall_cmd.vpe); |
eb78192b MZ |
759 | } |
760 | ||
67047f90 MZ |
761 | static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, |
762 | struct its_cmd_block *cmd, | |
eb78192b MZ |
763 | struct its_cmd_desc *desc) |
764 | { | |
64edfaa9 | 765 | unsigned long vpt_addr, vconf_addr; |
5c9a882e | 766 | u64 target; |
64edfaa9 | 767 | bool alloc; |
eb78192b MZ |
768 | |
769 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
770 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
771 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
64edfaa9 MZ |
772 | |
773 | if (!desc->its_vmapp_cmd.valid) { | |
774 | if (is_v4_1(its)) { | |
775 | alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); | |
776 | its_encode_alloc(cmd, alloc); | |
777 | } | |
778 | ||
779 | goto out; | |
780 | } | |
781 | ||
782 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
783 | target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; | |
784 | ||
5c9a882e | 785 | its_encode_target(cmd, target); |
eb78192b MZ |
786 | its_encode_vpt_addr(cmd, vpt_addr); |
787 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
788 | ||
64edfaa9 MZ |
789 | if (!is_v4_1(its)) |
790 | goto out; | |
791 | ||
792 | vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); | |
793 | ||
794 | alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); | |
795 | ||
796 | its_encode_alloc(cmd, alloc); | |
797 | ||
798 | /* We can only signal PTZ when alloc==1. Why do we have two bits? */ | |
799 | its_encode_ptz(cmd, alloc); | |
800 | its_encode_vconf_addr(cmd, vconf_addr); | |
801 | its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); | |
802 | ||
803 | out: | |
eb78192b MZ |
804 | its_fixup_cmd(cmd); |
805 | ||
205e065d | 806 | return valid_vpe(its, desc->its_vmapp_cmd.vpe); |
eb78192b MZ |
807 | } |
808 | ||
67047f90 MZ |
809 | static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, |
810 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
811 | struct its_cmd_desc *desc) |
812 | { | |
813 | u32 db; | |
814 | ||
3858d4df | 815 | if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) |
d011e4e6 MZ |
816 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; |
817 | else | |
818 | db = 1023; | |
819 | ||
820 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
821 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
822 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
823 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
824 | its_encode_db_phys_id(cmd, db); | |
825 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
826 | ||
827 | its_fixup_cmd(cmd); | |
828 | ||
205e065d | 829 | return valid_vpe(its, desc->its_vmapti_cmd.vpe); |
d011e4e6 MZ |
830 | } |
831 | ||
67047f90 MZ |
832 | static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, |
833 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
834 | struct its_cmd_desc *desc) |
835 | { | |
836 | u32 db; | |
837 | ||
3858d4df | 838 | if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) |
d011e4e6 MZ |
839 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; |
840 | else | |
841 | db = 1023; | |
842 | ||
843 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
844 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
845 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
846 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
847 | its_encode_db_phys_id(cmd, db); | |
848 | its_encode_db_valid(cmd, true); | |
849 | ||
850 | its_fixup_cmd(cmd); | |
851 | ||
205e065d | 852 | return valid_vpe(its, desc->its_vmovi_cmd.vpe); |
d011e4e6 MZ |
853 | } |
854 | ||
67047f90 MZ |
855 | static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, |
856 | struct its_cmd_block *cmd, | |
3171a47a MZ |
857 | struct its_cmd_desc *desc) |
858 | { | |
5c9a882e MZ |
859 | u64 target; |
860 | ||
861 | target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; | |
3171a47a MZ |
862 | its_encode_cmd(cmd, GITS_CMD_VMOVP); |
863 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
864 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
865 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
5c9a882e | 866 | its_encode_target(cmd, target); |
3171a47a | 867 | |
dd3f050a MZ |
868 | if (is_v4_1(its)) { |
869 | its_encode_db(cmd, true); | |
870 | its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); | |
871 | } | |
872 | ||
3171a47a MZ |
873 | its_fixup_cmd(cmd); |
874 | ||
205e065d | 875 | return valid_vpe(its, desc->its_vmovp_cmd.vpe); |
3171a47a MZ |
876 | } |
877 | ||
28614696 MZ |
878 | static struct its_vpe *its_build_vinv_cmd(struct its_node *its, |
879 | struct its_cmd_block *cmd, | |
880 | struct its_cmd_desc *desc) | |
881 | { | |
882 | struct its_vlpi_map *map; | |
883 | ||
884 | map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, | |
885 | desc->its_inv_cmd.event_id); | |
886 | ||
887 | its_encode_cmd(cmd, GITS_CMD_INV); | |
888 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
889 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
890 | ||
891 | its_fixup_cmd(cmd); | |
892 | ||
893 | return valid_vpe(its, map->vpe); | |
894 | } | |
895 | ||
ed0e4aa9 MZ |
896 | static struct its_vpe *its_build_vint_cmd(struct its_node *its, |
897 | struct its_cmd_block *cmd, | |
898 | struct its_cmd_desc *desc) | |
899 | { | |
900 | struct its_vlpi_map *map; | |
901 | ||
902 | map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, | |
903 | desc->its_int_cmd.event_id); | |
904 | ||
905 | its_encode_cmd(cmd, GITS_CMD_INT); | |
906 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
907 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
908 | ||
909 | its_fixup_cmd(cmd); | |
910 | ||
911 | return valid_vpe(its, map->vpe); | |
912 | } | |
913 | ||
914 | static struct its_vpe *its_build_vclear_cmd(struct its_node *its, | |
915 | struct its_cmd_block *cmd, | |
916 | struct its_cmd_desc *desc) | |
917 | { | |
918 | struct its_vlpi_map *map; | |
919 | ||
920 | map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, | |
921 | desc->its_clear_cmd.event_id); | |
922 | ||
923 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
924 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
925 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
926 | ||
927 | its_fixup_cmd(cmd); | |
928 | ||
929 | return valid_vpe(its, map->vpe); | |
930 | } | |
931 | ||
d97c97ba MZ |
932 | static struct its_vpe *its_build_invdb_cmd(struct its_node *its, |
933 | struct its_cmd_block *cmd, | |
934 | struct its_cmd_desc *desc) | |
935 | { | |
936 | if (WARN_ON(!is_v4_1(its))) | |
937 | return NULL; | |
938 | ||
939 | its_encode_cmd(cmd, GITS_CMD_INVDB); | |
940 | its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); | |
941 | ||
942 | its_fixup_cmd(cmd); | |
943 | ||
944 | return valid_vpe(its, desc->its_invdb_cmd.vpe); | |
945 | } | |
946 | ||
e252cf8a MZ |
947 | static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, |
948 | struct its_cmd_block *cmd, | |
949 | struct its_cmd_desc *desc) | |
950 | { | |
951 | if (WARN_ON(!is_v4_1(its))) | |
952 | return NULL; | |
953 | ||
954 | its_encode_cmd(cmd, GITS_CMD_VSGI); | |
955 | its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); | |
956 | its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); | |
957 | its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); | |
958 | its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); | |
959 | its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); | |
960 | its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); | |
961 | ||
962 | its_fixup_cmd(cmd); | |
963 | ||
964 | return valid_vpe(its, desc->its_vsgi_cmd.vpe); | |
965 | } | |
966 | ||
cc2d3216 MZ |
967 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
968 | struct its_cmd_block *ptr) | |
969 | { | |
970 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
971 | } | |
972 | ||
973 | static int its_queue_full(struct its_node *its) | |
974 | { | |
975 | int widx; | |
976 | int ridx; | |
977 | ||
978 | widx = its->cmd_write - its->cmd_base; | |
979 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
980 | ||
981 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
982 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
983 | return 1; | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
989 | { | |
990 | struct its_cmd_block *cmd; | |
991 | u32 count = 1000000; /* 1s! */ | |
992 | ||
993 | while (its_queue_full(its)) { | |
994 | count--; | |
995 | if (!count) { | |
996 | pr_err_ratelimited("ITS queue not draining\n"); | |
997 | return NULL; | |
998 | } | |
999 | cpu_relax(); | |
1000 | udelay(1); | |
1001 | } | |
1002 | ||
1003 | cmd = its->cmd_write++; | |
1004 | ||
1005 | /* Handle queue wrapping */ | |
1006 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
1007 | its->cmd_write = its->cmd_base; | |
1008 | ||
34d677a9 MZ |
1009 | /* Clear command */ |
1010 | cmd->raw_cmd[0] = 0; | |
1011 | cmd->raw_cmd[1] = 0; | |
1012 | cmd->raw_cmd[2] = 0; | |
1013 | cmd->raw_cmd[3] = 0; | |
1014 | ||
cc2d3216 MZ |
1015 | return cmd; |
1016 | } | |
1017 | ||
1018 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
1019 | { | |
1020 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
1021 | ||
1022 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
1023 | ||
1024 | return its->cmd_write; | |
1025 | } | |
1026 | ||
1027 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
1028 | { | |
1029 | /* | |
1030 | * Make sure the commands written to memory are observable by | |
1031 | * the ITS. | |
1032 | */ | |
1033 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 1034 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
1035 | else |
1036 | dsb(ishst); | |
1037 | } | |
1038 | ||
a19b462f | 1039 | static int its_wait_for_range_completion(struct its_node *its, |
a050fa54 | 1040 | u64 prev_idx, |
a19b462f | 1041 | struct its_cmd_block *to) |
cc2d3216 | 1042 | { |
a050fa54 | 1043 | u64 rd_idx, to_idx, linear_idx; |
cc2d3216 MZ |
1044 | u32 count = 1000000; /* 1s! */ |
1045 | ||
a050fa54 | 1046 | /* Linearize to_idx if the command set has wrapped around */ |
cc2d3216 | 1047 | to_idx = its_cmd_ptr_to_offset(its, to); |
a050fa54 HG |
1048 | if (to_idx < prev_idx) |
1049 | to_idx += ITS_CMD_QUEUE_SZ; | |
1050 | ||
1051 | linear_idx = prev_idx; | |
cc2d3216 MZ |
1052 | |
1053 | while (1) { | |
a050fa54 HG |
1054 | s64 delta; |
1055 | ||
cc2d3216 | 1056 | rd_idx = readl_relaxed(its->base + GITS_CREADR); |
9bdd8b1c | 1057 | |
a050fa54 HG |
1058 | /* |
1059 | * Compute the read pointer progress, taking the | |
1060 | * potential wrap-around into account. | |
1061 | */ | |
1062 | delta = rd_idx - prev_idx; | |
1063 | if (rd_idx < prev_idx) | |
1064 | delta += ITS_CMD_QUEUE_SZ; | |
9bdd8b1c | 1065 | |
a050fa54 HG |
1066 | linear_idx += delta; |
1067 | if (linear_idx >= to_idx) | |
cc2d3216 MZ |
1068 | break; |
1069 | ||
1070 | count--; | |
1071 | if (!count) { | |
a050fa54 HG |
1072 | pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", |
1073 | to_idx, linear_idx); | |
a19b462f | 1074 | return -1; |
cc2d3216 | 1075 | } |
a050fa54 | 1076 | prev_idx = rd_idx; |
cc2d3216 MZ |
1077 | cpu_relax(); |
1078 | udelay(1); | |
1079 | } | |
a19b462f MZ |
1080 | |
1081 | return 0; | |
cc2d3216 MZ |
1082 | } |
1083 | ||
e4f9094b MZ |
1084 | /* Warning, macro hell follows */ |
1085 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
1086 | void name(struct its_node *its, \ | |
1087 | buildtype builder, \ | |
1088 | struct its_cmd_desc *desc) \ | |
1089 | { \ | |
1090 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
1091 | synctype *sync_obj; \ | |
1092 | unsigned long flags; \ | |
a050fa54 | 1093 | u64 rd_idx; \ |
e4f9094b MZ |
1094 | \ |
1095 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
1096 | \ | |
1097 | cmd = its_allocate_entry(its); \ | |
1098 | if (!cmd) { /* We're soooooo screewed... */ \ | |
1099 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
1100 | return; \ | |
1101 | } \ | |
67047f90 | 1102 | sync_obj = builder(its, cmd, desc); \ |
e4f9094b MZ |
1103 | its_flush_cmd(its, cmd); \ |
1104 | \ | |
1105 | if (sync_obj) { \ | |
1106 | sync_cmd = its_allocate_entry(its); \ | |
1107 | if (!sync_cmd) \ | |
1108 | goto post; \ | |
1109 | \ | |
67047f90 | 1110 | buildfn(its, sync_cmd, sync_obj); \ |
e4f9094b MZ |
1111 | its_flush_cmd(its, sync_cmd); \ |
1112 | } \ | |
1113 | \ | |
1114 | post: \ | |
a050fa54 | 1115 | rd_idx = readl_relaxed(its->base + GITS_CREADR); \ |
e4f9094b MZ |
1116 | next_cmd = its_post_commands(its); \ |
1117 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
1118 | \ | |
a050fa54 | 1119 | if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \ |
a19b462f | 1120 | pr_err_ratelimited("ITS cmd %ps failed\n", builder); \ |
e4f9094b | 1121 | } |
cc2d3216 | 1122 | |
67047f90 MZ |
1123 | static void its_build_sync_cmd(struct its_node *its, |
1124 | struct its_cmd_block *sync_cmd, | |
e4f9094b MZ |
1125 | struct its_collection *sync_col) |
1126 | { | |
1127 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
1128 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 1129 | |
e4f9094b | 1130 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
1131 | } |
1132 | ||
e4f9094b MZ |
1133 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
1134 | struct its_collection, its_build_sync_cmd) | |
1135 | ||
67047f90 MZ |
1136 | static void its_build_vsync_cmd(struct its_node *its, |
1137 | struct its_cmd_block *sync_cmd, | |
d011e4e6 MZ |
1138 | struct its_vpe *sync_vpe) |
1139 | { | |
1140 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
1141 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
1142 | ||
1143 | its_fixup_cmd(sync_cmd); | |
1144 | } | |
1145 | ||
1146 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
1147 | struct its_vpe, its_build_vsync_cmd) | |
1148 | ||
8d85dced | 1149 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 1150 | { |
8d85dced | 1151 | struct its_cmd_desc desc; |
cc2d3216 | 1152 | |
8d85dced MZ |
1153 | desc.its_int_cmd.dev = dev; |
1154 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 1155 | |
8d85dced MZ |
1156 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
1157 | } | |
cc2d3216 | 1158 | |
8d85dced MZ |
1159 | static void its_send_clear(struct its_device *dev, u32 event_id) |
1160 | { | |
1161 | struct its_cmd_desc desc; | |
cc2d3216 | 1162 | |
8d85dced MZ |
1163 | desc.its_clear_cmd.dev = dev; |
1164 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 1165 | |
8d85dced | 1166 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
1167 | } |
1168 | ||
1169 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
1170 | { | |
1171 | struct its_cmd_desc desc; | |
1172 | ||
1173 | desc.its_inv_cmd.dev = dev; | |
1174 | desc.its_inv_cmd.event_id = event_id; | |
1175 | ||
1176 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
1177 | } | |
1178 | ||
1179 | static void its_send_mapd(struct its_device *dev, int valid) | |
1180 | { | |
1181 | struct its_cmd_desc desc; | |
1182 | ||
1183 | desc.its_mapd_cmd.dev = dev; | |
1184 | desc.its_mapd_cmd.valid = !!valid; | |
1185 | ||
1186 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
1187 | } | |
1188 | ||
1189 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
1190 | int valid) | |
1191 | { | |
1192 | struct its_cmd_desc desc; | |
1193 | ||
1194 | desc.its_mapc_cmd.col = col; | |
1195 | desc.its_mapc_cmd.valid = !!valid; | |
1196 | ||
1197 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
1198 | } | |
1199 | ||
6a25ad3a | 1200 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
1201 | { |
1202 | struct its_cmd_desc desc; | |
1203 | ||
6a25ad3a MZ |
1204 | desc.its_mapti_cmd.dev = dev; |
1205 | desc.its_mapti_cmd.phys_id = irq_id; | |
1206 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 1207 | |
6a25ad3a | 1208 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
1209 | } |
1210 | ||
1211 | static void its_send_movi(struct its_device *dev, | |
1212 | struct its_collection *col, u32 id) | |
1213 | { | |
1214 | struct its_cmd_desc desc; | |
1215 | ||
1216 | desc.its_movi_cmd.dev = dev; | |
1217 | desc.its_movi_cmd.col = col; | |
591e5bec | 1218 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
1219 | |
1220 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
1221 | } | |
1222 | ||
1223 | static void its_send_discard(struct its_device *dev, u32 id) | |
1224 | { | |
1225 | struct its_cmd_desc desc; | |
1226 | ||
1227 | desc.its_discard_cmd.dev = dev; | |
1228 | desc.its_discard_cmd.event_id = id; | |
1229 | ||
1230 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
1231 | } | |
1232 | ||
1233 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
1234 | { | |
1235 | struct its_cmd_desc desc; | |
1236 | ||
1237 | desc.its_invall_cmd.col = col; | |
1238 | ||
1239 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
1240 | } | |
c48ed51c | 1241 | |
d011e4e6 MZ |
1242 | static void its_send_vmapti(struct its_device *dev, u32 id) |
1243 | { | |
c1d4d5cd | 1244 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1245 | struct its_cmd_desc desc; |
1246 | ||
1247 | desc.its_vmapti_cmd.vpe = map->vpe; | |
1248 | desc.its_vmapti_cmd.dev = dev; | |
1249 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
1250 | desc.its_vmapti_cmd.event_id = id; | |
1251 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
1252 | ||
1253 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
1254 | } | |
1255 | ||
1256 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
1257 | { | |
c1d4d5cd | 1258 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1259 | struct its_cmd_desc desc; |
1260 | ||
1261 | desc.its_vmovi_cmd.vpe = map->vpe; | |
1262 | desc.its_vmovi_cmd.dev = dev; | |
1263 | desc.its_vmovi_cmd.event_id = id; | |
1264 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
1265 | ||
1266 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
1267 | } | |
1268 | ||
75fd951b MZ |
1269 | static void its_send_vmapp(struct its_node *its, |
1270 | struct its_vpe *vpe, bool valid) | |
eb78192b MZ |
1271 | { |
1272 | struct its_cmd_desc desc; | |
eb78192b MZ |
1273 | |
1274 | desc.its_vmapp_cmd.vpe = vpe; | |
1275 | desc.its_vmapp_cmd.valid = valid; | |
75fd951b | 1276 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; |
eb78192b | 1277 | |
75fd951b | 1278 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); |
eb78192b MZ |
1279 | } |
1280 | ||
3171a47a MZ |
1281 | static void its_send_vmovp(struct its_vpe *vpe) |
1282 | { | |
84243125 | 1283 | struct its_cmd_desc desc = {}; |
3171a47a MZ |
1284 | struct its_node *its; |
1285 | unsigned long flags; | |
1286 | int col_id = vpe->col_idx; | |
1287 | ||
1288 | desc.its_vmovp_cmd.vpe = vpe; | |
3171a47a MZ |
1289 | |
1290 | if (!its_list_map) { | |
1291 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
3171a47a MZ |
1292 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1293 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1294 | return; | |
1295 | } | |
1296 | ||
1297 | /* | |
1298 | * Yet another marvel of the architecture. If using the | |
1299 | * its_list "feature", we need to make sure that all ITSs | |
1300 | * receive all VMOVP commands in the same order. The only way | |
1301 | * to guarantee this is to make vmovp a serialization point. | |
1302 | * | |
1303 | * Wall <-- Head. | |
1304 | */ | |
1305 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1306 | ||
1307 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
84243125 | 1308 | desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); |
3171a47a MZ |
1309 | |
1310 | /* Emit VMOVPs */ | |
1311 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 1312 | if (!is_v4(its)) |
3171a47a MZ |
1313 | continue; |
1314 | ||
009384b3 | 1315 | if (!require_its_list_vmovp(vpe->its_vm, its)) |
2247e1bf MZ |
1316 | continue; |
1317 | ||
3171a47a MZ |
1318 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1319 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1320 | } | |
1321 | ||
1322 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1323 | } | |
1324 | ||
40619a2e | 1325 | static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) |
eb78192b MZ |
1326 | { |
1327 | struct its_cmd_desc desc; | |
eb78192b MZ |
1328 | |
1329 | desc.its_vinvall_cmd.vpe = vpe; | |
40619a2e | 1330 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); |
eb78192b MZ |
1331 | } |
1332 | ||
28614696 MZ |
1333 | static void its_send_vinv(struct its_device *dev, u32 event_id) |
1334 | { | |
1335 | struct its_cmd_desc desc; | |
1336 | ||
1337 | /* | |
1338 | * There is no real VINV command. This is just a normal INV, | |
1339 | * with a VSYNC instead of a SYNC. | |
1340 | */ | |
1341 | desc.its_inv_cmd.dev = dev; | |
1342 | desc.its_inv_cmd.event_id = event_id; | |
1343 | ||
1344 | its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); | |
1345 | } | |
1346 | ||
ed0e4aa9 MZ |
1347 | static void its_send_vint(struct its_device *dev, u32 event_id) |
1348 | { | |
1349 | struct its_cmd_desc desc; | |
1350 | ||
1351 | /* | |
1352 | * There is no real VINT command. This is just a normal INT, | |
1353 | * with a VSYNC instead of a SYNC. | |
1354 | */ | |
1355 | desc.its_int_cmd.dev = dev; | |
1356 | desc.its_int_cmd.event_id = event_id; | |
1357 | ||
1358 | its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); | |
1359 | } | |
1360 | ||
1361 | static void its_send_vclear(struct its_device *dev, u32 event_id) | |
1362 | { | |
1363 | struct its_cmd_desc desc; | |
1364 | ||
1365 | /* | |
1366 | * There is no real VCLEAR command. This is just a normal CLEAR, | |
1367 | * with a VSYNC instead of a SYNC. | |
1368 | */ | |
1369 | desc.its_clear_cmd.dev = dev; | |
1370 | desc.its_clear_cmd.event_id = event_id; | |
1371 | ||
1372 | its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); | |
1373 | } | |
1374 | ||
d97c97ba MZ |
1375 | static void its_send_invdb(struct its_node *its, struct its_vpe *vpe) |
1376 | { | |
1377 | struct its_cmd_desc desc; | |
1378 | ||
1379 | desc.its_invdb_cmd.vpe = vpe; | |
1380 | its_send_single_vcommand(its, its_build_invdb_cmd, &desc); | |
1381 | } | |
1382 | ||
c48ed51c MZ |
1383 | /* |
1384 | * irqchip functions - assumes MSI, mostly. | |
1385 | */ | |
015ec038 | 1386 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 1387 | { |
c1d4d5cd | 1388 | struct its_vlpi_map *map = get_vlpi_map(d); |
015ec038 | 1389 | irq_hw_number_t hwirq; |
e1a2e201 | 1390 | void *va; |
adcdb94e | 1391 | u8 *cfg; |
c48ed51c | 1392 | |
c1d4d5cd MZ |
1393 | if (map) { |
1394 | va = page_address(map->vm->vprop_page); | |
d4d7b4ad MZ |
1395 | hwirq = map->vintid; |
1396 | ||
1397 | /* Remember the updated property */ | |
1398 | map->properties &= ~clr; | |
1399 | map->properties |= set | LPI_PROP_GROUP1; | |
015ec038 | 1400 | } else { |
e1a2e201 | 1401 | va = gic_rdists->prop_table_va; |
015ec038 MZ |
1402 | hwirq = d->hwirq; |
1403 | } | |
adcdb94e | 1404 | |
e1a2e201 | 1405 | cfg = va + hwirq - 8192; |
adcdb94e | 1406 | *cfg &= ~clr; |
015ec038 | 1407 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1408 | |
1409 | /* | |
1410 | * Make the above write visible to the redistributors. | |
1411 | * And yes, we're flushing exactly: One. Single. Byte. | |
1412 | * Humpf... | |
1413 | */ | |
1414 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1415 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1416 | else |
1417 | dsb(ishst); | |
015ec038 MZ |
1418 | } |
1419 | ||
2f4f064b MZ |
1420 | static void wait_for_syncr(void __iomem *rdbase) |
1421 | { | |
04d80dbe | 1422 | while (readl_relaxed(rdbase + GICR_SYNCR) & 1) |
2f4f064b MZ |
1423 | cpu_relax(); |
1424 | } | |
1425 | ||
425c09be MZ |
1426 | static void direct_lpi_inv(struct irq_data *d) |
1427 | { | |
f4a81f5a | 1428 | struct its_vlpi_map *map = get_vlpi_map(d); |
425c09be | 1429 | void __iomem *rdbase; |
f3a05921 | 1430 | unsigned long flags; |
f4a81f5a | 1431 | u64 val; |
f3a05921 | 1432 | int cpu; |
f4a81f5a MZ |
1433 | |
1434 | if (map) { | |
1435 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1436 | ||
1437 | WARN_ON(!is_v4_1(its_dev->its)); | |
1438 | ||
1439 | val = GICR_INVLPIR_V; | |
1440 | val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); | |
1441 | val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); | |
1442 | } else { | |
1443 | val = d->hwirq; | |
1444 | } | |
425c09be MZ |
1445 | |
1446 | /* Target the redistributor this LPI is currently routed to */ | |
f3a05921 | 1447 | cpu = irq_to_cpuid_lock(d, &flags); |
9058a4e9 | 1448 | raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); |
f3a05921 | 1449 | rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; |
f4a81f5a | 1450 | gic_write_lpir(val, rdbase + GICR_INVLPIR); |
425c09be MZ |
1451 | |
1452 | wait_for_syncr(rdbase); | |
9058a4e9 | 1453 | raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); |
f3a05921 | 1454 | irq_to_cpuid_unlock(d, flags); |
425c09be MZ |
1455 | } |
1456 | ||
015ec038 MZ |
1457 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) |
1458 | { | |
1459 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1460 | ||
1461 | lpi_write_config(d, clr, set); | |
f4a81f5a MZ |
1462 | if (gic_rdists->has_direct_lpi && |
1463 | (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) | |
425c09be | 1464 | direct_lpi_inv(d); |
28614696 | 1465 | else if (!irqd_is_forwarded_to_vcpu(d)) |
425c09be | 1466 | its_send_inv(its_dev, its_get_event_id(d)); |
28614696 MZ |
1467 | else |
1468 | its_send_vinv(its_dev, its_get_event_id(d)); | |
c48ed51c MZ |
1469 | } |
1470 | ||
015ec038 MZ |
1471 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1472 | { | |
1473 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1474 | u32 event = its_get_event_id(d); | |
c1d4d5cd | 1475 | struct its_vlpi_map *map; |
015ec038 | 1476 | |
3858d4df MZ |
1477 | /* |
1478 | * GICv4.1 does away with the per-LPI nonsense, nothing to do | |
1479 | * here. | |
1480 | */ | |
1481 | if (is_v4_1(its_dev->its)) | |
1482 | return; | |
1483 | ||
c1d4d5cd MZ |
1484 | map = dev_event_to_vlpi_map(its_dev, event); |
1485 | ||
1486 | if (map->db_enabled == enable) | |
015ec038 MZ |
1487 | return; |
1488 | ||
c1d4d5cd | 1489 | map->db_enabled = enable; |
015ec038 MZ |
1490 | |
1491 | /* | |
1492 | * More fun with the architecture: | |
1493 | * | |
1494 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1495 | * value or to 1023, depending on the enable bit. But that | |
1496 | * would be issueing a mapping for an /existing/ DevID+EventID | |
1497 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
1498 | * to the /same/ vPE, using this opportunity to adjust the | |
1499 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1500 | */ | |
1501 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1502 | } |
1503 | ||
1504 | static void its_mask_irq(struct irq_data *d) | |
1505 | { | |
015ec038 MZ |
1506 | if (irqd_is_forwarded_to_vcpu(d)) |
1507 | its_vlpi_set_doorbell(d, false); | |
1508 | ||
adcdb94e | 1509 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1510 | } |
1511 | ||
1512 | static void its_unmask_irq(struct irq_data *d) | |
1513 | { | |
015ec038 MZ |
1514 | if (irqd_is_forwarded_to_vcpu(d)) |
1515 | its_vlpi_set_doorbell(d, true); | |
1516 | ||
adcdb94e | 1517 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1518 | } |
1519 | ||
2f13ff1d MZ |
1520 | static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu) |
1521 | { | |
1522 | if (irqd_affinity_is_managed(d)) | |
1523 | return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1524 | ||
1525 | return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1526 | } | |
1527 | ||
1528 | static void its_inc_lpi_count(struct irq_data *d, int cpu) | |
1529 | { | |
1530 | if (irqd_affinity_is_managed(d)) | |
1531 | atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1532 | else | |
1533 | atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1534 | } | |
1535 | ||
1536 | static void its_dec_lpi_count(struct irq_data *d, int cpu) | |
1537 | { | |
1538 | if (irqd_affinity_is_managed(d)) | |
1539 | atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1540 | else | |
1541 | atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1542 | } | |
1543 | ||
c5d6082d MZ |
1544 | static unsigned int cpumask_pick_least_loaded(struct irq_data *d, |
1545 | const struct cpumask *cpu_mask) | |
1546 | { | |
1547 | unsigned int cpu = nr_cpu_ids, tmp; | |
1548 | int count = S32_MAX; | |
1549 | ||
1550 | for_each_cpu(tmp, cpu_mask) { | |
1551 | int this_count = its_read_lpi_count(d, tmp); | |
1552 | if (this_count < count) { | |
1553 | cpu = tmp; | |
1554 | count = this_count; | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | return cpu; | |
1559 | } | |
1560 | ||
1561 | /* | |
1562 | * As suggested by Thomas Gleixner in: | |
1563 | * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de | |
1564 | */ | |
1565 | static int its_select_cpu(struct irq_data *d, | |
1566 | const struct cpumask *aff_mask) | |
1567 | { | |
1568 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1569 | cpumask_var_t tmpmask; | |
1570 | int cpu, node; | |
1571 | ||
1572 | if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC)) | |
1573 | return -ENOMEM; | |
1574 | ||
1575 | node = its_dev->its->numa_node; | |
1576 | ||
1577 | if (!irqd_affinity_is_managed(d)) { | |
1578 | /* First try the NUMA node */ | |
1579 | if (node != NUMA_NO_NODE) { | |
1580 | /* | |
1581 | * Try the intersection of the affinity mask and the | |
1582 | * node mask (and the online mask, just to be safe). | |
1583 | */ | |
1584 | cpumask_and(tmpmask, cpumask_of_node(node), aff_mask); | |
1585 | cpumask_and(tmpmask, tmpmask, cpu_online_mask); | |
1586 | ||
1587 | /* | |
1588 | * Ideally, we would check if the mask is empty, and | |
1589 | * try again on the full node here. | |
1590 | * | |
1591 | * But it turns out that the way ACPI describes the | |
1592 | * affinity for ITSs only deals about memory, and | |
1593 | * not target CPUs, so it cannot describe a single | |
1594 | * ITS placed next to two NUMA nodes. | |
1595 | * | |
1596 | * Instead, just fallback on the online mask. This | |
1597 | * diverges from Thomas' suggestion above. | |
1598 | */ | |
1599 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1600 | if (cpu < nr_cpu_ids) | |
1601 | goto out; | |
1602 | ||
1603 | /* If we can't cross sockets, give up */ | |
1604 | if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) | |
1605 | goto out; | |
1606 | ||
1607 | /* If the above failed, expand the search */ | |
1608 | } | |
1609 | ||
1610 | /* Try the intersection of the affinity and online masks */ | |
1611 | cpumask_and(tmpmask, aff_mask, cpu_online_mask); | |
1612 | ||
1613 | /* If that doesn't fly, the online mask is the last resort */ | |
1614 | if (cpumask_empty(tmpmask)) | |
1615 | cpumask_copy(tmpmask, cpu_online_mask); | |
1616 | ||
1617 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1618 | } else { | |
1619 | cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask); | |
1620 | ||
1621 | /* If we cannot cross sockets, limit the search to that node */ | |
1622 | if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && | |
1623 | node != NUMA_NO_NODE) | |
1624 | cpumask_and(tmpmask, tmpmask, cpumask_of_node(node)); | |
1625 | ||
1626 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1627 | } | |
1628 | out: | |
1629 | free_cpumask_var(tmpmask); | |
1630 | ||
1631 | pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); | |
1632 | return cpu; | |
1633 | } | |
1634 | ||
c48ed51c MZ |
1635 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1636 | bool force) | |
1637 | { | |
c48ed51c MZ |
1638 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1639 | struct its_collection *target_col; | |
1640 | u32 id = its_get_event_id(d); | |
c5d6082d | 1641 | int cpu, prev_cpu; |
c48ed51c | 1642 | |
015ec038 MZ |
1643 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1644 | if (irqd_is_forwarded_to_vcpu(d)) | |
1645 | return -EINVAL; | |
1646 | ||
2f13ff1d MZ |
1647 | prev_cpu = its_dev->event_map.col_map[id]; |
1648 | its_dec_lpi_count(d, prev_cpu); | |
1649 | ||
c5d6082d MZ |
1650 | if (!force) |
1651 | cpu = its_select_cpu(d, mask_val); | |
1652 | else | |
1653 | cpu = cpumask_pick_least_loaded(d, mask_val); | |
fbf8f40e | 1654 | |
c5d6082d | 1655 | if (cpu < 0 || cpu >= nr_cpu_ids) |
2f13ff1d | 1656 | goto err; |
c48ed51c | 1657 | |
8b8d94a7 | 1658 | /* don't set the affinity when the target cpu is same as current one */ |
2f13ff1d | 1659 | if (cpu != prev_cpu) { |
8b8d94a7 M |
1660 | target_col = &its_dev->its->collections[cpu]; |
1661 | its_send_movi(its_dev, target_col, id); | |
1662 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1663 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1664 | } |
c48ed51c | 1665 | |
2f13ff1d MZ |
1666 | its_inc_lpi_count(d, cpu); |
1667 | ||
c48ed51c | 1668 | return IRQ_SET_MASK_OK_DONE; |
2f13ff1d MZ |
1669 | |
1670 | err: | |
1671 | its_inc_lpi_count(d, prev_cpu); | |
1672 | return -EINVAL; | |
c48ed51c MZ |
1673 | } |
1674 | ||
558b0165 AB |
1675 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1676 | { | |
1677 | struct its_node *its = its_dev->its; | |
1678 | ||
1679 | return its->phys_base + GITS_TRANSLATER; | |
1680 | } | |
1681 | ||
b48ac83d MZ |
1682 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1683 | { | |
1684 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1685 | struct its_node *its; | |
1686 | u64 addr; | |
1687 | ||
1688 | its = its_dev->its; | |
558b0165 | 1689 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1690 | |
b11283eb VM |
1691 | msg->address_lo = lower_32_bits(addr); |
1692 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1693 | msg->data = its_get_event_id(d); |
44bb7e24 | 1694 | |
35ae7df2 | 1695 | iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); |
b48ac83d MZ |
1696 | } |
1697 | ||
8d85dced MZ |
1698 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1699 | enum irqchip_irq_state which, | |
1700 | bool state) | |
1701 | { | |
1702 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1703 | u32 event = its_get_event_id(d); | |
1704 | ||
1705 | if (which != IRQCHIP_STATE_PENDING) | |
1706 | return -EINVAL; | |
1707 | ||
ed0e4aa9 MZ |
1708 | if (irqd_is_forwarded_to_vcpu(d)) { |
1709 | if (state) | |
1710 | its_send_vint(its_dev, event); | |
1711 | else | |
1712 | its_send_vclear(its_dev, event); | |
1713 | } else { | |
1714 | if (state) | |
1715 | its_send_int(its_dev, event); | |
1716 | else | |
1717 | its_send_clear(its_dev, event); | |
1718 | } | |
8d85dced MZ |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | ||
009384b3 MZ |
1723 | /* |
1724 | * Two favourable cases: | |
1725 | * | |
1726 | * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times | |
1727 | * for vSGI delivery | |
1728 | * | |
1729 | * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough | |
1730 | * and we're better off mapping all VPEs always | |
1731 | * | |
1732 | * If neither (a) nor (b) is true, then we map vPEs on demand. | |
1733 | * | |
1734 | */ | |
1735 | static bool gic_requires_eager_mapping(void) | |
1736 | { | |
1737 | if (!its_list_map || gic_rdists->has_rvpeid) | |
1738 | return true; | |
1739 | ||
1740 | return false; | |
1741 | } | |
1742 | ||
2247e1bf MZ |
1743 | static void its_map_vm(struct its_node *its, struct its_vm *vm) |
1744 | { | |
1745 | unsigned long flags; | |
1746 | ||
009384b3 | 1747 | if (gic_requires_eager_mapping()) |
2247e1bf MZ |
1748 | return; |
1749 | ||
1750 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1751 | ||
1752 | /* | |
1753 | * If the VM wasn't mapped yet, iterate over the vpes and get | |
1754 | * them mapped now. | |
1755 | */ | |
1756 | vm->vlpi_count[its->list_nr]++; | |
1757 | ||
1758 | if (vm->vlpi_count[its->list_nr] == 1) { | |
1759 | int i; | |
1760 | ||
1761 | for (i = 0; i < vm->nr_vpes; i++) { | |
1762 | struct its_vpe *vpe = vm->vpes[i]; | |
44c4c25e | 1763 | struct irq_data *d = irq_get_irq_data(vpe->irq); |
2247e1bf MZ |
1764 | |
1765 | /* Map the VPE to the first possible CPU */ | |
1766 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
1767 | its_send_vmapp(its, vpe, true); | |
1768 | its_send_vinvall(its, vpe); | |
44c4c25e | 1769 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
2247e1bf MZ |
1770 | } |
1771 | } | |
1772 | ||
1773 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1774 | } | |
1775 | ||
1776 | static void its_unmap_vm(struct its_node *its, struct its_vm *vm) | |
1777 | { | |
1778 | unsigned long flags; | |
1779 | ||
1780 | /* Not using the ITS list? Everything is always mapped. */ | |
009384b3 | 1781 | if (gic_requires_eager_mapping()) |
2247e1bf MZ |
1782 | return; |
1783 | ||
1784 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1785 | ||
1786 | if (!--vm->vlpi_count[its->list_nr]) { | |
1787 | int i; | |
1788 | ||
1789 | for (i = 0; i < vm->nr_vpes; i++) | |
1790 | its_send_vmapp(its, vm->vpes[i], false); | |
1791 | } | |
1792 | ||
1793 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1794 | } | |
1795 | ||
d011e4e6 MZ |
1796 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1797 | { | |
1798 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1799 | u32 event = its_get_event_id(d); | |
1800 | int ret = 0; | |
1801 | ||
1802 | if (!info->map) | |
1803 | return -EINVAL; | |
1804 | ||
11635fa2 | 1805 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1806 | |
1807 | if (!its_dev->event_map.vm) { | |
1808 | struct its_vlpi_map *maps; | |
1809 | ||
6396bb22 | 1810 | maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), |
11635fa2 | 1811 | GFP_ATOMIC); |
d011e4e6 MZ |
1812 | if (!maps) { |
1813 | ret = -ENOMEM; | |
1814 | goto out; | |
1815 | } | |
1816 | ||
1817 | its_dev->event_map.vm = info->map->vm; | |
1818 | its_dev->event_map.vlpi_maps = maps; | |
1819 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1820 | ret = -EINVAL; | |
1821 | goto out; | |
1822 | } | |
1823 | ||
1824 | /* Get our private copy of the mapping information */ | |
1825 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1826 | ||
1827 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1828 | /* Already mapped, move it around */ | |
1829 | its_send_vmovi(its_dev, event); | |
1830 | } else { | |
2247e1bf MZ |
1831 | /* Ensure all the VPEs are mapped on this ITS */ |
1832 | its_map_vm(its_dev->its, info->map->vm); | |
1833 | ||
d4d7b4ad MZ |
1834 | /* |
1835 | * Flag the interrupt as forwarded so that we can | |
1836 | * start poking the virtual property table. | |
1837 | */ | |
1838 | irqd_set_forwarded_to_vcpu(d); | |
1839 | ||
1840 | /* Write out the property to the prop table */ | |
1841 | lpi_write_config(d, 0xff, info->map->properties); | |
1842 | ||
d011e4e6 MZ |
1843 | /* Drop the physical mapping */ |
1844 | its_send_discard(its_dev, event); | |
1845 | ||
1846 | /* and install the virtual one */ | |
1847 | its_send_vmapti(its_dev, event); | |
d011e4e6 MZ |
1848 | |
1849 | /* Increment the number of VLPIs */ | |
1850 | its_dev->event_map.nr_vlpis++; | |
1851 | } | |
1852 | ||
1853 | out: | |
11635fa2 | 1854 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1855 | return ret; |
1856 | } | |
1857 | ||
1858 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1859 | { | |
1860 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
046b5054 | 1861 | struct its_vlpi_map *map; |
d011e4e6 MZ |
1862 | int ret = 0; |
1863 | ||
11635fa2 | 1864 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 | 1865 | |
046b5054 MZ |
1866 | map = get_vlpi_map(d); |
1867 | ||
1868 | if (!its_dev->event_map.vm || !map) { | |
d011e4e6 MZ |
1869 | ret = -EINVAL; |
1870 | goto out; | |
1871 | } | |
1872 | ||
1873 | /* Copy our mapping information to the incoming request */ | |
c1d4d5cd | 1874 | *info->map = *map; |
d011e4e6 MZ |
1875 | |
1876 | out: | |
11635fa2 | 1877 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1878 | return ret; |
1879 | } | |
1880 | ||
1881 | static int its_vlpi_unmap(struct irq_data *d) | |
1882 | { | |
1883 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1884 | u32 event = its_get_event_id(d); | |
1885 | int ret = 0; | |
1886 | ||
11635fa2 | 1887 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1888 | |
1889 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1890 | ret = -EINVAL; | |
1891 | goto out; | |
1892 | } | |
1893 | ||
1894 | /* Drop the virtual mapping */ | |
1895 | its_send_discard(its_dev, event); | |
1896 | ||
1897 | /* and restore the physical one */ | |
1898 | irqd_clr_forwarded_to_vcpu(d); | |
1899 | its_send_mapti(its_dev, d->hwirq, event); | |
1900 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1901 | LPI_PROP_ENABLED | | |
1902 | LPI_PROP_GROUP1)); | |
1903 | ||
2247e1bf MZ |
1904 | /* Potentially unmap the VM from this ITS */ |
1905 | its_unmap_vm(its_dev->its, its_dev->event_map.vm); | |
1906 | ||
d011e4e6 MZ |
1907 | /* |
1908 | * Drop the refcount and make the device available again if | |
1909 | * this was the last VLPI. | |
1910 | */ | |
1911 | if (!--its_dev->event_map.nr_vlpis) { | |
1912 | its_dev->event_map.vm = NULL; | |
1913 | kfree(its_dev->event_map.vlpi_maps); | |
1914 | } | |
1915 | ||
1916 | out: | |
11635fa2 | 1917 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1918 | return ret; |
1919 | } | |
1920 | ||
015ec038 MZ |
1921 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1922 | { | |
1923 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1924 | ||
1925 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1926 | return -EINVAL; | |
1927 | ||
1928 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1929 | lpi_update_config(d, 0xff, info->config); | |
1930 | else | |
1931 | lpi_write_config(d, 0xff, info->config); | |
1932 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
c808eea8 MZ |
1937 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1938 | { | |
1939 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1940 | struct its_cmd_info *info = vcpu_info; | |
1941 | ||
1942 | /* Need a v4 ITS */ | |
0dd57fed | 1943 | if (!is_v4(its_dev->its)) |
c808eea8 MZ |
1944 | return -EINVAL; |
1945 | ||
d011e4e6 MZ |
1946 | /* Unmap request? */ |
1947 | if (!info) | |
1948 | return its_vlpi_unmap(d); | |
1949 | ||
c808eea8 MZ |
1950 | switch (info->cmd_type) { |
1951 | case MAP_VLPI: | |
d011e4e6 | 1952 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1953 | |
1954 | case GET_VLPI: | |
d011e4e6 | 1955 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1956 | |
1957 | case PROP_UPDATE_VLPI: | |
1958 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1959 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1960 | |
1961 | default: | |
1962 | return -EINVAL; | |
1963 | } | |
1964 | } | |
1965 | ||
c48ed51c MZ |
1966 | static struct irq_chip its_irq_chip = { |
1967 | .name = "ITS", | |
1968 | .irq_mask = its_mask_irq, | |
1969 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1970 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1971 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1972 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1973 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1974 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1975 | }; |
1976 | ||
880cb3cd | 1977 | |
bf9529f8 MZ |
1978 | /* |
1979 | * How we allocate LPIs: | |
1980 | * | |
880cb3cd MZ |
1981 | * lpi_range_list contains ranges of LPIs that are to available to |
1982 | * allocate from. To allocate LPIs, just pick the first range that | |
1983 | * fits the required allocation, and reduce it by the required | |
1984 | * amount. Once empty, remove the range from the list. | |
1985 | * | |
1986 | * To free a range of LPIs, add a free range to the list, sort it and | |
1987 | * merge the result if the new range happens to be adjacent to an | |
1988 | * already free block. | |
bf9529f8 | 1989 | * |
880cb3cd MZ |
1990 | * The consequence of the above is that allocation is cost is low, but |
1991 | * freeing is expensive. We assumes that freeing rarely occurs. | |
1992 | */ | |
4cb205c0 | 1993 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
880cb3cd | 1994 | |
880cb3cd MZ |
1995 | static DEFINE_MUTEX(lpi_range_lock); |
1996 | static LIST_HEAD(lpi_range_list); | |
1997 | ||
1998 | struct lpi_range { | |
1999 | struct list_head entry; | |
2000 | u32 base_id; | |
2001 | u32 span; | |
2002 | }; | |
bf9529f8 | 2003 | |
880cb3cd | 2004 | static struct lpi_range *mk_lpi_range(u32 base, u32 span) |
bf9529f8 | 2005 | { |
880cb3cd MZ |
2006 | struct lpi_range *range; |
2007 | ||
1c73fac5 | 2008 | range = kmalloc(sizeof(*range), GFP_KERNEL); |
880cb3cd | 2009 | if (range) { |
880cb3cd MZ |
2010 | range->base_id = base; |
2011 | range->span = span; | |
2012 | } | |
2013 | ||
2014 | return range; | |
bf9529f8 MZ |
2015 | } |
2016 | ||
880cb3cd MZ |
2017 | static int alloc_lpi_range(u32 nr_lpis, u32 *base) |
2018 | { | |
2019 | struct lpi_range *range, *tmp; | |
2020 | int err = -ENOSPC; | |
2021 | ||
2022 | mutex_lock(&lpi_range_lock); | |
2023 | ||
2024 | list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) { | |
2025 | if (range->span >= nr_lpis) { | |
2026 | *base = range->base_id; | |
2027 | range->base_id += nr_lpis; | |
2028 | range->span -= nr_lpis; | |
2029 | ||
2030 | if (range->span == 0) { | |
2031 | list_del(&range->entry); | |
2032 | kfree(range); | |
2033 | } | |
2034 | ||
2035 | err = 0; | |
2036 | break; | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | mutex_unlock(&lpi_range_lock); | |
2041 | ||
2042 | pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); | |
2043 | return err; | |
bf9529f8 MZ |
2044 | } |
2045 | ||
12eade12 RV |
2046 | static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b) |
2047 | { | |
2048 | if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) | |
2049 | return; | |
2050 | if (a->base_id + a->span != b->base_id) | |
2051 | return; | |
2052 | b->base_id = a->base_id; | |
2053 | b->span += a->span; | |
2054 | list_del(&a->entry); | |
2055 | kfree(a); | |
2056 | } | |
2057 | ||
880cb3cd | 2058 | static int free_lpi_range(u32 base, u32 nr_lpis) |
bf9529f8 | 2059 | { |
12eade12 | 2060 | struct lpi_range *new, *old; |
880cb3cd MZ |
2061 | |
2062 | new = mk_lpi_range(base, nr_lpis); | |
b31a3838 RV |
2063 | if (!new) |
2064 | return -ENOMEM; | |
880cb3cd MZ |
2065 | |
2066 | mutex_lock(&lpi_range_lock); | |
2067 | ||
12eade12 RV |
2068 | list_for_each_entry_reverse(old, &lpi_range_list, entry) { |
2069 | if (old->base_id < base) | |
2070 | break; | |
880cb3cd | 2071 | } |
12eade12 RV |
2072 | /* |
2073 | * old is the last element with ->base_id smaller than base, | |
2074 | * so new goes right after it. If there are no elements with | |
2075 | * ->base_id smaller than base, &old->entry ends up pointing | |
2076 | * at the head of the list, and inserting new it the start of | |
2077 | * the list is the right thing to do in that case as well. | |
2078 | */ | |
2079 | list_add(&new->entry, &old->entry); | |
2080 | /* | |
2081 | * Now check if we can merge with the preceding and/or | |
2082 | * following ranges. | |
2083 | */ | |
2084 | merge_lpi_ranges(old, new); | |
2085 | merge_lpi_ranges(new, list_next_entry(new, entry)); | |
880cb3cd | 2086 | |
880cb3cd | 2087 | mutex_unlock(&lpi_range_lock); |
b31a3838 | 2088 | return 0; |
880cb3cd MZ |
2089 | } |
2090 | ||
2091 | static int __init its_lpi_init(u32 id_bits) | |
2092 | { | |
2093 | u32 lpis = (1UL << id_bits) - 8192; | |
12b2905a | 2094 | u32 numlpis; |
880cb3cd MZ |
2095 | int err; |
2096 | ||
12b2905a MZ |
2097 | numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); |
2098 | ||
2099 | if (numlpis > 2 && !WARN_ON(numlpis > lpis)) { | |
2100 | lpis = numlpis; | |
2101 | pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", | |
2102 | lpis); | |
2103 | } | |
2104 | ||
880cb3cd MZ |
2105 | /* |
2106 | * Initializing the allocator is just the same as freeing the | |
2107 | * full range of LPIs. | |
2108 | */ | |
2109 | err = free_lpi_range(8192, lpis); | |
2110 | pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); | |
2111 | return err; | |
2112 | } | |
bf9529f8 | 2113 | |
38dd7c49 | 2114 | static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids) |
880cb3cd MZ |
2115 | { |
2116 | unsigned long *bitmap = NULL; | |
2117 | int err = 0; | |
bf9529f8 MZ |
2118 | |
2119 | do { | |
38dd7c49 | 2120 | err = alloc_lpi_range(nr_irqs, base); |
880cb3cd | 2121 | if (!err) |
bf9529f8 MZ |
2122 | break; |
2123 | ||
38dd7c49 MZ |
2124 | nr_irqs /= 2; |
2125 | } while (nr_irqs > 0); | |
bf9529f8 | 2126 | |
45725e0f MZ |
2127 | if (!nr_irqs) |
2128 | err = -ENOSPC; | |
2129 | ||
880cb3cd | 2130 | if (err) |
bf9529f8 MZ |
2131 | goto out; |
2132 | ||
38dd7c49 | 2133 | bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC); |
bf9529f8 MZ |
2134 | if (!bitmap) |
2135 | goto out; | |
2136 | ||
38dd7c49 | 2137 | *nr_ids = nr_irqs; |
bf9529f8 MZ |
2138 | |
2139 | out: | |
c8415b94 MZ |
2140 | if (!bitmap) |
2141 | *base = *nr_ids = 0; | |
2142 | ||
bf9529f8 MZ |
2143 | return bitmap; |
2144 | } | |
2145 | ||
38dd7c49 | 2146 | static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids) |
bf9529f8 | 2147 | { |
880cb3cd | 2148 | WARN_ON(free_lpi_range(base, nr_ids)); |
cf2be8ba | 2149 | kfree(bitmap); |
bf9529f8 | 2150 | } |
1ac19ca6 | 2151 | |
053be485 MZ |
2152 | static void gic_reset_prop_table(void *va) |
2153 | { | |
2154 | /* Priority 0xa0, Group-1, disabled */ | |
2155 | memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ); | |
2156 | ||
2157 | /* Make sure the GIC will observe the written configuration */ | |
2158 | gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ); | |
2159 | } | |
2160 | ||
0e5ccf91 MZ |
2161 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
2162 | { | |
2163 | struct page *prop_page; | |
1ac19ca6 | 2164 | |
0e5ccf91 MZ |
2165 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
2166 | if (!prop_page) | |
2167 | return NULL; | |
2168 | ||
053be485 | 2169 | gic_reset_prop_table(page_address(prop_page)); |
0e5ccf91 MZ |
2170 | |
2171 | return prop_page; | |
2172 | } | |
2173 | ||
7d75bbb4 MZ |
2174 | static void its_free_prop_table(struct page *prop_page) |
2175 | { | |
2176 | free_pages((unsigned long)page_address(prop_page), | |
2177 | get_order(LPI_PROPBASE_SZ)); | |
2178 | } | |
1ac19ca6 | 2179 | |
5e2c9f9a MZ |
2180 | static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) |
2181 | { | |
2182 | phys_addr_t start, end, addr_end; | |
2183 | u64 i; | |
2184 | ||
2185 | /* | |
2186 | * We don't bother checking for a kdump kernel as by | |
2187 | * construction, the LPI tables are out of this kernel's | |
2188 | * memory map. | |
2189 | */ | |
2190 | if (is_kdump_kernel()) | |
2191 | return true; | |
2192 | ||
2193 | addr_end = addr + size - 1; | |
2194 | ||
2195 | for_each_reserved_mem_region(i, &start, &end) { | |
2196 | if (addr >= start && addr_end <= end) | |
2197 | return true; | |
2198 | } | |
2199 | ||
2200 | /* Not found, not a good sign... */ | |
2201 | pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n", | |
2202 | &addr, &addr_end); | |
2203 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
2204 | return false; | |
2205 | } | |
2206 | ||
3fb68fae MZ |
2207 | static int gic_reserve_range(phys_addr_t addr, unsigned long size) |
2208 | { | |
2209 | if (efi_enabled(EFI_CONFIG_TABLES)) | |
2210 | return efi_mem_reserve_persistent(addr, size); | |
2211 | ||
2212 | return 0; | |
2213 | } | |
2214 | ||
11e37d35 | 2215 | static int __init its_setup_lpi_prop_table(void) |
1ac19ca6 | 2216 | { |
c440a9d9 MZ |
2217 | if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { |
2218 | u64 val; | |
1ac19ca6 | 2219 | |
c440a9d9 MZ |
2220 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); |
2221 | lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1; | |
1ac19ca6 | 2222 | |
c440a9d9 MZ |
2223 | gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); |
2224 | gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, | |
2225 | LPI_PROPBASE_SZ, | |
2226 | MEMREMAP_WB); | |
2227 | gic_reset_prop_table(gic_rdists->prop_table_va); | |
2228 | } else { | |
2229 | struct page *page; | |
2230 | ||
2231 | lpi_id_bits = min_t(u32, | |
2232 | GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), | |
2233 | ITS_MAX_LPI_NRBITS); | |
2234 | page = its_allocate_prop_table(GFP_NOWAIT); | |
2235 | if (!page) { | |
2236 | pr_err("Failed to allocate PROPBASE\n"); | |
2237 | return -ENOMEM; | |
2238 | } | |
2239 | ||
2240 | gic_rdists->prop_table_pa = page_to_phys(page); | |
2241 | gic_rdists->prop_table_va = page_address(page); | |
3fb68fae MZ |
2242 | WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, |
2243 | LPI_PROPBASE_SZ)); | |
c440a9d9 | 2244 | } |
e1a2e201 MZ |
2245 | |
2246 | pr_info("GICv3: using LPI property table @%pa\n", | |
2247 | &gic_rdists->prop_table_pa); | |
1ac19ca6 | 2248 | |
6c31e123 | 2249 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
2250 | } |
2251 | ||
2252 | static const char *its_base_type_string[] = { | |
2253 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
2254 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 2255 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
2256 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
2257 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
2258 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
2259 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
2260 | }; | |
2261 | ||
2d81d425 SD |
2262 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
2263 | { | |
2264 | u32 idx = baser - its->tables; | |
2265 | ||
0968a619 | 2266 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
2267 | } |
2268 | ||
2269 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
2270 | u64 val) | |
2271 | { | |
2272 | u32 idx = baser - its->tables; | |
2273 | ||
0968a619 | 2274 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
2275 | baser->val = its_read_baser(its, baser); |
2276 | } | |
2277 | ||
9347359a | 2278 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
d5df9dc9 | 2279 | u64 cache, u64 shr, u32 order, bool indirect) |
9347359a SD |
2280 | { |
2281 | u64 val = its_read_baser(its, baser); | |
2282 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
2283 | u64 type = GITS_BASER_TYPE(val); | |
30ae9610 | 2284 | u64 baser_phys, tmp; |
d5df9dc9 | 2285 | u32 alloc_pages, psz; |
539d3782 | 2286 | struct page *page; |
9347359a | 2287 | void *base; |
9347359a | 2288 | |
d5df9dc9 | 2289 | psz = baser->psz; |
9347359a SD |
2290 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); |
2291 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
2292 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
2293 | &its->phys_base, its_base_type_string[type], | |
2294 | alloc_pages, GITS_BASER_PAGES_MAX); | |
2295 | alloc_pages = GITS_BASER_PAGES_MAX; | |
2296 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
2297 | } | |
2298 | ||
539d3782 SD |
2299 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); |
2300 | if (!page) | |
9347359a SD |
2301 | return -ENOMEM; |
2302 | ||
539d3782 | 2303 | base = (void *)page_address(page); |
30ae9610 SD |
2304 | baser_phys = virt_to_phys(base); |
2305 | ||
2306 | /* Check if the physical address of the memory is above 48bits */ | |
2307 | if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) { | |
2308 | ||
2309 | /* 52bit PA is supported only when PageSize=64K */ | |
2310 | if (psz != SZ_64K) { | |
2311 | pr_err("ITS: no 52bit PA support when psz=%d\n", psz); | |
2312 | free_pages((unsigned long)base, order); | |
2313 | return -ENXIO; | |
2314 | } | |
2315 | ||
2316 | /* Convert 52bit PA to 48bit field */ | |
2317 | baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys); | |
2318 | } | |
2319 | ||
9347359a | 2320 | retry_baser: |
30ae9610 | 2321 | val = (baser_phys | |
9347359a SD |
2322 | (type << GITS_BASER_TYPE_SHIFT) | |
2323 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
2324 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
2325 | cache | | |
2326 | shr | | |
2327 | GITS_BASER_VALID); | |
2328 | ||
3faf24ea SD |
2329 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
2330 | ||
9347359a SD |
2331 | switch (psz) { |
2332 | case SZ_4K: | |
2333 | val |= GITS_BASER_PAGE_SIZE_4K; | |
2334 | break; | |
2335 | case SZ_16K: | |
2336 | val |= GITS_BASER_PAGE_SIZE_16K; | |
2337 | break; | |
2338 | case SZ_64K: | |
2339 | val |= GITS_BASER_PAGE_SIZE_64K; | |
2340 | break; | |
2341 | } | |
2342 | ||
2343 | its_write_baser(its, baser, val); | |
2344 | tmp = baser->val; | |
2345 | ||
2346 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
2347 | /* | |
2348 | * Shareability didn't stick. Just use | |
2349 | * whatever the read reported, which is likely | |
2350 | * to be the only thing this redistributor | |
2351 | * supports. If that's zero, make it | |
2352 | * non-cacheable as well. | |
2353 | */ | |
2354 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
2355 | if (!shr) { | |
2356 | cache = GITS_BASER_nC; | |
328191c0 | 2357 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
2358 | } |
2359 | goto retry_baser; | |
2360 | } | |
2361 | ||
9347359a | 2362 | if (val != tmp) { |
b11283eb | 2363 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 2364 | &its->phys_base, its_base_type_string[type], |
b11283eb | 2365 | val, tmp); |
9347359a SD |
2366 | free_pages((unsigned long)base, order); |
2367 | return -ENXIO; | |
2368 | } | |
2369 | ||
2370 | baser->order = order; | |
2371 | baser->base = base; | |
2372 | baser->psz = psz; | |
3faf24ea | 2373 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 2374 | |
3faf24ea | 2375 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 2376 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
2377 | its_base_type_string[type], |
2378 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 2379 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
2380 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
2381 | ||
2382 | return 0; | |
2383 | } | |
2384 | ||
4cacac57 MZ |
2385 | static bool its_parse_indirect_baser(struct its_node *its, |
2386 | struct its_baser *baser, | |
d5df9dc9 | 2387 | u32 *order, u32 ids) |
4b75c459 | 2388 | { |
4cacac57 MZ |
2389 | u64 tmp = its_read_baser(its, baser); |
2390 | u64 type = GITS_BASER_TYPE(tmp); | |
2391 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 2392 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 | 2393 | u32 new_order = *order; |
d5df9dc9 | 2394 | u32 psz = baser->psz; |
3faf24ea SD |
2395 | bool indirect = false; |
2396 | ||
2397 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
2398 | if ((esz << ids) > (psz * 2)) { | |
2399 | /* | |
2400 | * Find out whether hw supports a single or two-level table by | |
2401 | * table by reading bit at offset '62' after writing '1' to it. | |
2402 | */ | |
2403 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
2404 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
2405 | ||
2406 | if (indirect) { | |
2407 | /* | |
2408 | * The size of the lvl2 table is equal to ITS page size | |
2409 | * which is 'psz'. For computing lvl1 table size, | |
2410 | * subtract ID bits that sparse lvl2 table from 'ids' | |
2411 | * which is reported by ITS hardware times lvl1 table | |
2412 | * entry size. | |
2413 | */ | |
d524eaa2 | 2414 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
2415 | esz = GITS_LVL1_ENTRY_SIZE; |
2416 | } | |
2417 | } | |
4b75c459 SD |
2418 | |
2419 | /* | |
2420 | * Allocate as many entries as required to fit the | |
2421 | * range of device IDs that the ITS can grok... The ID | |
2422 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
2423 | * massive waste of memory if two-level device table |
2424 | * feature is not supported by hardware. | |
4b75c459 SD |
2425 | */ |
2426 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
2427 | if (new_order >= MAX_ORDER) { | |
2428 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 2429 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
576a8342 | 2430 | pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", |
4cacac57 | 2431 | &its->phys_base, its_base_type_string[type], |
576a8342 | 2432 | device_ids(its), ids); |
4b75c459 SD |
2433 | } |
2434 | ||
2435 | *order = new_order; | |
3faf24ea SD |
2436 | |
2437 | return indirect; | |
4b75c459 SD |
2438 | } |
2439 | ||
5e516846 MZ |
2440 | static u32 compute_common_aff(u64 val) |
2441 | { | |
2442 | u32 aff, clpiaff; | |
2443 | ||
2444 | aff = FIELD_GET(GICR_TYPER_AFFINITY, val); | |
2445 | clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val); | |
2446 | ||
2447 | return aff & ~(GENMASK(31, 0) >> (clpiaff * 8)); | |
2448 | } | |
2449 | ||
2450 | static u32 compute_its_aff(struct its_node *its) | |
2451 | { | |
2452 | u64 val; | |
2453 | u32 svpet; | |
2454 | ||
2455 | /* | |
2456 | * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute | |
2457 | * the resulting affinity. We then use that to see if this match | |
2458 | * our own affinity. | |
2459 | */ | |
2460 | svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); | |
2461 | val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet); | |
2462 | val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); | |
2463 | return compute_common_aff(val); | |
2464 | } | |
2465 | ||
2466 | static struct its_node *find_sibling_its(struct its_node *cur_its) | |
2467 | { | |
2468 | struct its_node *its; | |
2469 | u32 aff; | |
2470 | ||
2471 | if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) | |
2472 | return NULL; | |
2473 | ||
2474 | aff = compute_its_aff(cur_its); | |
2475 | ||
2476 | list_for_each_entry(its, &its_nodes, entry) { | |
2477 | u64 baser; | |
2478 | ||
2479 | if (!is_v4_1(its) || its == cur_its) | |
2480 | continue; | |
2481 | ||
2482 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2483 | continue; | |
2484 | ||
2485 | if (aff != compute_its_aff(its)) | |
2486 | continue; | |
2487 | ||
2488 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2489 | baser = its->tables[2].val; | |
2490 | if (!(baser & GITS_BASER_VALID)) | |
2491 | continue; | |
2492 | ||
2493 | return its; | |
2494 | } | |
2495 | ||
2496 | return NULL; | |
2497 | } | |
2498 | ||
1ac19ca6 MZ |
2499 | static void its_free_tables(struct its_node *its) |
2500 | { | |
2501 | int i; | |
2502 | ||
2503 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
2504 | if (its->tables[i].base) { |
2505 | free_pages((unsigned long)its->tables[i].base, | |
2506 | its->tables[i].order); | |
2507 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
2508 | } |
2509 | } | |
2510 | } | |
2511 | ||
d5df9dc9 MZ |
2512 | static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) |
2513 | { | |
2514 | u64 psz = SZ_64K; | |
2515 | ||
2516 | while (psz) { | |
2517 | u64 val, gpsz; | |
2518 | ||
2519 | val = its_read_baser(its, baser); | |
2520 | val &= ~GITS_BASER_PAGE_SIZE_MASK; | |
2521 | ||
2522 | switch (psz) { | |
2523 | case SZ_64K: | |
2524 | gpsz = GITS_BASER_PAGE_SIZE_64K; | |
2525 | break; | |
2526 | case SZ_16K: | |
2527 | gpsz = GITS_BASER_PAGE_SIZE_16K; | |
2528 | break; | |
2529 | case SZ_4K: | |
2530 | default: | |
2531 | gpsz = GITS_BASER_PAGE_SIZE_4K; | |
2532 | break; | |
2533 | } | |
2534 | ||
2535 | gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT; | |
2536 | ||
2537 | val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz); | |
2538 | its_write_baser(its, baser, val); | |
2539 | ||
2540 | if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) | |
2541 | break; | |
2542 | ||
2543 | switch (psz) { | |
2544 | case SZ_64K: | |
2545 | psz = SZ_16K; | |
2546 | break; | |
2547 | case SZ_16K: | |
2548 | psz = SZ_4K; | |
2549 | break; | |
2550 | case SZ_4K: | |
2551 | default: | |
2552 | return -1; | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | baser->psz = psz; | |
2557 | return 0; | |
2558 | } | |
2559 | ||
0e0b0f69 | 2560 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 2561 | { |
1ac19ca6 | 2562 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 2563 | u64 cache = GITS_BASER_RaWaWb; |
9347359a | 2564 | int err, i; |
94100970 | 2565 | |
fa150019 AB |
2566 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
2567 | /* erratum 24313: ignore memory access type */ | |
2568 | cache = GITS_BASER_nCnB; | |
466b7d16 | 2569 | |
1ac19ca6 | 2570 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
2571 | struct its_baser *baser = its->tables + i; |
2572 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 2573 | u64 type = GITS_BASER_TYPE(val); |
3faf24ea | 2574 | bool indirect = false; |
d5df9dc9 | 2575 | u32 order; |
1ac19ca6 | 2576 | |
d5df9dc9 | 2577 | if (type == GITS_BASER_TYPE_NONE) |
1ac19ca6 MZ |
2578 | continue; |
2579 | ||
d5df9dc9 MZ |
2580 | if (its_probe_baser_psz(its, baser)) { |
2581 | its_free_tables(its); | |
2582 | return -ENXIO; | |
2583 | } | |
2584 | ||
2585 | order = get_order(baser->psz); | |
2586 | ||
2587 | switch (type) { | |
4cacac57 | 2588 | case GITS_BASER_TYPE_DEVICE: |
d5df9dc9 | 2589 | indirect = its_parse_indirect_baser(its, baser, &order, |
576a8342 | 2590 | device_ids(its)); |
8d565748 ZY |
2591 | break; |
2592 | ||
4cacac57 | 2593 | case GITS_BASER_TYPE_VCPU: |
5e516846 MZ |
2594 | if (is_v4_1(its)) { |
2595 | struct its_node *sibling; | |
2596 | ||
2597 | WARN_ON(i != 2); | |
2598 | if ((sibling = find_sibling_its(its))) { | |
2599 | *baser = sibling->tables[2]; | |
2600 | its_write_baser(its, baser, baser->val); | |
2601 | continue; | |
2602 | } | |
2603 | } | |
2604 | ||
d5df9dc9 | 2605 | indirect = its_parse_indirect_baser(its, baser, &order, |
32bd44dc | 2606 | ITS_MAX_VPEID_BITS); |
4cacac57 MZ |
2607 | break; |
2608 | } | |
f54b97ed | 2609 | |
d5df9dc9 | 2610 | err = its_setup_baser(its, baser, cache, shr, order, indirect); |
9347359a SD |
2611 | if (err < 0) { |
2612 | its_free_tables(its); | |
2613 | return err; | |
1ac19ca6 MZ |
2614 | } |
2615 | ||
9347359a | 2616 | /* Update settings which will be used for next BASERn */ |
9347359a SD |
2617 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; |
2618 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
2619 | } |
2620 | ||
2621 | return 0; | |
1ac19ca6 MZ |
2622 | } |
2623 | ||
5e516846 MZ |
2624 | static u64 inherit_vpe_l1_table_from_its(void) |
2625 | { | |
2626 | struct its_node *its; | |
2627 | u64 val; | |
2628 | u32 aff; | |
2629 | ||
2630 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2631 | aff = compute_common_aff(val); | |
2632 | ||
2633 | list_for_each_entry(its, &its_nodes, entry) { | |
2634 | u64 baser, addr; | |
2635 | ||
2636 | if (!is_v4_1(its)) | |
2637 | continue; | |
2638 | ||
2639 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2640 | continue; | |
2641 | ||
2642 | if (aff != compute_its_aff(its)) | |
2643 | continue; | |
2644 | ||
2645 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2646 | baser = its->tables[2].val; | |
2647 | if (!(baser & GITS_BASER_VALID)) | |
2648 | continue; | |
2649 | ||
2650 | /* We have a winner! */ | |
8b718d40 ZY |
2651 | gic_data_rdist()->vpe_l1_base = its->tables[2].base; |
2652 | ||
5e516846 MZ |
2653 | val = GICR_VPROPBASER_4_1_VALID; |
2654 | if (baser & GITS_BASER_INDIRECT) | |
2655 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2656 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, | |
2657 | FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)); | |
2658 | switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) { | |
2659 | case GIC_PAGE_SIZE_64K: | |
2660 | addr = GITS_BASER_ADDR_48_to_52(baser); | |
2661 | break; | |
2662 | default: | |
2663 | addr = baser & GENMASK_ULL(47, 12); | |
2664 | break; | |
2665 | } | |
2666 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12); | |
2667 | val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK, | |
2668 | FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser)); | |
2669 | val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK, | |
2670 | FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser)); | |
2671 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); | |
2672 | ||
2673 | return val; | |
2674 | } | |
2675 | ||
2676 | return 0; | |
2677 | } | |
2678 | ||
2679 | static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask) | |
2680 | { | |
2681 | u32 aff; | |
2682 | u64 val; | |
2683 | int cpu; | |
2684 | ||
2685 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2686 | aff = compute_common_aff(val); | |
2687 | ||
2688 | for_each_possible_cpu(cpu) { | |
2689 | void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; | |
5e516846 MZ |
2690 | |
2691 | if (!base || cpu == smp_processor_id()) | |
2692 | continue; | |
2693 | ||
2694 | val = gic_read_typer(base + GICR_TYPER); | |
4bccf1d7 | 2695 | if (aff != compute_common_aff(val)) |
5e516846 MZ |
2696 | continue; |
2697 | ||
2698 | /* | |
2699 | * At this point, we have a victim. This particular CPU | |
2700 | * has already booted, and has an affinity that matches | |
2701 | * ours wrt CommonLPIAff. Let's use its own VPROPBASER. | |
2702 | * Make sure we don't write the Z bit in that case. | |
2703 | */ | |
5186a6cc | 2704 | val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); |
5e516846 MZ |
2705 | val &= ~GICR_VPROPBASER_4_1_Z; |
2706 | ||
8b718d40 | 2707 | gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; |
5e516846 MZ |
2708 | *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; |
2709 | ||
2710 | return val; | |
2711 | } | |
2712 | ||
2713 | return 0; | |
2714 | } | |
2715 | ||
4e6437f1 ZY |
2716 | static bool allocate_vpe_l2_table(int cpu, u32 id) |
2717 | { | |
2718 | void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; | |
490d332e MZ |
2719 | unsigned int psz, esz, idx, npg, gpsz; |
2720 | u64 val; | |
4e6437f1 ZY |
2721 | struct page *page; |
2722 | __le64 *table; | |
2723 | ||
2724 | if (!gic_rdists->has_rvpeid) | |
2725 | return true; | |
2726 | ||
28d160de MZ |
2727 | /* Skip non-present CPUs */ |
2728 | if (!base) | |
2729 | return true; | |
2730 | ||
5186a6cc | 2731 | val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); |
4e6437f1 ZY |
2732 | |
2733 | esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; | |
2734 | gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); | |
2735 | npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1; | |
2736 | ||
2737 | switch (gpsz) { | |
2738 | default: | |
2739 | WARN_ON(1); | |
2740 | /* fall through */ | |
2741 | case GIC_PAGE_SIZE_4K: | |
2742 | psz = SZ_4K; | |
2743 | break; | |
2744 | case GIC_PAGE_SIZE_16K: | |
2745 | psz = SZ_16K; | |
2746 | break; | |
2747 | case GIC_PAGE_SIZE_64K: | |
2748 | psz = SZ_64K; | |
2749 | break; | |
2750 | } | |
2751 | ||
2752 | /* Don't allow vpe_id that exceeds single, flat table limit */ | |
2753 | if (!(val & GICR_VPROPBASER_4_1_INDIRECT)) | |
2754 | return (id < (npg * psz / (esz * SZ_8))); | |
2755 | ||
2756 | /* Compute 1st level table index & check if that exceeds table limit */ | |
2757 | idx = id >> ilog2(psz / (esz * SZ_8)); | |
2758 | if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE)) | |
2759 | return false; | |
2760 | ||
2761 | table = gic_data_rdist_cpu(cpu)->vpe_l1_base; | |
2762 | ||
2763 | /* Allocate memory for 2nd level table */ | |
2764 | if (!table[idx]) { | |
2765 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); | |
2766 | if (!page) | |
2767 | return false; | |
2768 | ||
2769 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
2770 | if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK)) | |
2771 | gic_flush_dcache_to_poc(page_address(page), psz); | |
2772 | ||
2773 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
2774 | ||
2775 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
2776 | if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK)) | |
2777 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); | |
2778 | ||
2779 | /* Ensure updated table contents are visible to RD hardware */ | |
2780 | dsb(sy); | |
2781 | } | |
2782 | ||
2783 | return true; | |
2784 | } | |
2785 | ||
5e516846 MZ |
2786 | static int allocate_vpe_l1_table(void) |
2787 | { | |
2788 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
2789 | u64 val, gpsz, npg, pa; | |
2790 | unsigned int psz = SZ_64K; | |
2791 | unsigned int np, epp, esz; | |
2792 | struct page *page; | |
2793 | ||
2794 | if (!gic_rdists->has_rvpeid) | |
2795 | return 0; | |
2796 | ||
2797 | /* | |
2798 | * if VPENDBASER.Valid is set, disable any previously programmed | |
2799 | * VPE by setting PendingLast while clearing Valid. This has the | |
2800 | * effect of making sure no doorbell will be generated and we can | |
2801 | * then safely clear VPROPBASER.Valid. | |
2802 | */ | |
5186a6cc ZY |
2803 | if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid) |
2804 | gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast, | |
5e516846 MZ |
2805 | vlpi_base + GICR_VPENDBASER); |
2806 | ||
2807 | /* | |
2808 | * If we can inherit the configuration from another RD, let's do | |
2809 | * so. Otherwise, we have to go through the allocation process. We | |
2810 | * assume that all RDs have the exact same requirements, as | |
2811 | * nothing will work otherwise. | |
2812 | */ | |
2813 | val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); | |
2814 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2815 | goto out; | |
2816 | ||
2817 | gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_KERNEL); | |
2818 | if (!gic_data_rdist()->vpe_table_mask) | |
2819 | return -ENOMEM; | |
2820 | ||
2821 | val = inherit_vpe_l1_table_from_its(); | |
2822 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2823 | goto out; | |
2824 | ||
2825 | /* First probe the page size */ | |
2826 | val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K); | |
5186a6cc ZY |
2827 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
2828 | val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER); | |
5e516846 MZ |
2829 | gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); |
2830 | esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val); | |
2831 | ||
2832 | switch (gpsz) { | |
2833 | default: | |
2834 | gpsz = GIC_PAGE_SIZE_4K; | |
2835 | /* fall through */ | |
2836 | case GIC_PAGE_SIZE_4K: | |
2837 | psz = SZ_4K; | |
2838 | break; | |
2839 | case GIC_PAGE_SIZE_16K: | |
2840 | psz = SZ_16K; | |
2841 | break; | |
2842 | case GIC_PAGE_SIZE_64K: | |
2843 | psz = SZ_64K; | |
2844 | break; | |
2845 | } | |
2846 | ||
2847 | /* | |
2848 | * Start populating the register from scratch, including RO fields | |
2849 | * (which we want to print in debug cases...) | |
2850 | */ | |
2851 | val = 0; | |
2852 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz); | |
2853 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz); | |
2854 | ||
2855 | /* How many entries per GIC page? */ | |
2856 | esz++; | |
2857 | epp = psz / (esz * SZ_8); | |
2858 | ||
2859 | /* | |
2860 | * If we need more than just a single L1 page, flag the table | |
2861 | * as indirect and compute the number of required L1 pages. | |
2862 | */ | |
2863 | if (epp < ITS_MAX_VPEID) { | |
2864 | int nl2; | |
2865 | ||
2866 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2867 | ||
2868 | /* Number of L2 pages required to cover the VPEID space */ | |
2869 | nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp); | |
2870 | ||
2871 | /* Number of L1 pages to point to the L2 pages */ | |
2872 | npg = DIV_ROUND_UP(nl2 * SZ_8, psz); | |
2873 | } else { | |
2874 | npg = 1; | |
2875 | } | |
2876 | ||
e88bd316 | 2877 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); |
5e516846 MZ |
2878 | |
2879 | /* Right, that's the number of CPU pages we need for L1 */ | |
2880 | np = DIV_ROUND_UP(npg * psz, PAGE_SIZE); | |
2881 | ||
2882 | pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", | |
2883 | np, npg, psz, epp, esz); | |
2884 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(np * PAGE_SIZE)); | |
2885 | if (!page) | |
2886 | return -ENOMEM; | |
2887 | ||
8b718d40 | 2888 | gic_data_rdist()->vpe_l1_base = page_address(page); |
5e516846 MZ |
2889 | pa = virt_to_phys(page_address(page)); |
2890 | WARN_ON(!IS_ALIGNED(pa, psz)); | |
2891 | ||
2892 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12); | |
2893 | val |= GICR_VPROPBASER_RaWb; | |
2894 | val |= GICR_VPROPBASER_InnerShareable; | |
2895 | val |= GICR_VPROPBASER_4_1_Z; | |
2896 | val |= GICR_VPROPBASER_4_1_VALID; | |
2897 | ||
2898 | out: | |
5186a6cc | 2899 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
5e516846 MZ |
2900 | cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); |
2901 | ||
2902 | pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n", | |
2903 | smp_processor_id(), val, | |
2904 | cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); | |
2905 | ||
2906 | return 0; | |
2907 | } | |
2908 | ||
1ac19ca6 MZ |
2909 | static int its_alloc_collections(struct its_node *its) |
2910 | { | |
83559b47 MZ |
2911 | int i; |
2912 | ||
6396bb22 | 2913 | its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), |
1ac19ca6 MZ |
2914 | GFP_KERNEL); |
2915 | if (!its->collections) | |
2916 | return -ENOMEM; | |
2917 | ||
83559b47 MZ |
2918 | for (i = 0; i < nr_cpu_ids; i++) |
2919 | its->collections[i].target_address = ~0ULL; | |
2920 | ||
1ac19ca6 MZ |
2921 | return 0; |
2922 | } | |
2923 | ||
7c297a2d MZ |
2924 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
2925 | { | |
2926 | struct page *pend_page; | |
adaab500 | 2927 | |
7c297a2d | 2928 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, |
adaab500 | 2929 | get_order(LPI_PENDBASE_SZ)); |
7c297a2d MZ |
2930 | if (!pend_page) |
2931 | return NULL; | |
2932 | ||
2933 | /* Make sure the GIC will observe the zero-ed page */ | |
2934 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
2935 | ||
2936 | return pend_page; | |
2937 | } | |
2938 | ||
7d75bbb4 MZ |
2939 | static void its_free_pending_table(struct page *pt) |
2940 | { | |
adaab500 | 2941 | free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); |
7d75bbb4 MZ |
2942 | } |
2943 | ||
c6e2ccb6 | 2944 | /* |
5e2c9f9a MZ |
2945 | * Booting with kdump and LPIs enabled is generally fine. Any other |
2946 | * case is wrong in the absence of firmware/EFI support. | |
c6e2ccb6 | 2947 | */ |
c440a9d9 MZ |
2948 | static bool enabled_lpis_allowed(void) |
2949 | { | |
5e2c9f9a MZ |
2950 | phys_addr_t addr; |
2951 | u64 val; | |
c6e2ccb6 | 2952 | |
5e2c9f9a MZ |
2953 | /* Check whether the property table is in a reserved region */ |
2954 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); | |
2955 | addr = val & GENMASK_ULL(51, 12); | |
2956 | ||
2957 | return gic_check_reserved_range(addr, LPI_PROPBASE_SZ); | |
c440a9d9 MZ |
2958 | } |
2959 | ||
11e37d35 | 2960 | static int __init allocate_lpi_tables(void) |
1ac19ca6 | 2961 | { |
c440a9d9 | 2962 | u64 val; |
11e37d35 | 2963 | int err, cpu; |
1ac19ca6 | 2964 | |
c440a9d9 MZ |
2965 | /* |
2966 | * If LPIs are enabled while we run this from the boot CPU, | |
2967 | * flag the RD tables as pre-allocated if the stars do align. | |
2968 | */ | |
2969 | val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); | |
2970 | if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { | |
2971 | gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | | |
2972 | RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING); | |
2973 | pr_info("GICv3: Using preallocated redistributor tables\n"); | |
2974 | } | |
2975 | ||
11e37d35 MZ |
2976 | err = its_setup_lpi_prop_table(); |
2977 | if (err) | |
2978 | return err; | |
2979 | ||
2980 | /* | |
2981 | * We allocate all the pending tables anyway, as we may have a | |
2982 | * mix of RDs that have had LPIs enabled, and some that | |
2983 | * don't. We'll free the unused ones as each CPU comes online. | |
2984 | */ | |
2985 | for_each_possible_cpu(cpu) { | |
2986 | struct page *pend_page; | |
7c297a2d MZ |
2987 | |
2988 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 | 2989 | if (!pend_page) { |
11e37d35 MZ |
2990 | pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu); |
2991 | return -ENOMEM; | |
1ac19ca6 MZ |
2992 | } |
2993 | ||
11e37d35 | 2994 | gic_data_rdist_cpu(cpu)->pend_page = pend_page; |
1ac19ca6 MZ |
2995 | } |
2996 | ||
11e37d35 MZ |
2997 | return 0; |
2998 | } | |
2999 | ||
e64fab1a | 3000 | static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set) |
6479450f HG |
3001 | { |
3002 | u32 count = 1000000; /* 1s! */ | |
3003 | bool clean; | |
3004 | u64 val; | |
3005 | ||
5186a6cc | 3006 | val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER); |
6479450f | 3007 | val &= ~GICR_VPENDBASER_Valid; |
e64fab1a MZ |
3008 | val &= ~clr; |
3009 | val |= set; | |
5186a6cc | 3010 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); |
6479450f HG |
3011 | |
3012 | do { | |
5186a6cc | 3013 | val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER); |
6479450f HG |
3014 | clean = !(val & GICR_VPENDBASER_Dirty); |
3015 | if (!clean) { | |
3016 | count--; | |
3017 | cpu_relax(); | |
3018 | udelay(1); | |
3019 | } | |
3020 | } while (!clean && count); | |
3021 | ||
e64fab1a MZ |
3022 | if (unlikely(val & GICR_VPENDBASER_Dirty)) { |
3023 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); | |
3024 | val |= GICR_VPENDBASER_PendingLast; | |
3025 | } | |
3026 | ||
6479450f HG |
3027 | return val; |
3028 | } | |
3029 | ||
11e37d35 MZ |
3030 | static void its_cpu_init_lpis(void) |
3031 | { | |
3032 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
3033 | struct page *pend_page; | |
3034 | phys_addr_t paddr; | |
3035 | u64 val, tmp; | |
3036 | ||
3037 | if (gic_data_rdist()->lpi_enabled) | |
3038 | return; | |
3039 | ||
c440a9d9 MZ |
3040 | val = readl_relaxed(rbase + GICR_CTLR); |
3041 | if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && | |
3042 | (val & GICR_CTLR_ENABLE_LPIS)) { | |
f842ca8e MZ |
3043 | /* |
3044 | * Check that we get the same property table on all | |
3045 | * RDs. If we don't, this is hopeless. | |
3046 | */ | |
3047 | paddr = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
3048 | paddr &= GENMASK_ULL(51, 12); | |
3049 | if (WARN_ON(gic_rdists->prop_table_pa != paddr)) | |
3050 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
3051 | ||
c440a9d9 MZ |
3052 | paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER); |
3053 | paddr &= GENMASK_ULL(51, 16); | |
3054 | ||
5e2c9f9a | 3055 | WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ)); |
c440a9d9 MZ |
3056 | its_free_pending_table(gic_data_rdist()->pend_page); |
3057 | gic_data_rdist()->pend_page = NULL; | |
3058 | ||
3059 | goto out; | |
3060 | } | |
3061 | ||
11e37d35 MZ |
3062 | pend_page = gic_data_rdist()->pend_page; |
3063 | paddr = page_to_phys(pend_page); | |
3fb68fae | 3064 | WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ)); |
11e37d35 | 3065 | |
1ac19ca6 | 3066 | /* set PROPBASE */ |
e1a2e201 | 3067 | val = (gic_rdists->prop_table_pa | |
1ac19ca6 | 3068 | GICR_PROPBASER_InnerShareable | |
2fd632a0 | 3069 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
3070 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
3071 | ||
0968a619 VM |
3072 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
3073 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
3074 | |
3075 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
3076 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
3077 | /* | |
3078 | * The HW reports non-shareable, we must | |
3079 | * remove the cacheability attributes as | |
3080 | * well. | |
3081 | */ | |
3082 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
3083 | GICR_PROPBASER_CACHEABILITY_MASK); | |
3084 | val |= GICR_PROPBASER_nC; | |
0968a619 | 3085 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 3086 | } |
1ac19ca6 MZ |
3087 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
3088 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
3089 | } | |
3090 | ||
3091 | /* set PENDBASE */ | |
3092 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 3093 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 3094 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 3095 | |
0968a619 VM |
3096 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
3097 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
3098 | |
3099 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
3100 | /* | |
3101 | * The HW reports non-shareable, we must remove the | |
3102 | * cacheability attributes as well. | |
3103 | */ | |
3104 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
3105 | GICR_PENDBASER_CACHEABILITY_MASK); | |
3106 | val |= GICR_PENDBASER_nC; | |
0968a619 | 3107 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 3108 | } |
1ac19ca6 MZ |
3109 | |
3110 | /* Enable LPIs */ | |
3111 | val = readl_relaxed(rbase + GICR_CTLR); | |
3112 | val |= GICR_CTLR_ENABLE_LPIS; | |
3113 | writel_relaxed(val, rbase + GICR_CTLR); | |
3114 | ||
5e516846 | 3115 | if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { |
6479450f HG |
3116 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
3117 | ||
3118 | /* | |
3119 | * It's possible for CPU to receive VLPIs before it is | |
3120 | * sheduled as a vPE, especially for the first CPU, and the | |
3121 | * VLPI with INTID larger than 2^(IDbits+1) will be considered | |
3122 | * as out of range and dropped by GIC. | |
3123 | * So we initialize IDbits to known value to avoid VLPI drop. | |
3124 | */ | |
3125 | val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
3126 | pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n", | |
3127 | smp_processor_id(), val); | |
5186a6cc | 3128 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
6479450f HG |
3129 | |
3130 | /* | |
3131 | * Also clear Valid bit of GICR_VPENDBASER, in case some | |
3132 | * ancient programming gets left in and has possibility of | |
3133 | * corrupting memory. | |
3134 | */ | |
e64fab1a | 3135 | val = its_clear_vpend_valid(vlpi_base, 0, 0); |
6479450f HG |
3136 | } |
3137 | ||
5e516846 MZ |
3138 | if (allocate_vpe_l1_table()) { |
3139 | /* | |
3140 | * If the allocation has failed, we're in massive trouble. | |
3141 | * Disable direct injection, and pray that no VM was | |
3142 | * already running... | |
3143 | */ | |
3144 | gic_rdists->has_rvpeid = false; | |
3145 | gic_rdists->has_vlpis = false; | |
3146 | } | |
3147 | ||
1ac19ca6 MZ |
3148 | /* Make sure the GIC has seen the above */ |
3149 | dsb(sy); | |
c440a9d9 | 3150 | out: |
11e37d35 | 3151 | gic_data_rdist()->lpi_enabled = true; |
c440a9d9 | 3152 | pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n", |
11e37d35 | 3153 | smp_processor_id(), |
c440a9d9 | 3154 | gic_data_rdist()->pend_page ? "allocated" : "reserved", |
11e37d35 | 3155 | &paddr); |
1ac19ca6 MZ |
3156 | } |
3157 | ||
920181ce | 3158 | static void its_cpu_init_collection(struct its_node *its) |
1ac19ca6 | 3159 | { |
920181ce DB |
3160 | int cpu = smp_processor_id(); |
3161 | u64 target; | |
1ac19ca6 | 3162 | |
920181ce DB |
3163 | /* avoid cross node collections and its mapping */ |
3164 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
3165 | struct device_node *cpu_node; | |
fbf8f40e | 3166 | |
920181ce DB |
3167 | cpu_node = of_get_cpu_node(cpu, NULL); |
3168 | if (its->numa_node != NUMA_NO_NODE && | |
3169 | its->numa_node != of_node_to_nid(cpu_node)) | |
3170 | return; | |
3171 | } | |
fbf8f40e | 3172 | |
920181ce DB |
3173 | /* |
3174 | * We now have to bind each collection to its target | |
3175 | * redistributor. | |
3176 | */ | |
3177 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
1ac19ca6 | 3178 | /* |
920181ce | 3179 | * This ITS wants the physical address of the |
1ac19ca6 MZ |
3180 | * redistributor. |
3181 | */ | |
920181ce DB |
3182 | target = gic_data_rdist()->phys_base; |
3183 | } else { | |
3184 | /* This ITS wants a linear CPU number. */ | |
3185 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
3186 | target = GICR_TYPER_CPU_NUMBER(target) << 16; | |
3187 | } | |
1ac19ca6 | 3188 | |
920181ce DB |
3189 | /* Perform collection mapping */ |
3190 | its->collections[cpu].target_address = target; | |
3191 | its->collections[cpu].col_id = cpu; | |
1ac19ca6 | 3192 | |
920181ce DB |
3193 | its_send_mapc(its, &its->collections[cpu], 1); |
3194 | its_send_invall(its, &its->collections[cpu]); | |
3195 | } | |
3196 | ||
3197 | static void its_cpu_init_collections(void) | |
3198 | { | |
3199 | struct its_node *its; | |
3200 | ||
a8db7456 | 3201 | raw_spin_lock(&its_lock); |
920181ce DB |
3202 | |
3203 | list_for_each_entry(its, &its_nodes, entry) | |
3204 | its_cpu_init_collection(its); | |
1ac19ca6 | 3205 | |
a8db7456 | 3206 | raw_spin_unlock(&its_lock); |
1ac19ca6 | 3207 | } |
84a6a2e7 MZ |
3208 | |
3209 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
3210 | { | |
3211 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 3212 | unsigned long flags; |
84a6a2e7 | 3213 | |
3e39e8f5 | 3214 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
3215 | |
3216 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
3217 | if (tmp->device_id == dev_id) { | |
3218 | its_dev = tmp; | |
3219 | break; | |
3220 | } | |
3221 | } | |
3222 | ||
3e39e8f5 | 3223 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
3224 | |
3225 | return its_dev; | |
3226 | } | |
3227 | ||
466b7d16 SD |
3228 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
3229 | { | |
3230 | int i; | |
3231 | ||
3232 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
3233 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
3234 | return &its->tables[i]; | |
3235 | } | |
3236 | ||
3237 | return NULL; | |
3238 | } | |
3239 | ||
539d3782 SD |
3240 | static bool its_alloc_table_entry(struct its_node *its, |
3241 | struct its_baser *baser, u32 id) | |
3faf24ea | 3242 | { |
3faf24ea SD |
3243 | struct page *page; |
3244 | u32 esz, idx; | |
3245 | __le64 *table; | |
3246 | ||
3faf24ea SD |
3247 | /* Don't allow device id that exceeds single, flat table limit */ |
3248 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
3249 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 3250 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
3251 | |
3252 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 3253 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
3254 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
3255 | return false; | |
3256 | ||
3257 | table = baser->base; | |
3258 | ||
3259 | /* Allocate memory for 2nd level table */ | |
3260 | if (!table[idx]) { | |
539d3782 SD |
3261 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
3262 | get_order(baser->psz)); | |
3faf24ea SD |
3263 | if (!page) |
3264 | return false; | |
3265 | ||
3266 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
3267 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 3268 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
3269 | |
3270 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
3271 | ||
3272 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
3273 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 3274 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
3275 | |
3276 | /* Ensure updated table contents are visible to ITS hardware */ | |
3277 | dsb(sy); | |
3278 | } | |
3279 | ||
3280 | return true; | |
3281 | } | |
3282 | ||
70cc81ed MZ |
3283 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
3284 | { | |
3285 | struct its_baser *baser; | |
3286 | ||
3287 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
3288 | ||
3289 | /* Don't allow device id that exceeds ITS hardware limit */ | |
3290 | if (!baser) | |
576a8342 | 3291 | return (ilog2(dev_id) < device_ids(its)); |
70cc81ed | 3292 | |
539d3782 | 3293 | return its_alloc_table_entry(its, baser, dev_id); |
70cc81ed MZ |
3294 | } |
3295 | ||
7d75bbb4 MZ |
3296 | static bool its_alloc_vpe_table(u32 vpe_id) |
3297 | { | |
3298 | struct its_node *its; | |
4e6437f1 | 3299 | int cpu; |
7d75bbb4 MZ |
3300 | |
3301 | /* | |
3302 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
3303 | * could try and only do it on ITSs corresponding to devices | |
3304 | * that have interrupts targeted at this VPE, but the | |
3305 | * complexity becomes crazy (and you have tons of memory | |
3306 | * anyway, right?). | |
3307 | */ | |
3308 | list_for_each_entry(its, &its_nodes, entry) { | |
3309 | struct its_baser *baser; | |
3310 | ||
0dd57fed | 3311 | if (!is_v4(its)) |
7d75bbb4 | 3312 | continue; |
3faf24ea | 3313 | |
7d75bbb4 MZ |
3314 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
3315 | if (!baser) | |
3316 | return false; | |
3faf24ea | 3317 | |
539d3782 | 3318 | if (!its_alloc_table_entry(its, baser, vpe_id)) |
7d75bbb4 | 3319 | return false; |
3faf24ea SD |
3320 | } |
3321 | ||
4e6437f1 ZY |
3322 | /* Non v4.1? No need to iterate RDs and go back early. */ |
3323 | if (!gic_rdists->has_rvpeid) | |
3324 | return true; | |
3325 | ||
3326 | /* | |
3327 | * Make sure the L2 tables are allocated for all copies of | |
3328 | * the L1 table on *all* v4.1 RDs. | |
3329 | */ | |
3330 | for_each_possible_cpu(cpu) { | |
3331 | if (!allocate_vpe_l2_table(cpu, vpe_id)) | |
3332 | return false; | |
3333 | } | |
3334 | ||
3faf24ea SD |
3335 | return true; |
3336 | } | |
3337 | ||
84a6a2e7 | 3338 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 3339 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
3340 | { |
3341 | struct its_device *dev; | |
93f94ea0 | 3342 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 3343 | unsigned long flags; |
591e5bec | 3344 | u16 *col_map = NULL; |
84a6a2e7 MZ |
3345 | void *itt; |
3346 | int lpi_base; | |
3347 | int nr_lpis; | |
c8481267 | 3348 | int nr_ites; |
84a6a2e7 MZ |
3349 | int sz; |
3350 | ||
3faf24ea | 3351 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
3352 | return NULL; |
3353 | ||
147c8f37 MZ |
3354 | if (WARN_ON(!is_power_of_2(nvecs))) |
3355 | nvecs = roundup_pow_of_two(nvecs); | |
3356 | ||
84a6a2e7 | 3357 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 | 3358 | /* |
147c8f37 MZ |
3359 | * Even if the device wants a single LPI, the ITT must be |
3360 | * sized as a power of two (and you need at least one bit...). | |
c8481267 | 3361 | */ |
147c8f37 | 3362 | nr_ites = max(2, nvecs); |
ffedbf0c | 3363 | sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); |
84a6a2e7 | 3364 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
539d3782 | 3365 | itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); |
93f94ea0 | 3366 | if (alloc_lpis) { |
38dd7c49 | 3367 | lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); |
93f94ea0 | 3368 | if (lpi_map) |
6396bb22 | 3369 | col_map = kcalloc(nr_lpis, sizeof(*col_map), |
93f94ea0 MZ |
3370 | GFP_KERNEL); |
3371 | } else { | |
6396bb22 | 3372 | col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL); |
93f94ea0 MZ |
3373 | nr_lpis = 0; |
3374 | lpi_base = 0; | |
3375 | } | |
84a6a2e7 | 3376 | |
93f94ea0 | 3377 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
3378 | kfree(dev); |
3379 | kfree(itt); | |
3380 | kfree(lpi_map); | |
591e5bec | 3381 | kfree(col_map); |
84a6a2e7 MZ |
3382 | return NULL; |
3383 | } | |
3384 | ||
328191c0 | 3385 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 3386 | |
84a6a2e7 MZ |
3387 | dev->its = its; |
3388 | dev->itt = itt; | |
c8481267 | 3389 | dev->nr_ites = nr_ites; |
591e5bec MZ |
3390 | dev->event_map.lpi_map = lpi_map; |
3391 | dev->event_map.col_map = col_map; | |
3392 | dev->event_map.lpi_base = lpi_base; | |
3393 | dev->event_map.nr_lpis = nr_lpis; | |
11635fa2 | 3394 | raw_spin_lock_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
3395 | dev->device_id = dev_id; |
3396 | INIT_LIST_HEAD(&dev->entry); | |
3397 | ||
3e39e8f5 | 3398 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 3399 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 3400 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 3401 | |
84a6a2e7 MZ |
3402 | /* Map device to its ITT */ |
3403 | its_send_mapd(dev, 1); | |
3404 | ||
3405 | return dev; | |
3406 | } | |
3407 | ||
3408 | static void its_free_device(struct its_device *its_dev) | |
3409 | { | |
3e39e8f5 MZ |
3410 | unsigned long flags; |
3411 | ||
3412 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 3413 | list_del(&its_dev->entry); |
3e39e8f5 | 3414 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
898aa5ce | 3415 | kfree(its_dev->event_map.col_map); |
84a6a2e7 MZ |
3416 | kfree(its_dev->itt); |
3417 | kfree(its_dev); | |
3418 | } | |
b48ac83d | 3419 | |
8208d170 | 3420 | static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq) |
b48ac83d MZ |
3421 | { |
3422 | int idx; | |
3423 | ||
342be106 | 3424 | /* Find a free LPI region in lpi_map and allocate them. */ |
8208d170 MZ |
3425 | idx = bitmap_find_free_region(dev->event_map.lpi_map, |
3426 | dev->event_map.nr_lpis, | |
3427 | get_count_order(nvecs)); | |
3428 | if (idx < 0) | |
b48ac83d MZ |
3429 | return -ENOSPC; |
3430 | ||
591e5bec | 3431 | *hwirq = dev->event_map.lpi_base + idx; |
b48ac83d | 3432 | |
b48ac83d MZ |
3433 | return 0; |
3434 | } | |
3435 | ||
54456db9 MZ |
3436 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
3437 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 3438 | { |
b48ac83d | 3439 | struct its_node *its; |
b48ac83d | 3440 | struct its_device *its_dev; |
54456db9 MZ |
3441 | struct msi_domain_info *msi_info; |
3442 | u32 dev_id; | |
9791ec7d | 3443 | int err = 0; |
54456db9 MZ |
3444 | |
3445 | /* | |
a7c90f51 | 3446 | * We ignore "dev" entirely, and rely on the dev_id that has |
54456db9 MZ |
3447 | * been passed via the scratchpad. This limits this domain's |
3448 | * usefulness to upper layers that definitely know that they | |
3449 | * are built on top of the ITS. | |
3450 | */ | |
3451 | dev_id = info->scratchpad[0].ul; | |
3452 | ||
3453 | msi_info = msi_get_domain_info(domain); | |
3454 | its = msi_info->data; | |
e8137f4f | 3455 | |
20b3d54e MZ |
3456 | if (!gic_rdists->has_direct_lpi && |
3457 | vpe_proxy.dev && | |
3458 | vpe_proxy.dev->its == its && | |
3459 | dev_id == vpe_proxy.dev->device_id) { | |
3460 | /* Bad luck. Get yourself a better implementation */ | |
3461 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
3462 | dev_id); | |
3463 | return -EINVAL; | |
3464 | } | |
3465 | ||
9791ec7d | 3466 | mutex_lock(&its->dev_alloc_lock); |
f130420e | 3467 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
3468 | if (its_dev) { |
3469 | /* | |
3470 | * We already have seen this ID, probably through | |
3471 | * another alias (PCI bridge of some sort). No need to | |
3472 | * create the device. | |
3473 | */ | |
9791ec7d | 3474 | its_dev->shared = true; |
f130420e | 3475 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
3476 | goto out; |
3477 | } | |
b48ac83d | 3478 | |
93f94ea0 | 3479 | its_dev = its_create_device(its, dev_id, nvec, true); |
9791ec7d MZ |
3480 | if (!its_dev) { |
3481 | err = -ENOMEM; | |
3482 | goto out; | |
3483 | } | |
b48ac83d | 3484 | |
f130420e | 3485 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 3486 | out: |
9791ec7d | 3487 | mutex_unlock(&its->dev_alloc_lock); |
b48ac83d | 3488 | info->scratchpad[0].ptr = its_dev; |
9791ec7d | 3489 | return err; |
b48ac83d MZ |
3490 | } |
3491 | ||
54456db9 MZ |
3492 | static struct msi_domain_ops its_msi_domain_ops = { |
3493 | .msi_prepare = its_msi_prepare, | |
3494 | }; | |
3495 | ||
b48ac83d MZ |
3496 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
3497 | unsigned int virq, | |
3498 | irq_hw_number_t hwirq) | |
3499 | { | |
f833f57f MZ |
3500 | struct irq_fwspec fwspec; |
3501 | ||
3502 | if (irq_domain_get_of_node(domain->parent)) { | |
3503 | fwspec.fwnode = domain->parent->fwnode; | |
3504 | fwspec.param_count = 3; | |
3505 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
3506 | fwspec.param[1] = hwirq; | |
3507 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
3508 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
3509 | fwspec.fwnode = domain->parent->fwnode; | |
3510 | fwspec.param_count = 2; | |
3511 | fwspec.param[0] = hwirq; | |
3512 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
3513 | } else { |
3514 | return -EINVAL; | |
3515 | } | |
b48ac83d | 3516 | |
f833f57f | 3517 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
3518 | } |
3519 | ||
3520 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
3521 | unsigned int nr_irqs, void *args) | |
3522 | { | |
3523 | msi_alloc_info_t *info = args; | |
3524 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
35ae7df2 | 3525 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
3526 | irq_hw_number_t hwirq; |
3527 | int err; | |
3528 | int i; | |
3529 | ||
8208d170 MZ |
3530 | err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq); |
3531 | if (err) | |
3532 | return err; | |
b48ac83d | 3533 | |
35ae7df2 JG |
3534 | err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); |
3535 | if (err) | |
3536 | return err; | |
3537 | ||
8208d170 MZ |
3538 | for (i = 0; i < nr_irqs; i++) { |
3539 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); | |
b48ac83d MZ |
3540 | if (err) |
3541 | return err; | |
3542 | ||
3543 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
8208d170 | 3544 | hwirq + i, &its_irq_chip, its_dev); |
0d224d35 | 3545 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); |
f130420e | 3546 | pr_debug("ID:%d pID:%d vID:%d\n", |
8208d170 MZ |
3547 | (int)(hwirq + i - its_dev->event_map.lpi_base), |
3548 | (int)(hwirq + i), virq + i); | |
b48ac83d MZ |
3549 | } |
3550 | ||
3551 | return 0; | |
3552 | } | |
3553 | ||
72491643 | 3554 | static int its_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 3555 | struct irq_data *d, bool reserve) |
aca268df MZ |
3556 | { |
3557 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3558 | u32 event = its_get_event_id(d); | |
0d224d35 | 3559 | int cpu; |
fbf8f40e | 3560 | |
c5d6082d MZ |
3561 | cpu = its_select_cpu(d, cpu_online_mask); |
3562 | if (cpu < 0 || cpu >= nr_cpu_ids) | |
3563 | return -EINVAL; | |
c1797b11 | 3564 | |
2f13ff1d | 3565 | its_inc_lpi_count(d, cpu); |
0d224d35 MZ |
3566 | its_dev->event_map.col_map[event] = cpu; |
3567 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 3568 | |
aca268df | 3569 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 3570 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 3571 | return 0; |
aca268df MZ |
3572 | } |
3573 | ||
3574 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
3575 | struct irq_data *d) | |
3576 | { | |
3577 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3578 | u32 event = its_get_event_id(d); | |
3579 | ||
2f13ff1d | 3580 | its_dec_lpi_count(d, its_dev->event_map.col_map[event]); |
aca268df MZ |
3581 | /* Stop the delivery of interrupts */ |
3582 | its_send_discard(its_dev, event); | |
3583 | } | |
3584 | ||
b48ac83d MZ |
3585 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
3586 | unsigned int nr_irqs) | |
3587 | { | |
3588 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
3589 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
9791ec7d | 3590 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
3591 | int i; |
3592 | ||
c9c96e30 MZ |
3593 | bitmap_release_region(its_dev->event_map.lpi_map, |
3594 | its_get_event_id(irq_domain_get_irq_data(domain, virq)), | |
3595 | get_count_order(nr_irqs)); | |
3596 | ||
b48ac83d MZ |
3597 | for (i = 0; i < nr_irqs; i++) { |
3598 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
3599 | virq + i); | |
b48ac83d | 3600 | /* Nuke the entry in the domain */ |
2da39949 | 3601 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
3602 | } |
3603 | ||
9791ec7d MZ |
3604 | mutex_lock(&its->dev_alloc_lock); |
3605 | ||
3606 | /* | |
3607 | * If all interrupts have been freed, start mopping the | |
3608 | * floor. This is conditionned on the device not being shared. | |
3609 | */ | |
3610 | if (!its_dev->shared && | |
3611 | bitmap_empty(its_dev->event_map.lpi_map, | |
591e5bec | 3612 | its_dev->event_map.nr_lpis)) { |
38dd7c49 MZ |
3613 | its_lpi_free(its_dev->event_map.lpi_map, |
3614 | its_dev->event_map.lpi_base, | |
3615 | its_dev->event_map.nr_lpis); | |
b48ac83d MZ |
3616 | |
3617 | /* Unmap device/itt */ | |
3618 | its_send_mapd(its_dev, 0); | |
3619 | its_free_device(its_dev); | |
3620 | } | |
3621 | ||
9791ec7d MZ |
3622 | mutex_unlock(&its->dev_alloc_lock); |
3623 | ||
b48ac83d MZ |
3624 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
3625 | } | |
3626 | ||
3627 | static const struct irq_domain_ops its_domain_ops = { | |
3628 | .alloc = its_irq_domain_alloc, | |
3629 | .free = its_irq_domain_free, | |
aca268df MZ |
3630 | .activate = its_irq_domain_activate, |
3631 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 3632 | }; |
4c21f3c2 | 3633 | |
20b3d54e MZ |
3634 | /* |
3635 | * This is insane. | |
3636 | * | |
0684c704 | 3637 | * If a GICv4.0 doesn't implement Direct LPIs (which is extremely |
20b3d54e MZ |
3638 | * likely), the only way to perform an invalidate is to use a fake |
3639 | * device to issue an INV command, implying that the LPI has first | |
3640 | * been mapped to some event on that device. Since this is not exactly | |
3641 | * cheap, we try to keep that mapping around as long as possible, and | |
3642 | * only issue an UNMAP if we're short on available slots. | |
3643 | * | |
3644 | * Broken by design(tm). | |
0684c704 MZ |
3645 | * |
3646 | * GICv4.1, on the other hand, mandates that we're able to invalidate | |
3647 | * by writing to a MMIO register. It doesn't implement the whole of | |
3648 | * DirectLPI, but that's good enough. And most of the time, we don't | |
3649 | * even have to invalidate anything, as the redistributor can be told | |
3650 | * whether to generate a doorbell or not (we thus leave it enabled, | |
3651 | * always). | |
20b3d54e MZ |
3652 | */ |
3653 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
3654 | { | |
0684c704 MZ |
3655 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3656 | if (gic_rdists->has_rvpeid) | |
3657 | return; | |
3658 | ||
20b3d54e MZ |
3659 | /* Already unmapped? */ |
3660 | if (vpe->vpe_proxy_event == -1) | |
3661 | return; | |
3662 | ||
3663 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3664 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
3665 | ||
3666 | /* | |
3667 | * We don't track empty slots at all, so let's move the | |
3668 | * next_victim pointer if we can quickly reuse that slot | |
3669 | * instead of nuking an existing entry. Not clear that this is | |
3670 | * always a win though, and this might just generate a ripple | |
3671 | * effect... Let's just hope VPEs don't migrate too often. | |
3672 | */ | |
3673 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3674 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
3675 | ||
3676 | vpe->vpe_proxy_event = -1; | |
3677 | } | |
3678 | ||
3679 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
3680 | { | |
0684c704 MZ |
3681 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3682 | if (gic_rdists->has_rvpeid) | |
3683 | return; | |
3684 | ||
20b3d54e MZ |
3685 | if (!gic_rdists->has_direct_lpi) { |
3686 | unsigned long flags; | |
3687 | ||
3688 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3689 | its_vpe_db_proxy_unmap_locked(vpe); | |
3690 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3691 | } | |
3692 | } | |
3693 | ||
3694 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
3695 | { | |
0684c704 MZ |
3696 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3697 | if (gic_rdists->has_rvpeid) | |
3698 | return; | |
3699 | ||
20b3d54e MZ |
3700 | /* Already mapped? */ |
3701 | if (vpe->vpe_proxy_event != -1) | |
3702 | return; | |
3703 | ||
3704 | /* This slot was already allocated. Kick the other VPE out. */ | |
3705 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3706 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
3707 | ||
3708 | /* Map the new VPE instead */ | |
3709 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
3710 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
3711 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
3712 | ||
3713 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
3714 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
3715 | } | |
3716 | ||
958b90d1 MZ |
3717 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
3718 | { | |
3719 | unsigned long flags; | |
3720 | struct its_collection *target_col; | |
3721 | ||
0684c704 MZ |
3722 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3723 | if (gic_rdists->has_rvpeid) | |
3724 | return; | |
3725 | ||
958b90d1 MZ |
3726 | if (gic_rdists->has_direct_lpi) { |
3727 | void __iomem *rdbase; | |
3728 | ||
3729 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
3730 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 3731 | wait_for_syncr(rdbase); |
958b90d1 MZ |
3732 | |
3733 | return; | |
3734 | } | |
3735 | ||
3736 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3737 | ||
3738 | its_vpe_db_proxy_map_locked(vpe); | |
3739 | ||
3740 | target_col = &vpe_proxy.dev->its->collections[to]; | |
3741 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
3742 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
3743 | ||
3744 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3745 | } | |
3746 | ||
3171a47a MZ |
3747 | static int its_vpe_set_affinity(struct irq_data *d, |
3748 | const struct cpumask *mask_val, | |
3749 | bool force) | |
3750 | { | |
3751 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
dd3f050a | 3752 | int from, cpu = cpumask_first(mask_val); |
f3a05921 | 3753 | unsigned long flags; |
3171a47a MZ |
3754 | |
3755 | /* | |
3756 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 3757 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
3758 | * into the proxy device, we need to move the doorbell |
3759 | * interrupt to its new location. | |
f3a05921 MZ |
3760 | * |
3761 | * Another thing is that changing the affinity of a vPE affects | |
3762 | * *other interrupts* such as all the vLPIs that are routed to | |
3763 | * this vPE. This means that the irq_desc lock is not enough to | |
3764 | * protect us, and that we must ensure nobody samples vpe->col_idx | |
3765 | * during the update, hence the lock below which must also be | |
3766 | * taken on any vLPI handling path that evaluates vpe->col_idx. | |
3171a47a | 3767 | */ |
f3a05921 MZ |
3768 | from = vpe_to_cpuid_lock(vpe, &flags); |
3769 | if (from == cpu) | |
dd3f050a | 3770 | goto out; |
958b90d1 | 3771 | |
dd3f050a MZ |
3772 | vpe->col_idx = cpu; |
3773 | ||
3774 | /* | |
3775 | * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD | |
3776 | * is sharing its VPE table with the current one. | |
3777 | */ | |
3778 | if (gic_data_rdist_cpu(cpu)->vpe_table_mask && | |
3779 | cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask)) | |
3780 | goto out; | |
3171a47a | 3781 | |
dd3f050a MZ |
3782 | its_send_vmovp(vpe); |
3783 | its_vpe_db_proxy_move(vpe, from, cpu); | |
3784 | ||
3785 | out: | |
44c4c25e | 3786 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
f3a05921 | 3787 | vpe_to_cpuid_unlock(vpe, flags); |
44c4c25e | 3788 | |
3171a47a MZ |
3789 | return IRQ_SET_MASK_OK_DONE; |
3790 | } | |
3791 | ||
96806229 MZ |
3792 | static void its_wait_vpt_parse_complete(void) |
3793 | { | |
3794 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
3795 | u64 val; | |
3796 | ||
3797 | if (!gic_rdists->has_vpend_valid_dirty) | |
3798 | return; | |
3799 | ||
3800 | WARN_ON_ONCE(readq_relaxed_poll_timeout(vlpi_base + GICR_VPENDBASER, | |
3801 | val, | |
3802 | !(val & GICR_VPENDBASER_Dirty), | |
3803 | 10, 500)); | |
3804 | } | |
3805 | ||
e643d803 MZ |
3806 | static void its_vpe_schedule(struct its_vpe *vpe) |
3807 | { | |
50c33097 | 3808 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3809 | u64 val; |
3810 | ||
3811 | /* Schedule the VPE */ | |
3812 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
3813 | GENMASK_ULL(51, 12); | |
3814 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
3815 | val |= GICR_VPROPBASER_RaWb; | |
3816 | val |= GICR_VPROPBASER_InnerShareable; | |
5186a6cc | 3817 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
e643d803 MZ |
3818 | |
3819 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
3820 | GENMASK_ULL(51, 16); | |
3821 | val |= GICR_VPENDBASER_RaWaWb; | |
b2cb11f4 | 3822 | val |= GICR_VPENDBASER_InnerShareable; |
e643d803 MZ |
3823 | /* |
3824 | * There is no good way of finding out if the pending table is | |
3825 | * empty as we can race against the doorbell interrupt very | |
3826 | * easily. So in the end, vpe->pending_last is only an | |
3827 | * indication that the vcpu has something pending, not one | |
3828 | * that the pending table is empty. A good implementation | |
3829 | * would be able to read its coarse map pretty quickly anyway, | |
3830 | * making this a tolerable issue. | |
3831 | */ | |
3832 | val |= GICR_VPENDBASER_PendingLast; | |
3833 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
3834 | val |= GICR_VPENDBASER_Valid; | |
5186a6cc | 3835 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); |
96806229 MZ |
3836 | |
3837 | its_wait_vpt_parse_complete(); | |
e643d803 MZ |
3838 | } |
3839 | ||
3840 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
3841 | { | |
50c33097 | 3842 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3843 | u64 val; |
3844 | ||
e64fab1a | 3845 | val = its_clear_vpend_valid(vlpi_base, 0, 0); |
e643d803 | 3846 | |
e64fab1a MZ |
3847 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); |
3848 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
e643d803 MZ |
3849 | } |
3850 | ||
40619a2e MZ |
3851 | static void its_vpe_invall(struct its_vpe *vpe) |
3852 | { | |
3853 | struct its_node *its; | |
3854 | ||
3855 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 3856 | if (!is_v4(its)) |
40619a2e MZ |
3857 | continue; |
3858 | ||
2247e1bf MZ |
3859 | if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) |
3860 | continue; | |
3861 | ||
3c1cceeb MZ |
3862 | /* |
3863 | * Sending a VINVALL to a single ITS is enough, as all | |
3864 | * we need is to reach the redistributors. | |
3865 | */ | |
40619a2e | 3866 | its_send_vinvall(its, vpe); |
3c1cceeb | 3867 | return; |
40619a2e MZ |
3868 | } |
3869 | } | |
3870 | ||
e643d803 MZ |
3871 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
3872 | { | |
3873 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3874 | struct its_cmd_info *info = vcpu_info; | |
3875 | ||
3876 | switch (info->cmd_type) { | |
3877 | case SCHEDULE_VPE: | |
3878 | its_vpe_schedule(vpe); | |
3879 | return 0; | |
3880 | ||
3881 | case DESCHEDULE_VPE: | |
3882 | its_vpe_deschedule(vpe); | |
3883 | return 0; | |
3884 | ||
5e2f7642 | 3885 | case INVALL_VPE: |
40619a2e | 3886 | its_vpe_invall(vpe); |
5e2f7642 MZ |
3887 | return 0; |
3888 | ||
e643d803 MZ |
3889 | default: |
3890 | return -EINVAL; | |
3891 | } | |
3892 | } | |
3893 | ||
20b3d54e MZ |
3894 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
3895 | void (*cmd)(struct its_device *, u32)) | |
3896 | { | |
3897 | unsigned long flags; | |
3898 | ||
3899 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3900 | ||
3901 | its_vpe_db_proxy_map_locked(vpe); | |
3902 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3903 | ||
3904 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3905 | } | |
3906 | ||
f6a91da7 MZ |
3907 | static void its_vpe_send_inv(struct irq_data *d) |
3908 | { | |
3909 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 3910 | |
20b3d54e MZ |
3911 | if (gic_rdists->has_direct_lpi) { |
3912 | void __iomem *rdbase; | |
3913 | ||
425c09be | 3914 | /* Target the redistributor this VPE is currently known on */ |
9058a4e9 | 3915 | raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
20b3d54e | 3916 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; |
425c09be | 3917 | gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); |
2f4f064b | 3918 | wait_for_syncr(rdbase); |
9058a4e9 | 3919 | raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
20b3d54e MZ |
3920 | } else { |
3921 | its_vpe_send_cmd(vpe, its_send_inv); | |
3922 | } | |
f6a91da7 MZ |
3923 | } |
3924 | ||
3925 | static void its_vpe_mask_irq(struct irq_data *d) | |
3926 | { | |
3927 | /* | |
3928 | * We need to unmask the LPI, which is described by the parent | |
3929 | * irq_data. Instead of calling into the parent (which won't | |
3930 | * exactly do the right thing, let's simply use the | |
3931 | * parent_data pointer. Yes, I'm naughty. | |
3932 | */ | |
3933 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
3934 | its_vpe_send_inv(d); | |
3935 | } | |
3936 | ||
3937 | static void its_vpe_unmask_irq(struct irq_data *d) | |
3938 | { | |
3939 | /* Same hack as above... */ | |
3940 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
3941 | its_vpe_send_inv(d); | |
3942 | } | |
3943 | ||
e57a3e28 MZ |
3944 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
3945 | enum irqchip_irq_state which, | |
3946 | bool state) | |
3947 | { | |
3948 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3949 | ||
3950 | if (which != IRQCHIP_STATE_PENDING) | |
3951 | return -EINVAL; | |
3952 | ||
3953 | if (gic_rdists->has_direct_lpi) { | |
3954 | void __iomem *rdbase; | |
3955 | ||
3956 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
3957 | if (state) { | |
3958 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
3959 | } else { | |
3960 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 3961 | wait_for_syncr(rdbase); |
e57a3e28 MZ |
3962 | } |
3963 | } else { | |
3964 | if (state) | |
3965 | its_vpe_send_cmd(vpe, its_send_int); | |
3966 | else | |
3967 | its_vpe_send_cmd(vpe, its_send_clear); | |
3968 | } | |
3969 | ||
3970 | return 0; | |
3971 | } | |
3972 | ||
7809f701 MZ |
3973 | static int its_vpe_retrigger(struct irq_data *d) |
3974 | { | |
3975 | return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true); | |
3976 | } | |
3977 | ||
8fff27ae MZ |
3978 | static struct irq_chip its_vpe_irq_chip = { |
3979 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
3980 | .irq_mask = its_vpe_mask_irq, |
3981 | .irq_unmask = its_vpe_unmask_irq, | |
3982 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 3983 | .irq_set_affinity = its_vpe_set_affinity, |
7809f701 | 3984 | .irq_retrigger = its_vpe_retrigger, |
e57a3e28 | 3985 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 3986 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
3987 | }; |
3988 | ||
d97c97ba MZ |
3989 | static struct its_node *find_4_1_its(void) |
3990 | { | |
3991 | static struct its_node *its = NULL; | |
3992 | ||
3993 | if (!its) { | |
3994 | list_for_each_entry(its, &its_nodes, entry) { | |
3995 | if (is_v4_1(its)) | |
3996 | return its; | |
3997 | } | |
3998 | ||
3999 | /* Oops? */ | |
4000 | its = NULL; | |
4001 | } | |
4002 | ||
4003 | return its; | |
4004 | } | |
4005 | ||
4006 | static void its_vpe_4_1_send_inv(struct irq_data *d) | |
4007 | { | |
4008 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4009 | struct its_node *its; | |
4010 | ||
4011 | /* | |
4012 | * GICv4.1 wants doorbells to be invalidated using the | |
4013 | * INVDB command in order to be broadcast to all RDs. Send | |
4014 | * it to the first valid ITS, and let the HW do its magic. | |
4015 | */ | |
4016 | its = find_4_1_its(); | |
4017 | if (its) | |
4018 | its_send_invdb(its, vpe); | |
4019 | } | |
4020 | ||
4021 | static void its_vpe_4_1_mask_irq(struct irq_data *d) | |
4022 | { | |
4023 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
4024 | its_vpe_4_1_send_inv(d); | |
4025 | } | |
4026 | ||
4027 | static void its_vpe_4_1_unmask_irq(struct irq_data *d) | |
4028 | { | |
4029 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
4030 | its_vpe_4_1_send_inv(d); | |
4031 | } | |
4032 | ||
91bf6395 MZ |
4033 | static void its_vpe_4_1_schedule(struct its_vpe *vpe, |
4034 | struct its_cmd_info *info) | |
4035 | { | |
4036 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
4037 | u64 val = 0; | |
4038 | ||
4039 | /* Schedule the VPE */ | |
4040 | val |= GICR_VPENDBASER_Valid; | |
4041 | val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; | |
4042 | val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; | |
4043 | val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); | |
4044 | ||
5186a6cc | 4045 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); |
96806229 MZ |
4046 | |
4047 | its_wait_vpt_parse_complete(); | |
91bf6395 MZ |
4048 | } |
4049 | ||
e64fab1a MZ |
4050 | static void its_vpe_4_1_deschedule(struct its_vpe *vpe, |
4051 | struct its_cmd_info *info) | |
4052 | { | |
4053 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
4054 | u64 val; | |
4055 | ||
4056 | if (info->req_db) { | |
4057 | /* | |
4058 | * vPE is going to block: make the vPE non-resident with | |
4059 | * PendingLast clear and DB set. The GIC guarantees that if | |
4060 | * we read-back PendingLast clear, then a doorbell will be | |
4061 | * delivered when an interrupt comes. | |
4062 | */ | |
4063 | val = its_clear_vpend_valid(vlpi_base, | |
4064 | GICR_VPENDBASER_PendingLast, | |
4065 | GICR_VPENDBASER_4_1_DB); | |
4066 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
4067 | } else { | |
4068 | /* | |
4069 | * We're not blocking, so just make the vPE non-resident | |
4070 | * with PendingLast set, indicating that we'll be back. | |
4071 | */ | |
4072 | val = its_clear_vpend_valid(vlpi_base, | |
4073 | 0, | |
4074 | GICR_VPENDBASER_PendingLast); | |
4075 | vpe->pending_last = true; | |
4076 | } | |
4077 | } | |
4078 | ||
b4a4bd0f MZ |
4079 | static void its_vpe_4_1_invall(struct its_vpe *vpe) |
4080 | { | |
4081 | void __iomem *rdbase; | |
4082 | u64 val; | |
4083 | ||
4084 | val = GICR_INVALLR_V; | |
4085 | val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); | |
4086 | ||
4087 | /* Target the redistributor this vPE is currently known on */ | |
9058a4e9 | 4088 | raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
b4a4bd0f MZ |
4089 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; |
4090 | gic_write_lpir(val, rdbase + GICR_INVALLR); | |
b978c25f ZY |
4091 | |
4092 | wait_for_syncr(rdbase); | |
9058a4e9 | 4093 | raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
b4a4bd0f MZ |
4094 | } |
4095 | ||
29c647f3 MZ |
4096 | static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
4097 | { | |
91bf6395 | 4098 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); |
29c647f3 MZ |
4099 | struct its_cmd_info *info = vcpu_info; |
4100 | ||
4101 | switch (info->cmd_type) { | |
4102 | case SCHEDULE_VPE: | |
91bf6395 | 4103 | its_vpe_4_1_schedule(vpe, info); |
29c647f3 MZ |
4104 | return 0; |
4105 | ||
4106 | case DESCHEDULE_VPE: | |
e64fab1a | 4107 | its_vpe_4_1_deschedule(vpe, info); |
29c647f3 MZ |
4108 | return 0; |
4109 | ||
4110 | case INVALL_VPE: | |
b4a4bd0f | 4111 | its_vpe_4_1_invall(vpe); |
29c647f3 MZ |
4112 | return 0; |
4113 | ||
4114 | default: | |
4115 | return -EINVAL; | |
4116 | } | |
4117 | } | |
4118 | ||
4119 | static struct irq_chip its_vpe_4_1_irq_chip = { | |
4120 | .name = "GICv4.1-vpe", | |
d97c97ba MZ |
4121 | .irq_mask = its_vpe_4_1_mask_irq, |
4122 | .irq_unmask = its_vpe_4_1_unmask_irq, | |
29c647f3 MZ |
4123 | .irq_eoi = irq_chip_eoi_parent, |
4124 | .irq_set_affinity = its_vpe_set_affinity, | |
4125 | .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity, | |
4126 | }; | |
4127 | ||
e252cf8a MZ |
4128 | static void its_configure_sgi(struct irq_data *d, bool clear) |
4129 | { | |
4130 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4131 | struct its_cmd_desc desc; | |
4132 | ||
4133 | desc.its_vsgi_cmd.vpe = vpe; | |
4134 | desc.its_vsgi_cmd.sgi = d->hwirq; | |
4135 | desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; | |
4136 | desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; | |
4137 | desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; | |
4138 | desc.its_vsgi_cmd.clear = clear; | |
4139 | ||
4140 | /* | |
4141 | * GICv4.1 allows us to send VSGI commands to any ITS as long as the | |
4142 | * destination VPE is mapped there. Since we map them eagerly at | |
4143 | * activation time, we're pretty sure the first GICv4.1 ITS will do. | |
4144 | */ | |
4145 | its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc); | |
4146 | } | |
4147 | ||
b4e8d644 MZ |
4148 | static void its_sgi_mask_irq(struct irq_data *d) |
4149 | { | |
4150 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4151 | ||
4152 | vpe->sgi_config[d->hwirq].enabled = false; | |
4153 | its_configure_sgi(d, false); | |
4154 | } | |
4155 | ||
4156 | static void its_sgi_unmask_irq(struct irq_data *d) | |
4157 | { | |
4158 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4159 | ||
4160 | vpe->sgi_config[d->hwirq].enabled = true; | |
4161 | its_configure_sgi(d, false); | |
4162 | } | |
4163 | ||
166cba71 MZ |
4164 | static int its_sgi_set_affinity(struct irq_data *d, |
4165 | const struct cpumask *mask_val, | |
4166 | bool force) | |
4167 | { | |
4168 | /* | |
4169 | * There is no notion of affinity for virtual SGIs, at least | |
4170 | * not on the host (since they can only be targetting a vPE). | |
4171 | * Tell the kernel we've done whatever it asked for. | |
4172 | */ | |
4b2dfe1e | 4173 | irq_data_update_effective_affinity(d, mask_val); |
166cba71 MZ |
4174 | return IRQ_SET_MASK_OK; |
4175 | } | |
4176 | ||
7017ff0e MZ |
4177 | static int its_sgi_set_irqchip_state(struct irq_data *d, |
4178 | enum irqchip_irq_state which, | |
4179 | bool state) | |
4180 | { | |
4181 | if (which != IRQCHIP_STATE_PENDING) | |
4182 | return -EINVAL; | |
4183 | ||
4184 | if (state) { | |
4185 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4186 | struct its_node *its = find_4_1_its(); | |
4187 | u64 val; | |
4188 | ||
4189 | val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); | |
4190 | val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); | |
4191 | writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); | |
4192 | } else { | |
4193 | its_configure_sgi(d, true); | |
4194 | } | |
4195 | ||
4196 | return 0; | |
4197 | } | |
4198 | ||
4199 | static int its_sgi_get_irqchip_state(struct irq_data *d, | |
4200 | enum irqchip_irq_state which, bool *val) | |
4201 | { | |
4202 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4203 | void __iomem *base; | |
4204 | unsigned long flags; | |
4205 | u32 count = 1000000; /* 1s! */ | |
4206 | u32 status; | |
4207 | int cpu; | |
4208 | ||
4209 | if (which != IRQCHIP_STATE_PENDING) | |
4210 | return -EINVAL; | |
4211 | ||
4212 | /* | |
4213 | * Locking galore! We can race against two different events: | |
4214 | * | |
4215 | * - Concurent vPE affinity change: we must make sure it cannot | |
4216 | * happen, or we'll talk to the wrong redistributor. This is | |
4217 | * identical to what happens with vLPIs. | |
4218 | * | |
4219 | * - Concurrent VSGIPENDR access: As it involves accessing two | |
4220 | * MMIO registers, this must be made atomic one way or another. | |
4221 | */ | |
4222 | cpu = vpe_to_cpuid_lock(vpe, &flags); | |
4223 | raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); | |
4224 | base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; | |
4225 | writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); | |
4226 | do { | |
4227 | status = readl_relaxed(base + GICR_VSGIPENDR); | |
4228 | if (!(status & GICR_VSGIPENDR_BUSY)) | |
4229 | goto out; | |
4230 | ||
4231 | count--; | |
4232 | if (!count) { | |
4233 | pr_err_ratelimited("Unable to get SGI status\n"); | |
4234 | goto out; | |
4235 | } | |
4236 | cpu_relax(); | |
4237 | udelay(1); | |
4238 | } while (count); | |
4239 | ||
4240 | out: | |
4241 | raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); | |
4242 | vpe_to_cpuid_unlock(vpe, flags); | |
4243 | ||
4244 | if (!count) | |
4245 | return -ENXIO; | |
4246 | ||
4247 | *val = !!(status & (1 << d->hwirq)); | |
4248 | ||
4249 | return 0; | |
4250 | } | |
4251 | ||
05d32df1 MZ |
4252 | static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
4253 | { | |
4254 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4255 | struct its_cmd_info *info = vcpu_info; | |
4256 | ||
4257 | switch (info->cmd_type) { | |
4258 | case PROP_UPDATE_VSGI: | |
4259 | vpe->sgi_config[d->hwirq].priority = info->priority; | |
4260 | vpe->sgi_config[d->hwirq].group = info->group; | |
4261 | its_configure_sgi(d, false); | |
4262 | return 0; | |
4263 | ||
4264 | default: | |
4265 | return -EINVAL; | |
4266 | } | |
4267 | } | |
4268 | ||
166cba71 MZ |
4269 | static struct irq_chip its_sgi_irq_chip = { |
4270 | .name = "GICv4.1-sgi", | |
b4e8d644 MZ |
4271 | .irq_mask = its_sgi_mask_irq, |
4272 | .irq_unmask = its_sgi_unmask_irq, | |
166cba71 | 4273 | .irq_set_affinity = its_sgi_set_affinity, |
7017ff0e MZ |
4274 | .irq_set_irqchip_state = its_sgi_set_irqchip_state, |
4275 | .irq_get_irqchip_state = its_sgi_get_irqchip_state, | |
05d32df1 | 4276 | .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity, |
166cba71 MZ |
4277 | }; |
4278 | ||
4279 | static int its_sgi_irq_domain_alloc(struct irq_domain *domain, | |
4280 | unsigned int virq, unsigned int nr_irqs, | |
4281 | void *args) | |
4282 | { | |
4283 | struct its_vpe *vpe = args; | |
4284 | int i; | |
4285 | ||
4286 | /* Yes, we do want 16 SGIs */ | |
4287 | WARN_ON(nr_irqs != 16); | |
4288 | ||
4289 | for (i = 0; i < 16; i++) { | |
4290 | vpe->sgi_config[i].priority = 0; | |
4291 | vpe->sgi_config[i].enabled = false; | |
4292 | vpe->sgi_config[i].group = false; | |
4293 | ||
4294 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
4295 | &its_sgi_irq_chip, vpe); | |
4296 | irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); | |
4297 | } | |
4298 | ||
4299 | return 0; | |
4300 | } | |
4301 | ||
4302 | static void its_sgi_irq_domain_free(struct irq_domain *domain, | |
4303 | unsigned int virq, | |
4304 | unsigned int nr_irqs) | |
4305 | { | |
4306 | /* Nothing to do */ | |
4307 | } | |
4308 | ||
4309 | static int its_sgi_irq_domain_activate(struct irq_domain *domain, | |
4310 | struct irq_data *d, bool reserve) | |
4311 | { | |
e252cf8a MZ |
4312 | /* Write out the initial SGI configuration */ |
4313 | its_configure_sgi(d, false); | |
166cba71 MZ |
4314 | return 0; |
4315 | } | |
4316 | ||
4317 | static void its_sgi_irq_domain_deactivate(struct irq_domain *domain, | |
4318 | struct irq_data *d) | |
4319 | { | |
e252cf8a MZ |
4320 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); |
4321 | ||
4322 | /* | |
4323 | * The VSGI command is awkward: | |
4324 | * | |
4325 | * - To change the configuration, CLEAR must be set to false, | |
4326 | * leaving the pending bit unchanged. | |
4327 | * - To clear the pending bit, CLEAR must be set to true, leaving | |
4328 | * the configuration unchanged. | |
4329 | * | |
4330 | * You just can't do both at once, hence the two commands below. | |
4331 | */ | |
4332 | vpe->sgi_config[d->hwirq].enabled = false; | |
4333 | its_configure_sgi(d, false); | |
4334 | its_configure_sgi(d, true); | |
166cba71 MZ |
4335 | } |
4336 | ||
4337 | static const struct irq_domain_ops its_sgi_domain_ops = { | |
4338 | .alloc = its_sgi_irq_domain_alloc, | |
4339 | .free = its_sgi_irq_domain_free, | |
4340 | .activate = its_sgi_irq_domain_activate, | |
4341 | .deactivate = its_sgi_irq_domain_deactivate, | |
4342 | }; | |
4343 | ||
7d75bbb4 MZ |
4344 | static int its_vpe_id_alloc(void) |
4345 | { | |
32bd44dc | 4346 | return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL); |
7d75bbb4 MZ |
4347 | } |
4348 | ||
4349 | static void its_vpe_id_free(u16 id) | |
4350 | { | |
4351 | ida_simple_remove(&its_vpeid_ida, id); | |
4352 | } | |
4353 | ||
4354 | static int its_vpe_init(struct its_vpe *vpe) | |
4355 | { | |
4356 | struct page *vpt_page; | |
4357 | int vpe_id; | |
4358 | ||
4359 | /* Allocate vpe_id */ | |
4360 | vpe_id = its_vpe_id_alloc(); | |
4361 | if (vpe_id < 0) | |
4362 | return vpe_id; | |
4363 | ||
4364 | /* Allocate VPT */ | |
4365 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
4366 | if (!vpt_page) { | |
4367 | its_vpe_id_free(vpe_id); | |
4368 | return -ENOMEM; | |
4369 | } | |
4370 | ||
4371 | if (!its_alloc_vpe_table(vpe_id)) { | |
4372 | its_vpe_id_free(vpe_id); | |
34f8eb92 | 4373 | its_free_pending_table(vpt_page); |
7d75bbb4 MZ |
4374 | return -ENOMEM; |
4375 | } | |
4376 | ||
f3a05921 | 4377 | raw_spin_lock_init(&vpe->vpe_lock); |
7d75bbb4 MZ |
4378 | vpe->vpe_id = vpe_id; |
4379 | vpe->vpt_page = vpt_page; | |
64edfaa9 MZ |
4380 | if (gic_rdists->has_rvpeid) |
4381 | atomic_set(&vpe->vmapp_count, 0); | |
4382 | else | |
4383 | vpe->vpe_proxy_event = -1; | |
7d75bbb4 MZ |
4384 | |
4385 | return 0; | |
4386 | } | |
4387 | ||
4388 | static void its_vpe_teardown(struct its_vpe *vpe) | |
4389 | { | |
20b3d54e | 4390 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
4391 | its_vpe_id_free(vpe->vpe_id); |
4392 | its_free_pending_table(vpe->vpt_page); | |
4393 | } | |
4394 | ||
4395 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
4396 | unsigned int virq, | |
4397 | unsigned int nr_irqs) | |
4398 | { | |
4399 | struct its_vm *vm = domain->host_data; | |
4400 | int i; | |
4401 | ||
4402 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
4403 | ||
4404 | for (i = 0; i < nr_irqs; i++) { | |
4405 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
4406 | virq + i); | |
4407 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
4408 | ||
4409 | BUG_ON(vm != vpe->its_vm); | |
4410 | ||
4411 | clear_bit(data->hwirq, vm->db_bitmap); | |
4412 | its_vpe_teardown(vpe); | |
4413 | irq_domain_reset_irq_data(data); | |
4414 | } | |
4415 | ||
4416 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
38dd7c49 | 4417 | its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); |
7d75bbb4 MZ |
4418 | its_free_prop_table(vm->vprop_page); |
4419 | } | |
4420 | } | |
4421 | ||
4422 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
4423 | unsigned int nr_irqs, void *args) | |
4424 | { | |
29c647f3 | 4425 | struct irq_chip *irqchip = &its_vpe_irq_chip; |
7d75bbb4 MZ |
4426 | struct its_vm *vm = args; |
4427 | unsigned long *bitmap; | |
4428 | struct page *vprop_page; | |
4429 | int base, nr_ids, i, err = 0; | |
4430 | ||
4431 | BUG_ON(!vm); | |
4432 | ||
38dd7c49 | 4433 | bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids); |
7d75bbb4 MZ |
4434 | if (!bitmap) |
4435 | return -ENOMEM; | |
4436 | ||
4437 | if (nr_ids < nr_irqs) { | |
38dd7c49 | 4438 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4439 | return -ENOMEM; |
4440 | } | |
4441 | ||
4442 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
4443 | if (!vprop_page) { | |
38dd7c49 | 4444 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4445 | return -ENOMEM; |
4446 | } | |
4447 | ||
4448 | vm->db_bitmap = bitmap; | |
4449 | vm->db_lpi_base = base; | |
4450 | vm->nr_db_lpis = nr_ids; | |
4451 | vm->vprop_page = vprop_page; | |
4452 | ||
29c647f3 MZ |
4453 | if (gic_rdists->has_rvpeid) |
4454 | irqchip = &its_vpe_4_1_irq_chip; | |
4455 | ||
7d75bbb4 MZ |
4456 | for (i = 0; i < nr_irqs; i++) { |
4457 | vm->vpes[i]->vpe_db_lpi = base + i; | |
4458 | err = its_vpe_init(vm->vpes[i]); | |
4459 | if (err) | |
4460 | break; | |
4461 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
4462 | vm->vpes[i]->vpe_db_lpi); | |
4463 | if (err) | |
4464 | break; | |
4465 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
29c647f3 | 4466 | irqchip, vm->vpes[i]); |
7d75bbb4 MZ |
4467 | set_bit(i, bitmap); |
4468 | } | |
4469 | ||
4470 | if (err) { | |
4471 | if (i > 0) | |
4472 | its_vpe_irq_domain_free(domain, virq, i - 1); | |
4473 | ||
38dd7c49 | 4474 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4475 | its_free_prop_table(vprop_page); |
4476 | } | |
4477 | ||
4478 | return err; | |
4479 | } | |
4480 | ||
72491643 | 4481 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 4482 | struct irq_data *d, bool reserve) |
eb78192b MZ |
4483 | { |
4484 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
40619a2e | 4485 | struct its_node *its; |
eb78192b | 4486 | |
009384b3 MZ |
4487 | /* |
4488 | * If we use the list map, we issue VMAPP on demand... Unless | |
4489 | * we're on a GICv4.1 and we eagerly map the VPE on all ITSs | |
4490 | * so that VSGIs can work. | |
4491 | */ | |
4492 | if (!gic_requires_eager_mapping()) | |
6ef930f2 | 4493 | return 0; |
eb78192b MZ |
4494 | |
4495 | /* Map the VPE to the first possible CPU */ | |
4496 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
40619a2e MZ |
4497 | |
4498 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 4499 | if (!is_v4(its)) |
40619a2e MZ |
4500 | continue; |
4501 | ||
75fd951b | 4502 | its_send_vmapp(its, vpe, true); |
40619a2e MZ |
4503 | its_send_vinvall(its, vpe); |
4504 | } | |
4505 | ||
44c4c25e MZ |
4506 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
4507 | ||
72491643 | 4508 | return 0; |
eb78192b MZ |
4509 | } |
4510 | ||
4511 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
4512 | struct irq_data *d) | |
4513 | { | |
4514 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
75fd951b MZ |
4515 | struct its_node *its; |
4516 | ||
2247e1bf | 4517 | /* |
009384b3 MZ |
4518 | * If we use the list map on GICv4.0, we unmap the VPE once no |
4519 | * VLPIs are associated with the VM. | |
2247e1bf | 4520 | */ |
009384b3 | 4521 | if (!gic_requires_eager_mapping()) |
2247e1bf | 4522 | return; |
eb78192b | 4523 | |
75fd951b | 4524 | list_for_each_entry(its, &its_nodes, entry) { |
0dd57fed | 4525 | if (!is_v4(its)) |
75fd951b | 4526 | continue; |
eb78192b | 4527 | |
75fd951b MZ |
4528 | its_send_vmapp(its, vpe, false); |
4529 | } | |
eb78192b MZ |
4530 | } |
4531 | ||
8fff27ae | 4532 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
4533 | .alloc = its_vpe_irq_domain_alloc, |
4534 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
4535 | .activate = its_vpe_irq_domain_activate, |
4536 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
4537 | }; |
4538 | ||
4559fbb3 YW |
4539 | static int its_force_quiescent(void __iomem *base) |
4540 | { | |
4541 | u32 count = 1000000; /* 1s */ | |
4542 | u32 val; | |
4543 | ||
4544 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
4545 | /* |
4546 | * GIC architecture specification requires the ITS to be both | |
4547 | * disabled and quiescent for writes to GITS_BASER<n> or | |
4548 | * GITS_CBASER to not have UNPREDICTABLE results. | |
4549 | */ | |
4550 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
4551 | return 0; |
4552 | ||
4553 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 4554 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
4555 | writel_relaxed(val, base + GITS_CTLR); |
4556 | ||
4557 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
4558 | while (1) { | |
4559 | val = readl_relaxed(base + GITS_CTLR); | |
4560 | if (val & GITS_CTLR_QUIESCENT) | |
4561 | return 0; | |
4562 | ||
4563 | count--; | |
4564 | if (!count) | |
4565 | return -EBUSY; | |
4566 | ||
4567 | cpu_relax(); | |
4568 | udelay(1); | |
4569 | } | |
4570 | } | |
4571 | ||
9d111d49 | 4572 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
4573 | { |
4574 | struct its_node *its = data; | |
4575 | ||
576a8342 MZ |
4576 | /* erratum 22375: only alloc 8MB table size (20 bits) */ |
4577 | its->typer &= ~GITS_TYPER_DEVBITS; | |
4578 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); | |
94100970 | 4579 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
4580 | |
4581 | return true; | |
94100970 RR |
4582 | } |
4583 | ||
9d111d49 | 4584 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
4585 | { |
4586 | struct its_node *its = data; | |
4587 | ||
4588 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
4589 | |
4590 | return true; | |
fbf8f40e GK |
4591 | } |
4592 | ||
9d111d49 | 4593 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
4594 | { |
4595 | struct its_node *its = data; | |
4596 | ||
4597 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
ffedbf0c MZ |
4598 | its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; |
4599 | its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); | |
9d111d49 AB |
4600 | |
4601 | return true; | |
90922a2d SD |
4602 | } |
4603 | ||
558b0165 AB |
4604 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
4605 | { | |
4606 | struct its_node *its = its_dev->its; | |
4607 | ||
4608 | /* | |
4609 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
4610 | * which maps 32-bit writes targeted at a separate window of | |
4611 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
4612 | * with device ID taken from bits [device_id_bits + 1:2] of | |
4613 | * the window offset. | |
4614 | */ | |
4615 | return its->pre_its_base + (its_dev->device_id << 2); | |
4616 | } | |
4617 | ||
4618 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
4619 | { | |
4620 | struct its_node *its = data; | |
4621 | u32 pre_its_window[2]; | |
4622 | u32 ids; | |
4623 | ||
4624 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
4625 | "socionext,synquacer-pre-its", | |
4626 | pre_its_window, | |
4627 | ARRAY_SIZE(pre_its_window))) { | |
4628 | ||
4629 | its->pre_its_base = pre_its_window[0]; | |
4630 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
4631 | ||
4632 | ids = ilog2(pre_its_window[1]) - 2; | |
576a8342 MZ |
4633 | if (device_ids(its) > ids) { |
4634 | its->typer &= ~GITS_TYPER_DEVBITS; | |
4635 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); | |
4636 | } | |
558b0165 AB |
4637 | |
4638 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
4639 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4640 | return true; | |
4641 | } | |
4642 | return false; | |
4643 | } | |
4644 | ||
5c9a882e MZ |
4645 | static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) |
4646 | { | |
4647 | struct its_node *its = data; | |
4648 | ||
4649 | /* | |
4650 | * Hip07 insists on using the wrong address for the VLPI | |
4651 | * page. Trick it into doing the right thing... | |
4652 | */ | |
4653 | its->vlpi_redist_offset = SZ_128K; | |
4654 | return true; | |
90922a2d SD |
4655 | } |
4656 | ||
67510cca | 4657 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
4658 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
4659 | { | |
4660 | .desc = "ITS: Cavium errata 22375, 24313", | |
4661 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
4662 | .mask = 0xffff0fff, | |
4663 | .init = its_enable_quirk_cavium_22375, | |
4664 | }, | |
fbf8f40e GK |
4665 | #endif |
4666 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
4667 | { | |
4668 | .desc = "ITS: Cavium erratum 23144", | |
4669 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
4670 | .mask = 0xffff0fff, | |
4671 | .init = its_enable_quirk_cavium_23144, | |
4672 | }, | |
90922a2d SD |
4673 | #endif |
4674 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
4675 | { | |
4676 | .desc = "ITS: QDF2400 erratum 0065", | |
4677 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
4678 | .mask = 0xffffffff, | |
4679 | .init = its_enable_quirk_qdf2400_e0065, | |
4680 | }, | |
558b0165 AB |
4681 | #endif |
4682 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
4683 | { | |
4684 | /* | |
4685 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
4686 | * implementation, but with a 'pre-ITS' added that requires | |
4687 | * special handling in software. | |
4688 | */ | |
4689 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
4690 | .iidr = 0x0001143b, | |
4691 | .mask = 0xffffffff, | |
4692 | .init = its_enable_quirk_socionext_synquacer, | |
4693 | }, | |
5c9a882e MZ |
4694 | #endif |
4695 | #ifdef CONFIG_HISILICON_ERRATUM_161600802 | |
4696 | { | |
4697 | .desc = "ITS: Hip07 erratum 161600802", | |
4698 | .iidr = 0x00000004, | |
4699 | .mask = 0xffffffff, | |
4700 | .init = its_enable_quirk_hip07_161600802, | |
4701 | }, | |
94100970 | 4702 | #endif |
67510cca RR |
4703 | { |
4704 | } | |
4705 | }; | |
4706 | ||
4707 | static void its_enable_quirks(struct its_node *its) | |
4708 | { | |
4709 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
4710 | ||
4711 | gic_enable_quirks(iidr, its_quirks, its); | |
4712 | } | |
4713 | ||
dba0bc7b DB |
4714 | static int its_save_disable(void) |
4715 | { | |
4716 | struct its_node *its; | |
4717 | int err = 0; | |
4718 | ||
a8db7456 | 4719 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
4720 | list_for_each_entry(its, &its_nodes, entry) { |
4721 | void __iomem *base; | |
4722 | ||
4723 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
4724 | continue; | |
4725 | ||
4726 | base = its->base; | |
4727 | its->ctlr_save = readl_relaxed(base + GITS_CTLR); | |
4728 | err = its_force_quiescent(base); | |
4729 | if (err) { | |
4730 | pr_err("ITS@%pa: failed to quiesce: %d\n", | |
4731 | &its->phys_base, err); | |
4732 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
4733 | goto err; | |
4734 | } | |
4735 | ||
4736 | its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); | |
4737 | } | |
4738 | ||
4739 | err: | |
4740 | if (err) { | |
4741 | list_for_each_entry_continue_reverse(its, &its_nodes, entry) { | |
4742 | void __iomem *base; | |
4743 | ||
4744 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
4745 | continue; | |
4746 | ||
4747 | base = its->base; | |
4748 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
4749 | } | |
4750 | } | |
a8db7456 | 4751 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
4752 | |
4753 | return err; | |
4754 | } | |
4755 | ||
4756 | static void its_restore_enable(void) | |
4757 | { | |
4758 | struct its_node *its; | |
4759 | int ret; | |
4760 | ||
a8db7456 | 4761 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
4762 | list_for_each_entry(its, &its_nodes, entry) { |
4763 | void __iomem *base; | |
4764 | int i; | |
4765 | ||
4766 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
4767 | continue; | |
4768 | ||
4769 | base = its->base; | |
4770 | ||
4771 | /* | |
4772 | * Make sure that the ITS is disabled. If it fails to quiesce, | |
4773 | * don't restore it since writing to CBASER or BASER<n> | |
4774 | * registers is undefined according to the GIC v3 ITS | |
4775 | * Specification. | |
4776 | */ | |
4777 | ret = its_force_quiescent(base); | |
4778 | if (ret) { | |
4779 | pr_err("ITS@%pa: failed to quiesce on resume: %d\n", | |
4780 | &its->phys_base, ret); | |
4781 | continue; | |
4782 | } | |
4783 | ||
4784 | gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); | |
4785 | ||
4786 | /* | |
4787 | * Writing CBASER resets CREADR to 0, so make CWRITER and | |
4788 | * cmd_write line up with it. | |
4789 | */ | |
4790 | its->cmd_write = its->cmd_base; | |
4791 | gits_write_cwriter(0, base + GITS_CWRITER); | |
4792 | ||
4793 | /* Restore GITS_BASER from the value cache. */ | |
4794 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
4795 | struct its_baser *baser = &its->tables[i]; | |
4796 | ||
4797 | if (!(baser->val & GITS_BASER_VALID)) | |
4798 | continue; | |
4799 | ||
4800 | its_write_baser(its, baser, baser->val); | |
4801 | } | |
4802 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
920181ce DB |
4803 | |
4804 | /* | |
4805 | * Reinit the collection if it's stored in the ITS. This is | |
4806 | * indicated by the col_id being less than the HCC field. | |
4807 | * CID < HCC as specified in the GIC v3 Documentation. | |
4808 | */ | |
4809 | if (its->collections[smp_processor_id()].col_id < | |
4810 | GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) | |
4811 | its_cpu_init_collection(its); | |
dba0bc7b | 4812 | } |
a8db7456 | 4813 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
4814 | } |
4815 | ||
4816 | static struct syscore_ops its_syscore_ops = { | |
4817 | .suspend = its_save_disable, | |
4818 | .resume = its_restore_enable, | |
4819 | }; | |
4820 | ||
db40f0a7 | 4821 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
4822 | { |
4823 | struct irq_domain *inner_domain; | |
4824 | struct msi_domain_info *info; | |
4825 | ||
4826 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
4827 | if (!info) | |
4828 | return -ENOMEM; | |
4829 | ||
db40f0a7 | 4830 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
4831 | if (!inner_domain) { |
4832 | kfree(info); | |
4833 | return -ENOMEM; | |
4834 | } | |
4835 | ||
db40f0a7 | 4836 | inner_domain->parent = its_parent; |
96f0d93a | 4837 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
558b0165 | 4838 | inner_domain->flags |= its->msi_domain_flags; |
d14ae5e6 TN |
4839 | info->ops = &its_msi_domain_ops; |
4840 | info->data = its; | |
4841 | inner_domain->host_data = info; | |
4842 | ||
4843 | return 0; | |
4844 | } | |
4845 | ||
8fff27ae MZ |
4846 | static int its_init_vpe_domain(void) |
4847 | { | |
20b3d54e MZ |
4848 | struct its_node *its; |
4849 | u32 devid; | |
4850 | int entries; | |
4851 | ||
4852 | if (gic_rdists->has_direct_lpi) { | |
4853 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
4854 | return 0; | |
4855 | } | |
4856 | ||
4857 | /* Any ITS will do, even if not v4 */ | |
4858 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
4859 | ||
4860 | entries = roundup_pow_of_two(nr_cpu_ids); | |
6396bb22 | 4861 | vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes), |
20b3d54e MZ |
4862 | GFP_KERNEL); |
4863 | if (!vpe_proxy.vpes) { | |
4864 | pr_err("ITS: Can't allocate GICv4 proxy device array\n"); | |
4865 | return -ENOMEM; | |
4866 | } | |
4867 | ||
4868 | /* Use the last possible DevID */ | |
576a8342 | 4869 | devid = GENMASK(device_ids(its) - 1, 0); |
20b3d54e MZ |
4870 | vpe_proxy.dev = its_create_device(its, devid, entries, false); |
4871 | if (!vpe_proxy.dev) { | |
4872 | kfree(vpe_proxy.vpes); | |
4873 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
4874 | return -ENOMEM; | |
4875 | } | |
4876 | ||
c427a475 | 4877 | BUG_ON(entries > vpe_proxy.dev->nr_ites); |
20b3d54e MZ |
4878 | |
4879 | raw_spin_lock_init(&vpe_proxy.lock); | |
4880 | vpe_proxy.next_victim = 0; | |
4881 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
4882 | devid, vpe_proxy.dev->nr_ites); | |
4883 | ||
8fff27ae MZ |
4884 | return 0; |
4885 | } | |
4886 | ||
3dfa576b MZ |
4887 | static int __init its_compute_its_list_map(struct resource *res, |
4888 | void __iomem *its_base) | |
4889 | { | |
4890 | int its_number; | |
4891 | u32 ctlr; | |
4892 | ||
4893 | /* | |
4894 | * This is assumed to be done early enough that we're | |
4895 | * guaranteed to be single-threaded, hence no | |
4896 | * locking. Should this change, we should address | |
4897 | * this. | |
4898 | */ | |
ab60491e MZ |
4899 | its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX); |
4900 | if (its_number >= GICv4_ITS_LIST_MAX) { | |
3dfa576b MZ |
4901 | pr_err("ITS@%pa: No ITSList entry available!\n", |
4902 | &res->start); | |
4903 | return -EINVAL; | |
4904 | } | |
4905 | ||
4906 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
4907 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
4908 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
4909 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
4910 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
4911 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
4912 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
4913 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
4914 | } | |
4915 | ||
4916 | if (test_and_set_bit(its_number, &its_list_map)) { | |
4917 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
4918 | &res->start, its_number); | |
4919 | return -EINVAL; | |
4920 | } | |
4921 | ||
4922 | return its_number; | |
4923 | } | |
4924 | ||
db40f0a7 TN |
4925 | static int __init its_probe_one(struct resource *res, |
4926 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 4927 | { |
4c21f3c2 MZ |
4928 | struct its_node *its; |
4929 | void __iomem *its_base; | |
3dfa576b MZ |
4930 | u32 val, ctlr; |
4931 | u64 baser, tmp, typer; | |
539d3782 | 4932 | struct page *page; |
4c21f3c2 MZ |
4933 | int err; |
4934 | ||
5e46a484 | 4935 | its_base = ioremap(res->start, SZ_64K); |
4c21f3c2 | 4936 | if (!its_base) { |
db40f0a7 | 4937 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
4938 | return -ENOMEM; |
4939 | } | |
4940 | ||
4941 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
4942 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 4943 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
4944 | err = -ENODEV; |
4945 | goto out_unmap; | |
4946 | } | |
4947 | ||
4559fbb3 YW |
4948 | err = its_force_quiescent(its_base); |
4949 | if (err) { | |
db40f0a7 | 4950 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
4951 | goto out_unmap; |
4952 | } | |
4953 | ||
db40f0a7 | 4954 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
4955 | |
4956 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
4957 | if (!its) { | |
4958 | err = -ENOMEM; | |
4959 | goto out_unmap; | |
4960 | } | |
4961 | ||
4962 | raw_spin_lock_init(&its->lock); | |
9791ec7d | 4963 | mutex_init(&its->dev_alloc_lock); |
4c21f3c2 MZ |
4964 | INIT_LIST_HEAD(&its->entry); |
4965 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 4966 | typer = gic_read_typer(its_base + GITS_TYPER); |
0dd57fed | 4967 | its->typer = typer; |
4c21f3c2 | 4968 | its->base = its_base; |
db40f0a7 | 4969 | its->phys_base = res->start; |
0dd57fed | 4970 | if (is_v4(its)) { |
3dfa576b MZ |
4971 | if (!(typer & GITS_TYPER_VMOVP)) { |
4972 | err = its_compute_its_list_map(res, its_base); | |
4973 | if (err < 0) | |
4974 | goto out_free_its; | |
4975 | ||
debf6d02 MZ |
4976 | its->list_nr = err; |
4977 | ||
3dfa576b MZ |
4978 | pr_info("ITS@%pa: Using ITS number %d\n", |
4979 | &res->start, err); | |
4980 | } else { | |
4981 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
4982 | } | |
5e516846 MZ |
4983 | |
4984 | if (is_v4_1(its)) { | |
4985 | u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer); | |
5e46a484 MZ |
4986 | |
4987 | its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K); | |
4988 | if (!its->sgir_base) { | |
4989 | err = -ENOMEM; | |
4990 | goto out_free_its; | |
4991 | } | |
4992 | ||
5e516846 MZ |
4993 | its->mpidr = readl_relaxed(its_base + GITS_MPIDR); |
4994 | ||
4995 | pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", | |
4996 | &res->start, its->mpidr, svpet); | |
4997 | } | |
3dfa576b MZ |
4998 | } |
4999 | ||
db40f0a7 | 5000 | its->numa_node = numa_node; |
4c21f3c2 | 5001 | |
539d3782 SD |
5002 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
5003 | get_order(ITS_CMD_QUEUE_SZ)); | |
5004 | if (!page) { | |
4c21f3c2 | 5005 | err = -ENOMEM; |
5e46a484 | 5006 | goto out_unmap_sgir; |
4c21f3c2 | 5007 | } |
539d3782 | 5008 | its->cmd_base = (void *)page_address(page); |
4c21f3c2 | 5009 | its->cmd_write = its->cmd_base; |
558b0165 AB |
5010 | its->fwnode_handle = handle; |
5011 | its->get_msi_base = its_irq_get_msi_base; | |
5012 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4c21f3c2 | 5013 | |
67510cca RR |
5014 | its_enable_quirks(its); |
5015 | ||
0e0b0f69 | 5016 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
5017 | if (err) |
5018 | goto out_free_cmd; | |
5019 | ||
5020 | err = its_alloc_collections(its); | |
5021 | if (err) | |
5022 | goto out_free_tables; | |
5023 | ||
5024 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 5025 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
5026 | GITS_CBASER_InnerShareable | |
5027 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
5028 | GITS_CBASER_VALID); | |
5029 | ||
0968a619 VM |
5030 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
5031 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 5032 | |
4ad3e363 | 5033 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
5034 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
5035 | /* | |
5036 | * The HW reports non-shareable, we must | |
5037 | * remove the cacheability attributes as | |
5038 | * well. | |
5039 | */ | |
5040 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
5041 | GITS_CBASER_CACHEABILITY_MASK); | |
5042 | baser |= GITS_CBASER_nC; | |
0968a619 | 5043 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 5044 | } |
4c21f3c2 MZ |
5045 | pr_info("ITS: using cache flushing for cmd queue\n"); |
5046 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
5047 | } | |
5048 | ||
0968a619 | 5049 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 5050 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d | 5051 | ctlr |= GITS_CTLR_ENABLE; |
0dd57fed | 5052 | if (is_v4(its)) |
d51c4b4d MZ |
5053 | ctlr |= GITS_CTLR_ImDe; |
5054 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 5055 | |
dba0bc7b DB |
5056 | if (GITS_TYPER_HCC(typer)) |
5057 | its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE; | |
5058 | ||
db40f0a7 | 5059 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
5060 | if (err) |
5061 | goto out_free_tables; | |
4c21f3c2 | 5062 | |
a8db7456 | 5063 | raw_spin_lock(&its_lock); |
4c21f3c2 | 5064 | list_add(&its->entry, &its_nodes); |
a8db7456 | 5065 | raw_spin_unlock(&its_lock); |
4c21f3c2 MZ |
5066 | |
5067 | return 0; | |
5068 | ||
4c21f3c2 MZ |
5069 | out_free_tables: |
5070 | its_free_tables(its); | |
5071 | out_free_cmd: | |
5bc13c2c | 5072 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
5e46a484 MZ |
5073 | out_unmap_sgir: |
5074 | if (its->sgir_base) | |
5075 | iounmap(its->sgir_base); | |
4c21f3c2 MZ |
5076 | out_free_its: |
5077 | kfree(its); | |
5078 | out_unmap: | |
5079 | iounmap(its_base); | |
db40f0a7 | 5080 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
5081 | return err; |
5082 | } | |
5083 | ||
5084 | static bool gic_rdists_supports_plpis(void) | |
5085 | { | |
589ce5f4 | 5086 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
5087 | } |
5088 | ||
6eb486b6 SD |
5089 | static int redist_disable_lpis(void) |
5090 | { | |
5091 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
5092 | u64 timeout = USEC_PER_SEC; | |
5093 | u64 val; | |
5094 | ||
5095 | if (!gic_rdists_supports_plpis()) { | |
5096 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
5097 | return -ENXIO; | |
5098 | } | |
5099 | ||
5100 | val = readl_relaxed(rbase + GICR_CTLR); | |
5101 | if (!(val & GICR_CTLR_ENABLE_LPIS)) | |
5102 | return 0; | |
5103 | ||
11e37d35 MZ |
5104 | /* |
5105 | * If coming via a CPU hotplug event, we don't need to disable | |
5106 | * LPIs before trying to re-enable them. They are already | |
5107 | * configured and all is well in the world. | |
c440a9d9 MZ |
5108 | * |
5109 | * If running with preallocated tables, there is nothing to do. | |
11e37d35 | 5110 | */ |
c440a9d9 MZ |
5111 | if (gic_data_rdist()->lpi_enabled || |
5112 | (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) | |
11e37d35 MZ |
5113 | return 0; |
5114 | ||
5115 | /* | |
5116 | * From that point on, we only try to do some damage control. | |
5117 | */ | |
5118 | pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n", | |
6eb486b6 SD |
5119 | smp_processor_id()); |
5120 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
5121 | ||
5122 | /* Disable LPIs */ | |
5123 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
5124 | writel_relaxed(val, rbase + GICR_CTLR); | |
5125 | ||
5126 | /* Make sure any change to GICR_CTLR is observable by the GIC */ | |
5127 | dsb(sy); | |
5128 | ||
5129 | /* | |
5130 | * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs | |
5131 | * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. | |
5132 | * Error out if we time out waiting for RWP to clear. | |
5133 | */ | |
5134 | while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { | |
5135 | if (!timeout) { | |
5136 | pr_err("CPU%d: Timeout while disabling LPIs\n", | |
5137 | smp_processor_id()); | |
5138 | return -ETIMEDOUT; | |
5139 | } | |
5140 | udelay(1); | |
5141 | timeout--; | |
5142 | } | |
5143 | ||
5144 | /* | |
5145 | * After it has been written to 1, it is IMPLEMENTATION | |
5146 | * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be | |
5147 | * cleared to 0. Error out if clearing the bit failed. | |
5148 | */ | |
5149 | if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { | |
5150 | pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id()); | |
5151 | return -EBUSY; | |
5152 | } | |
5153 | ||
5154 | return 0; | |
5155 | } | |
5156 | ||
4c21f3c2 MZ |
5157 | int its_cpu_init(void) |
5158 | { | |
4c21f3c2 | 5159 | if (!list_empty(&its_nodes)) { |
6eb486b6 SD |
5160 | int ret; |
5161 | ||
5162 | ret = redist_disable_lpis(); | |
5163 | if (ret) | |
5164 | return ret; | |
5165 | ||
4c21f3c2 | 5166 | its_cpu_init_lpis(); |
920181ce | 5167 | its_cpu_init_collections(); |
4c21f3c2 MZ |
5168 | } |
5169 | ||
5170 | return 0; | |
5171 | } | |
5172 | ||
935bba7c | 5173 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
5174 | { .compatible = "arm,gic-v3-its", }, |
5175 | {}, | |
5176 | }; | |
5177 | ||
db40f0a7 | 5178 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
5179 | { |
5180 | struct device_node *np; | |
db40f0a7 | 5181 | struct resource res; |
4c21f3c2 MZ |
5182 | |
5183 | for (np = of_find_matching_node(node, its_device_id); np; | |
5184 | np = of_find_matching_node(np, its_device_id)) { | |
95a25625 SB |
5185 | if (!of_device_is_available(np)) |
5186 | continue; | |
d14ae5e6 | 5187 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
5188 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
5189 | np); | |
d14ae5e6 TN |
5190 | continue; |
5191 | } | |
5192 | ||
db40f0a7 | 5193 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 5194 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
5195 | continue; |
5196 | } | |
5197 | ||
5198 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 5199 | } |
db40f0a7 TN |
5200 | return 0; |
5201 | } | |
5202 | ||
3f010cf1 TN |
5203 | #ifdef CONFIG_ACPI |
5204 | ||
5205 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
5206 | ||
d1ce263f | 5207 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
5208 | struct its_srat_map { |
5209 | /* numa node id */ | |
5210 | u32 numa_node; | |
5211 | /* GIC ITS ID */ | |
5212 | u32 its_id; | |
5213 | }; | |
5214 | ||
fdf6e7a8 | 5215 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
5216 | static int its_in_srat __initdata; |
5217 | ||
5218 | static int __init acpi_get_its_numa_node(u32 its_id) | |
5219 | { | |
5220 | int i; | |
5221 | ||
5222 | for (i = 0; i < its_in_srat; i++) { | |
5223 | if (its_id == its_srat_maps[i].its_id) | |
5224 | return its_srat_maps[i].numa_node; | |
5225 | } | |
5226 | return NUMA_NO_NODE; | |
5227 | } | |
5228 | ||
60574d1e | 5229 | static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header, |
fdf6e7a8 HG |
5230 | const unsigned long end) |
5231 | { | |
5232 | return 0; | |
5233 | } | |
5234 | ||
60574d1e | 5235 | static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header, |
dbd2b826 GK |
5236 | const unsigned long end) |
5237 | { | |
5238 | int node; | |
5239 | struct acpi_srat_gic_its_affinity *its_affinity; | |
5240 | ||
5241 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
5242 | if (!its_affinity) | |
5243 | return -EINVAL; | |
5244 | ||
5245 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
5246 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
5247 | its_affinity->header.length); | |
5248 | return -EINVAL; | |
5249 | } | |
5250 | ||
dbd2b826 GK |
5251 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); |
5252 | ||
5253 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
5254 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
5255 | return 0; | |
5256 | } | |
5257 | ||
5258 | its_srat_maps[its_in_srat].numa_node = node; | |
5259 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
5260 | its_in_srat++; | |
5261 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
5262 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
5263 | ||
5264 | return 0; | |
5265 | } | |
5266 | ||
5267 | static void __init acpi_table_parse_srat_its(void) | |
5268 | { | |
fdf6e7a8 HG |
5269 | int count; |
5270 | ||
5271 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
5272 | sizeof(struct acpi_table_srat), | |
5273 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
5274 | gic_acpi_match_srat_its, 0); | |
5275 | if (count <= 0) | |
5276 | return; | |
5277 | ||
6da2ec56 KC |
5278 | its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map), |
5279 | GFP_KERNEL); | |
fdf6e7a8 HG |
5280 | if (!its_srat_maps) { |
5281 | pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n"); | |
5282 | return; | |
5283 | } | |
5284 | ||
dbd2b826 GK |
5285 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
5286 | sizeof(struct acpi_table_srat), | |
5287 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
5288 | gic_acpi_parse_srat_its, 0); | |
5289 | } | |
fdf6e7a8 HG |
5290 | |
5291 | /* free the its_srat_maps after ITS probing */ | |
5292 | static void __init acpi_its_srat_maps_free(void) | |
5293 | { | |
5294 | kfree(its_srat_maps); | |
5295 | } | |
dbd2b826 GK |
5296 | #else |
5297 | static void __init acpi_table_parse_srat_its(void) { } | |
5298 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 5299 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
5300 | #endif |
5301 | ||
60574d1e | 5302 | static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, |
3f010cf1 TN |
5303 | const unsigned long end) |
5304 | { | |
5305 | struct acpi_madt_generic_translator *its_entry; | |
5306 | struct fwnode_handle *dom_handle; | |
5307 | struct resource res; | |
5308 | int err; | |
5309 | ||
5310 | its_entry = (struct acpi_madt_generic_translator *)header; | |
5311 | memset(&res, 0, sizeof(res)); | |
5312 | res.start = its_entry->base_address; | |
5313 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
5314 | res.flags = IORESOURCE_MEM; | |
5315 | ||
5778cc77 | 5316 | dom_handle = irq_domain_alloc_fwnode(&res.start); |
3f010cf1 TN |
5317 | if (!dom_handle) { |
5318 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
5319 | &res.start); | |
5320 | return -ENOMEM; | |
5321 | } | |
5322 | ||
8b4282e6 SK |
5323 | err = iort_register_domain_token(its_entry->translation_id, res.start, |
5324 | dom_handle); | |
3f010cf1 TN |
5325 | if (err) { |
5326 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
5327 | &res.start, its_entry->translation_id); | |
5328 | goto dom_err; | |
5329 | } | |
5330 | ||
dbd2b826 GK |
5331 | err = its_probe_one(&res, dom_handle, |
5332 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
5333 | if (!err) |
5334 | return 0; | |
5335 | ||
5336 | iort_deregister_domain_token(its_entry->translation_id); | |
5337 | dom_err: | |
5338 | irq_domain_free_fwnode(dom_handle); | |
5339 | return err; | |
5340 | } | |
5341 | ||
5342 | static void __init its_acpi_probe(void) | |
5343 | { | |
dbd2b826 | 5344 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
5345 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
5346 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 5347 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
5348 | } |
5349 | #else | |
5350 | static void __init its_acpi_probe(void) { } | |
5351 | #endif | |
5352 | ||
db40f0a7 TN |
5353 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
5354 | struct irq_domain *parent_domain) | |
5355 | { | |
5356 | struct device_node *of_node; | |
8fff27ae MZ |
5357 | struct its_node *its; |
5358 | bool has_v4 = false; | |
3c40706d | 5359 | bool has_v4_1 = false; |
8fff27ae | 5360 | int err; |
db40f0a7 | 5361 | |
5e516846 MZ |
5362 | gic_rdists = rdists; |
5363 | ||
db40f0a7 TN |
5364 | its_parent = parent_domain; |
5365 | of_node = to_of_node(handle); | |
5366 | if (of_node) | |
5367 | its_of_probe(of_node); | |
5368 | else | |
3f010cf1 | 5369 | its_acpi_probe(); |
4c21f3c2 MZ |
5370 | |
5371 | if (list_empty(&its_nodes)) { | |
5372 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
5373 | return -ENXIO; | |
5374 | } | |
5375 | ||
11e37d35 | 5376 | err = allocate_lpi_tables(); |
8fff27ae MZ |
5377 | if (err) |
5378 | return err; | |
5379 | ||
3c40706d | 5380 | list_for_each_entry(its, &its_nodes, entry) { |
0dd57fed | 5381 | has_v4 |= is_v4(its); |
3c40706d MZ |
5382 | has_v4_1 |= is_v4_1(its); |
5383 | } | |
5384 | ||
5385 | /* Don't bother with inconsistent systems */ | |
5386 | if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) | |
5387 | rdists->has_rvpeid = false; | |
8fff27ae MZ |
5388 | |
5389 | if (has_v4 & rdists->has_vlpis) { | |
166cba71 MZ |
5390 | const struct irq_domain_ops *sgi_ops; |
5391 | ||
5392 | if (has_v4_1) | |
5393 | sgi_ops = &its_sgi_domain_ops; | |
5394 | else | |
5395 | sgi_ops = NULL; | |
5396 | ||
3d63cb53 | 5397 | if (its_init_vpe_domain() || |
166cba71 | 5398 | its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) { |
8fff27ae MZ |
5399 | rdists->has_vlpis = false; |
5400 | pr_err("ITS: Disabling GICv4 support\n"); | |
5401 | } | |
5402 | } | |
5403 | ||
dba0bc7b DB |
5404 | register_syscore_ops(&its_syscore_ops); |
5405 | ||
8fff27ae | 5406 | return 0; |
4c21f3c2 | 5407 | } |