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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cc2d3216 | 2 | /* |
d7276b80 | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
cc2d3216 MZ |
5 | */ |
6 | ||
3f010cf1 | 7 | #include <linux/acpi.h> |
8d3554b8 | 8 | #include <linux/acpi_iort.h> |
ffedbf0c | 9 | #include <linux/bitfield.h> |
cc2d3216 MZ |
10 | #include <linux/bitmap.h> |
11 | #include <linux/cpu.h> | |
c6e2ccb6 | 12 | #include <linux/crash_dump.h> |
cc2d3216 | 13 | #include <linux/delay.h> |
44bb7e24 | 14 | #include <linux/dma-iommu.h> |
3fb68fae | 15 | #include <linux/efi.h> |
cc2d3216 | 16 | #include <linux/interrupt.h> |
3f010cf1 | 17 | #include <linux/irqdomain.h> |
880cb3cd | 18 | #include <linux/list.h> |
cc2d3216 | 19 | #include <linux/log2.h> |
5e2c9f9a | 20 | #include <linux/memblock.h> |
cc2d3216 MZ |
21 | #include <linux/mm.h> |
22 | #include <linux/msi.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/of_pci.h> | |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/percpu.h> | |
29 | #include <linux/slab.h> | |
dba0bc7b | 30 | #include <linux/syscore_ops.h> |
cc2d3216 | 31 | |
41a83e06 | 32 | #include <linux/irqchip.h> |
cc2d3216 | 33 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 34 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 35 | |
cc2d3216 MZ |
36 | #include <asm/cputype.h> |
37 | #include <asm/exception.h> | |
38 | ||
67510cca RR |
39 | #include "irq-gic-common.h" |
40 | ||
94100970 RR |
41 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
42 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 43 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
dba0bc7b | 44 | #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) |
cc2d3216 | 45 | |
c48ed51c | 46 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
c440a9d9 | 47 | #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) |
c48ed51c | 48 | |
a13b0404 MZ |
49 | static u32 lpi_id_bits; |
50 | ||
51 | /* | |
52 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
53 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
54 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
55 | */ | |
56 | #define LPI_NRBITS lpi_id_bits | |
57 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
58 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
59 | ||
2130b789 | 60 | #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI |
a13b0404 | 61 | |
cc2d3216 MZ |
62 | /* |
63 | * Collection structure - just an ID, and a redistributor address to | |
64 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
65 | * CPU. | |
66 | */ | |
67 | struct its_collection { | |
68 | u64 target_address; | |
69 | u16 col_id; | |
70 | }; | |
71 | ||
466b7d16 | 72 | /* |
9347359a SD |
73 | * The ITS_BASER structure - contains memory information, cached |
74 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
75 | */ |
76 | struct its_baser { | |
77 | void *base; | |
78 | u64 val; | |
79 | u32 order; | |
9347359a | 80 | u32 psz; |
466b7d16 SD |
81 | }; |
82 | ||
558b0165 AB |
83 | struct its_device; |
84 | ||
cc2d3216 MZ |
85 | /* |
86 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
87 | * top-level MSI domain, the command queue, the collections, and the |
88 | * list of devices writing to it. | |
9791ec7d MZ |
89 | * |
90 | * dev_alloc_lock has to be taken for device allocations, while the | |
91 | * spinlock must be taken to parse data structures such as the device | |
92 | * list. | |
cc2d3216 MZ |
93 | */ |
94 | struct its_node { | |
95 | raw_spinlock_t lock; | |
9791ec7d | 96 | struct mutex dev_alloc_lock; |
cc2d3216 | 97 | struct list_head entry; |
cc2d3216 | 98 | void __iomem *base; |
db40f0a7 | 99 | phys_addr_t phys_base; |
cc2d3216 MZ |
100 | struct its_cmd_block *cmd_base; |
101 | struct its_cmd_block *cmd_write; | |
466b7d16 | 102 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 103 | struct its_collection *collections; |
558b0165 AB |
104 | struct fwnode_handle *fwnode_handle; |
105 | u64 (*get_msi_base)(struct its_device *its_dev); | |
0dd57fed | 106 | u64 typer; |
dba0bc7b DB |
107 | u64 cbaser_save; |
108 | u32 ctlr_save; | |
5e516846 | 109 | u32 mpidr; |
cc2d3216 MZ |
110 | struct list_head its_device_list; |
111 | u64 flags; | |
debf6d02 | 112 | unsigned long list_nr; |
fbf8f40e | 113 | int numa_node; |
558b0165 AB |
114 | unsigned int msi_domain_flags; |
115 | u32 pre_its_base; /* for Socionext Synquacer */ | |
5c9a882e | 116 | int vlpi_redist_offset; |
cc2d3216 MZ |
117 | }; |
118 | ||
0dd57fed | 119 | #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) |
5e516846 | 120 | #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) |
576a8342 | 121 | #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) |
0dd57fed | 122 | |
cc2d3216 MZ |
123 | #define ITS_ITT_ALIGN SZ_256 |
124 | ||
32bd44dc | 125 | /* The maximum number of VPEID bits supported by VLPI commands */ |
f2d83409 MZ |
126 | #define ITS_MAX_VPEID_BITS \ |
127 | ({ \ | |
128 | int nvpeid = 16; \ | |
129 | if (gic_rdists->has_rvpeid && \ | |
130 | gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ | |
131 | nvpeid = 1 + (gic_rdists->gicd_typer2 & \ | |
132 | GICD_TYPER2_VID); \ | |
133 | \ | |
134 | nvpeid; \ | |
135 | }) | |
32bd44dc SD |
136 | #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) |
137 | ||
2eca0d6c SD |
138 | /* Convert page order to size in bytes */ |
139 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
140 | ||
591e5bec MZ |
141 | struct event_lpi_map { |
142 | unsigned long *lpi_map; | |
143 | u16 *col_map; | |
144 | irq_hw_number_t lpi_base; | |
145 | int nr_lpis; | |
11635fa2 | 146 | raw_spinlock_t vlpi_lock; |
d011e4e6 MZ |
147 | struct its_vm *vm; |
148 | struct its_vlpi_map *vlpi_maps; | |
149 | int nr_vlpis; | |
591e5bec MZ |
150 | }; |
151 | ||
cc2d3216 | 152 | /* |
d011e4e6 MZ |
153 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
154 | * translation table, and a list of interrupts. If it some of its | |
155 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
156 | * indicates which one. | |
cc2d3216 MZ |
157 | */ |
158 | struct its_device { | |
159 | struct list_head entry; | |
160 | struct its_node *its; | |
591e5bec | 161 | struct event_lpi_map event_map; |
cc2d3216 | 162 | void *itt; |
cc2d3216 MZ |
163 | u32 nr_ites; |
164 | u32 device_id; | |
9791ec7d | 165 | bool shared; |
cc2d3216 MZ |
166 | }; |
167 | ||
20b3d54e MZ |
168 | static struct { |
169 | raw_spinlock_t lock; | |
170 | struct its_device *dev; | |
171 | struct its_vpe **vpes; | |
172 | int next_victim; | |
173 | } vpe_proxy; | |
174 | ||
1ac19ca6 | 175 | static LIST_HEAD(its_nodes); |
a8db7456 | 176 | static DEFINE_RAW_SPINLOCK(its_lock); |
1ac19ca6 | 177 | static struct rdists *gic_rdists; |
db40f0a7 | 178 | static struct irq_domain *its_parent; |
1ac19ca6 | 179 | |
3dfa576b | 180 | static unsigned long its_list_map; |
3171a47a MZ |
181 | static u16 vmovp_seq_num; |
182 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
183 | ||
7d75bbb4 | 184 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 185 | |
1ac19ca6 | 186 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
11e37d35 | 187 | #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu)) |
1ac19ca6 | 188 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
e643d803 | 189 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 190 | |
84243125 ZY |
191 | static u16 get_its_list(struct its_vm *vm) |
192 | { | |
193 | struct its_node *its; | |
194 | unsigned long its_list = 0; | |
195 | ||
196 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 197 | if (!is_v4(its)) |
84243125 ZY |
198 | continue; |
199 | ||
200 | if (vm->vlpi_count[its->list_nr]) | |
201 | __set_bit(its->list_nr, &its_list); | |
202 | } | |
203 | ||
204 | return (u16)its_list; | |
205 | } | |
206 | ||
425c09be MZ |
207 | static inline u32 its_get_event_id(struct irq_data *d) |
208 | { | |
209 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
210 | return d->hwirq - its_dev->event_map.lpi_base; | |
211 | } | |
212 | ||
591e5bec MZ |
213 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
214 | u32 event) | |
215 | { | |
216 | struct its_node *its = its_dev->its; | |
217 | ||
218 | return its->collections + its_dev->event_map.col_map[event]; | |
219 | } | |
220 | ||
c1d4d5cd MZ |
221 | static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev, |
222 | u32 event) | |
223 | { | |
224 | if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) | |
225 | return NULL; | |
226 | ||
227 | return &its_dev->event_map.vlpi_maps[event]; | |
228 | } | |
229 | ||
425c09be MZ |
230 | static struct its_collection *irq_to_col(struct irq_data *d) |
231 | { | |
232 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
233 | ||
234 | return dev_event_to_col(its_dev, its_get_event_id(d)); | |
235 | } | |
236 | ||
83559b47 MZ |
237 | static struct its_collection *valid_col(struct its_collection *col) |
238 | { | |
20faba84 | 239 | if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) |
83559b47 MZ |
240 | return NULL; |
241 | ||
242 | return col; | |
243 | } | |
244 | ||
205e065d MZ |
245 | static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) |
246 | { | |
247 | if (valid_col(its->collections + vpe->col_idx)) | |
248 | return vpe; | |
249 | ||
250 | return NULL; | |
251 | } | |
252 | ||
cc2d3216 MZ |
253 | /* |
254 | * ITS command descriptors - parameters to be encoded in a command | |
255 | * block. | |
256 | */ | |
257 | struct its_cmd_desc { | |
258 | union { | |
259 | struct { | |
260 | struct its_device *dev; | |
261 | u32 event_id; | |
262 | } its_inv_cmd; | |
263 | ||
8d85dced MZ |
264 | struct { |
265 | struct its_device *dev; | |
266 | u32 event_id; | |
267 | } its_clear_cmd; | |
268 | ||
cc2d3216 MZ |
269 | struct { |
270 | struct its_device *dev; | |
271 | u32 event_id; | |
272 | } its_int_cmd; | |
273 | ||
274 | struct { | |
275 | struct its_device *dev; | |
276 | int valid; | |
277 | } its_mapd_cmd; | |
278 | ||
279 | struct { | |
280 | struct its_collection *col; | |
281 | int valid; | |
282 | } its_mapc_cmd; | |
283 | ||
284 | struct { | |
285 | struct its_device *dev; | |
286 | u32 phys_id; | |
287 | u32 event_id; | |
6a25ad3a | 288 | } its_mapti_cmd; |
cc2d3216 MZ |
289 | |
290 | struct { | |
291 | struct its_device *dev; | |
292 | struct its_collection *col; | |
591e5bec | 293 | u32 event_id; |
cc2d3216 MZ |
294 | } its_movi_cmd; |
295 | ||
296 | struct { | |
297 | struct its_device *dev; | |
298 | u32 event_id; | |
299 | } its_discard_cmd; | |
300 | ||
301 | struct { | |
302 | struct its_collection *col; | |
303 | } its_invall_cmd; | |
d011e4e6 | 304 | |
eb78192b MZ |
305 | struct { |
306 | struct its_vpe *vpe; | |
307 | } its_vinvall_cmd; | |
308 | ||
309 | struct { | |
310 | struct its_vpe *vpe; | |
311 | struct its_collection *col; | |
312 | bool valid; | |
313 | } its_vmapp_cmd; | |
314 | ||
d011e4e6 MZ |
315 | struct { |
316 | struct its_vpe *vpe; | |
317 | struct its_device *dev; | |
318 | u32 virt_id; | |
319 | u32 event_id; | |
320 | bool db_enabled; | |
321 | } its_vmapti_cmd; | |
322 | ||
323 | struct { | |
324 | struct its_vpe *vpe; | |
325 | struct its_device *dev; | |
326 | u32 event_id; | |
327 | bool db_enabled; | |
328 | } its_vmovi_cmd; | |
3171a47a MZ |
329 | |
330 | struct { | |
331 | struct its_vpe *vpe; | |
332 | struct its_collection *col; | |
333 | u16 seq_num; | |
334 | u16 its_list; | |
335 | } its_vmovp_cmd; | |
cc2d3216 MZ |
336 | }; |
337 | }; | |
338 | ||
339 | /* | |
340 | * The ITS command block, which is what the ITS actually parses. | |
341 | */ | |
342 | struct its_cmd_block { | |
2bbdfcc5 BDC |
343 | union { |
344 | u64 raw_cmd[4]; | |
345 | __le64 raw_cmd_le[4]; | |
346 | }; | |
cc2d3216 MZ |
347 | }; |
348 | ||
349 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
350 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
351 | ||
67047f90 MZ |
352 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *, |
353 | struct its_cmd_block *, | |
cc2d3216 MZ |
354 | struct its_cmd_desc *); |
355 | ||
67047f90 MZ |
356 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *, |
357 | struct its_cmd_block *, | |
d011e4e6 MZ |
358 | struct its_cmd_desc *); |
359 | ||
4d36f136 MZ |
360 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
361 | { | |
362 | u64 mask = GENMASK_ULL(h, l); | |
363 | *raw_cmd &= ~mask; | |
364 | *raw_cmd |= (val << l) & mask; | |
365 | } | |
366 | ||
cc2d3216 MZ |
367 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
368 | { | |
4d36f136 | 369 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
370 | } |
371 | ||
372 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
373 | { | |
4d36f136 | 374 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
375 | } |
376 | ||
377 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
378 | { | |
4d36f136 | 379 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
380 | } |
381 | ||
382 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
383 | { | |
4d36f136 | 384 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
385 | } |
386 | ||
387 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
388 | { | |
4d36f136 | 389 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
390 | } |
391 | ||
392 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
393 | { | |
30ae9610 | 394 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); |
cc2d3216 MZ |
395 | } |
396 | ||
397 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
398 | { | |
4d36f136 | 399 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
400 | } |
401 | ||
402 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
403 | { | |
30ae9610 | 404 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); |
cc2d3216 MZ |
405 | } |
406 | ||
407 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
408 | { | |
4d36f136 | 409 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
410 | } |
411 | ||
d011e4e6 MZ |
412 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
413 | { | |
414 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
415 | } | |
416 | ||
417 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
418 | { | |
419 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
420 | } | |
421 | ||
422 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
423 | { | |
424 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
425 | } | |
426 | ||
427 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
428 | { | |
429 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
430 | } | |
431 | ||
3171a47a MZ |
432 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
433 | { | |
434 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
435 | } | |
436 | ||
437 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
438 | { | |
439 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
440 | } | |
441 | ||
eb78192b MZ |
442 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
443 | { | |
30ae9610 | 444 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); |
eb78192b MZ |
445 | } |
446 | ||
447 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
448 | { | |
449 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
450 | } | |
451 | ||
cc2d3216 MZ |
452 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
453 | { | |
454 | /* Let's fixup BE commands */ | |
2bbdfcc5 BDC |
455 | cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); |
456 | cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
457 | cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
458 | cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
cc2d3216 MZ |
459 | } |
460 | ||
67047f90 MZ |
461 | static struct its_collection *its_build_mapd_cmd(struct its_node *its, |
462 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
463 | struct its_cmd_desc *desc) |
464 | { | |
465 | unsigned long itt_addr; | |
c8481267 | 466 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
467 | |
468 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
469 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
470 | ||
471 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
472 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
473 | its_encode_size(cmd, size - 1); | |
474 | its_encode_itt(cmd, itt_addr); | |
475 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
476 | ||
477 | its_fixup_cmd(cmd); | |
478 | ||
591e5bec | 479 | return NULL; |
cc2d3216 MZ |
480 | } |
481 | ||
67047f90 MZ |
482 | static struct its_collection *its_build_mapc_cmd(struct its_node *its, |
483 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
484 | struct its_cmd_desc *desc) |
485 | { | |
486 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
487 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
488 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
489 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
490 | ||
491 | its_fixup_cmd(cmd); | |
492 | ||
493 | return desc->its_mapc_cmd.col; | |
494 | } | |
495 | ||
67047f90 MZ |
496 | static struct its_collection *its_build_mapti_cmd(struct its_node *its, |
497 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
498 | struct its_cmd_desc *desc) |
499 | { | |
591e5bec MZ |
500 | struct its_collection *col; |
501 | ||
6a25ad3a MZ |
502 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
503 | desc->its_mapti_cmd.event_id); | |
591e5bec | 504 | |
6a25ad3a MZ |
505 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
506 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
507 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
508 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 509 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
510 | |
511 | its_fixup_cmd(cmd); | |
512 | ||
83559b47 | 513 | return valid_col(col); |
cc2d3216 MZ |
514 | } |
515 | ||
67047f90 MZ |
516 | static struct its_collection *its_build_movi_cmd(struct its_node *its, |
517 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
518 | struct its_cmd_desc *desc) |
519 | { | |
591e5bec MZ |
520 | struct its_collection *col; |
521 | ||
522 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
523 | desc->its_movi_cmd.event_id); | |
524 | ||
cc2d3216 MZ |
525 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
526 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 527 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
528 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
529 | ||
530 | its_fixup_cmd(cmd); | |
531 | ||
83559b47 | 532 | return valid_col(col); |
cc2d3216 MZ |
533 | } |
534 | ||
67047f90 MZ |
535 | static struct its_collection *its_build_discard_cmd(struct its_node *its, |
536 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
537 | struct its_cmd_desc *desc) |
538 | { | |
591e5bec MZ |
539 | struct its_collection *col; |
540 | ||
541 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
542 | desc->its_discard_cmd.event_id); | |
543 | ||
cc2d3216 MZ |
544 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
545 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
546 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
547 | ||
548 | its_fixup_cmd(cmd); | |
549 | ||
83559b47 | 550 | return valid_col(col); |
cc2d3216 MZ |
551 | } |
552 | ||
67047f90 MZ |
553 | static struct its_collection *its_build_inv_cmd(struct its_node *its, |
554 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
555 | struct its_cmd_desc *desc) |
556 | { | |
591e5bec MZ |
557 | struct its_collection *col; |
558 | ||
559 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
560 | desc->its_inv_cmd.event_id); | |
561 | ||
cc2d3216 MZ |
562 | its_encode_cmd(cmd, GITS_CMD_INV); |
563 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
564 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
565 | ||
566 | its_fixup_cmd(cmd); | |
567 | ||
83559b47 | 568 | return valid_col(col); |
cc2d3216 MZ |
569 | } |
570 | ||
67047f90 MZ |
571 | static struct its_collection *its_build_int_cmd(struct its_node *its, |
572 | struct its_cmd_block *cmd, | |
8d85dced MZ |
573 | struct its_cmd_desc *desc) |
574 | { | |
575 | struct its_collection *col; | |
576 | ||
577 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
578 | desc->its_int_cmd.event_id); | |
579 | ||
580 | its_encode_cmd(cmd, GITS_CMD_INT); | |
581 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
582 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
583 | ||
584 | its_fixup_cmd(cmd); | |
585 | ||
83559b47 | 586 | return valid_col(col); |
8d85dced MZ |
587 | } |
588 | ||
67047f90 MZ |
589 | static struct its_collection *its_build_clear_cmd(struct its_node *its, |
590 | struct its_cmd_block *cmd, | |
8d85dced MZ |
591 | struct its_cmd_desc *desc) |
592 | { | |
593 | struct its_collection *col; | |
594 | ||
595 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
596 | desc->its_clear_cmd.event_id); | |
597 | ||
598 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
599 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
600 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
601 | ||
602 | its_fixup_cmd(cmd); | |
603 | ||
83559b47 | 604 | return valid_col(col); |
8d85dced MZ |
605 | } |
606 | ||
67047f90 MZ |
607 | static struct its_collection *its_build_invall_cmd(struct its_node *its, |
608 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
609 | struct its_cmd_desc *desc) |
610 | { | |
611 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
612 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
613 | ||
614 | its_fixup_cmd(cmd); | |
615 | ||
616 | return NULL; | |
617 | } | |
618 | ||
67047f90 MZ |
619 | static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, |
620 | struct its_cmd_block *cmd, | |
eb78192b MZ |
621 | struct its_cmd_desc *desc) |
622 | { | |
623 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
624 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
625 | ||
626 | its_fixup_cmd(cmd); | |
627 | ||
205e065d | 628 | return valid_vpe(its, desc->its_vinvall_cmd.vpe); |
eb78192b MZ |
629 | } |
630 | ||
67047f90 MZ |
631 | static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, |
632 | struct its_cmd_block *cmd, | |
eb78192b MZ |
633 | struct its_cmd_desc *desc) |
634 | { | |
635 | unsigned long vpt_addr; | |
5c9a882e | 636 | u64 target; |
eb78192b MZ |
637 | |
638 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
5c9a882e | 639 | target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; |
eb78192b MZ |
640 | |
641 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
642 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
643 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
5c9a882e | 644 | its_encode_target(cmd, target); |
eb78192b MZ |
645 | its_encode_vpt_addr(cmd, vpt_addr); |
646 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
647 | ||
648 | its_fixup_cmd(cmd); | |
649 | ||
205e065d | 650 | return valid_vpe(its, desc->its_vmapp_cmd.vpe); |
eb78192b MZ |
651 | } |
652 | ||
67047f90 MZ |
653 | static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, |
654 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
655 | struct its_cmd_desc *desc) |
656 | { | |
657 | u32 db; | |
658 | ||
659 | if (desc->its_vmapti_cmd.db_enabled) | |
660 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; | |
661 | else | |
662 | db = 1023; | |
663 | ||
664 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
665 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
666 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
667 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
668 | its_encode_db_phys_id(cmd, db); | |
669 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
670 | ||
671 | its_fixup_cmd(cmd); | |
672 | ||
205e065d | 673 | return valid_vpe(its, desc->its_vmapti_cmd.vpe); |
d011e4e6 MZ |
674 | } |
675 | ||
67047f90 MZ |
676 | static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, |
677 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
678 | struct its_cmd_desc *desc) |
679 | { | |
680 | u32 db; | |
681 | ||
682 | if (desc->its_vmovi_cmd.db_enabled) | |
683 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; | |
684 | else | |
685 | db = 1023; | |
686 | ||
687 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
688 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
689 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
690 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
691 | its_encode_db_phys_id(cmd, db); | |
692 | its_encode_db_valid(cmd, true); | |
693 | ||
694 | its_fixup_cmd(cmd); | |
695 | ||
205e065d | 696 | return valid_vpe(its, desc->its_vmovi_cmd.vpe); |
d011e4e6 MZ |
697 | } |
698 | ||
67047f90 MZ |
699 | static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, |
700 | struct its_cmd_block *cmd, | |
3171a47a MZ |
701 | struct its_cmd_desc *desc) |
702 | { | |
5c9a882e MZ |
703 | u64 target; |
704 | ||
705 | target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; | |
3171a47a MZ |
706 | its_encode_cmd(cmd, GITS_CMD_VMOVP); |
707 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
708 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
709 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
5c9a882e | 710 | its_encode_target(cmd, target); |
3171a47a MZ |
711 | |
712 | its_fixup_cmd(cmd); | |
713 | ||
205e065d | 714 | return valid_vpe(its, desc->its_vmovp_cmd.vpe); |
3171a47a MZ |
715 | } |
716 | ||
28614696 MZ |
717 | static struct its_vpe *its_build_vinv_cmd(struct its_node *its, |
718 | struct its_cmd_block *cmd, | |
719 | struct its_cmd_desc *desc) | |
720 | { | |
721 | struct its_vlpi_map *map; | |
722 | ||
723 | map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, | |
724 | desc->its_inv_cmd.event_id); | |
725 | ||
726 | its_encode_cmd(cmd, GITS_CMD_INV); | |
727 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
728 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
729 | ||
730 | its_fixup_cmd(cmd); | |
731 | ||
732 | return valid_vpe(its, map->vpe); | |
733 | } | |
734 | ||
ed0e4aa9 MZ |
735 | static struct its_vpe *its_build_vint_cmd(struct its_node *its, |
736 | struct its_cmd_block *cmd, | |
737 | struct its_cmd_desc *desc) | |
738 | { | |
739 | struct its_vlpi_map *map; | |
740 | ||
741 | map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, | |
742 | desc->its_int_cmd.event_id); | |
743 | ||
744 | its_encode_cmd(cmd, GITS_CMD_INT); | |
745 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
746 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
747 | ||
748 | its_fixup_cmd(cmd); | |
749 | ||
750 | return valid_vpe(its, map->vpe); | |
751 | } | |
752 | ||
753 | static struct its_vpe *its_build_vclear_cmd(struct its_node *its, | |
754 | struct its_cmd_block *cmd, | |
755 | struct its_cmd_desc *desc) | |
756 | { | |
757 | struct its_vlpi_map *map; | |
758 | ||
759 | map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, | |
760 | desc->its_clear_cmd.event_id); | |
761 | ||
762 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
763 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
764 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
765 | ||
766 | its_fixup_cmd(cmd); | |
767 | ||
768 | return valid_vpe(its, map->vpe); | |
769 | } | |
770 | ||
cc2d3216 MZ |
771 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
772 | struct its_cmd_block *ptr) | |
773 | { | |
774 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
775 | } | |
776 | ||
777 | static int its_queue_full(struct its_node *its) | |
778 | { | |
779 | int widx; | |
780 | int ridx; | |
781 | ||
782 | widx = its->cmd_write - its->cmd_base; | |
783 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
784 | ||
785 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
786 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
787 | return 1; | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
793 | { | |
794 | struct its_cmd_block *cmd; | |
795 | u32 count = 1000000; /* 1s! */ | |
796 | ||
797 | while (its_queue_full(its)) { | |
798 | count--; | |
799 | if (!count) { | |
800 | pr_err_ratelimited("ITS queue not draining\n"); | |
801 | return NULL; | |
802 | } | |
803 | cpu_relax(); | |
804 | udelay(1); | |
805 | } | |
806 | ||
807 | cmd = its->cmd_write++; | |
808 | ||
809 | /* Handle queue wrapping */ | |
810 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
811 | its->cmd_write = its->cmd_base; | |
812 | ||
34d677a9 MZ |
813 | /* Clear command */ |
814 | cmd->raw_cmd[0] = 0; | |
815 | cmd->raw_cmd[1] = 0; | |
816 | cmd->raw_cmd[2] = 0; | |
817 | cmd->raw_cmd[3] = 0; | |
818 | ||
cc2d3216 MZ |
819 | return cmd; |
820 | } | |
821 | ||
822 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
823 | { | |
824 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
825 | ||
826 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
827 | ||
828 | return its->cmd_write; | |
829 | } | |
830 | ||
831 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
832 | { | |
833 | /* | |
834 | * Make sure the commands written to memory are observable by | |
835 | * the ITS. | |
836 | */ | |
837 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 838 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
839 | else |
840 | dsb(ishst); | |
841 | } | |
842 | ||
a19b462f | 843 | static int its_wait_for_range_completion(struct its_node *its, |
a050fa54 | 844 | u64 prev_idx, |
a19b462f | 845 | struct its_cmd_block *to) |
cc2d3216 | 846 | { |
a050fa54 | 847 | u64 rd_idx, to_idx, linear_idx; |
cc2d3216 MZ |
848 | u32 count = 1000000; /* 1s! */ |
849 | ||
a050fa54 | 850 | /* Linearize to_idx if the command set has wrapped around */ |
cc2d3216 | 851 | to_idx = its_cmd_ptr_to_offset(its, to); |
a050fa54 HG |
852 | if (to_idx < prev_idx) |
853 | to_idx += ITS_CMD_QUEUE_SZ; | |
854 | ||
855 | linear_idx = prev_idx; | |
cc2d3216 MZ |
856 | |
857 | while (1) { | |
a050fa54 HG |
858 | s64 delta; |
859 | ||
cc2d3216 | 860 | rd_idx = readl_relaxed(its->base + GITS_CREADR); |
9bdd8b1c | 861 | |
a050fa54 HG |
862 | /* |
863 | * Compute the read pointer progress, taking the | |
864 | * potential wrap-around into account. | |
865 | */ | |
866 | delta = rd_idx - prev_idx; | |
867 | if (rd_idx < prev_idx) | |
868 | delta += ITS_CMD_QUEUE_SZ; | |
9bdd8b1c | 869 | |
a050fa54 HG |
870 | linear_idx += delta; |
871 | if (linear_idx >= to_idx) | |
cc2d3216 MZ |
872 | break; |
873 | ||
874 | count--; | |
875 | if (!count) { | |
a050fa54 HG |
876 | pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", |
877 | to_idx, linear_idx); | |
a19b462f | 878 | return -1; |
cc2d3216 | 879 | } |
a050fa54 | 880 | prev_idx = rd_idx; |
cc2d3216 MZ |
881 | cpu_relax(); |
882 | udelay(1); | |
883 | } | |
a19b462f MZ |
884 | |
885 | return 0; | |
cc2d3216 MZ |
886 | } |
887 | ||
e4f9094b MZ |
888 | /* Warning, macro hell follows */ |
889 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
890 | void name(struct its_node *its, \ | |
891 | buildtype builder, \ | |
892 | struct its_cmd_desc *desc) \ | |
893 | { \ | |
894 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
895 | synctype *sync_obj; \ | |
896 | unsigned long flags; \ | |
a050fa54 | 897 | u64 rd_idx; \ |
e4f9094b MZ |
898 | \ |
899 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
900 | \ | |
901 | cmd = its_allocate_entry(its); \ | |
902 | if (!cmd) { /* We're soooooo screewed... */ \ | |
903 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
904 | return; \ | |
905 | } \ | |
67047f90 | 906 | sync_obj = builder(its, cmd, desc); \ |
e4f9094b MZ |
907 | its_flush_cmd(its, cmd); \ |
908 | \ | |
909 | if (sync_obj) { \ | |
910 | sync_cmd = its_allocate_entry(its); \ | |
911 | if (!sync_cmd) \ | |
912 | goto post; \ | |
913 | \ | |
67047f90 | 914 | buildfn(its, sync_cmd, sync_obj); \ |
e4f9094b MZ |
915 | its_flush_cmd(its, sync_cmd); \ |
916 | } \ | |
917 | \ | |
918 | post: \ | |
a050fa54 | 919 | rd_idx = readl_relaxed(its->base + GITS_CREADR); \ |
e4f9094b MZ |
920 | next_cmd = its_post_commands(its); \ |
921 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
922 | \ | |
a050fa54 | 923 | if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \ |
a19b462f | 924 | pr_err_ratelimited("ITS cmd %ps failed\n", builder); \ |
e4f9094b | 925 | } |
cc2d3216 | 926 | |
67047f90 MZ |
927 | static void its_build_sync_cmd(struct its_node *its, |
928 | struct its_cmd_block *sync_cmd, | |
e4f9094b MZ |
929 | struct its_collection *sync_col) |
930 | { | |
931 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
932 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 933 | |
e4f9094b | 934 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
935 | } |
936 | ||
e4f9094b MZ |
937 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
938 | struct its_collection, its_build_sync_cmd) | |
939 | ||
67047f90 MZ |
940 | static void its_build_vsync_cmd(struct its_node *its, |
941 | struct its_cmd_block *sync_cmd, | |
d011e4e6 MZ |
942 | struct its_vpe *sync_vpe) |
943 | { | |
944 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
945 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
946 | ||
947 | its_fixup_cmd(sync_cmd); | |
948 | } | |
949 | ||
950 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
951 | struct its_vpe, its_build_vsync_cmd) | |
952 | ||
8d85dced | 953 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 954 | { |
8d85dced | 955 | struct its_cmd_desc desc; |
cc2d3216 | 956 | |
8d85dced MZ |
957 | desc.its_int_cmd.dev = dev; |
958 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 959 | |
8d85dced MZ |
960 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
961 | } | |
cc2d3216 | 962 | |
8d85dced MZ |
963 | static void its_send_clear(struct its_device *dev, u32 event_id) |
964 | { | |
965 | struct its_cmd_desc desc; | |
cc2d3216 | 966 | |
8d85dced MZ |
967 | desc.its_clear_cmd.dev = dev; |
968 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 969 | |
8d85dced | 970 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
971 | } |
972 | ||
973 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
974 | { | |
975 | struct its_cmd_desc desc; | |
976 | ||
977 | desc.its_inv_cmd.dev = dev; | |
978 | desc.its_inv_cmd.event_id = event_id; | |
979 | ||
980 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
981 | } | |
982 | ||
983 | static void its_send_mapd(struct its_device *dev, int valid) | |
984 | { | |
985 | struct its_cmd_desc desc; | |
986 | ||
987 | desc.its_mapd_cmd.dev = dev; | |
988 | desc.its_mapd_cmd.valid = !!valid; | |
989 | ||
990 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
991 | } | |
992 | ||
993 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
994 | int valid) | |
995 | { | |
996 | struct its_cmd_desc desc; | |
997 | ||
998 | desc.its_mapc_cmd.col = col; | |
999 | desc.its_mapc_cmd.valid = !!valid; | |
1000 | ||
1001 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
1002 | } | |
1003 | ||
6a25ad3a | 1004 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
1005 | { |
1006 | struct its_cmd_desc desc; | |
1007 | ||
6a25ad3a MZ |
1008 | desc.its_mapti_cmd.dev = dev; |
1009 | desc.its_mapti_cmd.phys_id = irq_id; | |
1010 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 1011 | |
6a25ad3a | 1012 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
1013 | } |
1014 | ||
1015 | static void its_send_movi(struct its_device *dev, | |
1016 | struct its_collection *col, u32 id) | |
1017 | { | |
1018 | struct its_cmd_desc desc; | |
1019 | ||
1020 | desc.its_movi_cmd.dev = dev; | |
1021 | desc.its_movi_cmd.col = col; | |
591e5bec | 1022 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
1023 | |
1024 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
1025 | } | |
1026 | ||
1027 | static void its_send_discard(struct its_device *dev, u32 id) | |
1028 | { | |
1029 | struct its_cmd_desc desc; | |
1030 | ||
1031 | desc.its_discard_cmd.dev = dev; | |
1032 | desc.its_discard_cmd.event_id = id; | |
1033 | ||
1034 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
1035 | } | |
1036 | ||
1037 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
1038 | { | |
1039 | struct its_cmd_desc desc; | |
1040 | ||
1041 | desc.its_invall_cmd.col = col; | |
1042 | ||
1043 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
1044 | } | |
c48ed51c | 1045 | |
d011e4e6 MZ |
1046 | static void its_send_vmapti(struct its_device *dev, u32 id) |
1047 | { | |
c1d4d5cd | 1048 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1049 | struct its_cmd_desc desc; |
1050 | ||
1051 | desc.its_vmapti_cmd.vpe = map->vpe; | |
1052 | desc.its_vmapti_cmd.dev = dev; | |
1053 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
1054 | desc.its_vmapti_cmd.event_id = id; | |
1055 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
1056 | ||
1057 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
1058 | } | |
1059 | ||
1060 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
1061 | { | |
c1d4d5cd | 1062 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1063 | struct its_cmd_desc desc; |
1064 | ||
1065 | desc.its_vmovi_cmd.vpe = map->vpe; | |
1066 | desc.its_vmovi_cmd.dev = dev; | |
1067 | desc.its_vmovi_cmd.event_id = id; | |
1068 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
1069 | ||
1070 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
1071 | } | |
1072 | ||
75fd951b MZ |
1073 | static void its_send_vmapp(struct its_node *its, |
1074 | struct its_vpe *vpe, bool valid) | |
eb78192b MZ |
1075 | { |
1076 | struct its_cmd_desc desc; | |
eb78192b MZ |
1077 | |
1078 | desc.its_vmapp_cmd.vpe = vpe; | |
1079 | desc.its_vmapp_cmd.valid = valid; | |
75fd951b | 1080 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; |
eb78192b | 1081 | |
75fd951b | 1082 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); |
eb78192b MZ |
1083 | } |
1084 | ||
3171a47a MZ |
1085 | static void its_send_vmovp(struct its_vpe *vpe) |
1086 | { | |
84243125 | 1087 | struct its_cmd_desc desc = {}; |
3171a47a MZ |
1088 | struct its_node *its; |
1089 | unsigned long flags; | |
1090 | int col_id = vpe->col_idx; | |
1091 | ||
1092 | desc.its_vmovp_cmd.vpe = vpe; | |
3171a47a MZ |
1093 | |
1094 | if (!its_list_map) { | |
1095 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
3171a47a MZ |
1096 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1097 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1098 | return; | |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * Yet another marvel of the architecture. If using the | |
1103 | * its_list "feature", we need to make sure that all ITSs | |
1104 | * receive all VMOVP commands in the same order. The only way | |
1105 | * to guarantee this is to make vmovp a serialization point. | |
1106 | * | |
1107 | * Wall <-- Head. | |
1108 | */ | |
1109 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1110 | ||
1111 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
84243125 | 1112 | desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); |
3171a47a MZ |
1113 | |
1114 | /* Emit VMOVPs */ | |
1115 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 1116 | if (!is_v4(its)) |
3171a47a MZ |
1117 | continue; |
1118 | ||
2247e1bf MZ |
1119 | if (!vpe->its_vm->vlpi_count[its->list_nr]) |
1120 | continue; | |
1121 | ||
3171a47a MZ |
1122 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1123 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1124 | } | |
1125 | ||
1126 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1127 | } | |
1128 | ||
40619a2e | 1129 | static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) |
eb78192b MZ |
1130 | { |
1131 | struct its_cmd_desc desc; | |
eb78192b MZ |
1132 | |
1133 | desc.its_vinvall_cmd.vpe = vpe; | |
40619a2e | 1134 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); |
eb78192b MZ |
1135 | } |
1136 | ||
28614696 MZ |
1137 | static void its_send_vinv(struct its_device *dev, u32 event_id) |
1138 | { | |
1139 | struct its_cmd_desc desc; | |
1140 | ||
1141 | /* | |
1142 | * There is no real VINV command. This is just a normal INV, | |
1143 | * with a VSYNC instead of a SYNC. | |
1144 | */ | |
1145 | desc.its_inv_cmd.dev = dev; | |
1146 | desc.its_inv_cmd.event_id = event_id; | |
1147 | ||
1148 | its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); | |
1149 | } | |
1150 | ||
ed0e4aa9 MZ |
1151 | static void its_send_vint(struct its_device *dev, u32 event_id) |
1152 | { | |
1153 | struct its_cmd_desc desc; | |
1154 | ||
1155 | /* | |
1156 | * There is no real VINT command. This is just a normal INT, | |
1157 | * with a VSYNC instead of a SYNC. | |
1158 | */ | |
1159 | desc.its_int_cmd.dev = dev; | |
1160 | desc.its_int_cmd.event_id = event_id; | |
1161 | ||
1162 | its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); | |
1163 | } | |
1164 | ||
1165 | static void its_send_vclear(struct its_device *dev, u32 event_id) | |
1166 | { | |
1167 | struct its_cmd_desc desc; | |
1168 | ||
1169 | /* | |
1170 | * There is no real VCLEAR command. This is just a normal CLEAR, | |
1171 | * with a VSYNC instead of a SYNC. | |
1172 | */ | |
1173 | desc.its_clear_cmd.dev = dev; | |
1174 | desc.its_clear_cmd.event_id = event_id; | |
1175 | ||
1176 | its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); | |
1177 | } | |
1178 | ||
c48ed51c MZ |
1179 | /* |
1180 | * irqchip functions - assumes MSI, mostly. | |
1181 | */ | |
c1d4d5cd MZ |
1182 | static struct its_vlpi_map *get_vlpi_map(struct irq_data *d) |
1183 | { | |
093bf439 MZ |
1184 | if (irqd_is_forwarded_to_vcpu(d)) { |
1185 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1186 | u32 event = its_get_event_id(d); | |
c1d4d5cd | 1187 | |
093bf439 MZ |
1188 | return dev_event_to_vlpi_map(its_dev, event); |
1189 | } | |
c1d4d5cd | 1190 | |
093bf439 | 1191 | return NULL; |
c1d4d5cd | 1192 | } |
c48ed51c | 1193 | |
015ec038 | 1194 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 1195 | { |
c1d4d5cd | 1196 | struct its_vlpi_map *map = get_vlpi_map(d); |
015ec038 | 1197 | irq_hw_number_t hwirq; |
e1a2e201 | 1198 | void *va; |
adcdb94e | 1199 | u8 *cfg; |
c48ed51c | 1200 | |
c1d4d5cd MZ |
1201 | if (map) { |
1202 | va = page_address(map->vm->vprop_page); | |
d4d7b4ad MZ |
1203 | hwirq = map->vintid; |
1204 | ||
1205 | /* Remember the updated property */ | |
1206 | map->properties &= ~clr; | |
1207 | map->properties |= set | LPI_PROP_GROUP1; | |
015ec038 | 1208 | } else { |
e1a2e201 | 1209 | va = gic_rdists->prop_table_va; |
015ec038 MZ |
1210 | hwirq = d->hwirq; |
1211 | } | |
adcdb94e | 1212 | |
e1a2e201 | 1213 | cfg = va + hwirq - 8192; |
adcdb94e | 1214 | *cfg &= ~clr; |
015ec038 | 1215 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1216 | |
1217 | /* | |
1218 | * Make the above write visible to the redistributors. | |
1219 | * And yes, we're flushing exactly: One. Single. Byte. | |
1220 | * Humpf... | |
1221 | */ | |
1222 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1223 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1224 | else |
1225 | dsb(ishst); | |
015ec038 MZ |
1226 | } |
1227 | ||
2f4f064b MZ |
1228 | static void wait_for_syncr(void __iomem *rdbase) |
1229 | { | |
1230 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
1231 | cpu_relax(); | |
1232 | } | |
1233 | ||
425c09be MZ |
1234 | static void direct_lpi_inv(struct irq_data *d) |
1235 | { | |
1236 | struct its_collection *col; | |
1237 | void __iomem *rdbase; | |
1238 | ||
1239 | /* Target the redistributor this LPI is currently routed to */ | |
1240 | col = irq_to_col(d); | |
1241 | rdbase = per_cpu_ptr(gic_rdists->rdist, col->col_id)->rd_base; | |
1242 | gic_write_lpir(d->hwirq, rdbase + GICR_INVLPIR); | |
1243 | ||
1244 | wait_for_syncr(rdbase); | |
1245 | } | |
1246 | ||
015ec038 MZ |
1247 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) |
1248 | { | |
1249 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1250 | ||
1251 | lpi_write_config(d, clr, set); | |
425c09be MZ |
1252 | if (gic_rdists->has_direct_lpi && !irqd_is_forwarded_to_vcpu(d)) |
1253 | direct_lpi_inv(d); | |
28614696 | 1254 | else if (!irqd_is_forwarded_to_vcpu(d)) |
425c09be | 1255 | its_send_inv(its_dev, its_get_event_id(d)); |
28614696 MZ |
1256 | else |
1257 | its_send_vinv(its_dev, its_get_event_id(d)); | |
c48ed51c MZ |
1258 | } |
1259 | ||
015ec038 MZ |
1260 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1261 | { | |
1262 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1263 | u32 event = its_get_event_id(d); | |
c1d4d5cd | 1264 | struct its_vlpi_map *map; |
015ec038 | 1265 | |
c1d4d5cd MZ |
1266 | map = dev_event_to_vlpi_map(its_dev, event); |
1267 | ||
1268 | if (map->db_enabled == enable) | |
015ec038 MZ |
1269 | return; |
1270 | ||
c1d4d5cd | 1271 | map->db_enabled = enable; |
015ec038 MZ |
1272 | |
1273 | /* | |
1274 | * More fun with the architecture: | |
1275 | * | |
1276 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1277 | * value or to 1023, depending on the enable bit. But that | |
1278 | * would be issueing a mapping for an /existing/ DevID+EventID | |
1279 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
1280 | * to the /same/ vPE, using this opportunity to adjust the | |
1281 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1282 | */ | |
1283 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1284 | } |
1285 | ||
1286 | static void its_mask_irq(struct irq_data *d) | |
1287 | { | |
015ec038 MZ |
1288 | if (irqd_is_forwarded_to_vcpu(d)) |
1289 | its_vlpi_set_doorbell(d, false); | |
1290 | ||
adcdb94e | 1291 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1292 | } |
1293 | ||
1294 | static void its_unmask_irq(struct irq_data *d) | |
1295 | { | |
015ec038 MZ |
1296 | if (irqd_is_forwarded_to_vcpu(d)) |
1297 | its_vlpi_set_doorbell(d, true); | |
1298 | ||
adcdb94e | 1299 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1300 | } |
1301 | ||
c48ed51c MZ |
1302 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1303 | bool force) | |
1304 | { | |
fbf8f40e GK |
1305 | unsigned int cpu; |
1306 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
1307 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1308 | struct its_collection *target_col; | |
1309 | u32 id = its_get_event_id(d); | |
1310 | ||
015ec038 MZ |
1311 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1312 | if (irqd_is_forwarded_to_vcpu(d)) | |
1313 | return -EINVAL; | |
1314 | ||
fbf8f40e GK |
1315 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
1316 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1317 | if (its_dev->its->numa_node >= 0) { | |
1318 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
1319 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
1320 | return -EINVAL; | |
1321 | } | |
1322 | } | |
1323 | ||
1324 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
1325 | ||
c48ed51c MZ |
1326 | if (cpu >= nr_cpu_ids) |
1327 | return -EINVAL; | |
1328 | ||
8b8d94a7 M |
1329 | /* don't set the affinity when the target cpu is same as current one */ |
1330 | if (cpu != its_dev->event_map.col_map[id]) { | |
1331 | target_col = &its_dev->its->collections[cpu]; | |
1332 | its_send_movi(its_dev, target_col, id); | |
1333 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1334 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1335 | } |
c48ed51c MZ |
1336 | |
1337 | return IRQ_SET_MASK_OK_DONE; | |
1338 | } | |
1339 | ||
558b0165 AB |
1340 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1341 | { | |
1342 | struct its_node *its = its_dev->its; | |
1343 | ||
1344 | return its->phys_base + GITS_TRANSLATER; | |
1345 | } | |
1346 | ||
b48ac83d MZ |
1347 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1348 | { | |
1349 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1350 | struct its_node *its; | |
1351 | u64 addr; | |
1352 | ||
1353 | its = its_dev->its; | |
558b0165 | 1354 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1355 | |
b11283eb VM |
1356 | msg->address_lo = lower_32_bits(addr); |
1357 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1358 | msg->data = its_get_event_id(d); |
44bb7e24 | 1359 | |
35ae7df2 | 1360 | iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); |
b48ac83d MZ |
1361 | } |
1362 | ||
8d85dced MZ |
1363 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1364 | enum irqchip_irq_state which, | |
1365 | bool state) | |
1366 | { | |
1367 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1368 | u32 event = its_get_event_id(d); | |
1369 | ||
1370 | if (which != IRQCHIP_STATE_PENDING) | |
1371 | return -EINVAL; | |
1372 | ||
ed0e4aa9 MZ |
1373 | if (irqd_is_forwarded_to_vcpu(d)) { |
1374 | if (state) | |
1375 | its_send_vint(its_dev, event); | |
1376 | else | |
1377 | its_send_vclear(its_dev, event); | |
1378 | } else { | |
1379 | if (state) | |
1380 | its_send_int(its_dev, event); | |
1381 | else | |
1382 | its_send_clear(its_dev, event); | |
1383 | } | |
8d85dced MZ |
1384 | |
1385 | return 0; | |
1386 | } | |
1387 | ||
2247e1bf MZ |
1388 | static void its_map_vm(struct its_node *its, struct its_vm *vm) |
1389 | { | |
1390 | unsigned long flags; | |
1391 | ||
1392 | /* Not using the ITS list? Everything is always mapped. */ | |
1393 | if (!its_list_map) | |
1394 | return; | |
1395 | ||
1396 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1397 | ||
1398 | /* | |
1399 | * If the VM wasn't mapped yet, iterate over the vpes and get | |
1400 | * them mapped now. | |
1401 | */ | |
1402 | vm->vlpi_count[its->list_nr]++; | |
1403 | ||
1404 | if (vm->vlpi_count[its->list_nr] == 1) { | |
1405 | int i; | |
1406 | ||
1407 | for (i = 0; i < vm->nr_vpes; i++) { | |
1408 | struct its_vpe *vpe = vm->vpes[i]; | |
44c4c25e | 1409 | struct irq_data *d = irq_get_irq_data(vpe->irq); |
2247e1bf MZ |
1410 | |
1411 | /* Map the VPE to the first possible CPU */ | |
1412 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
1413 | its_send_vmapp(its, vpe, true); | |
1414 | its_send_vinvall(its, vpe); | |
44c4c25e | 1415 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
2247e1bf MZ |
1416 | } |
1417 | } | |
1418 | ||
1419 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1420 | } | |
1421 | ||
1422 | static void its_unmap_vm(struct its_node *its, struct its_vm *vm) | |
1423 | { | |
1424 | unsigned long flags; | |
1425 | ||
1426 | /* Not using the ITS list? Everything is always mapped. */ | |
1427 | if (!its_list_map) | |
1428 | return; | |
1429 | ||
1430 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1431 | ||
1432 | if (!--vm->vlpi_count[its->list_nr]) { | |
1433 | int i; | |
1434 | ||
1435 | for (i = 0; i < vm->nr_vpes; i++) | |
1436 | its_send_vmapp(its, vm->vpes[i], false); | |
1437 | } | |
1438 | ||
1439 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1440 | } | |
1441 | ||
d011e4e6 MZ |
1442 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1443 | { | |
1444 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1445 | u32 event = its_get_event_id(d); | |
1446 | int ret = 0; | |
1447 | ||
1448 | if (!info->map) | |
1449 | return -EINVAL; | |
1450 | ||
11635fa2 | 1451 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1452 | |
1453 | if (!its_dev->event_map.vm) { | |
1454 | struct its_vlpi_map *maps; | |
1455 | ||
6396bb22 | 1456 | maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), |
11635fa2 | 1457 | GFP_ATOMIC); |
d011e4e6 MZ |
1458 | if (!maps) { |
1459 | ret = -ENOMEM; | |
1460 | goto out; | |
1461 | } | |
1462 | ||
1463 | its_dev->event_map.vm = info->map->vm; | |
1464 | its_dev->event_map.vlpi_maps = maps; | |
1465 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1466 | ret = -EINVAL; | |
1467 | goto out; | |
1468 | } | |
1469 | ||
1470 | /* Get our private copy of the mapping information */ | |
1471 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1472 | ||
1473 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1474 | /* Already mapped, move it around */ | |
1475 | its_send_vmovi(its_dev, event); | |
1476 | } else { | |
2247e1bf MZ |
1477 | /* Ensure all the VPEs are mapped on this ITS */ |
1478 | its_map_vm(its_dev->its, info->map->vm); | |
1479 | ||
d4d7b4ad MZ |
1480 | /* |
1481 | * Flag the interrupt as forwarded so that we can | |
1482 | * start poking the virtual property table. | |
1483 | */ | |
1484 | irqd_set_forwarded_to_vcpu(d); | |
1485 | ||
1486 | /* Write out the property to the prop table */ | |
1487 | lpi_write_config(d, 0xff, info->map->properties); | |
1488 | ||
d011e4e6 MZ |
1489 | /* Drop the physical mapping */ |
1490 | its_send_discard(its_dev, event); | |
1491 | ||
1492 | /* and install the virtual one */ | |
1493 | its_send_vmapti(its_dev, event); | |
d011e4e6 MZ |
1494 | |
1495 | /* Increment the number of VLPIs */ | |
1496 | its_dev->event_map.nr_vlpis++; | |
1497 | } | |
1498 | ||
1499 | out: | |
11635fa2 | 1500 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1501 | return ret; |
1502 | } | |
1503 | ||
1504 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1505 | { | |
1506 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
046b5054 | 1507 | struct its_vlpi_map *map; |
d011e4e6 MZ |
1508 | int ret = 0; |
1509 | ||
11635fa2 | 1510 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 | 1511 | |
046b5054 MZ |
1512 | map = get_vlpi_map(d); |
1513 | ||
1514 | if (!its_dev->event_map.vm || !map) { | |
d011e4e6 MZ |
1515 | ret = -EINVAL; |
1516 | goto out; | |
1517 | } | |
1518 | ||
1519 | /* Copy our mapping information to the incoming request */ | |
c1d4d5cd | 1520 | *info->map = *map; |
d011e4e6 MZ |
1521 | |
1522 | out: | |
11635fa2 | 1523 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1524 | return ret; |
1525 | } | |
1526 | ||
1527 | static int its_vlpi_unmap(struct irq_data *d) | |
1528 | { | |
1529 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1530 | u32 event = its_get_event_id(d); | |
1531 | int ret = 0; | |
1532 | ||
11635fa2 | 1533 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1534 | |
1535 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1536 | ret = -EINVAL; | |
1537 | goto out; | |
1538 | } | |
1539 | ||
1540 | /* Drop the virtual mapping */ | |
1541 | its_send_discard(its_dev, event); | |
1542 | ||
1543 | /* and restore the physical one */ | |
1544 | irqd_clr_forwarded_to_vcpu(d); | |
1545 | its_send_mapti(its_dev, d->hwirq, event); | |
1546 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1547 | LPI_PROP_ENABLED | | |
1548 | LPI_PROP_GROUP1)); | |
1549 | ||
2247e1bf MZ |
1550 | /* Potentially unmap the VM from this ITS */ |
1551 | its_unmap_vm(its_dev->its, its_dev->event_map.vm); | |
1552 | ||
d011e4e6 MZ |
1553 | /* |
1554 | * Drop the refcount and make the device available again if | |
1555 | * this was the last VLPI. | |
1556 | */ | |
1557 | if (!--its_dev->event_map.nr_vlpis) { | |
1558 | its_dev->event_map.vm = NULL; | |
1559 | kfree(its_dev->event_map.vlpi_maps); | |
1560 | } | |
1561 | ||
1562 | out: | |
11635fa2 | 1563 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1564 | return ret; |
1565 | } | |
1566 | ||
015ec038 MZ |
1567 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1568 | { | |
1569 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1570 | ||
1571 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1572 | return -EINVAL; | |
1573 | ||
1574 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1575 | lpi_update_config(d, 0xff, info->config); | |
1576 | else | |
1577 | lpi_write_config(d, 0xff, info->config); | |
1578 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
c808eea8 MZ |
1583 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1584 | { | |
1585 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1586 | struct its_cmd_info *info = vcpu_info; | |
1587 | ||
1588 | /* Need a v4 ITS */ | |
0dd57fed | 1589 | if (!is_v4(its_dev->its)) |
c808eea8 MZ |
1590 | return -EINVAL; |
1591 | ||
d011e4e6 MZ |
1592 | /* Unmap request? */ |
1593 | if (!info) | |
1594 | return its_vlpi_unmap(d); | |
1595 | ||
c808eea8 MZ |
1596 | switch (info->cmd_type) { |
1597 | case MAP_VLPI: | |
d011e4e6 | 1598 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1599 | |
1600 | case GET_VLPI: | |
d011e4e6 | 1601 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1602 | |
1603 | case PROP_UPDATE_VLPI: | |
1604 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1605 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1606 | |
1607 | default: | |
1608 | return -EINVAL; | |
1609 | } | |
1610 | } | |
1611 | ||
c48ed51c MZ |
1612 | static struct irq_chip its_irq_chip = { |
1613 | .name = "ITS", | |
1614 | .irq_mask = its_mask_irq, | |
1615 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1616 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1617 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1618 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1619 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1620 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1621 | }; |
1622 | ||
880cb3cd | 1623 | |
bf9529f8 MZ |
1624 | /* |
1625 | * How we allocate LPIs: | |
1626 | * | |
880cb3cd MZ |
1627 | * lpi_range_list contains ranges of LPIs that are to available to |
1628 | * allocate from. To allocate LPIs, just pick the first range that | |
1629 | * fits the required allocation, and reduce it by the required | |
1630 | * amount. Once empty, remove the range from the list. | |
1631 | * | |
1632 | * To free a range of LPIs, add a free range to the list, sort it and | |
1633 | * merge the result if the new range happens to be adjacent to an | |
1634 | * already free block. | |
bf9529f8 | 1635 | * |
880cb3cd MZ |
1636 | * The consequence of the above is that allocation is cost is low, but |
1637 | * freeing is expensive. We assumes that freeing rarely occurs. | |
1638 | */ | |
4cb205c0 | 1639 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
880cb3cd | 1640 | |
880cb3cd MZ |
1641 | static DEFINE_MUTEX(lpi_range_lock); |
1642 | static LIST_HEAD(lpi_range_list); | |
1643 | ||
1644 | struct lpi_range { | |
1645 | struct list_head entry; | |
1646 | u32 base_id; | |
1647 | u32 span; | |
1648 | }; | |
bf9529f8 | 1649 | |
880cb3cd | 1650 | static struct lpi_range *mk_lpi_range(u32 base, u32 span) |
bf9529f8 | 1651 | { |
880cb3cd MZ |
1652 | struct lpi_range *range; |
1653 | ||
1c73fac5 | 1654 | range = kmalloc(sizeof(*range), GFP_KERNEL); |
880cb3cd | 1655 | if (range) { |
880cb3cd MZ |
1656 | range->base_id = base; |
1657 | range->span = span; | |
1658 | } | |
1659 | ||
1660 | return range; | |
bf9529f8 MZ |
1661 | } |
1662 | ||
880cb3cd MZ |
1663 | static int alloc_lpi_range(u32 nr_lpis, u32 *base) |
1664 | { | |
1665 | struct lpi_range *range, *tmp; | |
1666 | int err = -ENOSPC; | |
1667 | ||
1668 | mutex_lock(&lpi_range_lock); | |
1669 | ||
1670 | list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) { | |
1671 | if (range->span >= nr_lpis) { | |
1672 | *base = range->base_id; | |
1673 | range->base_id += nr_lpis; | |
1674 | range->span -= nr_lpis; | |
1675 | ||
1676 | if (range->span == 0) { | |
1677 | list_del(&range->entry); | |
1678 | kfree(range); | |
1679 | } | |
1680 | ||
1681 | err = 0; | |
1682 | break; | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | mutex_unlock(&lpi_range_lock); | |
1687 | ||
1688 | pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); | |
1689 | return err; | |
bf9529f8 MZ |
1690 | } |
1691 | ||
12eade12 RV |
1692 | static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b) |
1693 | { | |
1694 | if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) | |
1695 | return; | |
1696 | if (a->base_id + a->span != b->base_id) | |
1697 | return; | |
1698 | b->base_id = a->base_id; | |
1699 | b->span += a->span; | |
1700 | list_del(&a->entry); | |
1701 | kfree(a); | |
1702 | } | |
1703 | ||
880cb3cd | 1704 | static int free_lpi_range(u32 base, u32 nr_lpis) |
bf9529f8 | 1705 | { |
12eade12 | 1706 | struct lpi_range *new, *old; |
880cb3cd MZ |
1707 | |
1708 | new = mk_lpi_range(base, nr_lpis); | |
b31a3838 RV |
1709 | if (!new) |
1710 | return -ENOMEM; | |
880cb3cd MZ |
1711 | |
1712 | mutex_lock(&lpi_range_lock); | |
1713 | ||
12eade12 RV |
1714 | list_for_each_entry_reverse(old, &lpi_range_list, entry) { |
1715 | if (old->base_id < base) | |
1716 | break; | |
880cb3cd | 1717 | } |
12eade12 RV |
1718 | /* |
1719 | * old is the last element with ->base_id smaller than base, | |
1720 | * so new goes right after it. If there are no elements with | |
1721 | * ->base_id smaller than base, &old->entry ends up pointing | |
1722 | * at the head of the list, and inserting new it the start of | |
1723 | * the list is the right thing to do in that case as well. | |
1724 | */ | |
1725 | list_add(&new->entry, &old->entry); | |
1726 | /* | |
1727 | * Now check if we can merge with the preceding and/or | |
1728 | * following ranges. | |
1729 | */ | |
1730 | merge_lpi_ranges(old, new); | |
1731 | merge_lpi_ranges(new, list_next_entry(new, entry)); | |
880cb3cd | 1732 | |
880cb3cd | 1733 | mutex_unlock(&lpi_range_lock); |
b31a3838 | 1734 | return 0; |
880cb3cd MZ |
1735 | } |
1736 | ||
1737 | static int __init its_lpi_init(u32 id_bits) | |
1738 | { | |
1739 | u32 lpis = (1UL << id_bits) - 8192; | |
12b2905a | 1740 | u32 numlpis; |
880cb3cd MZ |
1741 | int err; |
1742 | ||
12b2905a MZ |
1743 | numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); |
1744 | ||
1745 | if (numlpis > 2 && !WARN_ON(numlpis > lpis)) { | |
1746 | lpis = numlpis; | |
1747 | pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", | |
1748 | lpis); | |
1749 | } | |
1750 | ||
880cb3cd MZ |
1751 | /* |
1752 | * Initializing the allocator is just the same as freeing the | |
1753 | * full range of LPIs. | |
1754 | */ | |
1755 | err = free_lpi_range(8192, lpis); | |
1756 | pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); | |
1757 | return err; | |
1758 | } | |
bf9529f8 | 1759 | |
38dd7c49 | 1760 | static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids) |
880cb3cd MZ |
1761 | { |
1762 | unsigned long *bitmap = NULL; | |
1763 | int err = 0; | |
bf9529f8 MZ |
1764 | |
1765 | do { | |
38dd7c49 | 1766 | err = alloc_lpi_range(nr_irqs, base); |
880cb3cd | 1767 | if (!err) |
bf9529f8 MZ |
1768 | break; |
1769 | ||
38dd7c49 MZ |
1770 | nr_irqs /= 2; |
1771 | } while (nr_irqs > 0); | |
bf9529f8 | 1772 | |
45725e0f MZ |
1773 | if (!nr_irqs) |
1774 | err = -ENOSPC; | |
1775 | ||
880cb3cd | 1776 | if (err) |
bf9529f8 MZ |
1777 | goto out; |
1778 | ||
38dd7c49 | 1779 | bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC); |
bf9529f8 MZ |
1780 | if (!bitmap) |
1781 | goto out; | |
1782 | ||
38dd7c49 | 1783 | *nr_ids = nr_irqs; |
bf9529f8 MZ |
1784 | |
1785 | out: | |
c8415b94 MZ |
1786 | if (!bitmap) |
1787 | *base = *nr_ids = 0; | |
1788 | ||
bf9529f8 MZ |
1789 | return bitmap; |
1790 | } | |
1791 | ||
38dd7c49 | 1792 | static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids) |
bf9529f8 | 1793 | { |
880cb3cd | 1794 | WARN_ON(free_lpi_range(base, nr_ids)); |
cf2be8ba | 1795 | kfree(bitmap); |
bf9529f8 | 1796 | } |
1ac19ca6 | 1797 | |
053be485 MZ |
1798 | static void gic_reset_prop_table(void *va) |
1799 | { | |
1800 | /* Priority 0xa0, Group-1, disabled */ | |
1801 | memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ); | |
1802 | ||
1803 | /* Make sure the GIC will observe the written configuration */ | |
1804 | gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ); | |
1805 | } | |
1806 | ||
0e5ccf91 MZ |
1807 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
1808 | { | |
1809 | struct page *prop_page; | |
1ac19ca6 | 1810 | |
0e5ccf91 MZ |
1811 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
1812 | if (!prop_page) | |
1813 | return NULL; | |
1814 | ||
053be485 | 1815 | gic_reset_prop_table(page_address(prop_page)); |
0e5ccf91 MZ |
1816 | |
1817 | return prop_page; | |
1818 | } | |
1819 | ||
7d75bbb4 MZ |
1820 | static void its_free_prop_table(struct page *prop_page) |
1821 | { | |
1822 | free_pages((unsigned long)page_address(prop_page), | |
1823 | get_order(LPI_PROPBASE_SZ)); | |
1824 | } | |
1ac19ca6 | 1825 | |
5e2c9f9a MZ |
1826 | static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) |
1827 | { | |
1828 | phys_addr_t start, end, addr_end; | |
1829 | u64 i; | |
1830 | ||
1831 | /* | |
1832 | * We don't bother checking for a kdump kernel as by | |
1833 | * construction, the LPI tables are out of this kernel's | |
1834 | * memory map. | |
1835 | */ | |
1836 | if (is_kdump_kernel()) | |
1837 | return true; | |
1838 | ||
1839 | addr_end = addr + size - 1; | |
1840 | ||
1841 | for_each_reserved_mem_region(i, &start, &end) { | |
1842 | if (addr >= start && addr_end <= end) | |
1843 | return true; | |
1844 | } | |
1845 | ||
1846 | /* Not found, not a good sign... */ | |
1847 | pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n", | |
1848 | &addr, &addr_end); | |
1849 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
1850 | return false; | |
1851 | } | |
1852 | ||
3fb68fae MZ |
1853 | static int gic_reserve_range(phys_addr_t addr, unsigned long size) |
1854 | { | |
1855 | if (efi_enabled(EFI_CONFIG_TABLES)) | |
1856 | return efi_mem_reserve_persistent(addr, size); | |
1857 | ||
1858 | return 0; | |
1859 | } | |
1860 | ||
11e37d35 | 1861 | static int __init its_setup_lpi_prop_table(void) |
1ac19ca6 | 1862 | { |
c440a9d9 MZ |
1863 | if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { |
1864 | u64 val; | |
1ac19ca6 | 1865 | |
c440a9d9 MZ |
1866 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); |
1867 | lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1; | |
1ac19ca6 | 1868 | |
c440a9d9 MZ |
1869 | gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); |
1870 | gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, | |
1871 | LPI_PROPBASE_SZ, | |
1872 | MEMREMAP_WB); | |
1873 | gic_reset_prop_table(gic_rdists->prop_table_va); | |
1874 | } else { | |
1875 | struct page *page; | |
1876 | ||
1877 | lpi_id_bits = min_t(u32, | |
1878 | GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), | |
1879 | ITS_MAX_LPI_NRBITS); | |
1880 | page = its_allocate_prop_table(GFP_NOWAIT); | |
1881 | if (!page) { | |
1882 | pr_err("Failed to allocate PROPBASE\n"); | |
1883 | return -ENOMEM; | |
1884 | } | |
1885 | ||
1886 | gic_rdists->prop_table_pa = page_to_phys(page); | |
1887 | gic_rdists->prop_table_va = page_address(page); | |
3fb68fae MZ |
1888 | WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, |
1889 | LPI_PROPBASE_SZ)); | |
c440a9d9 | 1890 | } |
e1a2e201 MZ |
1891 | |
1892 | pr_info("GICv3: using LPI property table @%pa\n", | |
1893 | &gic_rdists->prop_table_pa); | |
1ac19ca6 | 1894 | |
6c31e123 | 1895 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
1896 | } |
1897 | ||
1898 | static const char *its_base_type_string[] = { | |
1899 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
1900 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 1901 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
1902 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
1903 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
1904 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
1905 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
1906 | }; | |
1907 | ||
2d81d425 SD |
1908 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
1909 | { | |
1910 | u32 idx = baser - its->tables; | |
1911 | ||
0968a619 | 1912 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1913 | } |
1914 | ||
1915 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
1916 | u64 val) | |
1917 | { | |
1918 | u32 idx = baser - its->tables; | |
1919 | ||
0968a619 | 1920 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1921 | baser->val = its_read_baser(its, baser); |
1922 | } | |
1923 | ||
9347359a | 1924 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
1925 | u64 cache, u64 shr, u32 psz, u32 order, |
1926 | bool indirect) | |
9347359a SD |
1927 | { |
1928 | u64 val = its_read_baser(its, baser); | |
1929 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
1930 | u64 type = GITS_BASER_TYPE(val); | |
30ae9610 | 1931 | u64 baser_phys, tmp; |
9347359a | 1932 | u32 alloc_pages; |
539d3782 | 1933 | struct page *page; |
9347359a | 1934 | void *base; |
9347359a SD |
1935 | |
1936 | retry_alloc_baser: | |
1937 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
1938 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
1939 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
1940 | &its->phys_base, its_base_type_string[type], | |
1941 | alloc_pages, GITS_BASER_PAGES_MAX); | |
1942 | alloc_pages = GITS_BASER_PAGES_MAX; | |
1943 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
1944 | } | |
1945 | ||
539d3782 SD |
1946 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); |
1947 | if (!page) | |
9347359a SD |
1948 | return -ENOMEM; |
1949 | ||
539d3782 | 1950 | base = (void *)page_address(page); |
30ae9610 SD |
1951 | baser_phys = virt_to_phys(base); |
1952 | ||
1953 | /* Check if the physical address of the memory is above 48bits */ | |
1954 | if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) { | |
1955 | ||
1956 | /* 52bit PA is supported only when PageSize=64K */ | |
1957 | if (psz != SZ_64K) { | |
1958 | pr_err("ITS: no 52bit PA support when psz=%d\n", psz); | |
1959 | free_pages((unsigned long)base, order); | |
1960 | return -ENXIO; | |
1961 | } | |
1962 | ||
1963 | /* Convert 52bit PA to 48bit field */ | |
1964 | baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys); | |
1965 | } | |
1966 | ||
9347359a | 1967 | retry_baser: |
30ae9610 | 1968 | val = (baser_phys | |
9347359a SD |
1969 | (type << GITS_BASER_TYPE_SHIFT) | |
1970 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
1971 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
1972 | cache | | |
1973 | shr | | |
1974 | GITS_BASER_VALID); | |
1975 | ||
3faf24ea SD |
1976 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
1977 | ||
9347359a SD |
1978 | switch (psz) { |
1979 | case SZ_4K: | |
1980 | val |= GITS_BASER_PAGE_SIZE_4K; | |
1981 | break; | |
1982 | case SZ_16K: | |
1983 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1984 | break; | |
1985 | case SZ_64K: | |
1986 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1987 | break; | |
1988 | } | |
1989 | ||
1990 | its_write_baser(its, baser, val); | |
1991 | tmp = baser->val; | |
1992 | ||
1993 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1994 | /* | |
1995 | * Shareability didn't stick. Just use | |
1996 | * whatever the read reported, which is likely | |
1997 | * to be the only thing this redistributor | |
1998 | * supports. If that's zero, make it | |
1999 | * non-cacheable as well. | |
2000 | */ | |
2001 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
2002 | if (!shr) { | |
2003 | cache = GITS_BASER_nC; | |
328191c0 | 2004 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
2005 | } |
2006 | goto retry_baser; | |
2007 | } | |
2008 | ||
2009 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
2010 | /* | |
2011 | * Page size didn't stick. Let's try a smaller | |
2012 | * size and retry. If we reach 4K, then | |
2013 | * something is horribly wrong... | |
2014 | */ | |
2015 | free_pages((unsigned long)base, order); | |
2016 | baser->base = NULL; | |
2017 | ||
2018 | switch (psz) { | |
2019 | case SZ_16K: | |
2020 | psz = SZ_4K; | |
2021 | goto retry_alloc_baser; | |
2022 | case SZ_64K: | |
2023 | psz = SZ_16K; | |
2024 | goto retry_alloc_baser; | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | if (val != tmp) { | |
b11283eb | 2029 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 2030 | &its->phys_base, its_base_type_string[type], |
b11283eb | 2031 | val, tmp); |
9347359a SD |
2032 | free_pages((unsigned long)base, order); |
2033 | return -ENXIO; | |
2034 | } | |
2035 | ||
2036 | baser->order = order; | |
2037 | baser->base = base; | |
2038 | baser->psz = psz; | |
3faf24ea | 2039 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 2040 | |
3faf24ea | 2041 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 2042 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
2043 | its_base_type_string[type], |
2044 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 2045 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
2046 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
2047 | ||
2048 | return 0; | |
2049 | } | |
2050 | ||
4cacac57 MZ |
2051 | static bool its_parse_indirect_baser(struct its_node *its, |
2052 | struct its_baser *baser, | |
32bd44dc | 2053 | u32 psz, u32 *order, u32 ids) |
4b75c459 | 2054 | { |
4cacac57 MZ |
2055 | u64 tmp = its_read_baser(its, baser); |
2056 | u64 type = GITS_BASER_TYPE(tmp); | |
2057 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 2058 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 | 2059 | u32 new_order = *order; |
3faf24ea SD |
2060 | bool indirect = false; |
2061 | ||
2062 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
2063 | if ((esz << ids) > (psz * 2)) { | |
2064 | /* | |
2065 | * Find out whether hw supports a single or two-level table by | |
2066 | * table by reading bit at offset '62' after writing '1' to it. | |
2067 | */ | |
2068 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
2069 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
2070 | ||
2071 | if (indirect) { | |
2072 | /* | |
2073 | * The size of the lvl2 table is equal to ITS page size | |
2074 | * which is 'psz'. For computing lvl1 table size, | |
2075 | * subtract ID bits that sparse lvl2 table from 'ids' | |
2076 | * which is reported by ITS hardware times lvl1 table | |
2077 | * entry size. | |
2078 | */ | |
d524eaa2 | 2079 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
2080 | esz = GITS_LVL1_ENTRY_SIZE; |
2081 | } | |
2082 | } | |
4b75c459 SD |
2083 | |
2084 | /* | |
2085 | * Allocate as many entries as required to fit the | |
2086 | * range of device IDs that the ITS can grok... The ID | |
2087 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
2088 | * massive waste of memory if two-level device table |
2089 | * feature is not supported by hardware. | |
4b75c459 SD |
2090 | */ |
2091 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
2092 | if (new_order >= MAX_ORDER) { | |
2093 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 2094 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
576a8342 | 2095 | pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", |
4cacac57 | 2096 | &its->phys_base, its_base_type_string[type], |
576a8342 | 2097 | device_ids(its), ids); |
4b75c459 SD |
2098 | } |
2099 | ||
2100 | *order = new_order; | |
3faf24ea SD |
2101 | |
2102 | return indirect; | |
4b75c459 SD |
2103 | } |
2104 | ||
5e516846 MZ |
2105 | static u32 compute_common_aff(u64 val) |
2106 | { | |
2107 | u32 aff, clpiaff; | |
2108 | ||
2109 | aff = FIELD_GET(GICR_TYPER_AFFINITY, val); | |
2110 | clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val); | |
2111 | ||
2112 | return aff & ~(GENMASK(31, 0) >> (clpiaff * 8)); | |
2113 | } | |
2114 | ||
2115 | static u32 compute_its_aff(struct its_node *its) | |
2116 | { | |
2117 | u64 val; | |
2118 | u32 svpet; | |
2119 | ||
2120 | /* | |
2121 | * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute | |
2122 | * the resulting affinity. We then use that to see if this match | |
2123 | * our own affinity. | |
2124 | */ | |
2125 | svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); | |
2126 | val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet); | |
2127 | val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); | |
2128 | return compute_common_aff(val); | |
2129 | } | |
2130 | ||
2131 | static struct its_node *find_sibling_its(struct its_node *cur_its) | |
2132 | { | |
2133 | struct its_node *its; | |
2134 | u32 aff; | |
2135 | ||
2136 | if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) | |
2137 | return NULL; | |
2138 | ||
2139 | aff = compute_its_aff(cur_its); | |
2140 | ||
2141 | list_for_each_entry(its, &its_nodes, entry) { | |
2142 | u64 baser; | |
2143 | ||
2144 | if (!is_v4_1(its) || its == cur_its) | |
2145 | continue; | |
2146 | ||
2147 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2148 | continue; | |
2149 | ||
2150 | if (aff != compute_its_aff(its)) | |
2151 | continue; | |
2152 | ||
2153 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2154 | baser = its->tables[2].val; | |
2155 | if (!(baser & GITS_BASER_VALID)) | |
2156 | continue; | |
2157 | ||
2158 | return its; | |
2159 | } | |
2160 | ||
2161 | return NULL; | |
2162 | } | |
2163 | ||
1ac19ca6 MZ |
2164 | static void its_free_tables(struct its_node *its) |
2165 | { | |
2166 | int i; | |
2167 | ||
2168 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
2169 | if (its->tables[i].base) { |
2170 | free_pages((unsigned long)its->tables[i].base, | |
2171 | its->tables[i].order); | |
2172 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
2173 | } |
2174 | } | |
2175 | } | |
2176 | ||
0e0b0f69 | 2177 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 2178 | { |
1ac19ca6 | 2179 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 2180 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
2181 | u32 psz = SZ_64K; |
2182 | int err, i; | |
94100970 | 2183 | |
fa150019 AB |
2184 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
2185 | /* erratum 24313: ignore memory access type */ | |
2186 | cache = GITS_BASER_nCnB; | |
466b7d16 | 2187 | |
1ac19ca6 | 2188 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
2189 | struct its_baser *baser = its->tables + i; |
2190 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 2191 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 2192 | u32 order = get_order(psz); |
3faf24ea | 2193 | bool indirect = false; |
1ac19ca6 | 2194 | |
4cacac57 MZ |
2195 | switch (type) { |
2196 | case GITS_BASER_TYPE_NONE: | |
1ac19ca6 MZ |
2197 | continue; |
2198 | ||
4cacac57 | 2199 | case GITS_BASER_TYPE_DEVICE: |
32bd44dc SD |
2200 | indirect = its_parse_indirect_baser(its, baser, |
2201 | psz, &order, | |
576a8342 | 2202 | device_ids(its)); |
8d565748 ZY |
2203 | break; |
2204 | ||
4cacac57 | 2205 | case GITS_BASER_TYPE_VCPU: |
5e516846 MZ |
2206 | if (is_v4_1(its)) { |
2207 | struct its_node *sibling; | |
2208 | ||
2209 | WARN_ON(i != 2); | |
2210 | if ((sibling = find_sibling_its(its))) { | |
2211 | *baser = sibling->tables[2]; | |
2212 | its_write_baser(its, baser, baser->val); | |
2213 | continue; | |
2214 | } | |
2215 | } | |
2216 | ||
4cacac57 | 2217 | indirect = its_parse_indirect_baser(its, baser, |
32bd44dc SD |
2218 | psz, &order, |
2219 | ITS_MAX_VPEID_BITS); | |
4cacac57 MZ |
2220 | break; |
2221 | } | |
f54b97ed | 2222 | |
3faf24ea | 2223 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
2224 | if (err < 0) { |
2225 | its_free_tables(its); | |
2226 | return err; | |
1ac19ca6 MZ |
2227 | } |
2228 | ||
9347359a SD |
2229 | /* Update settings which will be used for next BASERn */ |
2230 | psz = baser->psz; | |
2231 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
2232 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
2233 | } |
2234 | ||
2235 | return 0; | |
1ac19ca6 MZ |
2236 | } |
2237 | ||
5e516846 MZ |
2238 | static u64 inherit_vpe_l1_table_from_its(void) |
2239 | { | |
2240 | struct its_node *its; | |
2241 | u64 val; | |
2242 | u32 aff; | |
2243 | ||
2244 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2245 | aff = compute_common_aff(val); | |
2246 | ||
2247 | list_for_each_entry(its, &its_nodes, entry) { | |
2248 | u64 baser, addr; | |
2249 | ||
2250 | if (!is_v4_1(its)) | |
2251 | continue; | |
2252 | ||
2253 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2254 | continue; | |
2255 | ||
2256 | if (aff != compute_its_aff(its)) | |
2257 | continue; | |
2258 | ||
2259 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2260 | baser = its->tables[2].val; | |
2261 | if (!(baser & GITS_BASER_VALID)) | |
2262 | continue; | |
2263 | ||
2264 | /* We have a winner! */ | |
2265 | val = GICR_VPROPBASER_4_1_VALID; | |
2266 | if (baser & GITS_BASER_INDIRECT) | |
2267 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2268 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, | |
2269 | FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)); | |
2270 | switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) { | |
2271 | case GIC_PAGE_SIZE_64K: | |
2272 | addr = GITS_BASER_ADDR_48_to_52(baser); | |
2273 | break; | |
2274 | default: | |
2275 | addr = baser & GENMASK_ULL(47, 12); | |
2276 | break; | |
2277 | } | |
2278 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12); | |
2279 | val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK, | |
2280 | FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser)); | |
2281 | val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK, | |
2282 | FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser)); | |
2283 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); | |
2284 | ||
2285 | return val; | |
2286 | } | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
2291 | static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask) | |
2292 | { | |
2293 | u32 aff; | |
2294 | u64 val; | |
2295 | int cpu; | |
2296 | ||
2297 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2298 | aff = compute_common_aff(val); | |
2299 | ||
2300 | for_each_possible_cpu(cpu) { | |
2301 | void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; | |
2302 | u32 tmp; | |
2303 | ||
2304 | if (!base || cpu == smp_processor_id()) | |
2305 | continue; | |
2306 | ||
2307 | val = gic_read_typer(base + GICR_TYPER); | |
2308 | tmp = compute_common_aff(val); | |
2309 | if (tmp != aff) | |
2310 | continue; | |
2311 | ||
2312 | /* | |
2313 | * At this point, we have a victim. This particular CPU | |
2314 | * has already booted, and has an affinity that matches | |
2315 | * ours wrt CommonLPIAff. Let's use its own VPROPBASER. | |
2316 | * Make sure we don't write the Z bit in that case. | |
2317 | */ | |
2318 | val = gits_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); | |
2319 | val &= ~GICR_VPROPBASER_4_1_Z; | |
2320 | ||
2321 | *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; | |
2322 | ||
2323 | return val; | |
2324 | } | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
2329 | static int allocate_vpe_l1_table(void) | |
2330 | { | |
2331 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
2332 | u64 val, gpsz, npg, pa; | |
2333 | unsigned int psz = SZ_64K; | |
2334 | unsigned int np, epp, esz; | |
2335 | struct page *page; | |
2336 | ||
2337 | if (!gic_rdists->has_rvpeid) | |
2338 | return 0; | |
2339 | ||
2340 | /* | |
2341 | * if VPENDBASER.Valid is set, disable any previously programmed | |
2342 | * VPE by setting PendingLast while clearing Valid. This has the | |
2343 | * effect of making sure no doorbell will be generated and we can | |
2344 | * then safely clear VPROPBASER.Valid. | |
2345 | */ | |
2346 | if (gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid) | |
2347 | gits_write_vpendbaser(GICR_VPENDBASER_PendingLast, | |
2348 | vlpi_base + GICR_VPENDBASER); | |
2349 | ||
2350 | /* | |
2351 | * If we can inherit the configuration from another RD, let's do | |
2352 | * so. Otherwise, we have to go through the allocation process. We | |
2353 | * assume that all RDs have the exact same requirements, as | |
2354 | * nothing will work otherwise. | |
2355 | */ | |
2356 | val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); | |
2357 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2358 | goto out; | |
2359 | ||
2360 | gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_KERNEL); | |
2361 | if (!gic_data_rdist()->vpe_table_mask) | |
2362 | return -ENOMEM; | |
2363 | ||
2364 | val = inherit_vpe_l1_table_from_its(); | |
2365 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2366 | goto out; | |
2367 | ||
2368 | /* First probe the page size */ | |
2369 | val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K); | |
2370 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2371 | val = gits_read_vpropbaser(vlpi_base + GICR_VPROPBASER); | |
2372 | gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); | |
2373 | esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val); | |
2374 | ||
2375 | switch (gpsz) { | |
2376 | default: | |
2377 | gpsz = GIC_PAGE_SIZE_4K; | |
2378 | /* fall through */ | |
2379 | case GIC_PAGE_SIZE_4K: | |
2380 | psz = SZ_4K; | |
2381 | break; | |
2382 | case GIC_PAGE_SIZE_16K: | |
2383 | psz = SZ_16K; | |
2384 | break; | |
2385 | case GIC_PAGE_SIZE_64K: | |
2386 | psz = SZ_64K; | |
2387 | break; | |
2388 | } | |
2389 | ||
2390 | /* | |
2391 | * Start populating the register from scratch, including RO fields | |
2392 | * (which we want to print in debug cases...) | |
2393 | */ | |
2394 | val = 0; | |
2395 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz); | |
2396 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz); | |
2397 | ||
2398 | /* How many entries per GIC page? */ | |
2399 | esz++; | |
2400 | epp = psz / (esz * SZ_8); | |
2401 | ||
2402 | /* | |
2403 | * If we need more than just a single L1 page, flag the table | |
2404 | * as indirect and compute the number of required L1 pages. | |
2405 | */ | |
2406 | if (epp < ITS_MAX_VPEID) { | |
2407 | int nl2; | |
2408 | ||
2409 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2410 | ||
2411 | /* Number of L2 pages required to cover the VPEID space */ | |
2412 | nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp); | |
2413 | ||
2414 | /* Number of L1 pages to point to the L2 pages */ | |
2415 | npg = DIV_ROUND_UP(nl2 * SZ_8, psz); | |
2416 | } else { | |
2417 | npg = 1; | |
2418 | } | |
2419 | ||
2420 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg); | |
2421 | ||
2422 | /* Right, that's the number of CPU pages we need for L1 */ | |
2423 | np = DIV_ROUND_UP(npg * psz, PAGE_SIZE); | |
2424 | ||
2425 | pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", | |
2426 | np, npg, psz, epp, esz); | |
2427 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(np * PAGE_SIZE)); | |
2428 | if (!page) | |
2429 | return -ENOMEM; | |
2430 | ||
2431 | gic_data_rdist()->vpe_l1_page = page; | |
2432 | pa = virt_to_phys(page_address(page)); | |
2433 | WARN_ON(!IS_ALIGNED(pa, psz)); | |
2434 | ||
2435 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12); | |
2436 | val |= GICR_VPROPBASER_RaWb; | |
2437 | val |= GICR_VPROPBASER_InnerShareable; | |
2438 | val |= GICR_VPROPBASER_4_1_Z; | |
2439 | val |= GICR_VPROPBASER_4_1_VALID; | |
2440 | ||
2441 | out: | |
2442 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2443 | cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); | |
2444 | ||
2445 | pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n", | |
2446 | smp_processor_id(), val, | |
2447 | cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); | |
2448 | ||
2449 | return 0; | |
2450 | } | |
2451 | ||
1ac19ca6 MZ |
2452 | static int its_alloc_collections(struct its_node *its) |
2453 | { | |
83559b47 MZ |
2454 | int i; |
2455 | ||
6396bb22 | 2456 | its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), |
1ac19ca6 MZ |
2457 | GFP_KERNEL); |
2458 | if (!its->collections) | |
2459 | return -ENOMEM; | |
2460 | ||
83559b47 MZ |
2461 | for (i = 0; i < nr_cpu_ids; i++) |
2462 | its->collections[i].target_address = ~0ULL; | |
2463 | ||
1ac19ca6 MZ |
2464 | return 0; |
2465 | } | |
2466 | ||
7c297a2d MZ |
2467 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
2468 | { | |
2469 | struct page *pend_page; | |
adaab500 | 2470 | |
7c297a2d | 2471 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, |
adaab500 | 2472 | get_order(LPI_PENDBASE_SZ)); |
7c297a2d MZ |
2473 | if (!pend_page) |
2474 | return NULL; | |
2475 | ||
2476 | /* Make sure the GIC will observe the zero-ed page */ | |
2477 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
2478 | ||
2479 | return pend_page; | |
2480 | } | |
2481 | ||
7d75bbb4 MZ |
2482 | static void its_free_pending_table(struct page *pt) |
2483 | { | |
adaab500 | 2484 | free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); |
7d75bbb4 MZ |
2485 | } |
2486 | ||
c6e2ccb6 | 2487 | /* |
5e2c9f9a MZ |
2488 | * Booting with kdump and LPIs enabled is generally fine. Any other |
2489 | * case is wrong in the absence of firmware/EFI support. | |
c6e2ccb6 | 2490 | */ |
c440a9d9 MZ |
2491 | static bool enabled_lpis_allowed(void) |
2492 | { | |
5e2c9f9a MZ |
2493 | phys_addr_t addr; |
2494 | u64 val; | |
c6e2ccb6 | 2495 | |
5e2c9f9a MZ |
2496 | /* Check whether the property table is in a reserved region */ |
2497 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); | |
2498 | addr = val & GENMASK_ULL(51, 12); | |
2499 | ||
2500 | return gic_check_reserved_range(addr, LPI_PROPBASE_SZ); | |
c440a9d9 MZ |
2501 | } |
2502 | ||
11e37d35 | 2503 | static int __init allocate_lpi_tables(void) |
1ac19ca6 | 2504 | { |
c440a9d9 | 2505 | u64 val; |
11e37d35 | 2506 | int err, cpu; |
1ac19ca6 | 2507 | |
c440a9d9 MZ |
2508 | /* |
2509 | * If LPIs are enabled while we run this from the boot CPU, | |
2510 | * flag the RD tables as pre-allocated if the stars do align. | |
2511 | */ | |
2512 | val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); | |
2513 | if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { | |
2514 | gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | | |
2515 | RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING); | |
2516 | pr_info("GICv3: Using preallocated redistributor tables\n"); | |
2517 | } | |
2518 | ||
11e37d35 MZ |
2519 | err = its_setup_lpi_prop_table(); |
2520 | if (err) | |
2521 | return err; | |
2522 | ||
2523 | /* | |
2524 | * We allocate all the pending tables anyway, as we may have a | |
2525 | * mix of RDs that have had LPIs enabled, and some that | |
2526 | * don't. We'll free the unused ones as each CPU comes online. | |
2527 | */ | |
2528 | for_each_possible_cpu(cpu) { | |
2529 | struct page *pend_page; | |
7c297a2d MZ |
2530 | |
2531 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 | 2532 | if (!pend_page) { |
11e37d35 MZ |
2533 | pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu); |
2534 | return -ENOMEM; | |
1ac19ca6 MZ |
2535 | } |
2536 | ||
11e37d35 | 2537 | gic_data_rdist_cpu(cpu)->pend_page = pend_page; |
1ac19ca6 MZ |
2538 | } |
2539 | ||
11e37d35 MZ |
2540 | return 0; |
2541 | } | |
2542 | ||
6479450f HG |
2543 | static u64 its_clear_vpend_valid(void __iomem *vlpi_base) |
2544 | { | |
2545 | u32 count = 1000000; /* 1s! */ | |
2546 | bool clean; | |
2547 | u64 val; | |
2548 | ||
2549 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2550 | val &= ~GICR_VPENDBASER_Valid; | |
2551 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2552 | ||
2553 | do { | |
2554 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2555 | clean = !(val & GICR_VPENDBASER_Dirty); | |
2556 | if (!clean) { | |
2557 | count--; | |
2558 | cpu_relax(); | |
2559 | udelay(1); | |
2560 | } | |
2561 | } while (!clean && count); | |
2562 | ||
2563 | return val; | |
2564 | } | |
2565 | ||
11e37d35 MZ |
2566 | static void its_cpu_init_lpis(void) |
2567 | { | |
2568 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
2569 | struct page *pend_page; | |
2570 | phys_addr_t paddr; | |
2571 | u64 val, tmp; | |
2572 | ||
2573 | if (gic_data_rdist()->lpi_enabled) | |
2574 | return; | |
2575 | ||
c440a9d9 MZ |
2576 | val = readl_relaxed(rbase + GICR_CTLR); |
2577 | if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && | |
2578 | (val & GICR_CTLR_ENABLE_LPIS)) { | |
f842ca8e MZ |
2579 | /* |
2580 | * Check that we get the same property table on all | |
2581 | * RDs. If we don't, this is hopeless. | |
2582 | */ | |
2583 | paddr = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
2584 | paddr &= GENMASK_ULL(51, 12); | |
2585 | if (WARN_ON(gic_rdists->prop_table_pa != paddr)) | |
2586 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
2587 | ||
c440a9d9 MZ |
2588 | paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER); |
2589 | paddr &= GENMASK_ULL(51, 16); | |
2590 | ||
5e2c9f9a | 2591 | WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ)); |
c440a9d9 MZ |
2592 | its_free_pending_table(gic_data_rdist()->pend_page); |
2593 | gic_data_rdist()->pend_page = NULL; | |
2594 | ||
2595 | goto out; | |
2596 | } | |
2597 | ||
11e37d35 MZ |
2598 | pend_page = gic_data_rdist()->pend_page; |
2599 | paddr = page_to_phys(pend_page); | |
3fb68fae | 2600 | WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ)); |
11e37d35 | 2601 | |
1ac19ca6 | 2602 | /* set PROPBASE */ |
e1a2e201 | 2603 | val = (gic_rdists->prop_table_pa | |
1ac19ca6 | 2604 | GICR_PROPBASER_InnerShareable | |
2fd632a0 | 2605 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
2606 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
2607 | ||
0968a619 VM |
2608 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
2609 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
2610 | |
2611 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
2612 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
2613 | /* | |
2614 | * The HW reports non-shareable, we must | |
2615 | * remove the cacheability attributes as | |
2616 | * well. | |
2617 | */ | |
2618 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
2619 | GICR_PROPBASER_CACHEABILITY_MASK); | |
2620 | val |= GICR_PROPBASER_nC; | |
0968a619 | 2621 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 2622 | } |
1ac19ca6 MZ |
2623 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
2624 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
2625 | } | |
2626 | ||
2627 | /* set PENDBASE */ | |
2628 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 2629 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 2630 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 2631 | |
0968a619 VM |
2632 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
2633 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
2634 | |
2635 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
2636 | /* | |
2637 | * The HW reports non-shareable, we must remove the | |
2638 | * cacheability attributes as well. | |
2639 | */ | |
2640 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
2641 | GICR_PENDBASER_CACHEABILITY_MASK); | |
2642 | val |= GICR_PENDBASER_nC; | |
0968a619 | 2643 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 2644 | } |
1ac19ca6 MZ |
2645 | |
2646 | /* Enable LPIs */ | |
2647 | val = readl_relaxed(rbase + GICR_CTLR); | |
2648 | val |= GICR_CTLR_ENABLE_LPIS; | |
2649 | writel_relaxed(val, rbase + GICR_CTLR); | |
2650 | ||
5e516846 | 2651 | if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { |
6479450f HG |
2652 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
2653 | ||
2654 | /* | |
2655 | * It's possible for CPU to receive VLPIs before it is | |
2656 | * sheduled as a vPE, especially for the first CPU, and the | |
2657 | * VLPI with INTID larger than 2^(IDbits+1) will be considered | |
2658 | * as out of range and dropped by GIC. | |
2659 | * So we initialize IDbits to known value to avoid VLPI drop. | |
2660 | */ | |
2661 | val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
2662 | pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n", | |
2663 | smp_processor_id(), val); | |
2664 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2665 | ||
2666 | /* | |
2667 | * Also clear Valid bit of GICR_VPENDBASER, in case some | |
2668 | * ancient programming gets left in and has possibility of | |
2669 | * corrupting memory. | |
2670 | */ | |
2671 | val = its_clear_vpend_valid(vlpi_base); | |
2672 | WARN_ON(val & GICR_VPENDBASER_Dirty); | |
2673 | } | |
2674 | ||
5e516846 MZ |
2675 | if (allocate_vpe_l1_table()) { |
2676 | /* | |
2677 | * If the allocation has failed, we're in massive trouble. | |
2678 | * Disable direct injection, and pray that no VM was | |
2679 | * already running... | |
2680 | */ | |
2681 | gic_rdists->has_rvpeid = false; | |
2682 | gic_rdists->has_vlpis = false; | |
2683 | } | |
2684 | ||
1ac19ca6 MZ |
2685 | /* Make sure the GIC has seen the above */ |
2686 | dsb(sy); | |
c440a9d9 | 2687 | out: |
11e37d35 | 2688 | gic_data_rdist()->lpi_enabled = true; |
c440a9d9 | 2689 | pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n", |
11e37d35 | 2690 | smp_processor_id(), |
c440a9d9 | 2691 | gic_data_rdist()->pend_page ? "allocated" : "reserved", |
11e37d35 | 2692 | &paddr); |
1ac19ca6 MZ |
2693 | } |
2694 | ||
920181ce | 2695 | static void its_cpu_init_collection(struct its_node *its) |
1ac19ca6 | 2696 | { |
920181ce DB |
2697 | int cpu = smp_processor_id(); |
2698 | u64 target; | |
1ac19ca6 | 2699 | |
920181ce DB |
2700 | /* avoid cross node collections and its mapping */ |
2701 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
2702 | struct device_node *cpu_node; | |
fbf8f40e | 2703 | |
920181ce DB |
2704 | cpu_node = of_get_cpu_node(cpu, NULL); |
2705 | if (its->numa_node != NUMA_NO_NODE && | |
2706 | its->numa_node != of_node_to_nid(cpu_node)) | |
2707 | return; | |
2708 | } | |
fbf8f40e | 2709 | |
920181ce DB |
2710 | /* |
2711 | * We now have to bind each collection to its target | |
2712 | * redistributor. | |
2713 | */ | |
2714 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
1ac19ca6 | 2715 | /* |
920181ce | 2716 | * This ITS wants the physical address of the |
1ac19ca6 MZ |
2717 | * redistributor. |
2718 | */ | |
920181ce DB |
2719 | target = gic_data_rdist()->phys_base; |
2720 | } else { | |
2721 | /* This ITS wants a linear CPU number. */ | |
2722 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2723 | target = GICR_TYPER_CPU_NUMBER(target) << 16; | |
2724 | } | |
1ac19ca6 | 2725 | |
920181ce DB |
2726 | /* Perform collection mapping */ |
2727 | its->collections[cpu].target_address = target; | |
2728 | its->collections[cpu].col_id = cpu; | |
1ac19ca6 | 2729 | |
920181ce DB |
2730 | its_send_mapc(its, &its->collections[cpu], 1); |
2731 | its_send_invall(its, &its->collections[cpu]); | |
2732 | } | |
2733 | ||
2734 | static void its_cpu_init_collections(void) | |
2735 | { | |
2736 | struct its_node *its; | |
2737 | ||
a8db7456 | 2738 | raw_spin_lock(&its_lock); |
920181ce DB |
2739 | |
2740 | list_for_each_entry(its, &its_nodes, entry) | |
2741 | its_cpu_init_collection(its); | |
1ac19ca6 | 2742 | |
a8db7456 | 2743 | raw_spin_unlock(&its_lock); |
1ac19ca6 | 2744 | } |
84a6a2e7 MZ |
2745 | |
2746 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
2747 | { | |
2748 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 2749 | unsigned long flags; |
84a6a2e7 | 2750 | |
3e39e8f5 | 2751 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
2752 | |
2753 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
2754 | if (tmp->device_id == dev_id) { | |
2755 | its_dev = tmp; | |
2756 | break; | |
2757 | } | |
2758 | } | |
2759 | ||
3e39e8f5 | 2760 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
2761 | |
2762 | return its_dev; | |
2763 | } | |
2764 | ||
466b7d16 SD |
2765 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
2766 | { | |
2767 | int i; | |
2768 | ||
2769 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
2770 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
2771 | return &its->tables[i]; | |
2772 | } | |
2773 | ||
2774 | return NULL; | |
2775 | } | |
2776 | ||
539d3782 SD |
2777 | static bool its_alloc_table_entry(struct its_node *its, |
2778 | struct its_baser *baser, u32 id) | |
3faf24ea | 2779 | { |
3faf24ea SD |
2780 | struct page *page; |
2781 | u32 esz, idx; | |
2782 | __le64 *table; | |
2783 | ||
3faf24ea SD |
2784 | /* Don't allow device id that exceeds single, flat table limit */ |
2785 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
2786 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 2787 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
2788 | |
2789 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 2790 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
2791 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
2792 | return false; | |
2793 | ||
2794 | table = baser->base; | |
2795 | ||
2796 | /* Allocate memory for 2nd level table */ | |
2797 | if (!table[idx]) { | |
539d3782 SD |
2798 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
2799 | get_order(baser->psz)); | |
3faf24ea SD |
2800 | if (!page) |
2801 | return false; | |
2802 | ||
2803 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
2804 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 2805 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
2806 | |
2807 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
2808 | ||
2809 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
2810 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 2811 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
2812 | |
2813 | /* Ensure updated table contents are visible to ITS hardware */ | |
2814 | dsb(sy); | |
2815 | } | |
2816 | ||
2817 | return true; | |
2818 | } | |
2819 | ||
70cc81ed MZ |
2820 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
2821 | { | |
2822 | struct its_baser *baser; | |
2823 | ||
2824 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
2825 | ||
2826 | /* Don't allow device id that exceeds ITS hardware limit */ | |
2827 | if (!baser) | |
576a8342 | 2828 | return (ilog2(dev_id) < device_ids(its)); |
70cc81ed | 2829 | |
539d3782 | 2830 | return its_alloc_table_entry(its, baser, dev_id); |
70cc81ed MZ |
2831 | } |
2832 | ||
7d75bbb4 MZ |
2833 | static bool its_alloc_vpe_table(u32 vpe_id) |
2834 | { | |
2835 | struct its_node *its; | |
2836 | ||
2837 | /* | |
2838 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
2839 | * could try and only do it on ITSs corresponding to devices | |
2840 | * that have interrupts targeted at this VPE, but the | |
2841 | * complexity becomes crazy (and you have tons of memory | |
2842 | * anyway, right?). | |
2843 | */ | |
2844 | list_for_each_entry(its, &its_nodes, entry) { | |
2845 | struct its_baser *baser; | |
2846 | ||
0dd57fed | 2847 | if (!is_v4(its)) |
7d75bbb4 | 2848 | continue; |
3faf24ea | 2849 | |
7d75bbb4 MZ |
2850 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
2851 | if (!baser) | |
2852 | return false; | |
3faf24ea | 2853 | |
539d3782 | 2854 | if (!its_alloc_table_entry(its, baser, vpe_id)) |
7d75bbb4 | 2855 | return false; |
3faf24ea SD |
2856 | } |
2857 | ||
2858 | return true; | |
2859 | } | |
2860 | ||
84a6a2e7 | 2861 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 2862 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
2863 | { |
2864 | struct its_device *dev; | |
93f94ea0 | 2865 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 2866 | unsigned long flags; |
591e5bec | 2867 | u16 *col_map = NULL; |
84a6a2e7 MZ |
2868 | void *itt; |
2869 | int lpi_base; | |
2870 | int nr_lpis; | |
c8481267 | 2871 | int nr_ites; |
84a6a2e7 MZ |
2872 | int sz; |
2873 | ||
3faf24ea | 2874 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
2875 | return NULL; |
2876 | ||
147c8f37 MZ |
2877 | if (WARN_ON(!is_power_of_2(nvecs))) |
2878 | nvecs = roundup_pow_of_two(nvecs); | |
2879 | ||
84a6a2e7 | 2880 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 | 2881 | /* |
147c8f37 MZ |
2882 | * Even if the device wants a single LPI, the ITT must be |
2883 | * sized as a power of two (and you need at least one bit...). | |
c8481267 | 2884 | */ |
147c8f37 | 2885 | nr_ites = max(2, nvecs); |
ffedbf0c | 2886 | sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); |
84a6a2e7 | 2887 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
539d3782 | 2888 | itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); |
93f94ea0 | 2889 | if (alloc_lpis) { |
38dd7c49 | 2890 | lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); |
93f94ea0 | 2891 | if (lpi_map) |
6396bb22 | 2892 | col_map = kcalloc(nr_lpis, sizeof(*col_map), |
93f94ea0 MZ |
2893 | GFP_KERNEL); |
2894 | } else { | |
6396bb22 | 2895 | col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL); |
93f94ea0 MZ |
2896 | nr_lpis = 0; |
2897 | lpi_base = 0; | |
2898 | } | |
84a6a2e7 | 2899 | |
93f94ea0 | 2900 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
2901 | kfree(dev); |
2902 | kfree(itt); | |
2903 | kfree(lpi_map); | |
591e5bec | 2904 | kfree(col_map); |
84a6a2e7 MZ |
2905 | return NULL; |
2906 | } | |
2907 | ||
328191c0 | 2908 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 2909 | |
84a6a2e7 MZ |
2910 | dev->its = its; |
2911 | dev->itt = itt; | |
c8481267 | 2912 | dev->nr_ites = nr_ites; |
591e5bec MZ |
2913 | dev->event_map.lpi_map = lpi_map; |
2914 | dev->event_map.col_map = col_map; | |
2915 | dev->event_map.lpi_base = lpi_base; | |
2916 | dev->event_map.nr_lpis = nr_lpis; | |
11635fa2 | 2917 | raw_spin_lock_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
2918 | dev->device_id = dev_id; |
2919 | INIT_LIST_HEAD(&dev->entry); | |
2920 | ||
3e39e8f5 | 2921 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 2922 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 2923 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 2924 | |
84a6a2e7 MZ |
2925 | /* Map device to its ITT */ |
2926 | its_send_mapd(dev, 1); | |
2927 | ||
2928 | return dev; | |
2929 | } | |
2930 | ||
2931 | static void its_free_device(struct its_device *its_dev) | |
2932 | { | |
3e39e8f5 MZ |
2933 | unsigned long flags; |
2934 | ||
2935 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 2936 | list_del(&its_dev->entry); |
3e39e8f5 | 2937 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
898aa5ce | 2938 | kfree(its_dev->event_map.col_map); |
84a6a2e7 MZ |
2939 | kfree(its_dev->itt); |
2940 | kfree(its_dev); | |
2941 | } | |
b48ac83d | 2942 | |
8208d170 | 2943 | static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq) |
b48ac83d MZ |
2944 | { |
2945 | int idx; | |
2946 | ||
342be106 | 2947 | /* Find a free LPI region in lpi_map and allocate them. */ |
8208d170 MZ |
2948 | idx = bitmap_find_free_region(dev->event_map.lpi_map, |
2949 | dev->event_map.nr_lpis, | |
2950 | get_count_order(nvecs)); | |
2951 | if (idx < 0) | |
b48ac83d MZ |
2952 | return -ENOSPC; |
2953 | ||
591e5bec | 2954 | *hwirq = dev->event_map.lpi_base + idx; |
b48ac83d | 2955 | |
b48ac83d MZ |
2956 | return 0; |
2957 | } | |
2958 | ||
54456db9 MZ |
2959 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
2960 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 2961 | { |
b48ac83d | 2962 | struct its_node *its; |
b48ac83d | 2963 | struct its_device *its_dev; |
54456db9 MZ |
2964 | struct msi_domain_info *msi_info; |
2965 | u32 dev_id; | |
9791ec7d | 2966 | int err = 0; |
54456db9 MZ |
2967 | |
2968 | /* | |
a7c90f51 | 2969 | * We ignore "dev" entirely, and rely on the dev_id that has |
54456db9 MZ |
2970 | * been passed via the scratchpad. This limits this domain's |
2971 | * usefulness to upper layers that definitely know that they | |
2972 | * are built on top of the ITS. | |
2973 | */ | |
2974 | dev_id = info->scratchpad[0].ul; | |
2975 | ||
2976 | msi_info = msi_get_domain_info(domain); | |
2977 | its = msi_info->data; | |
e8137f4f | 2978 | |
20b3d54e MZ |
2979 | if (!gic_rdists->has_direct_lpi && |
2980 | vpe_proxy.dev && | |
2981 | vpe_proxy.dev->its == its && | |
2982 | dev_id == vpe_proxy.dev->device_id) { | |
2983 | /* Bad luck. Get yourself a better implementation */ | |
2984 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
2985 | dev_id); | |
2986 | return -EINVAL; | |
2987 | } | |
2988 | ||
9791ec7d | 2989 | mutex_lock(&its->dev_alloc_lock); |
f130420e | 2990 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
2991 | if (its_dev) { |
2992 | /* | |
2993 | * We already have seen this ID, probably through | |
2994 | * another alias (PCI bridge of some sort). No need to | |
2995 | * create the device. | |
2996 | */ | |
9791ec7d | 2997 | its_dev->shared = true; |
f130420e | 2998 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
2999 | goto out; |
3000 | } | |
b48ac83d | 3001 | |
93f94ea0 | 3002 | its_dev = its_create_device(its, dev_id, nvec, true); |
9791ec7d MZ |
3003 | if (!its_dev) { |
3004 | err = -ENOMEM; | |
3005 | goto out; | |
3006 | } | |
b48ac83d | 3007 | |
f130420e | 3008 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 3009 | out: |
9791ec7d | 3010 | mutex_unlock(&its->dev_alloc_lock); |
b48ac83d | 3011 | info->scratchpad[0].ptr = its_dev; |
9791ec7d | 3012 | return err; |
b48ac83d MZ |
3013 | } |
3014 | ||
54456db9 MZ |
3015 | static struct msi_domain_ops its_msi_domain_ops = { |
3016 | .msi_prepare = its_msi_prepare, | |
3017 | }; | |
3018 | ||
b48ac83d MZ |
3019 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
3020 | unsigned int virq, | |
3021 | irq_hw_number_t hwirq) | |
3022 | { | |
f833f57f MZ |
3023 | struct irq_fwspec fwspec; |
3024 | ||
3025 | if (irq_domain_get_of_node(domain->parent)) { | |
3026 | fwspec.fwnode = domain->parent->fwnode; | |
3027 | fwspec.param_count = 3; | |
3028 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
3029 | fwspec.param[1] = hwirq; | |
3030 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
3031 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
3032 | fwspec.fwnode = domain->parent->fwnode; | |
3033 | fwspec.param_count = 2; | |
3034 | fwspec.param[0] = hwirq; | |
3035 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
3036 | } else { |
3037 | return -EINVAL; | |
3038 | } | |
b48ac83d | 3039 | |
f833f57f | 3040 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
3041 | } |
3042 | ||
3043 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
3044 | unsigned int nr_irqs, void *args) | |
3045 | { | |
3046 | msi_alloc_info_t *info = args; | |
3047 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
35ae7df2 | 3048 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
3049 | irq_hw_number_t hwirq; |
3050 | int err; | |
3051 | int i; | |
3052 | ||
8208d170 MZ |
3053 | err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq); |
3054 | if (err) | |
3055 | return err; | |
b48ac83d | 3056 | |
35ae7df2 JG |
3057 | err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); |
3058 | if (err) | |
3059 | return err; | |
3060 | ||
8208d170 MZ |
3061 | for (i = 0; i < nr_irqs; i++) { |
3062 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); | |
b48ac83d MZ |
3063 | if (err) |
3064 | return err; | |
3065 | ||
3066 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
8208d170 | 3067 | hwirq + i, &its_irq_chip, its_dev); |
0d224d35 | 3068 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); |
f130420e | 3069 | pr_debug("ID:%d pID:%d vID:%d\n", |
8208d170 MZ |
3070 | (int)(hwirq + i - its_dev->event_map.lpi_base), |
3071 | (int)(hwirq + i), virq + i); | |
b48ac83d MZ |
3072 | } |
3073 | ||
3074 | return 0; | |
3075 | } | |
3076 | ||
72491643 | 3077 | static int its_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 3078 | struct irq_data *d, bool reserve) |
aca268df MZ |
3079 | { |
3080 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3081 | u32 event = its_get_event_id(d); | |
fbf8f40e | 3082 | const struct cpumask *cpu_mask = cpu_online_mask; |
0d224d35 | 3083 | int cpu; |
fbf8f40e GK |
3084 | |
3085 | /* get the cpu_mask of local node */ | |
3086 | if (its_dev->its->numa_node >= 0) | |
3087 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 3088 | |
591e5bec | 3089 | /* Bind the LPI to the first possible CPU */ |
c1797b11 YY |
3090 | cpu = cpumask_first_and(cpu_mask, cpu_online_mask); |
3091 | if (cpu >= nr_cpu_ids) { | |
3092 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) | |
3093 | return -EINVAL; | |
3094 | ||
3095 | cpu = cpumask_first(cpu_online_mask); | |
3096 | } | |
3097 | ||
0d224d35 MZ |
3098 | its_dev->event_map.col_map[event] = cpu; |
3099 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 3100 | |
aca268df | 3101 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 3102 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 3103 | return 0; |
aca268df MZ |
3104 | } |
3105 | ||
3106 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
3107 | struct irq_data *d) | |
3108 | { | |
3109 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3110 | u32 event = its_get_event_id(d); | |
3111 | ||
3112 | /* Stop the delivery of interrupts */ | |
3113 | its_send_discard(its_dev, event); | |
3114 | } | |
3115 | ||
b48ac83d MZ |
3116 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
3117 | unsigned int nr_irqs) | |
3118 | { | |
3119 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
3120 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
9791ec7d | 3121 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
3122 | int i; |
3123 | ||
c9c96e30 MZ |
3124 | bitmap_release_region(its_dev->event_map.lpi_map, |
3125 | its_get_event_id(irq_domain_get_irq_data(domain, virq)), | |
3126 | get_count_order(nr_irqs)); | |
3127 | ||
b48ac83d MZ |
3128 | for (i = 0; i < nr_irqs; i++) { |
3129 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
3130 | virq + i); | |
b48ac83d | 3131 | /* Nuke the entry in the domain */ |
2da39949 | 3132 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
3133 | } |
3134 | ||
9791ec7d MZ |
3135 | mutex_lock(&its->dev_alloc_lock); |
3136 | ||
3137 | /* | |
3138 | * If all interrupts have been freed, start mopping the | |
3139 | * floor. This is conditionned on the device not being shared. | |
3140 | */ | |
3141 | if (!its_dev->shared && | |
3142 | bitmap_empty(its_dev->event_map.lpi_map, | |
591e5bec | 3143 | its_dev->event_map.nr_lpis)) { |
38dd7c49 MZ |
3144 | its_lpi_free(its_dev->event_map.lpi_map, |
3145 | its_dev->event_map.lpi_base, | |
3146 | its_dev->event_map.nr_lpis); | |
b48ac83d MZ |
3147 | |
3148 | /* Unmap device/itt */ | |
3149 | its_send_mapd(its_dev, 0); | |
3150 | its_free_device(its_dev); | |
3151 | } | |
3152 | ||
9791ec7d MZ |
3153 | mutex_unlock(&its->dev_alloc_lock); |
3154 | ||
b48ac83d MZ |
3155 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
3156 | } | |
3157 | ||
3158 | static const struct irq_domain_ops its_domain_ops = { | |
3159 | .alloc = its_irq_domain_alloc, | |
3160 | .free = its_irq_domain_free, | |
aca268df MZ |
3161 | .activate = its_irq_domain_activate, |
3162 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 3163 | }; |
4c21f3c2 | 3164 | |
20b3d54e MZ |
3165 | /* |
3166 | * This is insane. | |
3167 | * | |
3168 | * If a GICv4 doesn't implement Direct LPIs (which is extremely | |
3169 | * likely), the only way to perform an invalidate is to use a fake | |
3170 | * device to issue an INV command, implying that the LPI has first | |
3171 | * been mapped to some event on that device. Since this is not exactly | |
3172 | * cheap, we try to keep that mapping around as long as possible, and | |
3173 | * only issue an UNMAP if we're short on available slots. | |
3174 | * | |
3175 | * Broken by design(tm). | |
3176 | */ | |
3177 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
3178 | { | |
3179 | /* Already unmapped? */ | |
3180 | if (vpe->vpe_proxy_event == -1) | |
3181 | return; | |
3182 | ||
3183 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3184 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
3185 | ||
3186 | /* | |
3187 | * We don't track empty slots at all, so let's move the | |
3188 | * next_victim pointer if we can quickly reuse that slot | |
3189 | * instead of nuking an existing entry. Not clear that this is | |
3190 | * always a win though, and this might just generate a ripple | |
3191 | * effect... Let's just hope VPEs don't migrate too often. | |
3192 | */ | |
3193 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3194 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
3195 | ||
3196 | vpe->vpe_proxy_event = -1; | |
3197 | } | |
3198 | ||
3199 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
3200 | { | |
3201 | if (!gic_rdists->has_direct_lpi) { | |
3202 | unsigned long flags; | |
3203 | ||
3204 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3205 | its_vpe_db_proxy_unmap_locked(vpe); | |
3206 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
3211 | { | |
3212 | /* Already mapped? */ | |
3213 | if (vpe->vpe_proxy_event != -1) | |
3214 | return; | |
3215 | ||
3216 | /* This slot was already allocated. Kick the other VPE out. */ | |
3217 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3218 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
3219 | ||
3220 | /* Map the new VPE instead */ | |
3221 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
3222 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
3223 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
3224 | ||
3225 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
3226 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
3227 | } | |
3228 | ||
958b90d1 MZ |
3229 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
3230 | { | |
3231 | unsigned long flags; | |
3232 | struct its_collection *target_col; | |
3233 | ||
3234 | if (gic_rdists->has_direct_lpi) { | |
3235 | void __iomem *rdbase; | |
3236 | ||
3237 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
3238 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 3239 | wait_for_syncr(rdbase); |
958b90d1 MZ |
3240 | |
3241 | return; | |
3242 | } | |
3243 | ||
3244 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3245 | ||
3246 | its_vpe_db_proxy_map_locked(vpe); | |
3247 | ||
3248 | target_col = &vpe_proxy.dev->its->collections[to]; | |
3249 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
3250 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
3251 | ||
3252 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3253 | } | |
3254 | ||
3171a47a MZ |
3255 | static int its_vpe_set_affinity(struct irq_data *d, |
3256 | const struct cpumask *mask_val, | |
3257 | bool force) | |
3258 | { | |
3259 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3260 | int cpu = cpumask_first(mask_val); | |
3261 | ||
3262 | /* | |
3263 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 3264 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
3265 | * into the proxy device, we need to move the doorbell |
3266 | * interrupt to its new location. | |
3171a47a MZ |
3267 | */ |
3268 | if (vpe->col_idx != cpu) { | |
958b90d1 MZ |
3269 | int from = vpe->col_idx; |
3270 | ||
3171a47a MZ |
3271 | vpe->col_idx = cpu; |
3272 | its_send_vmovp(vpe); | |
958b90d1 | 3273 | its_vpe_db_proxy_move(vpe, from, cpu); |
3171a47a MZ |
3274 | } |
3275 | ||
44c4c25e MZ |
3276 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
3277 | ||
3171a47a MZ |
3278 | return IRQ_SET_MASK_OK_DONE; |
3279 | } | |
3280 | ||
e643d803 MZ |
3281 | static void its_vpe_schedule(struct its_vpe *vpe) |
3282 | { | |
50c33097 | 3283 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3284 | u64 val; |
3285 | ||
3286 | /* Schedule the VPE */ | |
3287 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
3288 | GENMASK_ULL(51, 12); | |
3289 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
3290 | val |= GICR_VPROPBASER_RaWb; | |
3291 | val |= GICR_VPROPBASER_InnerShareable; | |
3292 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
3293 | ||
3294 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
3295 | GENMASK_ULL(51, 16); | |
3296 | val |= GICR_VPENDBASER_RaWaWb; | |
3297 | val |= GICR_VPENDBASER_NonShareable; | |
3298 | /* | |
3299 | * There is no good way of finding out if the pending table is | |
3300 | * empty as we can race against the doorbell interrupt very | |
3301 | * easily. So in the end, vpe->pending_last is only an | |
3302 | * indication that the vcpu has something pending, not one | |
3303 | * that the pending table is empty. A good implementation | |
3304 | * would be able to read its coarse map pretty quickly anyway, | |
3305 | * making this a tolerable issue. | |
3306 | */ | |
3307 | val |= GICR_VPENDBASER_PendingLast; | |
3308 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
3309 | val |= GICR_VPENDBASER_Valid; | |
3310 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
3311 | } | |
3312 | ||
3313 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
3314 | { | |
50c33097 | 3315 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3316 | u64 val; |
3317 | ||
6479450f | 3318 | val = its_clear_vpend_valid(vlpi_base); |
e643d803 | 3319 | |
6479450f | 3320 | if (unlikely(val & GICR_VPENDBASER_Dirty)) { |
e643d803 MZ |
3321 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); |
3322 | vpe->idai = false; | |
3323 | vpe->pending_last = true; | |
3324 | } else { | |
3325 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); | |
3326 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
3327 | } | |
3328 | } | |
3329 | ||
40619a2e MZ |
3330 | static void its_vpe_invall(struct its_vpe *vpe) |
3331 | { | |
3332 | struct its_node *its; | |
3333 | ||
3334 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 3335 | if (!is_v4(its)) |
40619a2e MZ |
3336 | continue; |
3337 | ||
2247e1bf MZ |
3338 | if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) |
3339 | continue; | |
3340 | ||
3c1cceeb MZ |
3341 | /* |
3342 | * Sending a VINVALL to a single ITS is enough, as all | |
3343 | * we need is to reach the redistributors. | |
3344 | */ | |
40619a2e | 3345 | its_send_vinvall(its, vpe); |
3c1cceeb | 3346 | return; |
40619a2e MZ |
3347 | } |
3348 | } | |
3349 | ||
e643d803 MZ |
3350 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
3351 | { | |
3352 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3353 | struct its_cmd_info *info = vcpu_info; | |
3354 | ||
3355 | switch (info->cmd_type) { | |
3356 | case SCHEDULE_VPE: | |
3357 | its_vpe_schedule(vpe); | |
3358 | return 0; | |
3359 | ||
3360 | case DESCHEDULE_VPE: | |
3361 | its_vpe_deschedule(vpe); | |
3362 | return 0; | |
3363 | ||
5e2f7642 | 3364 | case INVALL_VPE: |
40619a2e | 3365 | its_vpe_invall(vpe); |
5e2f7642 MZ |
3366 | return 0; |
3367 | ||
e643d803 MZ |
3368 | default: |
3369 | return -EINVAL; | |
3370 | } | |
3371 | } | |
3372 | ||
20b3d54e MZ |
3373 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
3374 | void (*cmd)(struct its_device *, u32)) | |
3375 | { | |
3376 | unsigned long flags; | |
3377 | ||
3378 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3379 | ||
3380 | its_vpe_db_proxy_map_locked(vpe); | |
3381 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3382 | ||
3383 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3384 | } | |
3385 | ||
f6a91da7 MZ |
3386 | static void its_vpe_send_inv(struct irq_data *d) |
3387 | { | |
3388 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 3389 | |
20b3d54e MZ |
3390 | if (gic_rdists->has_direct_lpi) { |
3391 | void __iomem *rdbase; | |
3392 | ||
425c09be | 3393 | /* Target the redistributor this VPE is currently known on */ |
20b3d54e | 3394 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; |
425c09be | 3395 | gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); |
2f4f064b | 3396 | wait_for_syncr(rdbase); |
20b3d54e MZ |
3397 | } else { |
3398 | its_vpe_send_cmd(vpe, its_send_inv); | |
3399 | } | |
f6a91da7 MZ |
3400 | } |
3401 | ||
3402 | static void its_vpe_mask_irq(struct irq_data *d) | |
3403 | { | |
3404 | /* | |
3405 | * We need to unmask the LPI, which is described by the parent | |
3406 | * irq_data. Instead of calling into the parent (which won't | |
3407 | * exactly do the right thing, let's simply use the | |
3408 | * parent_data pointer. Yes, I'm naughty. | |
3409 | */ | |
3410 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
3411 | its_vpe_send_inv(d); | |
3412 | } | |
3413 | ||
3414 | static void its_vpe_unmask_irq(struct irq_data *d) | |
3415 | { | |
3416 | /* Same hack as above... */ | |
3417 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
3418 | its_vpe_send_inv(d); | |
3419 | } | |
3420 | ||
e57a3e28 MZ |
3421 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
3422 | enum irqchip_irq_state which, | |
3423 | bool state) | |
3424 | { | |
3425 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3426 | ||
3427 | if (which != IRQCHIP_STATE_PENDING) | |
3428 | return -EINVAL; | |
3429 | ||
3430 | if (gic_rdists->has_direct_lpi) { | |
3431 | void __iomem *rdbase; | |
3432 | ||
3433 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
3434 | if (state) { | |
3435 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
3436 | } else { | |
3437 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 3438 | wait_for_syncr(rdbase); |
e57a3e28 MZ |
3439 | } |
3440 | } else { | |
3441 | if (state) | |
3442 | its_vpe_send_cmd(vpe, its_send_int); | |
3443 | else | |
3444 | its_vpe_send_cmd(vpe, its_send_clear); | |
3445 | } | |
3446 | ||
3447 | return 0; | |
3448 | } | |
3449 | ||
8fff27ae MZ |
3450 | static struct irq_chip its_vpe_irq_chip = { |
3451 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
3452 | .irq_mask = its_vpe_mask_irq, |
3453 | .irq_unmask = its_vpe_unmask_irq, | |
3454 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 3455 | .irq_set_affinity = its_vpe_set_affinity, |
e57a3e28 | 3456 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 3457 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
3458 | }; |
3459 | ||
7d75bbb4 MZ |
3460 | static int its_vpe_id_alloc(void) |
3461 | { | |
32bd44dc | 3462 | return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL); |
7d75bbb4 MZ |
3463 | } |
3464 | ||
3465 | static void its_vpe_id_free(u16 id) | |
3466 | { | |
3467 | ida_simple_remove(&its_vpeid_ida, id); | |
3468 | } | |
3469 | ||
3470 | static int its_vpe_init(struct its_vpe *vpe) | |
3471 | { | |
3472 | struct page *vpt_page; | |
3473 | int vpe_id; | |
3474 | ||
3475 | /* Allocate vpe_id */ | |
3476 | vpe_id = its_vpe_id_alloc(); | |
3477 | if (vpe_id < 0) | |
3478 | return vpe_id; | |
3479 | ||
3480 | /* Allocate VPT */ | |
3481 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
3482 | if (!vpt_page) { | |
3483 | its_vpe_id_free(vpe_id); | |
3484 | return -ENOMEM; | |
3485 | } | |
3486 | ||
3487 | if (!its_alloc_vpe_table(vpe_id)) { | |
3488 | its_vpe_id_free(vpe_id); | |
34f8eb92 | 3489 | its_free_pending_table(vpt_page); |
7d75bbb4 MZ |
3490 | return -ENOMEM; |
3491 | } | |
3492 | ||
3493 | vpe->vpe_id = vpe_id; | |
3494 | vpe->vpt_page = vpt_page; | |
20b3d54e | 3495 | vpe->vpe_proxy_event = -1; |
7d75bbb4 MZ |
3496 | |
3497 | return 0; | |
3498 | } | |
3499 | ||
3500 | static void its_vpe_teardown(struct its_vpe *vpe) | |
3501 | { | |
20b3d54e | 3502 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
3503 | its_vpe_id_free(vpe->vpe_id); |
3504 | its_free_pending_table(vpe->vpt_page); | |
3505 | } | |
3506 | ||
3507 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
3508 | unsigned int virq, | |
3509 | unsigned int nr_irqs) | |
3510 | { | |
3511 | struct its_vm *vm = domain->host_data; | |
3512 | int i; | |
3513 | ||
3514 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
3515 | ||
3516 | for (i = 0; i < nr_irqs; i++) { | |
3517 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
3518 | virq + i); | |
3519 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
3520 | ||
3521 | BUG_ON(vm != vpe->its_vm); | |
3522 | ||
3523 | clear_bit(data->hwirq, vm->db_bitmap); | |
3524 | its_vpe_teardown(vpe); | |
3525 | irq_domain_reset_irq_data(data); | |
3526 | } | |
3527 | ||
3528 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
38dd7c49 | 3529 | its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); |
7d75bbb4 MZ |
3530 | its_free_prop_table(vm->vprop_page); |
3531 | } | |
3532 | } | |
3533 | ||
3534 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
3535 | unsigned int nr_irqs, void *args) | |
3536 | { | |
3537 | struct its_vm *vm = args; | |
3538 | unsigned long *bitmap; | |
3539 | struct page *vprop_page; | |
3540 | int base, nr_ids, i, err = 0; | |
3541 | ||
3542 | BUG_ON(!vm); | |
3543 | ||
38dd7c49 | 3544 | bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids); |
7d75bbb4 MZ |
3545 | if (!bitmap) |
3546 | return -ENOMEM; | |
3547 | ||
3548 | if (nr_ids < nr_irqs) { | |
38dd7c49 | 3549 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3550 | return -ENOMEM; |
3551 | } | |
3552 | ||
3553 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
3554 | if (!vprop_page) { | |
38dd7c49 | 3555 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3556 | return -ENOMEM; |
3557 | } | |
3558 | ||
3559 | vm->db_bitmap = bitmap; | |
3560 | vm->db_lpi_base = base; | |
3561 | vm->nr_db_lpis = nr_ids; | |
3562 | vm->vprop_page = vprop_page; | |
3563 | ||
3564 | for (i = 0; i < nr_irqs; i++) { | |
3565 | vm->vpes[i]->vpe_db_lpi = base + i; | |
3566 | err = its_vpe_init(vm->vpes[i]); | |
3567 | if (err) | |
3568 | break; | |
3569 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
3570 | vm->vpes[i]->vpe_db_lpi); | |
3571 | if (err) | |
3572 | break; | |
3573 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
3574 | &its_vpe_irq_chip, vm->vpes[i]); | |
3575 | set_bit(i, bitmap); | |
3576 | } | |
3577 | ||
3578 | if (err) { | |
3579 | if (i > 0) | |
3580 | its_vpe_irq_domain_free(domain, virq, i - 1); | |
3581 | ||
38dd7c49 | 3582 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3583 | its_free_prop_table(vprop_page); |
3584 | } | |
3585 | ||
3586 | return err; | |
3587 | } | |
3588 | ||
72491643 | 3589 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 3590 | struct irq_data *d, bool reserve) |
eb78192b MZ |
3591 | { |
3592 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
40619a2e | 3593 | struct its_node *its; |
eb78192b | 3594 | |
2247e1bf MZ |
3595 | /* If we use the list map, we issue VMAPP on demand... */ |
3596 | if (its_list_map) | |
6ef930f2 | 3597 | return 0; |
eb78192b MZ |
3598 | |
3599 | /* Map the VPE to the first possible CPU */ | |
3600 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
40619a2e MZ |
3601 | |
3602 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 3603 | if (!is_v4(its)) |
40619a2e MZ |
3604 | continue; |
3605 | ||
75fd951b | 3606 | its_send_vmapp(its, vpe, true); |
40619a2e MZ |
3607 | its_send_vinvall(its, vpe); |
3608 | } | |
3609 | ||
44c4c25e MZ |
3610 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
3611 | ||
72491643 | 3612 | return 0; |
eb78192b MZ |
3613 | } |
3614 | ||
3615 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
3616 | struct irq_data *d) | |
3617 | { | |
3618 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
75fd951b MZ |
3619 | struct its_node *its; |
3620 | ||
2247e1bf MZ |
3621 | /* |
3622 | * If we use the list map, we unmap the VPE once no VLPIs are | |
3623 | * associated with the VM. | |
3624 | */ | |
3625 | if (its_list_map) | |
3626 | return; | |
eb78192b | 3627 | |
75fd951b | 3628 | list_for_each_entry(its, &its_nodes, entry) { |
0dd57fed | 3629 | if (!is_v4(its)) |
75fd951b | 3630 | continue; |
eb78192b | 3631 | |
75fd951b MZ |
3632 | its_send_vmapp(its, vpe, false); |
3633 | } | |
eb78192b MZ |
3634 | } |
3635 | ||
8fff27ae | 3636 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
3637 | .alloc = its_vpe_irq_domain_alloc, |
3638 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
3639 | .activate = its_vpe_irq_domain_activate, |
3640 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
3641 | }; |
3642 | ||
4559fbb3 YW |
3643 | static int its_force_quiescent(void __iomem *base) |
3644 | { | |
3645 | u32 count = 1000000; /* 1s */ | |
3646 | u32 val; | |
3647 | ||
3648 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
3649 | /* |
3650 | * GIC architecture specification requires the ITS to be both | |
3651 | * disabled and quiescent for writes to GITS_BASER<n> or | |
3652 | * GITS_CBASER to not have UNPREDICTABLE results. | |
3653 | */ | |
3654 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
3655 | return 0; |
3656 | ||
3657 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 3658 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
3659 | writel_relaxed(val, base + GITS_CTLR); |
3660 | ||
3661 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
3662 | while (1) { | |
3663 | val = readl_relaxed(base + GITS_CTLR); | |
3664 | if (val & GITS_CTLR_QUIESCENT) | |
3665 | return 0; | |
3666 | ||
3667 | count--; | |
3668 | if (!count) | |
3669 | return -EBUSY; | |
3670 | ||
3671 | cpu_relax(); | |
3672 | udelay(1); | |
3673 | } | |
3674 | } | |
3675 | ||
9d111d49 | 3676 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
3677 | { |
3678 | struct its_node *its = data; | |
3679 | ||
576a8342 MZ |
3680 | /* erratum 22375: only alloc 8MB table size (20 bits) */ |
3681 | its->typer &= ~GITS_TYPER_DEVBITS; | |
3682 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); | |
94100970 | 3683 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
3684 | |
3685 | return true; | |
94100970 RR |
3686 | } |
3687 | ||
9d111d49 | 3688 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
3689 | { |
3690 | struct its_node *its = data; | |
3691 | ||
3692 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
3693 | |
3694 | return true; | |
fbf8f40e GK |
3695 | } |
3696 | ||
9d111d49 | 3697 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
3698 | { |
3699 | struct its_node *its = data; | |
3700 | ||
3701 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
ffedbf0c MZ |
3702 | its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; |
3703 | its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); | |
9d111d49 AB |
3704 | |
3705 | return true; | |
90922a2d SD |
3706 | } |
3707 | ||
558b0165 AB |
3708 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
3709 | { | |
3710 | struct its_node *its = its_dev->its; | |
3711 | ||
3712 | /* | |
3713 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
3714 | * which maps 32-bit writes targeted at a separate window of | |
3715 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
3716 | * with device ID taken from bits [device_id_bits + 1:2] of | |
3717 | * the window offset. | |
3718 | */ | |
3719 | return its->pre_its_base + (its_dev->device_id << 2); | |
3720 | } | |
3721 | ||
3722 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
3723 | { | |
3724 | struct its_node *its = data; | |
3725 | u32 pre_its_window[2]; | |
3726 | u32 ids; | |
3727 | ||
3728 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
3729 | "socionext,synquacer-pre-its", | |
3730 | pre_its_window, | |
3731 | ARRAY_SIZE(pre_its_window))) { | |
3732 | ||
3733 | its->pre_its_base = pre_its_window[0]; | |
3734 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
3735 | ||
3736 | ids = ilog2(pre_its_window[1]) - 2; | |
576a8342 MZ |
3737 | if (device_ids(its) > ids) { |
3738 | its->typer &= ~GITS_TYPER_DEVBITS; | |
3739 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); | |
3740 | } | |
558b0165 AB |
3741 | |
3742 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
3743 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; | |
3744 | return true; | |
3745 | } | |
3746 | return false; | |
3747 | } | |
3748 | ||
5c9a882e MZ |
3749 | static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) |
3750 | { | |
3751 | struct its_node *its = data; | |
3752 | ||
3753 | /* | |
3754 | * Hip07 insists on using the wrong address for the VLPI | |
3755 | * page. Trick it into doing the right thing... | |
3756 | */ | |
3757 | its->vlpi_redist_offset = SZ_128K; | |
3758 | return true; | |
90922a2d SD |
3759 | } |
3760 | ||
67510cca | 3761 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
3762 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
3763 | { | |
3764 | .desc = "ITS: Cavium errata 22375, 24313", | |
3765 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
3766 | .mask = 0xffff0fff, | |
3767 | .init = its_enable_quirk_cavium_22375, | |
3768 | }, | |
fbf8f40e GK |
3769 | #endif |
3770 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
3771 | { | |
3772 | .desc = "ITS: Cavium erratum 23144", | |
3773 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
3774 | .mask = 0xffff0fff, | |
3775 | .init = its_enable_quirk_cavium_23144, | |
3776 | }, | |
90922a2d SD |
3777 | #endif |
3778 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
3779 | { | |
3780 | .desc = "ITS: QDF2400 erratum 0065", | |
3781 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
3782 | .mask = 0xffffffff, | |
3783 | .init = its_enable_quirk_qdf2400_e0065, | |
3784 | }, | |
558b0165 AB |
3785 | #endif |
3786 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
3787 | { | |
3788 | /* | |
3789 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
3790 | * implementation, but with a 'pre-ITS' added that requires | |
3791 | * special handling in software. | |
3792 | */ | |
3793 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
3794 | .iidr = 0x0001143b, | |
3795 | .mask = 0xffffffff, | |
3796 | .init = its_enable_quirk_socionext_synquacer, | |
3797 | }, | |
5c9a882e MZ |
3798 | #endif |
3799 | #ifdef CONFIG_HISILICON_ERRATUM_161600802 | |
3800 | { | |
3801 | .desc = "ITS: Hip07 erratum 161600802", | |
3802 | .iidr = 0x00000004, | |
3803 | .mask = 0xffffffff, | |
3804 | .init = its_enable_quirk_hip07_161600802, | |
3805 | }, | |
94100970 | 3806 | #endif |
67510cca RR |
3807 | { |
3808 | } | |
3809 | }; | |
3810 | ||
3811 | static void its_enable_quirks(struct its_node *its) | |
3812 | { | |
3813 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
3814 | ||
3815 | gic_enable_quirks(iidr, its_quirks, its); | |
3816 | } | |
3817 | ||
dba0bc7b DB |
3818 | static int its_save_disable(void) |
3819 | { | |
3820 | struct its_node *its; | |
3821 | int err = 0; | |
3822 | ||
a8db7456 | 3823 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
3824 | list_for_each_entry(its, &its_nodes, entry) { |
3825 | void __iomem *base; | |
3826 | ||
3827 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3828 | continue; | |
3829 | ||
3830 | base = its->base; | |
3831 | its->ctlr_save = readl_relaxed(base + GITS_CTLR); | |
3832 | err = its_force_quiescent(base); | |
3833 | if (err) { | |
3834 | pr_err("ITS@%pa: failed to quiesce: %d\n", | |
3835 | &its->phys_base, err); | |
3836 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
3837 | goto err; | |
3838 | } | |
3839 | ||
3840 | its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); | |
3841 | } | |
3842 | ||
3843 | err: | |
3844 | if (err) { | |
3845 | list_for_each_entry_continue_reverse(its, &its_nodes, entry) { | |
3846 | void __iomem *base; | |
3847 | ||
3848 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3849 | continue; | |
3850 | ||
3851 | base = its->base; | |
3852 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
3853 | } | |
3854 | } | |
a8db7456 | 3855 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
3856 | |
3857 | return err; | |
3858 | } | |
3859 | ||
3860 | static void its_restore_enable(void) | |
3861 | { | |
3862 | struct its_node *its; | |
3863 | int ret; | |
3864 | ||
a8db7456 | 3865 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
3866 | list_for_each_entry(its, &its_nodes, entry) { |
3867 | void __iomem *base; | |
3868 | int i; | |
3869 | ||
3870 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3871 | continue; | |
3872 | ||
3873 | base = its->base; | |
3874 | ||
3875 | /* | |
3876 | * Make sure that the ITS is disabled. If it fails to quiesce, | |
3877 | * don't restore it since writing to CBASER or BASER<n> | |
3878 | * registers is undefined according to the GIC v3 ITS | |
3879 | * Specification. | |
3880 | */ | |
3881 | ret = its_force_quiescent(base); | |
3882 | if (ret) { | |
3883 | pr_err("ITS@%pa: failed to quiesce on resume: %d\n", | |
3884 | &its->phys_base, ret); | |
3885 | continue; | |
3886 | } | |
3887 | ||
3888 | gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); | |
3889 | ||
3890 | /* | |
3891 | * Writing CBASER resets CREADR to 0, so make CWRITER and | |
3892 | * cmd_write line up with it. | |
3893 | */ | |
3894 | its->cmd_write = its->cmd_base; | |
3895 | gits_write_cwriter(0, base + GITS_CWRITER); | |
3896 | ||
3897 | /* Restore GITS_BASER from the value cache. */ | |
3898 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
3899 | struct its_baser *baser = &its->tables[i]; | |
3900 | ||
3901 | if (!(baser->val & GITS_BASER_VALID)) | |
3902 | continue; | |
3903 | ||
3904 | its_write_baser(its, baser, baser->val); | |
3905 | } | |
3906 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
920181ce DB |
3907 | |
3908 | /* | |
3909 | * Reinit the collection if it's stored in the ITS. This is | |
3910 | * indicated by the col_id being less than the HCC field. | |
3911 | * CID < HCC as specified in the GIC v3 Documentation. | |
3912 | */ | |
3913 | if (its->collections[smp_processor_id()].col_id < | |
3914 | GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) | |
3915 | its_cpu_init_collection(its); | |
dba0bc7b | 3916 | } |
a8db7456 | 3917 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
3918 | } |
3919 | ||
3920 | static struct syscore_ops its_syscore_ops = { | |
3921 | .suspend = its_save_disable, | |
3922 | .resume = its_restore_enable, | |
3923 | }; | |
3924 | ||
db40f0a7 | 3925 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
3926 | { |
3927 | struct irq_domain *inner_domain; | |
3928 | struct msi_domain_info *info; | |
3929 | ||
3930 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
3931 | if (!info) | |
3932 | return -ENOMEM; | |
3933 | ||
db40f0a7 | 3934 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
3935 | if (!inner_domain) { |
3936 | kfree(info); | |
3937 | return -ENOMEM; | |
3938 | } | |
3939 | ||
db40f0a7 | 3940 | inner_domain->parent = its_parent; |
96f0d93a | 3941 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
558b0165 | 3942 | inner_domain->flags |= its->msi_domain_flags; |
d14ae5e6 TN |
3943 | info->ops = &its_msi_domain_ops; |
3944 | info->data = its; | |
3945 | inner_domain->host_data = info; | |
3946 | ||
3947 | return 0; | |
3948 | } | |
3949 | ||
8fff27ae MZ |
3950 | static int its_init_vpe_domain(void) |
3951 | { | |
20b3d54e MZ |
3952 | struct its_node *its; |
3953 | u32 devid; | |
3954 | int entries; | |
3955 | ||
3956 | if (gic_rdists->has_direct_lpi) { | |
3957 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
3958 | return 0; | |
3959 | } | |
3960 | ||
3961 | /* Any ITS will do, even if not v4 */ | |
3962 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
3963 | ||
3964 | entries = roundup_pow_of_two(nr_cpu_ids); | |
6396bb22 | 3965 | vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes), |
20b3d54e MZ |
3966 | GFP_KERNEL); |
3967 | if (!vpe_proxy.vpes) { | |
3968 | pr_err("ITS: Can't allocate GICv4 proxy device array\n"); | |
3969 | return -ENOMEM; | |
3970 | } | |
3971 | ||
3972 | /* Use the last possible DevID */ | |
576a8342 | 3973 | devid = GENMASK(device_ids(its) - 1, 0); |
20b3d54e MZ |
3974 | vpe_proxy.dev = its_create_device(its, devid, entries, false); |
3975 | if (!vpe_proxy.dev) { | |
3976 | kfree(vpe_proxy.vpes); | |
3977 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
3978 | return -ENOMEM; | |
3979 | } | |
3980 | ||
c427a475 | 3981 | BUG_ON(entries > vpe_proxy.dev->nr_ites); |
20b3d54e MZ |
3982 | |
3983 | raw_spin_lock_init(&vpe_proxy.lock); | |
3984 | vpe_proxy.next_victim = 0; | |
3985 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
3986 | devid, vpe_proxy.dev->nr_ites); | |
3987 | ||
8fff27ae MZ |
3988 | return 0; |
3989 | } | |
3990 | ||
3dfa576b MZ |
3991 | static int __init its_compute_its_list_map(struct resource *res, |
3992 | void __iomem *its_base) | |
3993 | { | |
3994 | int its_number; | |
3995 | u32 ctlr; | |
3996 | ||
3997 | /* | |
3998 | * This is assumed to be done early enough that we're | |
3999 | * guaranteed to be single-threaded, hence no | |
4000 | * locking. Should this change, we should address | |
4001 | * this. | |
4002 | */ | |
ab60491e MZ |
4003 | its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX); |
4004 | if (its_number >= GICv4_ITS_LIST_MAX) { | |
3dfa576b MZ |
4005 | pr_err("ITS@%pa: No ITSList entry available!\n", |
4006 | &res->start); | |
4007 | return -EINVAL; | |
4008 | } | |
4009 | ||
4010 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
4011 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
4012 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
4013 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
4014 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
4015 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
4016 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
4017 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
4018 | } | |
4019 | ||
4020 | if (test_and_set_bit(its_number, &its_list_map)) { | |
4021 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
4022 | &res->start, its_number); | |
4023 | return -EINVAL; | |
4024 | } | |
4025 | ||
4026 | return its_number; | |
4027 | } | |
4028 | ||
db40f0a7 TN |
4029 | static int __init its_probe_one(struct resource *res, |
4030 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 4031 | { |
4c21f3c2 MZ |
4032 | struct its_node *its; |
4033 | void __iomem *its_base; | |
3dfa576b MZ |
4034 | u32 val, ctlr; |
4035 | u64 baser, tmp, typer; | |
539d3782 | 4036 | struct page *page; |
4c21f3c2 MZ |
4037 | int err; |
4038 | ||
db40f0a7 | 4039 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 4040 | if (!its_base) { |
db40f0a7 | 4041 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
4042 | return -ENOMEM; |
4043 | } | |
4044 | ||
4045 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
4046 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 4047 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
4048 | err = -ENODEV; |
4049 | goto out_unmap; | |
4050 | } | |
4051 | ||
4559fbb3 YW |
4052 | err = its_force_quiescent(its_base); |
4053 | if (err) { | |
db40f0a7 | 4054 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
4055 | goto out_unmap; |
4056 | } | |
4057 | ||
db40f0a7 | 4058 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
4059 | |
4060 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
4061 | if (!its) { | |
4062 | err = -ENOMEM; | |
4063 | goto out_unmap; | |
4064 | } | |
4065 | ||
4066 | raw_spin_lock_init(&its->lock); | |
9791ec7d | 4067 | mutex_init(&its->dev_alloc_lock); |
4c21f3c2 MZ |
4068 | INIT_LIST_HEAD(&its->entry); |
4069 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 4070 | typer = gic_read_typer(its_base + GITS_TYPER); |
0dd57fed | 4071 | its->typer = typer; |
4c21f3c2 | 4072 | its->base = its_base; |
db40f0a7 | 4073 | its->phys_base = res->start; |
0dd57fed | 4074 | if (is_v4(its)) { |
3dfa576b MZ |
4075 | if (!(typer & GITS_TYPER_VMOVP)) { |
4076 | err = its_compute_its_list_map(res, its_base); | |
4077 | if (err < 0) | |
4078 | goto out_free_its; | |
4079 | ||
debf6d02 MZ |
4080 | its->list_nr = err; |
4081 | ||
3dfa576b MZ |
4082 | pr_info("ITS@%pa: Using ITS number %d\n", |
4083 | &res->start, err); | |
4084 | } else { | |
4085 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
4086 | } | |
5e516846 MZ |
4087 | |
4088 | if (is_v4_1(its)) { | |
4089 | u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer); | |
4090 | its->mpidr = readl_relaxed(its_base + GITS_MPIDR); | |
4091 | ||
4092 | pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", | |
4093 | &res->start, its->mpidr, svpet); | |
4094 | } | |
3dfa576b MZ |
4095 | } |
4096 | ||
db40f0a7 | 4097 | its->numa_node = numa_node; |
4c21f3c2 | 4098 | |
539d3782 SD |
4099 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
4100 | get_order(ITS_CMD_QUEUE_SZ)); | |
4101 | if (!page) { | |
4c21f3c2 MZ |
4102 | err = -ENOMEM; |
4103 | goto out_free_its; | |
4104 | } | |
539d3782 | 4105 | its->cmd_base = (void *)page_address(page); |
4c21f3c2 | 4106 | its->cmd_write = its->cmd_base; |
558b0165 AB |
4107 | its->fwnode_handle = handle; |
4108 | its->get_msi_base = its_irq_get_msi_base; | |
4109 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4c21f3c2 | 4110 | |
67510cca RR |
4111 | its_enable_quirks(its); |
4112 | ||
0e0b0f69 | 4113 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
4114 | if (err) |
4115 | goto out_free_cmd; | |
4116 | ||
4117 | err = its_alloc_collections(its); | |
4118 | if (err) | |
4119 | goto out_free_tables; | |
4120 | ||
4121 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 4122 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
4123 | GITS_CBASER_InnerShareable | |
4124 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
4125 | GITS_CBASER_VALID); | |
4126 | ||
0968a619 VM |
4127 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
4128 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 4129 | |
4ad3e363 | 4130 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
4131 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
4132 | /* | |
4133 | * The HW reports non-shareable, we must | |
4134 | * remove the cacheability attributes as | |
4135 | * well. | |
4136 | */ | |
4137 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
4138 | GITS_CBASER_CACHEABILITY_MASK); | |
4139 | baser |= GITS_CBASER_nC; | |
0968a619 | 4140 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 4141 | } |
4c21f3c2 MZ |
4142 | pr_info("ITS: using cache flushing for cmd queue\n"); |
4143 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
4144 | } | |
4145 | ||
0968a619 | 4146 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 4147 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d | 4148 | ctlr |= GITS_CTLR_ENABLE; |
0dd57fed | 4149 | if (is_v4(its)) |
d51c4b4d MZ |
4150 | ctlr |= GITS_CTLR_ImDe; |
4151 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 4152 | |
dba0bc7b DB |
4153 | if (GITS_TYPER_HCC(typer)) |
4154 | its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE; | |
4155 | ||
db40f0a7 | 4156 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
4157 | if (err) |
4158 | goto out_free_tables; | |
4c21f3c2 | 4159 | |
a8db7456 | 4160 | raw_spin_lock(&its_lock); |
4c21f3c2 | 4161 | list_add(&its->entry, &its_nodes); |
a8db7456 | 4162 | raw_spin_unlock(&its_lock); |
4c21f3c2 MZ |
4163 | |
4164 | return 0; | |
4165 | ||
4c21f3c2 MZ |
4166 | out_free_tables: |
4167 | its_free_tables(its); | |
4168 | out_free_cmd: | |
5bc13c2c | 4169 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
4170 | out_free_its: |
4171 | kfree(its); | |
4172 | out_unmap: | |
4173 | iounmap(its_base); | |
db40f0a7 | 4174 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
4175 | return err; |
4176 | } | |
4177 | ||
4178 | static bool gic_rdists_supports_plpis(void) | |
4179 | { | |
589ce5f4 | 4180 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
4181 | } |
4182 | ||
6eb486b6 SD |
4183 | static int redist_disable_lpis(void) |
4184 | { | |
4185 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
4186 | u64 timeout = USEC_PER_SEC; | |
4187 | u64 val; | |
4188 | ||
4189 | if (!gic_rdists_supports_plpis()) { | |
4190 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
4191 | return -ENXIO; | |
4192 | } | |
4193 | ||
4194 | val = readl_relaxed(rbase + GICR_CTLR); | |
4195 | if (!(val & GICR_CTLR_ENABLE_LPIS)) | |
4196 | return 0; | |
4197 | ||
11e37d35 MZ |
4198 | /* |
4199 | * If coming via a CPU hotplug event, we don't need to disable | |
4200 | * LPIs before trying to re-enable them. They are already | |
4201 | * configured and all is well in the world. | |
c440a9d9 MZ |
4202 | * |
4203 | * If running with preallocated tables, there is nothing to do. | |
11e37d35 | 4204 | */ |
c440a9d9 MZ |
4205 | if (gic_data_rdist()->lpi_enabled || |
4206 | (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) | |
11e37d35 MZ |
4207 | return 0; |
4208 | ||
4209 | /* | |
4210 | * From that point on, we only try to do some damage control. | |
4211 | */ | |
4212 | pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n", | |
6eb486b6 SD |
4213 | smp_processor_id()); |
4214 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
4215 | ||
4216 | /* Disable LPIs */ | |
4217 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
4218 | writel_relaxed(val, rbase + GICR_CTLR); | |
4219 | ||
4220 | /* Make sure any change to GICR_CTLR is observable by the GIC */ | |
4221 | dsb(sy); | |
4222 | ||
4223 | /* | |
4224 | * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs | |
4225 | * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. | |
4226 | * Error out if we time out waiting for RWP to clear. | |
4227 | */ | |
4228 | while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { | |
4229 | if (!timeout) { | |
4230 | pr_err("CPU%d: Timeout while disabling LPIs\n", | |
4231 | smp_processor_id()); | |
4232 | return -ETIMEDOUT; | |
4233 | } | |
4234 | udelay(1); | |
4235 | timeout--; | |
4236 | } | |
4237 | ||
4238 | /* | |
4239 | * After it has been written to 1, it is IMPLEMENTATION | |
4240 | * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be | |
4241 | * cleared to 0. Error out if clearing the bit failed. | |
4242 | */ | |
4243 | if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { | |
4244 | pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id()); | |
4245 | return -EBUSY; | |
4246 | } | |
4247 | ||
4248 | return 0; | |
4249 | } | |
4250 | ||
4c21f3c2 MZ |
4251 | int its_cpu_init(void) |
4252 | { | |
4c21f3c2 | 4253 | if (!list_empty(&its_nodes)) { |
6eb486b6 SD |
4254 | int ret; |
4255 | ||
4256 | ret = redist_disable_lpis(); | |
4257 | if (ret) | |
4258 | return ret; | |
4259 | ||
4c21f3c2 | 4260 | its_cpu_init_lpis(); |
920181ce | 4261 | its_cpu_init_collections(); |
4c21f3c2 MZ |
4262 | } |
4263 | ||
4264 | return 0; | |
4265 | } | |
4266 | ||
935bba7c | 4267 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
4268 | { .compatible = "arm,gic-v3-its", }, |
4269 | {}, | |
4270 | }; | |
4271 | ||
db40f0a7 | 4272 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
4273 | { |
4274 | struct device_node *np; | |
db40f0a7 | 4275 | struct resource res; |
4c21f3c2 MZ |
4276 | |
4277 | for (np = of_find_matching_node(node, its_device_id); np; | |
4278 | np = of_find_matching_node(np, its_device_id)) { | |
95a25625 SB |
4279 | if (!of_device_is_available(np)) |
4280 | continue; | |
d14ae5e6 | 4281 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
4282 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
4283 | np); | |
d14ae5e6 TN |
4284 | continue; |
4285 | } | |
4286 | ||
db40f0a7 | 4287 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 4288 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
4289 | continue; |
4290 | } | |
4291 | ||
4292 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 4293 | } |
db40f0a7 TN |
4294 | return 0; |
4295 | } | |
4296 | ||
3f010cf1 TN |
4297 | #ifdef CONFIG_ACPI |
4298 | ||
4299 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
4300 | ||
d1ce263f | 4301 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
4302 | struct its_srat_map { |
4303 | /* numa node id */ | |
4304 | u32 numa_node; | |
4305 | /* GIC ITS ID */ | |
4306 | u32 its_id; | |
4307 | }; | |
4308 | ||
fdf6e7a8 | 4309 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
4310 | static int its_in_srat __initdata; |
4311 | ||
4312 | static int __init acpi_get_its_numa_node(u32 its_id) | |
4313 | { | |
4314 | int i; | |
4315 | ||
4316 | for (i = 0; i < its_in_srat; i++) { | |
4317 | if (its_id == its_srat_maps[i].its_id) | |
4318 | return its_srat_maps[i].numa_node; | |
4319 | } | |
4320 | return NUMA_NO_NODE; | |
4321 | } | |
4322 | ||
60574d1e | 4323 | static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header, |
fdf6e7a8 HG |
4324 | const unsigned long end) |
4325 | { | |
4326 | return 0; | |
4327 | } | |
4328 | ||
60574d1e | 4329 | static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header, |
dbd2b826 GK |
4330 | const unsigned long end) |
4331 | { | |
4332 | int node; | |
4333 | struct acpi_srat_gic_its_affinity *its_affinity; | |
4334 | ||
4335 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
4336 | if (!its_affinity) | |
4337 | return -EINVAL; | |
4338 | ||
4339 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
4340 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
4341 | its_affinity->header.length); | |
4342 | return -EINVAL; | |
4343 | } | |
4344 | ||
dbd2b826 GK |
4345 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); |
4346 | ||
4347 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
4348 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
4349 | return 0; | |
4350 | } | |
4351 | ||
4352 | its_srat_maps[its_in_srat].numa_node = node; | |
4353 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
4354 | its_in_srat++; | |
4355 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
4356 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
4357 | ||
4358 | return 0; | |
4359 | } | |
4360 | ||
4361 | static void __init acpi_table_parse_srat_its(void) | |
4362 | { | |
fdf6e7a8 HG |
4363 | int count; |
4364 | ||
4365 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
4366 | sizeof(struct acpi_table_srat), | |
4367 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
4368 | gic_acpi_match_srat_its, 0); | |
4369 | if (count <= 0) | |
4370 | return; | |
4371 | ||
6da2ec56 KC |
4372 | its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map), |
4373 | GFP_KERNEL); | |
fdf6e7a8 HG |
4374 | if (!its_srat_maps) { |
4375 | pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n"); | |
4376 | return; | |
4377 | } | |
4378 | ||
dbd2b826 GK |
4379 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
4380 | sizeof(struct acpi_table_srat), | |
4381 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
4382 | gic_acpi_parse_srat_its, 0); | |
4383 | } | |
fdf6e7a8 HG |
4384 | |
4385 | /* free the its_srat_maps after ITS probing */ | |
4386 | static void __init acpi_its_srat_maps_free(void) | |
4387 | { | |
4388 | kfree(its_srat_maps); | |
4389 | } | |
dbd2b826 GK |
4390 | #else |
4391 | static void __init acpi_table_parse_srat_its(void) { } | |
4392 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 4393 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
4394 | #endif |
4395 | ||
60574d1e | 4396 | static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, |
3f010cf1 TN |
4397 | const unsigned long end) |
4398 | { | |
4399 | struct acpi_madt_generic_translator *its_entry; | |
4400 | struct fwnode_handle *dom_handle; | |
4401 | struct resource res; | |
4402 | int err; | |
4403 | ||
4404 | its_entry = (struct acpi_madt_generic_translator *)header; | |
4405 | memset(&res, 0, sizeof(res)); | |
4406 | res.start = its_entry->base_address; | |
4407 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
4408 | res.flags = IORESOURCE_MEM; | |
4409 | ||
5778cc77 | 4410 | dom_handle = irq_domain_alloc_fwnode(&res.start); |
3f010cf1 TN |
4411 | if (!dom_handle) { |
4412 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
4413 | &res.start); | |
4414 | return -ENOMEM; | |
4415 | } | |
4416 | ||
8b4282e6 SK |
4417 | err = iort_register_domain_token(its_entry->translation_id, res.start, |
4418 | dom_handle); | |
3f010cf1 TN |
4419 | if (err) { |
4420 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
4421 | &res.start, its_entry->translation_id); | |
4422 | goto dom_err; | |
4423 | } | |
4424 | ||
dbd2b826 GK |
4425 | err = its_probe_one(&res, dom_handle, |
4426 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
4427 | if (!err) |
4428 | return 0; | |
4429 | ||
4430 | iort_deregister_domain_token(its_entry->translation_id); | |
4431 | dom_err: | |
4432 | irq_domain_free_fwnode(dom_handle); | |
4433 | return err; | |
4434 | } | |
4435 | ||
4436 | static void __init its_acpi_probe(void) | |
4437 | { | |
dbd2b826 | 4438 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
4439 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
4440 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 4441 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
4442 | } |
4443 | #else | |
4444 | static void __init its_acpi_probe(void) { } | |
4445 | #endif | |
4446 | ||
db40f0a7 TN |
4447 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
4448 | struct irq_domain *parent_domain) | |
4449 | { | |
4450 | struct device_node *of_node; | |
8fff27ae MZ |
4451 | struct its_node *its; |
4452 | bool has_v4 = false; | |
4453 | int err; | |
db40f0a7 | 4454 | |
5e516846 MZ |
4455 | gic_rdists = rdists; |
4456 | ||
db40f0a7 TN |
4457 | its_parent = parent_domain; |
4458 | of_node = to_of_node(handle); | |
4459 | if (of_node) | |
4460 | its_of_probe(of_node); | |
4461 | else | |
3f010cf1 | 4462 | its_acpi_probe(); |
4c21f3c2 MZ |
4463 | |
4464 | if (list_empty(&its_nodes)) { | |
4465 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
4466 | return -ENXIO; | |
4467 | } | |
4468 | ||
11e37d35 | 4469 | err = allocate_lpi_tables(); |
8fff27ae MZ |
4470 | if (err) |
4471 | return err; | |
4472 | ||
4473 | list_for_each_entry(its, &its_nodes, entry) | |
0dd57fed | 4474 | has_v4 |= is_v4(its); |
8fff27ae MZ |
4475 | |
4476 | if (has_v4 & rdists->has_vlpis) { | |
3d63cb53 MZ |
4477 | if (its_init_vpe_domain() || |
4478 | its_init_v4(parent_domain, &its_vpe_domain_ops)) { | |
8fff27ae MZ |
4479 | rdists->has_vlpis = false; |
4480 | pr_err("ITS: Disabling GICv4 support\n"); | |
4481 | } | |
4482 | } | |
4483 | ||
dba0bc7b DB |
4484 | register_syscore_ops(&its_syscore_ops); |
4485 | ||
8fff27ae | 4486 | return 0; |
4c21f3c2 | 4487 | } |