Commit | Line | Data |
---|---|---|
cc2d3216 | 1 | /* |
d7276b80 | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
c6e2ccb6 | 22 | #include <linux/crash_dump.h> |
cc2d3216 | 23 | #include <linux/delay.h> |
44bb7e24 | 24 | #include <linux/dma-iommu.h> |
3fb68fae | 25 | #include <linux/efi.h> |
cc2d3216 | 26 | #include <linux/interrupt.h> |
3f010cf1 | 27 | #include <linux/irqdomain.h> |
880cb3cd MZ |
28 | #include <linux/list.h> |
29 | #include <linux/list_sort.h> | |
cc2d3216 | 30 | #include <linux/log2.h> |
5e2c9f9a | 31 | #include <linux/memblock.h> |
cc2d3216 MZ |
32 | #include <linux/mm.h> |
33 | #include <linux/msi.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_address.h> | |
36 | #include <linux/of_irq.h> | |
37 | #include <linux/of_pci.h> | |
38 | #include <linux/of_platform.h> | |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
dba0bc7b | 41 | #include <linux/syscore_ops.h> |
cc2d3216 | 42 | |
41a83e06 | 43 | #include <linux/irqchip.h> |
cc2d3216 | 44 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 45 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 46 | |
cc2d3216 MZ |
47 | #include <asm/cputype.h> |
48 | #include <asm/exception.h> | |
49 | ||
67510cca RR |
50 | #include "irq-gic-common.h" |
51 | ||
94100970 RR |
52 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
53 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 54 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
dba0bc7b | 55 | #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) |
cc2d3216 | 56 | |
c48ed51c | 57 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
c440a9d9 | 58 | #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) |
c48ed51c | 59 | |
a13b0404 MZ |
60 | static u32 lpi_id_bits; |
61 | ||
62 | /* | |
63 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
64 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
65 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
66 | */ | |
67 | #define LPI_NRBITS lpi_id_bits | |
68 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
69 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
70 | ||
2130b789 | 71 | #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI |
a13b0404 | 72 | |
cc2d3216 MZ |
73 | /* |
74 | * Collection structure - just an ID, and a redistributor address to | |
75 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
76 | * CPU. | |
77 | */ | |
78 | struct its_collection { | |
79 | u64 target_address; | |
80 | u16 col_id; | |
81 | }; | |
82 | ||
466b7d16 | 83 | /* |
9347359a SD |
84 | * The ITS_BASER structure - contains memory information, cached |
85 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
86 | */ |
87 | struct its_baser { | |
88 | void *base; | |
89 | u64 val; | |
90 | u32 order; | |
9347359a | 91 | u32 psz; |
466b7d16 SD |
92 | }; |
93 | ||
558b0165 AB |
94 | struct its_device; |
95 | ||
cc2d3216 MZ |
96 | /* |
97 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
98 | * top-level MSI domain, the command queue, the collections, and the |
99 | * list of devices writing to it. | |
9791ec7d MZ |
100 | * |
101 | * dev_alloc_lock has to be taken for device allocations, while the | |
102 | * spinlock must be taken to parse data structures such as the device | |
103 | * list. | |
cc2d3216 MZ |
104 | */ |
105 | struct its_node { | |
106 | raw_spinlock_t lock; | |
9791ec7d | 107 | struct mutex dev_alloc_lock; |
cc2d3216 | 108 | struct list_head entry; |
cc2d3216 | 109 | void __iomem *base; |
db40f0a7 | 110 | phys_addr_t phys_base; |
cc2d3216 MZ |
111 | struct its_cmd_block *cmd_base; |
112 | struct its_cmd_block *cmd_write; | |
466b7d16 | 113 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 114 | struct its_collection *collections; |
558b0165 AB |
115 | struct fwnode_handle *fwnode_handle; |
116 | u64 (*get_msi_base)(struct its_device *its_dev); | |
dba0bc7b DB |
117 | u64 cbaser_save; |
118 | u32 ctlr_save; | |
cc2d3216 MZ |
119 | struct list_head its_device_list; |
120 | u64 flags; | |
debf6d02 | 121 | unsigned long list_nr; |
cc2d3216 | 122 | u32 ite_size; |
466b7d16 | 123 | u32 device_ids; |
fbf8f40e | 124 | int numa_node; |
558b0165 AB |
125 | unsigned int msi_domain_flags; |
126 | u32 pre_its_base; /* for Socionext Synquacer */ | |
3dfa576b | 127 | bool is_v4; |
5c9a882e | 128 | int vlpi_redist_offset; |
cc2d3216 MZ |
129 | }; |
130 | ||
131 | #define ITS_ITT_ALIGN SZ_256 | |
132 | ||
32bd44dc SD |
133 | /* The maximum number of VPEID bits supported by VLPI commands */ |
134 | #define ITS_MAX_VPEID_BITS (16) | |
135 | #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) | |
136 | ||
2eca0d6c SD |
137 | /* Convert page order to size in bytes */ |
138 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
139 | ||
591e5bec MZ |
140 | struct event_lpi_map { |
141 | unsigned long *lpi_map; | |
142 | u16 *col_map; | |
143 | irq_hw_number_t lpi_base; | |
144 | int nr_lpis; | |
d011e4e6 MZ |
145 | struct mutex vlpi_lock; |
146 | struct its_vm *vm; | |
147 | struct its_vlpi_map *vlpi_maps; | |
148 | int nr_vlpis; | |
591e5bec MZ |
149 | }; |
150 | ||
cc2d3216 | 151 | /* |
d011e4e6 MZ |
152 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
153 | * translation table, and a list of interrupts. If it some of its | |
154 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
155 | * indicates which one. | |
cc2d3216 MZ |
156 | */ |
157 | struct its_device { | |
158 | struct list_head entry; | |
159 | struct its_node *its; | |
591e5bec | 160 | struct event_lpi_map event_map; |
cc2d3216 | 161 | void *itt; |
cc2d3216 MZ |
162 | u32 nr_ites; |
163 | u32 device_id; | |
9791ec7d | 164 | bool shared; |
cc2d3216 MZ |
165 | }; |
166 | ||
20b3d54e MZ |
167 | static struct { |
168 | raw_spinlock_t lock; | |
169 | struct its_device *dev; | |
170 | struct its_vpe **vpes; | |
171 | int next_victim; | |
172 | } vpe_proxy; | |
173 | ||
1ac19ca6 | 174 | static LIST_HEAD(its_nodes); |
a8db7456 | 175 | static DEFINE_RAW_SPINLOCK(its_lock); |
1ac19ca6 | 176 | static struct rdists *gic_rdists; |
db40f0a7 | 177 | static struct irq_domain *its_parent; |
1ac19ca6 | 178 | |
3dfa576b | 179 | static unsigned long its_list_map; |
3171a47a MZ |
180 | static u16 vmovp_seq_num; |
181 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
182 | ||
7d75bbb4 | 183 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 184 | |
1ac19ca6 | 185 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
11e37d35 | 186 | #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu)) |
1ac19ca6 | 187 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
e643d803 | 188 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 189 | |
591e5bec MZ |
190 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
191 | u32 event) | |
192 | { | |
193 | struct its_node *its = its_dev->its; | |
194 | ||
195 | return its->collections + its_dev->event_map.col_map[event]; | |
196 | } | |
197 | ||
83559b47 MZ |
198 | static struct its_collection *valid_col(struct its_collection *col) |
199 | { | |
200 | if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(0, 15))) | |
201 | return NULL; | |
202 | ||
203 | return col; | |
204 | } | |
205 | ||
205e065d MZ |
206 | static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) |
207 | { | |
208 | if (valid_col(its->collections + vpe->col_idx)) | |
209 | return vpe; | |
210 | ||
211 | return NULL; | |
212 | } | |
213 | ||
cc2d3216 MZ |
214 | /* |
215 | * ITS command descriptors - parameters to be encoded in a command | |
216 | * block. | |
217 | */ | |
218 | struct its_cmd_desc { | |
219 | union { | |
220 | struct { | |
221 | struct its_device *dev; | |
222 | u32 event_id; | |
223 | } its_inv_cmd; | |
224 | ||
8d85dced MZ |
225 | struct { |
226 | struct its_device *dev; | |
227 | u32 event_id; | |
228 | } its_clear_cmd; | |
229 | ||
cc2d3216 MZ |
230 | struct { |
231 | struct its_device *dev; | |
232 | u32 event_id; | |
233 | } its_int_cmd; | |
234 | ||
235 | struct { | |
236 | struct its_device *dev; | |
237 | int valid; | |
238 | } its_mapd_cmd; | |
239 | ||
240 | struct { | |
241 | struct its_collection *col; | |
242 | int valid; | |
243 | } its_mapc_cmd; | |
244 | ||
245 | struct { | |
246 | struct its_device *dev; | |
247 | u32 phys_id; | |
248 | u32 event_id; | |
6a25ad3a | 249 | } its_mapti_cmd; |
cc2d3216 MZ |
250 | |
251 | struct { | |
252 | struct its_device *dev; | |
253 | struct its_collection *col; | |
591e5bec | 254 | u32 event_id; |
cc2d3216 MZ |
255 | } its_movi_cmd; |
256 | ||
257 | struct { | |
258 | struct its_device *dev; | |
259 | u32 event_id; | |
260 | } its_discard_cmd; | |
261 | ||
262 | struct { | |
263 | struct its_collection *col; | |
264 | } its_invall_cmd; | |
d011e4e6 | 265 | |
eb78192b MZ |
266 | struct { |
267 | struct its_vpe *vpe; | |
268 | } its_vinvall_cmd; | |
269 | ||
270 | struct { | |
271 | struct its_vpe *vpe; | |
272 | struct its_collection *col; | |
273 | bool valid; | |
274 | } its_vmapp_cmd; | |
275 | ||
d011e4e6 MZ |
276 | struct { |
277 | struct its_vpe *vpe; | |
278 | struct its_device *dev; | |
279 | u32 virt_id; | |
280 | u32 event_id; | |
281 | bool db_enabled; | |
282 | } its_vmapti_cmd; | |
283 | ||
284 | struct { | |
285 | struct its_vpe *vpe; | |
286 | struct its_device *dev; | |
287 | u32 event_id; | |
288 | bool db_enabled; | |
289 | } its_vmovi_cmd; | |
3171a47a MZ |
290 | |
291 | struct { | |
292 | struct its_vpe *vpe; | |
293 | struct its_collection *col; | |
294 | u16 seq_num; | |
295 | u16 its_list; | |
296 | } its_vmovp_cmd; | |
cc2d3216 MZ |
297 | }; |
298 | }; | |
299 | ||
300 | /* | |
301 | * The ITS command block, which is what the ITS actually parses. | |
302 | */ | |
303 | struct its_cmd_block { | |
304 | u64 raw_cmd[4]; | |
305 | }; | |
306 | ||
307 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
308 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
309 | ||
67047f90 MZ |
310 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *, |
311 | struct its_cmd_block *, | |
cc2d3216 MZ |
312 | struct its_cmd_desc *); |
313 | ||
67047f90 MZ |
314 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *, |
315 | struct its_cmd_block *, | |
d011e4e6 MZ |
316 | struct its_cmd_desc *); |
317 | ||
4d36f136 MZ |
318 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
319 | { | |
320 | u64 mask = GENMASK_ULL(h, l); | |
321 | *raw_cmd &= ~mask; | |
322 | *raw_cmd |= (val << l) & mask; | |
323 | } | |
324 | ||
cc2d3216 MZ |
325 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
326 | { | |
4d36f136 | 327 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
328 | } |
329 | ||
330 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
331 | { | |
4d36f136 | 332 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
333 | } |
334 | ||
335 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
336 | { | |
4d36f136 | 337 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
338 | } |
339 | ||
340 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
341 | { | |
4d36f136 | 342 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
343 | } |
344 | ||
345 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
346 | { | |
4d36f136 | 347 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
348 | } |
349 | ||
350 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
351 | { | |
30ae9610 | 352 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); |
cc2d3216 MZ |
353 | } |
354 | ||
355 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
356 | { | |
4d36f136 | 357 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
358 | } |
359 | ||
360 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
361 | { | |
30ae9610 | 362 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); |
cc2d3216 MZ |
363 | } |
364 | ||
365 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
366 | { | |
4d36f136 | 367 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
368 | } |
369 | ||
d011e4e6 MZ |
370 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
371 | { | |
372 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
373 | } | |
374 | ||
375 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
376 | { | |
377 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
378 | } | |
379 | ||
380 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
381 | { | |
382 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
383 | } | |
384 | ||
385 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
386 | { | |
387 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
388 | } | |
389 | ||
3171a47a MZ |
390 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
391 | { | |
392 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
393 | } | |
394 | ||
395 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
396 | { | |
397 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
398 | } | |
399 | ||
eb78192b MZ |
400 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
401 | { | |
30ae9610 | 402 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); |
eb78192b MZ |
403 | } |
404 | ||
405 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
406 | { | |
407 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
408 | } | |
409 | ||
cc2d3216 MZ |
410 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
411 | { | |
412 | /* Let's fixup BE commands */ | |
413 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
414 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
415 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
416 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
417 | } | |
418 | ||
67047f90 MZ |
419 | static struct its_collection *its_build_mapd_cmd(struct its_node *its, |
420 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
421 | struct its_cmd_desc *desc) |
422 | { | |
423 | unsigned long itt_addr; | |
c8481267 | 424 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
425 | |
426 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
427 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
428 | ||
429 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
430 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
431 | its_encode_size(cmd, size - 1); | |
432 | its_encode_itt(cmd, itt_addr); | |
433 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
434 | ||
435 | its_fixup_cmd(cmd); | |
436 | ||
591e5bec | 437 | return NULL; |
cc2d3216 MZ |
438 | } |
439 | ||
67047f90 MZ |
440 | static struct its_collection *its_build_mapc_cmd(struct its_node *its, |
441 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
442 | struct its_cmd_desc *desc) |
443 | { | |
444 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
445 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
446 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
447 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
448 | ||
449 | its_fixup_cmd(cmd); | |
450 | ||
451 | return desc->its_mapc_cmd.col; | |
452 | } | |
453 | ||
67047f90 MZ |
454 | static struct its_collection *its_build_mapti_cmd(struct its_node *its, |
455 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
456 | struct its_cmd_desc *desc) |
457 | { | |
591e5bec MZ |
458 | struct its_collection *col; |
459 | ||
6a25ad3a MZ |
460 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
461 | desc->its_mapti_cmd.event_id); | |
591e5bec | 462 | |
6a25ad3a MZ |
463 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
464 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
465 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
466 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 467 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
468 | |
469 | its_fixup_cmd(cmd); | |
470 | ||
83559b47 | 471 | return valid_col(col); |
cc2d3216 MZ |
472 | } |
473 | ||
67047f90 MZ |
474 | static struct its_collection *its_build_movi_cmd(struct its_node *its, |
475 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
476 | struct its_cmd_desc *desc) |
477 | { | |
591e5bec MZ |
478 | struct its_collection *col; |
479 | ||
480 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
481 | desc->its_movi_cmd.event_id); | |
482 | ||
cc2d3216 MZ |
483 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
484 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 485 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
486 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
487 | ||
488 | its_fixup_cmd(cmd); | |
489 | ||
83559b47 | 490 | return valid_col(col); |
cc2d3216 MZ |
491 | } |
492 | ||
67047f90 MZ |
493 | static struct its_collection *its_build_discard_cmd(struct its_node *its, |
494 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
495 | struct its_cmd_desc *desc) |
496 | { | |
591e5bec MZ |
497 | struct its_collection *col; |
498 | ||
499 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
500 | desc->its_discard_cmd.event_id); | |
501 | ||
cc2d3216 MZ |
502 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
503 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
504 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
505 | ||
506 | its_fixup_cmd(cmd); | |
507 | ||
83559b47 | 508 | return valid_col(col); |
cc2d3216 MZ |
509 | } |
510 | ||
67047f90 MZ |
511 | static struct its_collection *its_build_inv_cmd(struct its_node *its, |
512 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
513 | struct its_cmd_desc *desc) |
514 | { | |
591e5bec MZ |
515 | struct its_collection *col; |
516 | ||
517 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
518 | desc->its_inv_cmd.event_id); | |
519 | ||
cc2d3216 MZ |
520 | its_encode_cmd(cmd, GITS_CMD_INV); |
521 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
522 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
523 | ||
524 | its_fixup_cmd(cmd); | |
525 | ||
83559b47 | 526 | return valid_col(col); |
cc2d3216 MZ |
527 | } |
528 | ||
67047f90 MZ |
529 | static struct its_collection *its_build_int_cmd(struct its_node *its, |
530 | struct its_cmd_block *cmd, | |
8d85dced MZ |
531 | struct its_cmd_desc *desc) |
532 | { | |
533 | struct its_collection *col; | |
534 | ||
535 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
536 | desc->its_int_cmd.event_id); | |
537 | ||
538 | its_encode_cmd(cmd, GITS_CMD_INT); | |
539 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
540 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
541 | ||
542 | its_fixup_cmd(cmd); | |
543 | ||
83559b47 | 544 | return valid_col(col); |
8d85dced MZ |
545 | } |
546 | ||
67047f90 MZ |
547 | static struct its_collection *its_build_clear_cmd(struct its_node *its, |
548 | struct its_cmd_block *cmd, | |
8d85dced MZ |
549 | struct its_cmd_desc *desc) |
550 | { | |
551 | struct its_collection *col; | |
552 | ||
553 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
554 | desc->its_clear_cmd.event_id); | |
555 | ||
556 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
557 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
558 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
559 | ||
560 | its_fixup_cmd(cmd); | |
561 | ||
83559b47 | 562 | return valid_col(col); |
8d85dced MZ |
563 | } |
564 | ||
67047f90 MZ |
565 | static struct its_collection *its_build_invall_cmd(struct its_node *its, |
566 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
567 | struct its_cmd_desc *desc) |
568 | { | |
569 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
570 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
571 | ||
572 | its_fixup_cmd(cmd); | |
573 | ||
574 | return NULL; | |
575 | } | |
576 | ||
67047f90 MZ |
577 | static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, |
578 | struct its_cmd_block *cmd, | |
eb78192b MZ |
579 | struct its_cmd_desc *desc) |
580 | { | |
581 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
582 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
583 | ||
584 | its_fixup_cmd(cmd); | |
585 | ||
205e065d | 586 | return valid_vpe(its, desc->its_vinvall_cmd.vpe); |
eb78192b MZ |
587 | } |
588 | ||
67047f90 MZ |
589 | static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, |
590 | struct its_cmd_block *cmd, | |
eb78192b MZ |
591 | struct its_cmd_desc *desc) |
592 | { | |
593 | unsigned long vpt_addr; | |
5c9a882e | 594 | u64 target; |
eb78192b MZ |
595 | |
596 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
5c9a882e | 597 | target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; |
eb78192b MZ |
598 | |
599 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
600 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
601 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
5c9a882e | 602 | its_encode_target(cmd, target); |
eb78192b MZ |
603 | its_encode_vpt_addr(cmd, vpt_addr); |
604 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
605 | ||
606 | its_fixup_cmd(cmd); | |
607 | ||
205e065d | 608 | return valid_vpe(its, desc->its_vmapp_cmd.vpe); |
eb78192b MZ |
609 | } |
610 | ||
67047f90 MZ |
611 | static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, |
612 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
613 | struct its_cmd_desc *desc) |
614 | { | |
615 | u32 db; | |
616 | ||
617 | if (desc->its_vmapti_cmd.db_enabled) | |
618 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; | |
619 | else | |
620 | db = 1023; | |
621 | ||
622 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
623 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
624 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
625 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
626 | its_encode_db_phys_id(cmd, db); | |
627 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
628 | ||
629 | its_fixup_cmd(cmd); | |
630 | ||
205e065d | 631 | return valid_vpe(its, desc->its_vmapti_cmd.vpe); |
d011e4e6 MZ |
632 | } |
633 | ||
67047f90 MZ |
634 | static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, |
635 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
636 | struct its_cmd_desc *desc) |
637 | { | |
638 | u32 db; | |
639 | ||
640 | if (desc->its_vmovi_cmd.db_enabled) | |
641 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; | |
642 | else | |
643 | db = 1023; | |
644 | ||
645 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
646 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
647 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
648 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
649 | its_encode_db_phys_id(cmd, db); | |
650 | its_encode_db_valid(cmd, true); | |
651 | ||
652 | its_fixup_cmd(cmd); | |
653 | ||
205e065d | 654 | return valid_vpe(its, desc->its_vmovi_cmd.vpe); |
d011e4e6 MZ |
655 | } |
656 | ||
67047f90 MZ |
657 | static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, |
658 | struct its_cmd_block *cmd, | |
3171a47a MZ |
659 | struct its_cmd_desc *desc) |
660 | { | |
5c9a882e MZ |
661 | u64 target; |
662 | ||
663 | target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; | |
3171a47a MZ |
664 | its_encode_cmd(cmd, GITS_CMD_VMOVP); |
665 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
666 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
667 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
5c9a882e | 668 | its_encode_target(cmd, target); |
3171a47a MZ |
669 | |
670 | its_fixup_cmd(cmd); | |
671 | ||
205e065d | 672 | return valid_vpe(its, desc->its_vmovp_cmd.vpe); |
3171a47a MZ |
673 | } |
674 | ||
cc2d3216 MZ |
675 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
676 | struct its_cmd_block *ptr) | |
677 | { | |
678 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
679 | } | |
680 | ||
681 | static int its_queue_full(struct its_node *its) | |
682 | { | |
683 | int widx; | |
684 | int ridx; | |
685 | ||
686 | widx = its->cmd_write - its->cmd_base; | |
687 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
688 | ||
689 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
690 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
691 | return 1; | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
697 | { | |
698 | struct its_cmd_block *cmd; | |
699 | u32 count = 1000000; /* 1s! */ | |
700 | ||
701 | while (its_queue_full(its)) { | |
702 | count--; | |
703 | if (!count) { | |
704 | pr_err_ratelimited("ITS queue not draining\n"); | |
705 | return NULL; | |
706 | } | |
707 | cpu_relax(); | |
708 | udelay(1); | |
709 | } | |
710 | ||
711 | cmd = its->cmd_write++; | |
712 | ||
713 | /* Handle queue wrapping */ | |
714 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
715 | its->cmd_write = its->cmd_base; | |
716 | ||
34d677a9 MZ |
717 | /* Clear command */ |
718 | cmd->raw_cmd[0] = 0; | |
719 | cmd->raw_cmd[1] = 0; | |
720 | cmd->raw_cmd[2] = 0; | |
721 | cmd->raw_cmd[3] = 0; | |
722 | ||
cc2d3216 MZ |
723 | return cmd; |
724 | } | |
725 | ||
726 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
727 | { | |
728 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
729 | ||
730 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
731 | ||
732 | return its->cmd_write; | |
733 | } | |
734 | ||
735 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
736 | { | |
737 | /* | |
738 | * Make sure the commands written to memory are observable by | |
739 | * the ITS. | |
740 | */ | |
741 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 742 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
743 | else |
744 | dsb(ishst); | |
745 | } | |
746 | ||
a19b462f MZ |
747 | static int its_wait_for_range_completion(struct its_node *its, |
748 | struct its_cmd_block *from, | |
749 | struct its_cmd_block *to) | |
cc2d3216 MZ |
750 | { |
751 | u64 rd_idx, from_idx, to_idx; | |
752 | u32 count = 1000000; /* 1s! */ | |
753 | ||
754 | from_idx = its_cmd_ptr_to_offset(its, from); | |
755 | to_idx = its_cmd_ptr_to_offset(its, to); | |
756 | ||
757 | while (1) { | |
758 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
9bdd8b1c MZ |
759 | |
760 | /* Direct case */ | |
761 | if (from_idx < to_idx && rd_idx >= to_idx) | |
762 | break; | |
763 | ||
764 | /* Wrapped case */ | |
765 | if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx) | |
cc2d3216 MZ |
766 | break; |
767 | ||
768 | count--; | |
769 | if (!count) { | |
a19b462f MZ |
770 | pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n", |
771 | from_idx, to_idx, rd_idx); | |
772 | return -1; | |
cc2d3216 MZ |
773 | } |
774 | cpu_relax(); | |
775 | udelay(1); | |
776 | } | |
a19b462f MZ |
777 | |
778 | return 0; | |
cc2d3216 MZ |
779 | } |
780 | ||
e4f9094b MZ |
781 | /* Warning, macro hell follows */ |
782 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
783 | void name(struct its_node *its, \ | |
784 | buildtype builder, \ | |
785 | struct its_cmd_desc *desc) \ | |
786 | { \ | |
787 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
788 | synctype *sync_obj; \ | |
789 | unsigned long flags; \ | |
790 | \ | |
791 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
792 | \ | |
793 | cmd = its_allocate_entry(its); \ | |
794 | if (!cmd) { /* We're soooooo screewed... */ \ | |
795 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
796 | return; \ | |
797 | } \ | |
67047f90 | 798 | sync_obj = builder(its, cmd, desc); \ |
e4f9094b MZ |
799 | its_flush_cmd(its, cmd); \ |
800 | \ | |
801 | if (sync_obj) { \ | |
802 | sync_cmd = its_allocate_entry(its); \ | |
803 | if (!sync_cmd) \ | |
804 | goto post; \ | |
805 | \ | |
67047f90 | 806 | buildfn(its, sync_cmd, sync_obj); \ |
e4f9094b MZ |
807 | its_flush_cmd(its, sync_cmd); \ |
808 | } \ | |
809 | \ | |
810 | post: \ | |
811 | next_cmd = its_post_commands(its); \ | |
812 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
813 | \ | |
a19b462f MZ |
814 | if (its_wait_for_range_completion(its, cmd, next_cmd)) \ |
815 | pr_err_ratelimited("ITS cmd %ps failed\n", builder); \ | |
e4f9094b | 816 | } |
cc2d3216 | 817 | |
67047f90 MZ |
818 | static void its_build_sync_cmd(struct its_node *its, |
819 | struct its_cmd_block *sync_cmd, | |
e4f9094b MZ |
820 | struct its_collection *sync_col) |
821 | { | |
822 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
823 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 824 | |
e4f9094b | 825 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
826 | } |
827 | ||
e4f9094b MZ |
828 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
829 | struct its_collection, its_build_sync_cmd) | |
830 | ||
67047f90 MZ |
831 | static void its_build_vsync_cmd(struct its_node *its, |
832 | struct its_cmd_block *sync_cmd, | |
d011e4e6 MZ |
833 | struct its_vpe *sync_vpe) |
834 | { | |
835 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
836 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
837 | ||
838 | its_fixup_cmd(sync_cmd); | |
839 | } | |
840 | ||
841 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
842 | struct its_vpe, its_build_vsync_cmd) | |
843 | ||
8d85dced | 844 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 845 | { |
8d85dced | 846 | struct its_cmd_desc desc; |
cc2d3216 | 847 | |
8d85dced MZ |
848 | desc.its_int_cmd.dev = dev; |
849 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 850 | |
8d85dced MZ |
851 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
852 | } | |
cc2d3216 | 853 | |
8d85dced MZ |
854 | static void its_send_clear(struct its_device *dev, u32 event_id) |
855 | { | |
856 | struct its_cmd_desc desc; | |
cc2d3216 | 857 | |
8d85dced MZ |
858 | desc.its_clear_cmd.dev = dev; |
859 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 860 | |
8d85dced | 861 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
862 | } |
863 | ||
864 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
865 | { | |
866 | struct its_cmd_desc desc; | |
867 | ||
868 | desc.its_inv_cmd.dev = dev; | |
869 | desc.its_inv_cmd.event_id = event_id; | |
870 | ||
871 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
872 | } | |
873 | ||
874 | static void its_send_mapd(struct its_device *dev, int valid) | |
875 | { | |
876 | struct its_cmd_desc desc; | |
877 | ||
878 | desc.its_mapd_cmd.dev = dev; | |
879 | desc.its_mapd_cmd.valid = !!valid; | |
880 | ||
881 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
882 | } | |
883 | ||
884 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
885 | int valid) | |
886 | { | |
887 | struct its_cmd_desc desc; | |
888 | ||
889 | desc.its_mapc_cmd.col = col; | |
890 | desc.its_mapc_cmd.valid = !!valid; | |
891 | ||
892 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
893 | } | |
894 | ||
6a25ad3a | 895 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
896 | { |
897 | struct its_cmd_desc desc; | |
898 | ||
6a25ad3a MZ |
899 | desc.its_mapti_cmd.dev = dev; |
900 | desc.its_mapti_cmd.phys_id = irq_id; | |
901 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 902 | |
6a25ad3a | 903 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
904 | } |
905 | ||
906 | static void its_send_movi(struct its_device *dev, | |
907 | struct its_collection *col, u32 id) | |
908 | { | |
909 | struct its_cmd_desc desc; | |
910 | ||
911 | desc.its_movi_cmd.dev = dev; | |
912 | desc.its_movi_cmd.col = col; | |
591e5bec | 913 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
914 | |
915 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
916 | } | |
917 | ||
918 | static void its_send_discard(struct its_device *dev, u32 id) | |
919 | { | |
920 | struct its_cmd_desc desc; | |
921 | ||
922 | desc.its_discard_cmd.dev = dev; | |
923 | desc.its_discard_cmd.event_id = id; | |
924 | ||
925 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
926 | } | |
927 | ||
928 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
929 | { | |
930 | struct its_cmd_desc desc; | |
931 | ||
932 | desc.its_invall_cmd.col = col; | |
933 | ||
934 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
935 | } | |
c48ed51c | 936 | |
d011e4e6 MZ |
937 | static void its_send_vmapti(struct its_device *dev, u32 id) |
938 | { | |
939 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
940 | struct its_cmd_desc desc; | |
941 | ||
942 | desc.its_vmapti_cmd.vpe = map->vpe; | |
943 | desc.its_vmapti_cmd.dev = dev; | |
944 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
945 | desc.its_vmapti_cmd.event_id = id; | |
946 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
947 | ||
948 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
949 | } | |
950 | ||
951 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
952 | { | |
953 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
954 | struct its_cmd_desc desc; | |
955 | ||
956 | desc.its_vmovi_cmd.vpe = map->vpe; | |
957 | desc.its_vmovi_cmd.dev = dev; | |
958 | desc.its_vmovi_cmd.event_id = id; | |
959 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
960 | ||
961 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
962 | } | |
963 | ||
75fd951b MZ |
964 | static void its_send_vmapp(struct its_node *its, |
965 | struct its_vpe *vpe, bool valid) | |
eb78192b MZ |
966 | { |
967 | struct its_cmd_desc desc; | |
eb78192b MZ |
968 | |
969 | desc.its_vmapp_cmd.vpe = vpe; | |
970 | desc.its_vmapp_cmd.valid = valid; | |
75fd951b | 971 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; |
eb78192b | 972 | |
75fd951b | 973 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); |
eb78192b MZ |
974 | } |
975 | ||
3171a47a MZ |
976 | static void its_send_vmovp(struct its_vpe *vpe) |
977 | { | |
978 | struct its_cmd_desc desc; | |
979 | struct its_node *its; | |
980 | unsigned long flags; | |
981 | int col_id = vpe->col_idx; | |
982 | ||
983 | desc.its_vmovp_cmd.vpe = vpe; | |
984 | desc.its_vmovp_cmd.its_list = (u16)its_list_map; | |
985 | ||
986 | if (!its_list_map) { | |
987 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
988 | desc.its_vmovp_cmd.seq_num = 0; | |
989 | desc.its_vmovp_cmd.col = &its->collections[col_id]; | |
990 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
991 | return; | |
992 | } | |
993 | ||
994 | /* | |
995 | * Yet another marvel of the architecture. If using the | |
996 | * its_list "feature", we need to make sure that all ITSs | |
997 | * receive all VMOVP commands in the same order. The only way | |
998 | * to guarantee this is to make vmovp a serialization point. | |
999 | * | |
1000 | * Wall <-- Head. | |
1001 | */ | |
1002 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1003 | ||
1004 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
1005 | ||
1006 | /* Emit VMOVPs */ | |
1007 | list_for_each_entry(its, &its_nodes, entry) { | |
1008 | if (!its->is_v4) | |
1009 | continue; | |
1010 | ||
2247e1bf MZ |
1011 | if (!vpe->its_vm->vlpi_count[its->list_nr]) |
1012 | continue; | |
1013 | ||
3171a47a MZ |
1014 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1015 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1016 | } | |
1017 | ||
1018 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1019 | } | |
1020 | ||
40619a2e | 1021 | static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) |
eb78192b MZ |
1022 | { |
1023 | struct its_cmd_desc desc; | |
eb78192b MZ |
1024 | |
1025 | desc.its_vinvall_cmd.vpe = vpe; | |
40619a2e | 1026 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); |
eb78192b MZ |
1027 | } |
1028 | ||
c48ed51c MZ |
1029 | /* |
1030 | * irqchip functions - assumes MSI, mostly. | |
1031 | */ | |
1032 | ||
1033 | static inline u32 its_get_event_id(struct irq_data *d) | |
1034 | { | |
1035 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 1036 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
1037 | } |
1038 | ||
015ec038 | 1039 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 1040 | { |
015ec038 | 1041 | irq_hw_number_t hwirq; |
e1a2e201 | 1042 | void *va; |
adcdb94e | 1043 | u8 *cfg; |
c48ed51c | 1044 | |
015ec038 MZ |
1045 | if (irqd_is_forwarded_to_vcpu(d)) { |
1046 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1047 | u32 event = its_get_event_id(d); | |
d4d7b4ad | 1048 | struct its_vlpi_map *map; |
015ec038 | 1049 | |
e1a2e201 | 1050 | va = page_address(its_dev->event_map.vm->vprop_page); |
d4d7b4ad MZ |
1051 | map = &its_dev->event_map.vlpi_maps[event]; |
1052 | hwirq = map->vintid; | |
1053 | ||
1054 | /* Remember the updated property */ | |
1055 | map->properties &= ~clr; | |
1056 | map->properties |= set | LPI_PROP_GROUP1; | |
015ec038 | 1057 | } else { |
e1a2e201 | 1058 | va = gic_rdists->prop_table_va; |
015ec038 MZ |
1059 | hwirq = d->hwirq; |
1060 | } | |
adcdb94e | 1061 | |
e1a2e201 | 1062 | cfg = va + hwirq - 8192; |
adcdb94e | 1063 | *cfg &= ~clr; |
015ec038 | 1064 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1065 | |
1066 | /* | |
1067 | * Make the above write visible to the redistributors. | |
1068 | * And yes, we're flushing exactly: One. Single. Byte. | |
1069 | * Humpf... | |
1070 | */ | |
1071 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1072 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1073 | else |
1074 | dsb(ishst); | |
015ec038 MZ |
1075 | } |
1076 | ||
1077 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) | |
1078 | { | |
1079 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1080 | ||
1081 | lpi_write_config(d, clr, set); | |
adcdb94e | 1082 | its_send_inv(its_dev, its_get_event_id(d)); |
c48ed51c MZ |
1083 | } |
1084 | ||
015ec038 MZ |
1085 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1086 | { | |
1087 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1088 | u32 event = its_get_event_id(d); | |
1089 | ||
1090 | if (its_dev->event_map.vlpi_maps[event].db_enabled == enable) | |
1091 | return; | |
1092 | ||
1093 | its_dev->event_map.vlpi_maps[event].db_enabled = enable; | |
1094 | ||
1095 | /* | |
1096 | * More fun with the architecture: | |
1097 | * | |
1098 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1099 | * value or to 1023, depending on the enable bit. But that | |
1100 | * would be issueing a mapping for an /existing/ DevID+EventID | |
1101 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
1102 | * to the /same/ vPE, using this opportunity to adjust the | |
1103 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1104 | */ | |
1105 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1106 | } |
1107 | ||
1108 | static void its_mask_irq(struct irq_data *d) | |
1109 | { | |
015ec038 MZ |
1110 | if (irqd_is_forwarded_to_vcpu(d)) |
1111 | its_vlpi_set_doorbell(d, false); | |
1112 | ||
adcdb94e | 1113 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1114 | } |
1115 | ||
1116 | static void its_unmask_irq(struct irq_data *d) | |
1117 | { | |
015ec038 MZ |
1118 | if (irqd_is_forwarded_to_vcpu(d)) |
1119 | its_vlpi_set_doorbell(d, true); | |
1120 | ||
adcdb94e | 1121 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1122 | } |
1123 | ||
c48ed51c MZ |
1124 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1125 | bool force) | |
1126 | { | |
fbf8f40e GK |
1127 | unsigned int cpu; |
1128 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
1129 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1130 | struct its_collection *target_col; | |
1131 | u32 id = its_get_event_id(d); | |
1132 | ||
015ec038 MZ |
1133 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1134 | if (irqd_is_forwarded_to_vcpu(d)) | |
1135 | return -EINVAL; | |
1136 | ||
fbf8f40e GK |
1137 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
1138 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1139 | if (its_dev->its->numa_node >= 0) { | |
1140 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
1141 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
1142 | return -EINVAL; | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
1147 | ||
c48ed51c MZ |
1148 | if (cpu >= nr_cpu_ids) |
1149 | return -EINVAL; | |
1150 | ||
8b8d94a7 M |
1151 | /* don't set the affinity when the target cpu is same as current one */ |
1152 | if (cpu != its_dev->event_map.col_map[id]) { | |
1153 | target_col = &its_dev->its->collections[cpu]; | |
1154 | its_send_movi(its_dev, target_col, id); | |
1155 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1156 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1157 | } |
c48ed51c MZ |
1158 | |
1159 | return IRQ_SET_MASK_OK_DONE; | |
1160 | } | |
1161 | ||
558b0165 AB |
1162 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1163 | { | |
1164 | struct its_node *its = its_dev->its; | |
1165 | ||
1166 | return its->phys_base + GITS_TRANSLATER; | |
1167 | } | |
1168 | ||
b48ac83d MZ |
1169 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1170 | { | |
1171 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1172 | struct its_node *its; | |
1173 | u64 addr; | |
1174 | ||
1175 | its = its_dev->its; | |
558b0165 | 1176 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1177 | |
b11283eb VM |
1178 | msg->address_lo = lower_32_bits(addr); |
1179 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1180 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
1181 | |
1182 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
1183 | } |
1184 | ||
8d85dced MZ |
1185 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1186 | enum irqchip_irq_state which, | |
1187 | bool state) | |
1188 | { | |
1189 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1190 | u32 event = its_get_event_id(d); | |
1191 | ||
1192 | if (which != IRQCHIP_STATE_PENDING) | |
1193 | return -EINVAL; | |
1194 | ||
1195 | if (state) | |
1196 | its_send_int(its_dev, event); | |
1197 | else | |
1198 | its_send_clear(its_dev, event); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
2247e1bf MZ |
1203 | static void its_map_vm(struct its_node *its, struct its_vm *vm) |
1204 | { | |
1205 | unsigned long flags; | |
1206 | ||
1207 | /* Not using the ITS list? Everything is always mapped. */ | |
1208 | if (!its_list_map) | |
1209 | return; | |
1210 | ||
1211 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1212 | ||
1213 | /* | |
1214 | * If the VM wasn't mapped yet, iterate over the vpes and get | |
1215 | * them mapped now. | |
1216 | */ | |
1217 | vm->vlpi_count[its->list_nr]++; | |
1218 | ||
1219 | if (vm->vlpi_count[its->list_nr] == 1) { | |
1220 | int i; | |
1221 | ||
1222 | for (i = 0; i < vm->nr_vpes; i++) { | |
1223 | struct its_vpe *vpe = vm->vpes[i]; | |
44c4c25e | 1224 | struct irq_data *d = irq_get_irq_data(vpe->irq); |
2247e1bf MZ |
1225 | |
1226 | /* Map the VPE to the first possible CPU */ | |
1227 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
1228 | its_send_vmapp(its, vpe, true); | |
1229 | its_send_vinvall(its, vpe); | |
44c4c25e | 1230 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
2247e1bf MZ |
1231 | } |
1232 | } | |
1233 | ||
1234 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1235 | } | |
1236 | ||
1237 | static void its_unmap_vm(struct its_node *its, struct its_vm *vm) | |
1238 | { | |
1239 | unsigned long flags; | |
1240 | ||
1241 | /* Not using the ITS list? Everything is always mapped. */ | |
1242 | if (!its_list_map) | |
1243 | return; | |
1244 | ||
1245 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1246 | ||
1247 | if (!--vm->vlpi_count[its->list_nr]) { | |
1248 | int i; | |
1249 | ||
1250 | for (i = 0; i < vm->nr_vpes; i++) | |
1251 | its_send_vmapp(its, vm->vpes[i], false); | |
1252 | } | |
1253 | ||
1254 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1255 | } | |
1256 | ||
d011e4e6 MZ |
1257 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1258 | { | |
1259 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1260 | u32 event = its_get_event_id(d); | |
1261 | int ret = 0; | |
1262 | ||
1263 | if (!info->map) | |
1264 | return -EINVAL; | |
1265 | ||
1266 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1267 | ||
1268 | if (!its_dev->event_map.vm) { | |
1269 | struct its_vlpi_map *maps; | |
1270 | ||
6396bb22 | 1271 | maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), |
d011e4e6 MZ |
1272 | GFP_KERNEL); |
1273 | if (!maps) { | |
1274 | ret = -ENOMEM; | |
1275 | goto out; | |
1276 | } | |
1277 | ||
1278 | its_dev->event_map.vm = info->map->vm; | |
1279 | its_dev->event_map.vlpi_maps = maps; | |
1280 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1281 | ret = -EINVAL; | |
1282 | goto out; | |
1283 | } | |
1284 | ||
1285 | /* Get our private copy of the mapping information */ | |
1286 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1287 | ||
1288 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1289 | /* Already mapped, move it around */ | |
1290 | its_send_vmovi(its_dev, event); | |
1291 | } else { | |
2247e1bf MZ |
1292 | /* Ensure all the VPEs are mapped on this ITS */ |
1293 | its_map_vm(its_dev->its, info->map->vm); | |
1294 | ||
d4d7b4ad MZ |
1295 | /* |
1296 | * Flag the interrupt as forwarded so that we can | |
1297 | * start poking the virtual property table. | |
1298 | */ | |
1299 | irqd_set_forwarded_to_vcpu(d); | |
1300 | ||
1301 | /* Write out the property to the prop table */ | |
1302 | lpi_write_config(d, 0xff, info->map->properties); | |
1303 | ||
d011e4e6 MZ |
1304 | /* Drop the physical mapping */ |
1305 | its_send_discard(its_dev, event); | |
1306 | ||
1307 | /* and install the virtual one */ | |
1308 | its_send_vmapti(its_dev, event); | |
d011e4e6 MZ |
1309 | |
1310 | /* Increment the number of VLPIs */ | |
1311 | its_dev->event_map.nr_vlpis++; | |
1312 | } | |
1313 | ||
1314 | out: | |
1315 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1320 | { | |
1321 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1322 | u32 event = its_get_event_id(d); | |
1323 | int ret = 0; | |
1324 | ||
1325 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1326 | ||
1327 | if (!its_dev->event_map.vm || | |
1328 | !its_dev->event_map.vlpi_maps[event].vm) { | |
1329 | ret = -EINVAL; | |
1330 | goto out; | |
1331 | } | |
1332 | ||
1333 | /* Copy our mapping information to the incoming request */ | |
1334 | *info->map = its_dev->event_map.vlpi_maps[event]; | |
1335 | ||
1336 | out: | |
1337 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1338 | return ret; | |
1339 | } | |
1340 | ||
1341 | static int its_vlpi_unmap(struct irq_data *d) | |
1342 | { | |
1343 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1344 | u32 event = its_get_event_id(d); | |
1345 | int ret = 0; | |
1346 | ||
1347 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1348 | ||
1349 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1350 | ret = -EINVAL; | |
1351 | goto out; | |
1352 | } | |
1353 | ||
1354 | /* Drop the virtual mapping */ | |
1355 | its_send_discard(its_dev, event); | |
1356 | ||
1357 | /* and restore the physical one */ | |
1358 | irqd_clr_forwarded_to_vcpu(d); | |
1359 | its_send_mapti(its_dev, d->hwirq, event); | |
1360 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1361 | LPI_PROP_ENABLED | | |
1362 | LPI_PROP_GROUP1)); | |
1363 | ||
2247e1bf MZ |
1364 | /* Potentially unmap the VM from this ITS */ |
1365 | its_unmap_vm(its_dev->its, its_dev->event_map.vm); | |
1366 | ||
d011e4e6 MZ |
1367 | /* |
1368 | * Drop the refcount and make the device available again if | |
1369 | * this was the last VLPI. | |
1370 | */ | |
1371 | if (!--its_dev->event_map.nr_vlpis) { | |
1372 | its_dev->event_map.vm = NULL; | |
1373 | kfree(its_dev->event_map.vlpi_maps); | |
1374 | } | |
1375 | ||
1376 | out: | |
1377 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1378 | return ret; | |
1379 | } | |
1380 | ||
015ec038 MZ |
1381 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1382 | { | |
1383 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1384 | ||
1385 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1386 | return -EINVAL; | |
1387 | ||
1388 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1389 | lpi_update_config(d, 0xff, info->config); | |
1390 | else | |
1391 | lpi_write_config(d, 0xff, info->config); | |
1392 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
c808eea8 MZ |
1397 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1398 | { | |
1399 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1400 | struct its_cmd_info *info = vcpu_info; | |
1401 | ||
1402 | /* Need a v4 ITS */ | |
d011e4e6 | 1403 | if (!its_dev->its->is_v4) |
c808eea8 MZ |
1404 | return -EINVAL; |
1405 | ||
d011e4e6 MZ |
1406 | /* Unmap request? */ |
1407 | if (!info) | |
1408 | return its_vlpi_unmap(d); | |
1409 | ||
c808eea8 MZ |
1410 | switch (info->cmd_type) { |
1411 | case MAP_VLPI: | |
d011e4e6 | 1412 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1413 | |
1414 | case GET_VLPI: | |
d011e4e6 | 1415 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1416 | |
1417 | case PROP_UPDATE_VLPI: | |
1418 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1419 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1420 | |
1421 | default: | |
1422 | return -EINVAL; | |
1423 | } | |
1424 | } | |
1425 | ||
c48ed51c MZ |
1426 | static struct irq_chip its_irq_chip = { |
1427 | .name = "ITS", | |
1428 | .irq_mask = its_mask_irq, | |
1429 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1430 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1431 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1432 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1433 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1434 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1435 | }; |
1436 | ||
880cb3cd | 1437 | |
bf9529f8 MZ |
1438 | /* |
1439 | * How we allocate LPIs: | |
1440 | * | |
880cb3cd MZ |
1441 | * lpi_range_list contains ranges of LPIs that are to available to |
1442 | * allocate from. To allocate LPIs, just pick the first range that | |
1443 | * fits the required allocation, and reduce it by the required | |
1444 | * amount. Once empty, remove the range from the list. | |
1445 | * | |
1446 | * To free a range of LPIs, add a free range to the list, sort it and | |
1447 | * merge the result if the new range happens to be adjacent to an | |
1448 | * already free block. | |
bf9529f8 | 1449 | * |
880cb3cd MZ |
1450 | * The consequence of the above is that allocation is cost is low, but |
1451 | * freeing is expensive. We assumes that freeing rarely occurs. | |
1452 | */ | |
4cb205c0 | 1453 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
880cb3cd | 1454 | |
880cb3cd MZ |
1455 | static DEFINE_MUTEX(lpi_range_lock); |
1456 | static LIST_HEAD(lpi_range_list); | |
1457 | ||
1458 | struct lpi_range { | |
1459 | struct list_head entry; | |
1460 | u32 base_id; | |
1461 | u32 span; | |
1462 | }; | |
bf9529f8 | 1463 | |
880cb3cd | 1464 | static struct lpi_range *mk_lpi_range(u32 base, u32 span) |
bf9529f8 | 1465 | { |
880cb3cd MZ |
1466 | struct lpi_range *range; |
1467 | ||
1468 | range = kzalloc(sizeof(*range), GFP_KERNEL); | |
1469 | if (range) { | |
1470 | INIT_LIST_HEAD(&range->entry); | |
1471 | range->base_id = base; | |
1472 | range->span = span; | |
1473 | } | |
1474 | ||
1475 | return range; | |
bf9529f8 MZ |
1476 | } |
1477 | ||
880cb3cd | 1478 | static int lpi_range_cmp(void *priv, struct list_head *a, struct list_head *b) |
bf9529f8 | 1479 | { |
880cb3cd MZ |
1480 | struct lpi_range *ra, *rb; |
1481 | ||
1482 | ra = container_of(a, struct lpi_range, entry); | |
1483 | rb = container_of(b, struct lpi_range, entry); | |
1484 | ||
1485 | return rb->base_id - ra->base_id; | |
bf9529f8 MZ |
1486 | } |
1487 | ||
880cb3cd | 1488 | static void merge_lpi_ranges(void) |
bf9529f8 | 1489 | { |
880cb3cd | 1490 | struct lpi_range *range, *tmp; |
bf9529f8 | 1491 | |
880cb3cd MZ |
1492 | list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) { |
1493 | if (!list_is_last(&range->entry, &lpi_range_list) && | |
1494 | (tmp->base_id == (range->base_id + range->span))) { | |
1495 | tmp->base_id = range->base_id; | |
1496 | tmp->span += range->span; | |
1497 | list_del(&range->entry); | |
1498 | kfree(range); | |
1499 | } | |
bf9529f8 | 1500 | } |
880cb3cd | 1501 | } |
bf9529f8 | 1502 | |
880cb3cd MZ |
1503 | static int alloc_lpi_range(u32 nr_lpis, u32 *base) |
1504 | { | |
1505 | struct lpi_range *range, *tmp; | |
1506 | int err = -ENOSPC; | |
1507 | ||
1508 | mutex_lock(&lpi_range_lock); | |
1509 | ||
1510 | list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) { | |
1511 | if (range->span >= nr_lpis) { | |
1512 | *base = range->base_id; | |
1513 | range->base_id += nr_lpis; | |
1514 | range->span -= nr_lpis; | |
1515 | ||
1516 | if (range->span == 0) { | |
1517 | list_del(&range->entry); | |
1518 | kfree(range); | |
1519 | } | |
1520 | ||
1521 | err = 0; | |
1522 | break; | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | mutex_unlock(&lpi_range_lock); | |
1527 | ||
1528 | pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); | |
1529 | return err; | |
bf9529f8 MZ |
1530 | } |
1531 | ||
880cb3cd | 1532 | static int free_lpi_range(u32 base, u32 nr_lpis) |
bf9529f8 | 1533 | { |
880cb3cd MZ |
1534 | struct lpi_range *new; |
1535 | int err = 0; | |
1536 | ||
1537 | mutex_lock(&lpi_range_lock); | |
1538 | ||
1539 | new = mk_lpi_range(base, nr_lpis); | |
1540 | if (!new) { | |
1541 | err = -ENOMEM; | |
1542 | goto out; | |
1543 | } | |
1544 | ||
1545 | list_add(&new->entry, &lpi_range_list); | |
1546 | list_sort(NULL, &lpi_range_list, lpi_range_cmp); | |
1547 | merge_lpi_ranges(); | |
1548 | out: | |
1549 | mutex_unlock(&lpi_range_lock); | |
1550 | return err; | |
1551 | } | |
1552 | ||
1553 | static int __init its_lpi_init(u32 id_bits) | |
1554 | { | |
1555 | u32 lpis = (1UL << id_bits) - 8192; | |
12b2905a | 1556 | u32 numlpis; |
880cb3cd MZ |
1557 | int err; |
1558 | ||
12b2905a MZ |
1559 | numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); |
1560 | ||
1561 | if (numlpis > 2 && !WARN_ON(numlpis > lpis)) { | |
1562 | lpis = numlpis; | |
1563 | pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", | |
1564 | lpis); | |
1565 | } | |
1566 | ||
880cb3cd MZ |
1567 | /* |
1568 | * Initializing the allocator is just the same as freeing the | |
1569 | * full range of LPIs. | |
1570 | */ | |
1571 | err = free_lpi_range(8192, lpis); | |
1572 | pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); | |
1573 | return err; | |
1574 | } | |
bf9529f8 | 1575 | |
38dd7c49 | 1576 | static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids) |
880cb3cd MZ |
1577 | { |
1578 | unsigned long *bitmap = NULL; | |
1579 | int err = 0; | |
bf9529f8 MZ |
1580 | |
1581 | do { | |
38dd7c49 | 1582 | err = alloc_lpi_range(nr_irqs, base); |
880cb3cd | 1583 | if (!err) |
bf9529f8 MZ |
1584 | break; |
1585 | ||
38dd7c49 MZ |
1586 | nr_irqs /= 2; |
1587 | } while (nr_irqs > 0); | |
bf9529f8 | 1588 | |
45725e0f MZ |
1589 | if (!nr_irqs) |
1590 | err = -ENOSPC; | |
1591 | ||
880cb3cd | 1592 | if (err) |
bf9529f8 MZ |
1593 | goto out; |
1594 | ||
38dd7c49 | 1595 | bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC); |
bf9529f8 MZ |
1596 | if (!bitmap) |
1597 | goto out; | |
1598 | ||
38dd7c49 | 1599 | *nr_ids = nr_irqs; |
bf9529f8 MZ |
1600 | |
1601 | out: | |
c8415b94 MZ |
1602 | if (!bitmap) |
1603 | *base = *nr_ids = 0; | |
1604 | ||
bf9529f8 MZ |
1605 | return bitmap; |
1606 | } | |
1607 | ||
38dd7c49 | 1608 | static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids) |
bf9529f8 | 1609 | { |
880cb3cd | 1610 | WARN_ON(free_lpi_range(base, nr_ids)); |
cf2be8ba | 1611 | kfree(bitmap); |
bf9529f8 | 1612 | } |
1ac19ca6 | 1613 | |
053be485 MZ |
1614 | static void gic_reset_prop_table(void *va) |
1615 | { | |
1616 | /* Priority 0xa0, Group-1, disabled */ | |
1617 | memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ); | |
1618 | ||
1619 | /* Make sure the GIC will observe the written configuration */ | |
1620 | gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ); | |
1621 | } | |
1622 | ||
0e5ccf91 MZ |
1623 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
1624 | { | |
1625 | struct page *prop_page; | |
1ac19ca6 | 1626 | |
0e5ccf91 MZ |
1627 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
1628 | if (!prop_page) | |
1629 | return NULL; | |
1630 | ||
053be485 | 1631 | gic_reset_prop_table(page_address(prop_page)); |
0e5ccf91 MZ |
1632 | |
1633 | return prop_page; | |
1634 | } | |
1635 | ||
7d75bbb4 MZ |
1636 | static void its_free_prop_table(struct page *prop_page) |
1637 | { | |
1638 | free_pages((unsigned long)page_address(prop_page), | |
1639 | get_order(LPI_PROPBASE_SZ)); | |
1640 | } | |
1ac19ca6 | 1641 | |
5e2c9f9a MZ |
1642 | static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) |
1643 | { | |
1644 | phys_addr_t start, end, addr_end; | |
1645 | u64 i; | |
1646 | ||
1647 | /* | |
1648 | * We don't bother checking for a kdump kernel as by | |
1649 | * construction, the LPI tables are out of this kernel's | |
1650 | * memory map. | |
1651 | */ | |
1652 | if (is_kdump_kernel()) | |
1653 | return true; | |
1654 | ||
1655 | addr_end = addr + size - 1; | |
1656 | ||
1657 | for_each_reserved_mem_region(i, &start, &end) { | |
1658 | if (addr >= start && addr_end <= end) | |
1659 | return true; | |
1660 | } | |
1661 | ||
1662 | /* Not found, not a good sign... */ | |
1663 | pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n", | |
1664 | &addr, &addr_end); | |
1665 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
1666 | return false; | |
1667 | } | |
1668 | ||
3fb68fae MZ |
1669 | static int gic_reserve_range(phys_addr_t addr, unsigned long size) |
1670 | { | |
1671 | if (efi_enabled(EFI_CONFIG_TABLES)) | |
1672 | return efi_mem_reserve_persistent(addr, size); | |
1673 | ||
1674 | return 0; | |
1675 | } | |
1676 | ||
11e37d35 | 1677 | static int __init its_setup_lpi_prop_table(void) |
1ac19ca6 | 1678 | { |
c440a9d9 MZ |
1679 | if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { |
1680 | u64 val; | |
1ac19ca6 | 1681 | |
c440a9d9 MZ |
1682 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); |
1683 | lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1; | |
1ac19ca6 | 1684 | |
c440a9d9 MZ |
1685 | gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); |
1686 | gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, | |
1687 | LPI_PROPBASE_SZ, | |
1688 | MEMREMAP_WB); | |
1689 | gic_reset_prop_table(gic_rdists->prop_table_va); | |
1690 | } else { | |
1691 | struct page *page; | |
1692 | ||
1693 | lpi_id_bits = min_t(u32, | |
1694 | GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), | |
1695 | ITS_MAX_LPI_NRBITS); | |
1696 | page = its_allocate_prop_table(GFP_NOWAIT); | |
1697 | if (!page) { | |
1698 | pr_err("Failed to allocate PROPBASE\n"); | |
1699 | return -ENOMEM; | |
1700 | } | |
1701 | ||
1702 | gic_rdists->prop_table_pa = page_to_phys(page); | |
1703 | gic_rdists->prop_table_va = page_address(page); | |
3fb68fae MZ |
1704 | WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, |
1705 | LPI_PROPBASE_SZ)); | |
c440a9d9 | 1706 | } |
e1a2e201 MZ |
1707 | |
1708 | pr_info("GICv3: using LPI property table @%pa\n", | |
1709 | &gic_rdists->prop_table_pa); | |
1ac19ca6 | 1710 | |
6c31e123 | 1711 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
1712 | } |
1713 | ||
1714 | static const char *its_base_type_string[] = { | |
1715 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
1716 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 1717 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
1718 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
1719 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
1720 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
1721 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
1722 | }; | |
1723 | ||
2d81d425 SD |
1724 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
1725 | { | |
1726 | u32 idx = baser - its->tables; | |
1727 | ||
0968a619 | 1728 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1729 | } |
1730 | ||
1731 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
1732 | u64 val) | |
1733 | { | |
1734 | u32 idx = baser - its->tables; | |
1735 | ||
0968a619 | 1736 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1737 | baser->val = its_read_baser(its, baser); |
1738 | } | |
1739 | ||
9347359a | 1740 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
1741 | u64 cache, u64 shr, u32 psz, u32 order, |
1742 | bool indirect) | |
9347359a SD |
1743 | { |
1744 | u64 val = its_read_baser(its, baser); | |
1745 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
1746 | u64 type = GITS_BASER_TYPE(val); | |
30ae9610 | 1747 | u64 baser_phys, tmp; |
9347359a SD |
1748 | u32 alloc_pages; |
1749 | void *base; | |
9347359a SD |
1750 | |
1751 | retry_alloc_baser: | |
1752 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
1753 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
1754 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
1755 | &its->phys_base, its_base_type_string[type], | |
1756 | alloc_pages, GITS_BASER_PAGES_MAX); | |
1757 | alloc_pages = GITS_BASER_PAGES_MAX; | |
1758 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
1759 | } | |
1760 | ||
1761 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
1762 | if (!base) | |
1763 | return -ENOMEM; | |
1764 | ||
30ae9610 SD |
1765 | baser_phys = virt_to_phys(base); |
1766 | ||
1767 | /* Check if the physical address of the memory is above 48bits */ | |
1768 | if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) { | |
1769 | ||
1770 | /* 52bit PA is supported only when PageSize=64K */ | |
1771 | if (psz != SZ_64K) { | |
1772 | pr_err("ITS: no 52bit PA support when psz=%d\n", psz); | |
1773 | free_pages((unsigned long)base, order); | |
1774 | return -ENXIO; | |
1775 | } | |
1776 | ||
1777 | /* Convert 52bit PA to 48bit field */ | |
1778 | baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys); | |
1779 | } | |
1780 | ||
9347359a | 1781 | retry_baser: |
30ae9610 | 1782 | val = (baser_phys | |
9347359a SD |
1783 | (type << GITS_BASER_TYPE_SHIFT) | |
1784 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
1785 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
1786 | cache | | |
1787 | shr | | |
1788 | GITS_BASER_VALID); | |
1789 | ||
3faf24ea SD |
1790 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
1791 | ||
9347359a SD |
1792 | switch (psz) { |
1793 | case SZ_4K: | |
1794 | val |= GITS_BASER_PAGE_SIZE_4K; | |
1795 | break; | |
1796 | case SZ_16K: | |
1797 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1798 | break; | |
1799 | case SZ_64K: | |
1800 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1801 | break; | |
1802 | } | |
1803 | ||
1804 | its_write_baser(its, baser, val); | |
1805 | tmp = baser->val; | |
1806 | ||
1807 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1808 | /* | |
1809 | * Shareability didn't stick. Just use | |
1810 | * whatever the read reported, which is likely | |
1811 | * to be the only thing this redistributor | |
1812 | * supports. If that's zero, make it | |
1813 | * non-cacheable as well. | |
1814 | */ | |
1815 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
1816 | if (!shr) { | |
1817 | cache = GITS_BASER_nC; | |
328191c0 | 1818 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
1819 | } |
1820 | goto retry_baser; | |
1821 | } | |
1822 | ||
1823 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
1824 | /* | |
1825 | * Page size didn't stick. Let's try a smaller | |
1826 | * size and retry. If we reach 4K, then | |
1827 | * something is horribly wrong... | |
1828 | */ | |
1829 | free_pages((unsigned long)base, order); | |
1830 | baser->base = NULL; | |
1831 | ||
1832 | switch (psz) { | |
1833 | case SZ_16K: | |
1834 | psz = SZ_4K; | |
1835 | goto retry_alloc_baser; | |
1836 | case SZ_64K: | |
1837 | psz = SZ_16K; | |
1838 | goto retry_alloc_baser; | |
1839 | } | |
1840 | } | |
1841 | ||
1842 | if (val != tmp) { | |
b11283eb | 1843 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 1844 | &its->phys_base, its_base_type_string[type], |
b11283eb | 1845 | val, tmp); |
9347359a SD |
1846 | free_pages((unsigned long)base, order); |
1847 | return -ENXIO; | |
1848 | } | |
1849 | ||
1850 | baser->order = order; | |
1851 | baser->base = base; | |
1852 | baser->psz = psz; | |
3faf24ea | 1853 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 1854 | |
3faf24ea | 1855 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 1856 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
1857 | its_base_type_string[type], |
1858 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 1859 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
1860 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
1861 | ||
1862 | return 0; | |
1863 | } | |
1864 | ||
4cacac57 MZ |
1865 | static bool its_parse_indirect_baser(struct its_node *its, |
1866 | struct its_baser *baser, | |
32bd44dc | 1867 | u32 psz, u32 *order, u32 ids) |
4b75c459 | 1868 | { |
4cacac57 MZ |
1869 | u64 tmp = its_read_baser(its, baser); |
1870 | u64 type = GITS_BASER_TYPE(tmp); | |
1871 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 1872 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 | 1873 | u32 new_order = *order; |
3faf24ea SD |
1874 | bool indirect = false; |
1875 | ||
1876 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
1877 | if ((esz << ids) > (psz * 2)) { | |
1878 | /* | |
1879 | * Find out whether hw supports a single or two-level table by | |
1880 | * table by reading bit at offset '62' after writing '1' to it. | |
1881 | */ | |
1882 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
1883 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
1884 | ||
1885 | if (indirect) { | |
1886 | /* | |
1887 | * The size of the lvl2 table is equal to ITS page size | |
1888 | * which is 'psz'. For computing lvl1 table size, | |
1889 | * subtract ID bits that sparse lvl2 table from 'ids' | |
1890 | * which is reported by ITS hardware times lvl1 table | |
1891 | * entry size. | |
1892 | */ | |
d524eaa2 | 1893 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
1894 | esz = GITS_LVL1_ENTRY_SIZE; |
1895 | } | |
1896 | } | |
4b75c459 SD |
1897 | |
1898 | /* | |
1899 | * Allocate as many entries as required to fit the | |
1900 | * range of device IDs that the ITS can grok... The ID | |
1901 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1902 | * massive waste of memory if two-level device table |
1903 | * feature is not supported by hardware. | |
4b75c459 SD |
1904 | */ |
1905 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1906 | if (new_order >= MAX_ORDER) { | |
1907 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1908 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4cacac57 MZ |
1909 | pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n", |
1910 | &its->phys_base, its_base_type_string[type], | |
1911 | its->device_ids, ids); | |
4b75c459 SD |
1912 | } |
1913 | ||
1914 | *order = new_order; | |
3faf24ea SD |
1915 | |
1916 | return indirect; | |
4b75c459 SD |
1917 | } |
1918 | ||
1ac19ca6 MZ |
1919 | static void its_free_tables(struct its_node *its) |
1920 | { | |
1921 | int i; | |
1922 | ||
1923 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1924 | if (its->tables[i].base) { |
1925 | free_pages((unsigned long)its->tables[i].base, | |
1926 | its->tables[i].order); | |
1927 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1928 | } |
1929 | } | |
1930 | } | |
1931 | ||
0e0b0f69 | 1932 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1933 | { |
1ac19ca6 | 1934 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1935 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1936 | u32 psz = SZ_64K; |
1937 | int err, i; | |
94100970 | 1938 | |
fa150019 AB |
1939 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
1940 | /* erratum 24313: ignore memory access type */ | |
1941 | cache = GITS_BASER_nCnB; | |
466b7d16 | 1942 | |
1ac19ca6 | 1943 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1944 | struct its_baser *baser = its->tables + i; |
1945 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1946 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1947 | u32 order = get_order(psz); |
3faf24ea | 1948 | bool indirect = false; |
1ac19ca6 | 1949 | |
4cacac57 MZ |
1950 | switch (type) { |
1951 | case GITS_BASER_TYPE_NONE: | |
1ac19ca6 MZ |
1952 | continue; |
1953 | ||
4cacac57 | 1954 | case GITS_BASER_TYPE_DEVICE: |
32bd44dc SD |
1955 | indirect = its_parse_indirect_baser(its, baser, |
1956 | psz, &order, | |
1957 | its->device_ids); | |
4cacac57 MZ |
1958 | case GITS_BASER_TYPE_VCPU: |
1959 | indirect = its_parse_indirect_baser(its, baser, | |
32bd44dc SD |
1960 | psz, &order, |
1961 | ITS_MAX_VPEID_BITS); | |
4cacac57 MZ |
1962 | break; |
1963 | } | |
f54b97ed | 1964 | |
3faf24ea | 1965 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1966 | if (err < 0) { |
1967 | its_free_tables(its); | |
1968 | return err; | |
1ac19ca6 MZ |
1969 | } |
1970 | ||
9347359a SD |
1971 | /* Update settings which will be used for next BASERn */ |
1972 | psz = baser->psz; | |
1973 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1974 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1975 | } |
1976 | ||
1977 | return 0; | |
1ac19ca6 MZ |
1978 | } |
1979 | ||
1980 | static int its_alloc_collections(struct its_node *its) | |
1981 | { | |
83559b47 MZ |
1982 | int i; |
1983 | ||
6396bb22 | 1984 | its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), |
1ac19ca6 MZ |
1985 | GFP_KERNEL); |
1986 | if (!its->collections) | |
1987 | return -ENOMEM; | |
1988 | ||
83559b47 MZ |
1989 | for (i = 0; i < nr_cpu_ids; i++) |
1990 | its->collections[i].target_address = ~0ULL; | |
1991 | ||
1ac19ca6 MZ |
1992 | return 0; |
1993 | } | |
1994 | ||
7c297a2d MZ |
1995 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
1996 | { | |
1997 | struct page *pend_page; | |
adaab500 | 1998 | |
7c297a2d | 1999 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, |
adaab500 | 2000 | get_order(LPI_PENDBASE_SZ)); |
7c297a2d MZ |
2001 | if (!pend_page) |
2002 | return NULL; | |
2003 | ||
2004 | /* Make sure the GIC will observe the zero-ed page */ | |
2005 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
2006 | ||
2007 | return pend_page; | |
2008 | } | |
2009 | ||
7d75bbb4 MZ |
2010 | static void its_free_pending_table(struct page *pt) |
2011 | { | |
adaab500 | 2012 | free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); |
7d75bbb4 MZ |
2013 | } |
2014 | ||
c6e2ccb6 | 2015 | /* |
5e2c9f9a MZ |
2016 | * Booting with kdump and LPIs enabled is generally fine. Any other |
2017 | * case is wrong in the absence of firmware/EFI support. | |
c6e2ccb6 | 2018 | */ |
c440a9d9 MZ |
2019 | static bool enabled_lpis_allowed(void) |
2020 | { | |
5e2c9f9a MZ |
2021 | phys_addr_t addr; |
2022 | u64 val; | |
c6e2ccb6 | 2023 | |
5e2c9f9a MZ |
2024 | /* Check whether the property table is in a reserved region */ |
2025 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); | |
2026 | addr = val & GENMASK_ULL(51, 12); | |
2027 | ||
2028 | return gic_check_reserved_range(addr, LPI_PROPBASE_SZ); | |
c440a9d9 MZ |
2029 | } |
2030 | ||
11e37d35 | 2031 | static int __init allocate_lpi_tables(void) |
1ac19ca6 | 2032 | { |
c440a9d9 | 2033 | u64 val; |
11e37d35 | 2034 | int err, cpu; |
1ac19ca6 | 2035 | |
c440a9d9 MZ |
2036 | /* |
2037 | * If LPIs are enabled while we run this from the boot CPU, | |
2038 | * flag the RD tables as pre-allocated if the stars do align. | |
2039 | */ | |
2040 | val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); | |
2041 | if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { | |
2042 | gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | | |
2043 | RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING); | |
2044 | pr_info("GICv3: Using preallocated redistributor tables\n"); | |
2045 | } | |
2046 | ||
11e37d35 MZ |
2047 | err = its_setup_lpi_prop_table(); |
2048 | if (err) | |
2049 | return err; | |
2050 | ||
2051 | /* | |
2052 | * We allocate all the pending tables anyway, as we may have a | |
2053 | * mix of RDs that have had LPIs enabled, and some that | |
2054 | * don't. We'll free the unused ones as each CPU comes online. | |
2055 | */ | |
2056 | for_each_possible_cpu(cpu) { | |
2057 | struct page *pend_page; | |
7c297a2d MZ |
2058 | |
2059 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 | 2060 | if (!pend_page) { |
11e37d35 MZ |
2061 | pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu); |
2062 | return -ENOMEM; | |
1ac19ca6 MZ |
2063 | } |
2064 | ||
11e37d35 | 2065 | gic_data_rdist_cpu(cpu)->pend_page = pend_page; |
1ac19ca6 MZ |
2066 | } |
2067 | ||
11e37d35 MZ |
2068 | return 0; |
2069 | } | |
2070 | ||
6479450f HG |
2071 | static u64 its_clear_vpend_valid(void __iomem *vlpi_base) |
2072 | { | |
2073 | u32 count = 1000000; /* 1s! */ | |
2074 | bool clean; | |
2075 | u64 val; | |
2076 | ||
2077 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2078 | val &= ~GICR_VPENDBASER_Valid; | |
2079 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2080 | ||
2081 | do { | |
2082 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2083 | clean = !(val & GICR_VPENDBASER_Dirty); | |
2084 | if (!clean) { | |
2085 | count--; | |
2086 | cpu_relax(); | |
2087 | udelay(1); | |
2088 | } | |
2089 | } while (!clean && count); | |
2090 | ||
2091 | return val; | |
2092 | } | |
2093 | ||
11e37d35 MZ |
2094 | static void its_cpu_init_lpis(void) |
2095 | { | |
2096 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
2097 | struct page *pend_page; | |
2098 | phys_addr_t paddr; | |
2099 | u64 val, tmp; | |
2100 | ||
2101 | if (gic_data_rdist()->lpi_enabled) | |
2102 | return; | |
2103 | ||
c440a9d9 MZ |
2104 | val = readl_relaxed(rbase + GICR_CTLR); |
2105 | if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && | |
2106 | (val & GICR_CTLR_ENABLE_LPIS)) { | |
f842ca8e MZ |
2107 | /* |
2108 | * Check that we get the same property table on all | |
2109 | * RDs. If we don't, this is hopeless. | |
2110 | */ | |
2111 | paddr = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
2112 | paddr &= GENMASK_ULL(51, 12); | |
2113 | if (WARN_ON(gic_rdists->prop_table_pa != paddr)) | |
2114 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
2115 | ||
c440a9d9 MZ |
2116 | paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER); |
2117 | paddr &= GENMASK_ULL(51, 16); | |
2118 | ||
5e2c9f9a | 2119 | WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ)); |
c440a9d9 MZ |
2120 | its_free_pending_table(gic_data_rdist()->pend_page); |
2121 | gic_data_rdist()->pend_page = NULL; | |
2122 | ||
2123 | goto out; | |
2124 | } | |
2125 | ||
11e37d35 MZ |
2126 | pend_page = gic_data_rdist()->pend_page; |
2127 | paddr = page_to_phys(pend_page); | |
3fb68fae | 2128 | WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ)); |
11e37d35 | 2129 | |
1ac19ca6 | 2130 | /* set PROPBASE */ |
e1a2e201 | 2131 | val = (gic_rdists->prop_table_pa | |
1ac19ca6 | 2132 | GICR_PROPBASER_InnerShareable | |
2fd632a0 | 2133 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
2134 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
2135 | ||
0968a619 VM |
2136 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
2137 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
2138 | |
2139 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
2140 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
2141 | /* | |
2142 | * The HW reports non-shareable, we must | |
2143 | * remove the cacheability attributes as | |
2144 | * well. | |
2145 | */ | |
2146 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
2147 | GICR_PROPBASER_CACHEABILITY_MASK); | |
2148 | val |= GICR_PROPBASER_nC; | |
0968a619 | 2149 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 2150 | } |
1ac19ca6 MZ |
2151 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
2152 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
2153 | } | |
2154 | ||
2155 | /* set PENDBASE */ | |
2156 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 2157 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 2158 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 2159 | |
0968a619 VM |
2160 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
2161 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
2162 | |
2163 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
2164 | /* | |
2165 | * The HW reports non-shareable, we must remove the | |
2166 | * cacheability attributes as well. | |
2167 | */ | |
2168 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
2169 | GICR_PENDBASER_CACHEABILITY_MASK); | |
2170 | val |= GICR_PENDBASER_nC; | |
0968a619 | 2171 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 2172 | } |
1ac19ca6 MZ |
2173 | |
2174 | /* Enable LPIs */ | |
2175 | val = readl_relaxed(rbase + GICR_CTLR); | |
2176 | val |= GICR_CTLR_ENABLE_LPIS; | |
2177 | writel_relaxed(val, rbase + GICR_CTLR); | |
2178 | ||
6479450f HG |
2179 | if (gic_rdists->has_vlpis) { |
2180 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
2181 | ||
2182 | /* | |
2183 | * It's possible for CPU to receive VLPIs before it is | |
2184 | * sheduled as a vPE, especially for the first CPU, and the | |
2185 | * VLPI with INTID larger than 2^(IDbits+1) will be considered | |
2186 | * as out of range and dropped by GIC. | |
2187 | * So we initialize IDbits to known value to avoid VLPI drop. | |
2188 | */ | |
2189 | val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
2190 | pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n", | |
2191 | smp_processor_id(), val); | |
2192 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2193 | ||
2194 | /* | |
2195 | * Also clear Valid bit of GICR_VPENDBASER, in case some | |
2196 | * ancient programming gets left in and has possibility of | |
2197 | * corrupting memory. | |
2198 | */ | |
2199 | val = its_clear_vpend_valid(vlpi_base); | |
2200 | WARN_ON(val & GICR_VPENDBASER_Dirty); | |
2201 | } | |
2202 | ||
1ac19ca6 MZ |
2203 | /* Make sure the GIC has seen the above */ |
2204 | dsb(sy); | |
c440a9d9 | 2205 | out: |
11e37d35 | 2206 | gic_data_rdist()->lpi_enabled = true; |
c440a9d9 | 2207 | pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n", |
11e37d35 | 2208 | smp_processor_id(), |
c440a9d9 | 2209 | gic_data_rdist()->pend_page ? "allocated" : "reserved", |
11e37d35 | 2210 | &paddr); |
1ac19ca6 MZ |
2211 | } |
2212 | ||
920181ce | 2213 | static void its_cpu_init_collection(struct its_node *its) |
1ac19ca6 | 2214 | { |
920181ce DB |
2215 | int cpu = smp_processor_id(); |
2216 | u64 target; | |
1ac19ca6 | 2217 | |
920181ce DB |
2218 | /* avoid cross node collections and its mapping */ |
2219 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
2220 | struct device_node *cpu_node; | |
fbf8f40e | 2221 | |
920181ce DB |
2222 | cpu_node = of_get_cpu_node(cpu, NULL); |
2223 | if (its->numa_node != NUMA_NO_NODE && | |
2224 | its->numa_node != of_node_to_nid(cpu_node)) | |
2225 | return; | |
2226 | } | |
fbf8f40e | 2227 | |
920181ce DB |
2228 | /* |
2229 | * We now have to bind each collection to its target | |
2230 | * redistributor. | |
2231 | */ | |
2232 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
1ac19ca6 | 2233 | /* |
920181ce | 2234 | * This ITS wants the physical address of the |
1ac19ca6 MZ |
2235 | * redistributor. |
2236 | */ | |
920181ce DB |
2237 | target = gic_data_rdist()->phys_base; |
2238 | } else { | |
2239 | /* This ITS wants a linear CPU number. */ | |
2240 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2241 | target = GICR_TYPER_CPU_NUMBER(target) << 16; | |
2242 | } | |
1ac19ca6 | 2243 | |
920181ce DB |
2244 | /* Perform collection mapping */ |
2245 | its->collections[cpu].target_address = target; | |
2246 | its->collections[cpu].col_id = cpu; | |
1ac19ca6 | 2247 | |
920181ce DB |
2248 | its_send_mapc(its, &its->collections[cpu], 1); |
2249 | its_send_invall(its, &its->collections[cpu]); | |
2250 | } | |
2251 | ||
2252 | static void its_cpu_init_collections(void) | |
2253 | { | |
2254 | struct its_node *its; | |
2255 | ||
a8db7456 | 2256 | raw_spin_lock(&its_lock); |
920181ce DB |
2257 | |
2258 | list_for_each_entry(its, &its_nodes, entry) | |
2259 | its_cpu_init_collection(its); | |
1ac19ca6 | 2260 | |
a8db7456 | 2261 | raw_spin_unlock(&its_lock); |
1ac19ca6 | 2262 | } |
84a6a2e7 MZ |
2263 | |
2264 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
2265 | { | |
2266 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 2267 | unsigned long flags; |
84a6a2e7 | 2268 | |
3e39e8f5 | 2269 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
2270 | |
2271 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
2272 | if (tmp->device_id == dev_id) { | |
2273 | its_dev = tmp; | |
2274 | break; | |
2275 | } | |
2276 | } | |
2277 | ||
3e39e8f5 | 2278 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
2279 | |
2280 | return its_dev; | |
2281 | } | |
2282 | ||
466b7d16 SD |
2283 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
2284 | { | |
2285 | int i; | |
2286 | ||
2287 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
2288 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
2289 | return &its->tables[i]; | |
2290 | } | |
2291 | ||
2292 | return NULL; | |
2293 | } | |
2294 | ||
70cc81ed | 2295 | static bool its_alloc_table_entry(struct its_baser *baser, u32 id) |
3faf24ea | 2296 | { |
3faf24ea SD |
2297 | struct page *page; |
2298 | u32 esz, idx; | |
2299 | __le64 *table; | |
2300 | ||
3faf24ea SD |
2301 | /* Don't allow device id that exceeds single, flat table limit */ |
2302 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
2303 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 2304 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
2305 | |
2306 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 2307 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
2308 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
2309 | return false; | |
2310 | ||
2311 | table = baser->base; | |
2312 | ||
2313 | /* Allocate memory for 2nd level table */ | |
2314 | if (!table[idx]) { | |
2315 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
2316 | if (!page) | |
2317 | return false; | |
2318 | ||
2319 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
2320 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 2321 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
2322 | |
2323 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
2324 | ||
2325 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
2326 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 2327 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
2328 | |
2329 | /* Ensure updated table contents are visible to ITS hardware */ | |
2330 | dsb(sy); | |
2331 | } | |
2332 | ||
2333 | return true; | |
2334 | } | |
2335 | ||
70cc81ed MZ |
2336 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
2337 | { | |
2338 | struct its_baser *baser; | |
2339 | ||
2340 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
2341 | ||
2342 | /* Don't allow device id that exceeds ITS hardware limit */ | |
2343 | if (!baser) | |
2344 | return (ilog2(dev_id) < its->device_ids); | |
2345 | ||
2346 | return its_alloc_table_entry(baser, dev_id); | |
2347 | } | |
2348 | ||
7d75bbb4 MZ |
2349 | static bool its_alloc_vpe_table(u32 vpe_id) |
2350 | { | |
2351 | struct its_node *its; | |
2352 | ||
2353 | /* | |
2354 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
2355 | * could try and only do it on ITSs corresponding to devices | |
2356 | * that have interrupts targeted at this VPE, but the | |
2357 | * complexity becomes crazy (and you have tons of memory | |
2358 | * anyway, right?). | |
2359 | */ | |
2360 | list_for_each_entry(its, &its_nodes, entry) { | |
2361 | struct its_baser *baser; | |
2362 | ||
2363 | if (!its->is_v4) | |
2364 | continue; | |
3faf24ea | 2365 | |
7d75bbb4 MZ |
2366 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
2367 | if (!baser) | |
2368 | return false; | |
3faf24ea | 2369 | |
7d75bbb4 MZ |
2370 | if (!its_alloc_table_entry(baser, vpe_id)) |
2371 | return false; | |
3faf24ea SD |
2372 | } |
2373 | ||
2374 | return true; | |
2375 | } | |
2376 | ||
84a6a2e7 | 2377 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 2378 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
2379 | { |
2380 | struct its_device *dev; | |
93f94ea0 | 2381 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 2382 | unsigned long flags; |
591e5bec | 2383 | u16 *col_map = NULL; |
84a6a2e7 MZ |
2384 | void *itt; |
2385 | int lpi_base; | |
2386 | int nr_lpis; | |
c8481267 | 2387 | int nr_ites; |
84a6a2e7 MZ |
2388 | int sz; |
2389 | ||
3faf24ea | 2390 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
2391 | return NULL; |
2392 | ||
147c8f37 MZ |
2393 | if (WARN_ON(!is_power_of_2(nvecs))) |
2394 | nvecs = roundup_pow_of_two(nvecs); | |
2395 | ||
84a6a2e7 | 2396 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 | 2397 | /* |
147c8f37 MZ |
2398 | * Even if the device wants a single LPI, the ITT must be |
2399 | * sized as a power of two (and you need at least one bit...). | |
c8481267 | 2400 | */ |
147c8f37 | 2401 | nr_ites = max(2, nvecs); |
c8481267 | 2402 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 2403 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 2404 | itt = kzalloc(sz, GFP_KERNEL); |
93f94ea0 | 2405 | if (alloc_lpis) { |
38dd7c49 | 2406 | lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); |
93f94ea0 | 2407 | if (lpi_map) |
6396bb22 | 2408 | col_map = kcalloc(nr_lpis, sizeof(*col_map), |
93f94ea0 MZ |
2409 | GFP_KERNEL); |
2410 | } else { | |
6396bb22 | 2411 | col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL); |
93f94ea0 MZ |
2412 | nr_lpis = 0; |
2413 | lpi_base = 0; | |
2414 | } | |
84a6a2e7 | 2415 | |
93f94ea0 | 2416 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
2417 | kfree(dev); |
2418 | kfree(itt); | |
2419 | kfree(lpi_map); | |
591e5bec | 2420 | kfree(col_map); |
84a6a2e7 MZ |
2421 | return NULL; |
2422 | } | |
2423 | ||
328191c0 | 2424 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 2425 | |
84a6a2e7 MZ |
2426 | dev->its = its; |
2427 | dev->itt = itt; | |
c8481267 | 2428 | dev->nr_ites = nr_ites; |
591e5bec MZ |
2429 | dev->event_map.lpi_map = lpi_map; |
2430 | dev->event_map.col_map = col_map; | |
2431 | dev->event_map.lpi_base = lpi_base; | |
2432 | dev->event_map.nr_lpis = nr_lpis; | |
d011e4e6 | 2433 | mutex_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
2434 | dev->device_id = dev_id; |
2435 | INIT_LIST_HEAD(&dev->entry); | |
2436 | ||
3e39e8f5 | 2437 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 2438 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 2439 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 2440 | |
84a6a2e7 MZ |
2441 | /* Map device to its ITT */ |
2442 | its_send_mapd(dev, 1); | |
2443 | ||
2444 | return dev; | |
2445 | } | |
2446 | ||
2447 | static void its_free_device(struct its_device *its_dev) | |
2448 | { | |
3e39e8f5 MZ |
2449 | unsigned long flags; |
2450 | ||
2451 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 2452 | list_del(&its_dev->entry); |
3e39e8f5 | 2453 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
2454 | kfree(its_dev->itt); |
2455 | kfree(its_dev); | |
2456 | } | |
b48ac83d | 2457 | |
8208d170 | 2458 | static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq) |
b48ac83d MZ |
2459 | { |
2460 | int idx; | |
2461 | ||
8208d170 MZ |
2462 | idx = bitmap_find_free_region(dev->event_map.lpi_map, |
2463 | dev->event_map.nr_lpis, | |
2464 | get_count_order(nvecs)); | |
2465 | if (idx < 0) | |
b48ac83d MZ |
2466 | return -ENOSPC; |
2467 | ||
591e5bec MZ |
2468 | *hwirq = dev->event_map.lpi_base + idx; |
2469 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 2470 | |
b48ac83d MZ |
2471 | return 0; |
2472 | } | |
2473 | ||
54456db9 MZ |
2474 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
2475 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 2476 | { |
b48ac83d | 2477 | struct its_node *its; |
b48ac83d | 2478 | struct its_device *its_dev; |
54456db9 MZ |
2479 | struct msi_domain_info *msi_info; |
2480 | u32 dev_id; | |
9791ec7d | 2481 | int err = 0; |
54456db9 MZ |
2482 | |
2483 | /* | |
2484 | * We ignore "dev" entierely, and rely on the dev_id that has | |
2485 | * been passed via the scratchpad. This limits this domain's | |
2486 | * usefulness to upper layers that definitely know that they | |
2487 | * are built on top of the ITS. | |
2488 | */ | |
2489 | dev_id = info->scratchpad[0].ul; | |
2490 | ||
2491 | msi_info = msi_get_domain_info(domain); | |
2492 | its = msi_info->data; | |
e8137f4f | 2493 | |
20b3d54e MZ |
2494 | if (!gic_rdists->has_direct_lpi && |
2495 | vpe_proxy.dev && | |
2496 | vpe_proxy.dev->its == its && | |
2497 | dev_id == vpe_proxy.dev->device_id) { | |
2498 | /* Bad luck. Get yourself a better implementation */ | |
2499 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
2500 | dev_id); | |
2501 | return -EINVAL; | |
2502 | } | |
2503 | ||
9791ec7d | 2504 | mutex_lock(&its->dev_alloc_lock); |
f130420e | 2505 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
2506 | if (its_dev) { |
2507 | /* | |
2508 | * We already have seen this ID, probably through | |
2509 | * another alias (PCI bridge of some sort). No need to | |
2510 | * create the device. | |
2511 | */ | |
9791ec7d | 2512 | its_dev->shared = true; |
f130420e | 2513 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
2514 | goto out; |
2515 | } | |
b48ac83d | 2516 | |
93f94ea0 | 2517 | its_dev = its_create_device(its, dev_id, nvec, true); |
9791ec7d MZ |
2518 | if (!its_dev) { |
2519 | err = -ENOMEM; | |
2520 | goto out; | |
2521 | } | |
b48ac83d | 2522 | |
f130420e | 2523 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 2524 | out: |
9791ec7d | 2525 | mutex_unlock(&its->dev_alloc_lock); |
b48ac83d | 2526 | info->scratchpad[0].ptr = its_dev; |
9791ec7d | 2527 | return err; |
b48ac83d MZ |
2528 | } |
2529 | ||
54456db9 MZ |
2530 | static struct msi_domain_ops its_msi_domain_ops = { |
2531 | .msi_prepare = its_msi_prepare, | |
2532 | }; | |
2533 | ||
b48ac83d MZ |
2534 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
2535 | unsigned int virq, | |
2536 | irq_hw_number_t hwirq) | |
2537 | { | |
f833f57f MZ |
2538 | struct irq_fwspec fwspec; |
2539 | ||
2540 | if (irq_domain_get_of_node(domain->parent)) { | |
2541 | fwspec.fwnode = domain->parent->fwnode; | |
2542 | fwspec.param_count = 3; | |
2543 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
2544 | fwspec.param[1] = hwirq; | |
2545 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
2546 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
2547 | fwspec.fwnode = domain->parent->fwnode; | |
2548 | fwspec.param_count = 2; | |
2549 | fwspec.param[0] = hwirq; | |
2550 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
2551 | } else { |
2552 | return -EINVAL; | |
2553 | } | |
b48ac83d | 2554 | |
f833f57f | 2555 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
2556 | } |
2557 | ||
2558 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
2559 | unsigned int nr_irqs, void *args) | |
2560 | { | |
2561 | msi_alloc_info_t *info = args; | |
2562 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
2563 | irq_hw_number_t hwirq; | |
2564 | int err; | |
2565 | int i; | |
2566 | ||
8208d170 MZ |
2567 | err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq); |
2568 | if (err) | |
2569 | return err; | |
b48ac83d | 2570 | |
8208d170 MZ |
2571 | for (i = 0; i < nr_irqs; i++) { |
2572 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); | |
b48ac83d MZ |
2573 | if (err) |
2574 | return err; | |
2575 | ||
2576 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
8208d170 | 2577 | hwirq + i, &its_irq_chip, its_dev); |
0d224d35 | 2578 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); |
f130420e | 2579 | pr_debug("ID:%d pID:%d vID:%d\n", |
8208d170 MZ |
2580 | (int)(hwirq + i - its_dev->event_map.lpi_base), |
2581 | (int)(hwirq + i), virq + i); | |
b48ac83d MZ |
2582 | } |
2583 | ||
2584 | return 0; | |
2585 | } | |
2586 | ||
72491643 | 2587 | static int its_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 2588 | struct irq_data *d, bool reserve) |
aca268df MZ |
2589 | { |
2590 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2591 | u32 event = its_get_event_id(d); | |
fbf8f40e | 2592 | const struct cpumask *cpu_mask = cpu_online_mask; |
0d224d35 | 2593 | int cpu; |
fbf8f40e GK |
2594 | |
2595 | /* get the cpu_mask of local node */ | |
2596 | if (its_dev->its->numa_node >= 0) | |
2597 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 2598 | |
591e5bec | 2599 | /* Bind the LPI to the first possible CPU */ |
c1797b11 YY |
2600 | cpu = cpumask_first_and(cpu_mask, cpu_online_mask); |
2601 | if (cpu >= nr_cpu_ids) { | |
2602 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) | |
2603 | return -EINVAL; | |
2604 | ||
2605 | cpu = cpumask_first(cpu_online_mask); | |
2606 | } | |
2607 | ||
0d224d35 MZ |
2608 | its_dev->event_map.col_map[event] = cpu; |
2609 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 2610 | |
aca268df | 2611 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 2612 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 2613 | return 0; |
aca268df MZ |
2614 | } |
2615 | ||
2616 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
2617 | struct irq_data *d) | |
2618 | { | |
2619 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2620 | u32 event = its_get_event_id(d); | |
2621 | ||
2622 | /* Stop the delivery of interrupts */ | |
2623 | its_send_discard(its_dev, event); | |
2624 | } | |
2625 | ||
b48ac83d MZ |
2626 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
2627 | unsigned int nr_irqs) | |
2628 | { | |
2629 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
2630 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
9791ec7d | 2631 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
2632 | int i; |
2633 | ||
2634 | for (i = 0; i < nr_irqs; i++) { | |
2635 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2636 | virq + i); | |
aca268df | 2637 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
2638 | |
2639 | /* Mark interrupt index as unused */ | |
591e5bec | 2640 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
2641 | |
2642 | /* Nuke the entry in the domain */ | |
2da39949 | 2643 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
2644 | } |
2645 | ||
9791ec7d MZ |
2646 | mutex_lock(&its->dev_alloc_lock); |
2647 | ||
2648 | /* | |
2649 | * If all interrupts have been freed, start mopping the | |
2650 | * floor. This is conditionned on the device not being shared. | |
2651 | */ | |
2652 | if (!its_dev->shared && | |
2653 | bitmap_empty(its_dev->event_map.lpi_map, | |
591e5bec | 2654 | its_dev->event_map.nr_lpis)) { |
38dd7c49 MZ |
2655 | its_lpi_free(its_dev->event_map.lpi_map, |
2656 | its_dev->event_map.lpi_base, | |
2657 | its_dev->event_map.nr_lpis); | |
cf2be8ba | 2658 | kfree(its_dev->event_map.col_map); |
b48ac83d MZ |
2659 | |
2660 | /* Unmap device/itt */ | |
2661 | its_send_mapd(its_dev, 0); | |
2662 | its_free_device(its_dev); | |
2663 | } | |
2664 | ||
9791ec7d MZ |
2665 | mutex_unlock(&its->dev_alloc_lock); |
2666 | ||
b48ac83d MZ |
2667 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
2668 | } | |
2669 | ||
2670 | static const struct irq_domain_ops its_domain_ops = { | |
2671 | .alloc = its_irq_domain_alloc, | |
2672 | .free = its_irq_domain_free, | |
aca268df MZ |
2673 | .activate = its_irq_domain_activate, |
2674 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 2675 | }; |
4c21f3c2 | 2676 | |
20b3d54e MZ |
2677 | /* |
2678 | * This is insane. | |
2679 | * | |
2680 | * If a GICv4 doesn't implement Direct LPIs (which is extremely | |
2681 | * likely), the only way to perform an invalidate is to use a fake | |
2682 | * device to issue an INV command, implying that the LPI has first | |
2683 | * been mapped to some event on that device. Since this is not exactly | |
2684 | * cheap, we try to keep that mapping around as long as possible, and | |
2685 | * only issue an UNMAP if we're short on available slots. | |
2686 | * | |
2687 | * Broken by design(tm). | |
2688 | */ | |
2689 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
2690 | { | |
2691 | /* Already unmapped? */ | |
2692 | if (vpe->vpe_proxy_event == -1) | |
2693 | return; | |
2694 | ||
2695 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2696 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
2697 | ||
2698 | /* | |
2699 | * We don't track empty slots at all, so let's move the | |
2700 | * next_victim pointer if we can quickly reuse that slot | |
2701 | * instead of nuking an existing entry. Not clear that this is | |
2702 | * always a win though, and this might just generate a ripple | |
2703 | * effect... Let's just hope VPEs don't migrate too often. | |
2704 | */ | |
2705 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2706 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
2707 | ||
2708 | vpe->vpe_proxy_event = -1; | |
2709 | } | |
2710 | ||
2711 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
2712 | { | |
2713 | if (!gic_rdists->has_direct_lpi) { | |
2714 | unsigned long flags; | |
2715 | ||
2716 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2717 | its_vpe_db_proxy_unmap_locked(vpe); | |
2718 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
2723 | { | |
2724 | /* Already mapped? */ | |
2725 | if (vpe->vpe_proxy_event != -1) | |
2726 | return; | |
2727 | ||
2728 | /* This slot was already allocated. Kick the other VPE out. */ | |
2729 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2730 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
2731 | ||
2732 | /* Map the new VPE instead */ | |
2733 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
2734 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
2735 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
2736 | ||
2737 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
2738 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
2739 | } | |
2740 | ||
958b90d1 MZ |
2741 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
2742 | { | |
2743 | unsigned long flags; | |
2744 | struct its_collection *target_col; | |
2745 | ||
2746 | if (gic_rdists->has_direct_lpi) { | |
2747 | void __iomem *rdbase; | |
2748 | ||
2749 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
2750 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2751 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2752 | cpu_relax(); | |
2753 | ||
2754 | return; | |
2755 | } | |
2756 | ||
2757 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2758 | ||
2759 | its_vpe_db_proxy_map_locked(vpe); | |
2760 | ||
2761 | target_col = &vpe_proxy.dev->its->collections[to]; | |
2762 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
2763 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
2764 | ||
2765 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2766 | } | |
2767 | ||
3171a47a MZ |
2768 | static int its_vpe_set_affinity(struct irq_data *d, |
2769 | const struct cpumask *mask_val, | |
2770 | bool force) | |
2771 | { | |
2772 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2773 | int cpu = cpumask_first(mask_val); | |
2774 | ||
2775 | /* | |
2776 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 2777 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
2778 | * into the proxy device, we need to move the doorbell |
2779 | * interrupt to its new location. | |
3171a47a MZ |
2780 | */ |
2781 | if (vpe->col_idx != cpu) { | |
958b90d1 MZ |
2782 | int from = vpe->col_idx; |
2783 | ||
3171a47a MZ |
2784 | vpe->col_idx = cpu; |
2785 | its_send_vmovp(vpe); | |
958b90d1 | 2786 | its_vpe_db_proxy_move(vpe, from, cpu); |
3171a47a MZ |
2787 | } |
2788 | ||
44c4c25e MZ |
2789 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
2790 | ||
3171a47a MZ |
2791 | return IRQ_SET_MASK_OK_DONE; |
2792 | } | |
2793 | ||
e643d803 MZ |
2794 | static void its_vpe_schedule(struct its_vpe *vpe) |
2795 | { | |
50c33097 | 2796 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
2797 | u64 val; |
2798 | ||
2799 | /* Schedule the VPE */ | |
2800 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
2801 | GENMASK_ULL(51, 12); | |
2802 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
2803 | val |= GICR_VPROPBASER_RaWb; | |
2804 | val |= GICR_VPROPBASER_InnerShareable; | |
2805 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2806 | ||
2807 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
2808 | GENMASK_ULL(51, 16); | |
2809 | val |= GICR_VPENDBASER_RaWaWb; | |
2810 | val |= GICR_VPENDBASER_NonShareable; | |
2811 | /* | |
2812 | * There is no good way of finding out if the pending table is | |
2813 | * empty as we can race against the doorbell interrupt very | |
2814 | * easily. So in the end, vpe->pending_last is only an | |
2815 | * indication that the vcpu has something pending, not one | |
2816 | * that the pending table is empty. A good implementation | |
2817 | * would be able to read its coarse map pretty quickly anyway, | |
2818 | * making this a tolerable issue. | |
2819 | */ | |
2820 | val |= GICR_VPENDBASER_PendingLast; | |
2821 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
2822 | val |= GICR_VPENDBASER_Valid; | |
2823 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2824 | } | |
2825 | ||
2826 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
2827 | { | |
50c33097 | 2828 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
2829 | u64 val; |
2830 | ||
6479450f | 2831 | val = its_clear_vpend_valid(vlpi_base); |
e643d803 | 2832 | |
6479450f | 2833 | if (unlikely(val & GICR_VPENDBASER_Dirty)) { |
e643d803 MZ |
2834 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); |
2835 | vpe->idai = false; | |
2836 | vpe->pending_last = true; | |
2837 | } else { | |
2838 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); | |
2839 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
2840 | } | |
2841 | } | |
2842 | ||
40619a2e MZ |
2843 | static void its_vpe_invall(struct its_vpe *vpe) |
2844 | { | |
2845 | struct its_node *its; | |
2846 | ||
2847 | list_for_each_entry(its, &its_nodes, entry) { | |
2848 | if (!its->is_v4) | |
2849 | continue; | |
2850 | ||
2247e1bf MZ |
2851 | if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) |
2852 | continue; | |
2853 | ||
3c1cceeb MZ |
2854 | /* |
2855 | * Sending a VINVALL to a single ITS is enough, as all | |
2856 | * we need is to reach the redistributors. | |
2857 | */ | |
40619a2e | 2858 | its_send_vinvall(its, vpe); |
3c1cceeb | 2859 | return; |
40619a2e MZ |
2860 | } |
2861 | } | |
2862 | ||
e643d803 MZ |
2863 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
2864 | { | |
2865 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2866 | struct its_cmd_info *info = vcpu_info; | |
2867 | ||
2868 | switch (info->cmd_type) { | |
2869 | case SCHEDULE_VPE: | |
2870 | its_vpe_schedule(vpe); | |
2871 | return 0; | |
2872 | ||
2873 | case DESCHEDULE_VPE: | |
2874 | its_vpe_deschedule(vpe); | |
2875 | return 0; | |
2876 | ||
5e2f7642 | 2877 | case INVALL_VPE: |
40619a2e | 2878 | its_vpe_invall(vpe); |
5e2f7642 MZ |
2879 | return 0; |
2880 | ||
e643d803 MZ |
2881 | default: |
2882 | return -EINVAL; | |
2883 | } | |
2884 | } | |
2885 | ||
20b3d54e MZ |
2886 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
2887 | void (*cmd)(struct its_device *, u32)) | |
2888 | { | |
2889 | unsigned long flags; | |
2890 | ||
2891 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2892 | ||
2893 | its_vpe_db_proxy_map_locked(vpe); | |
2894 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2895 | ||
2896 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2897 | } | |
2898 | ||
f6a91da7 MZ |
2899 | static void its_vpe_send_inv(struct irq_data *d) |
2900 | { | |
2901 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 2902 | |
20b3d54e MZ |
2903 | if (gic_rdists->has_direct_lpi) { |
2904 | void __iomem *rdbase; | |
2905 | ||
2906 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2907 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR); | |
2908 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2909 | cpu_relax(); | |
2910 | } else { | |
2911 | its_vpe_send_cmd(vpe, its_send_inv); | |
2912 | } | |
f6a91da7 MZ |
2913 | } |
2914 | ||
2915 | static void its_vpe_mask_irq(struct irq_data *d) | |
2916 | { | |
2917 | /* | |
2918 | * We need to unmask the LPI, which is described by the parent | |
2919 | * irq_data. Instead of calling into the parent (which won't | |
2920 | * exactly do the right thing, let's simply use the | |
2921 | * parent_data pointer. Yes, I'm naughty. | |
2922 | */ | |
2923 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
2924 | its_vpe_send_inv(d); | |
2925 | } | |
2926 | ||
2927 | static void its_vpe_unmask_irq(struct irq_data *d) | |
2928 | { | |
2929 | /* Same hack as above... */ | |
2930 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
2931 | its_vpe_send_inv(d); | |
2932 | } | |
2933 | ||
e57a3e28 MZ |
2934 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
2935 | enum irqchip_irq_state which, | |
2936 | bool state) | |
2937 | { | |
2938 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2939 | ||
2940 | if (which != IRQCHIP_STATE_PENDING) | |
2941 | return -EINVAL; | |
2942 | ||
2943 | if (gic_rdists->has_direct_lpi) { | |
2944 | void __iomem *rdbase; | |
2945 | ||
2946 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2947 | if (state) { | |
2948 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
2949 | } else { | |
2950 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2951 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2952 | cpu_relax(); | |
2953 | } | |
2954 | } else { | |
2955 | if (state) | |
2956 | its_vpe_send_cmd(vpe, its_send_int); | |
2957 | else | |
2958 | its_vpe_send_cmd(vpe, its_send_clear); | |
2959 | } | |
2960 | ||
2961 | return 0; | |
2962 | } | |
2963 | ||
8fff27ae MZ |
2964 | static struct irq_chip its_vpe_irq_chip = { |
2965 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
2966 | .irq_mask = its_vpe_mask_irq, |
2967 | .irq_unmask = its_vpe_unmask_irq, | |
2968 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 2969 | .irq_set_affinity = its_vpe_set_affinity, |
e57a3e28 | 2970 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 2971 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
2972 | }; |
2973 | ||
7d75bbb4 MZ |
2974 | static int its_vpe_id_alloc(void) |
2975 | { | |
32bd44dc | 2976 | return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL); |
7d75bbb4 MZ |
2977 | } |
2978 | ||
2979 | static void its_vpe_id_free(u16 id) | |
2980 | { | |
2981 | ida_simple_remove(&its_vpeid_ida, id); | |
2982 | } | |
2983 | ||
2984 | static int its_vpe_init(struct its_vpe *vpe) | |
2985 | { | |
2986 | struct page *vpt_page; | |
2987 | int vpe_id; | |
2988 | ||
2989 | /* Allocate vpe_id */ | |
2990 | vpe_id = its_vpe_id_alloc(); | |
2991 | if (vpe_id < 0) | |
2992 | return vpe_id; | |
2993 | ||
2994 | /* Allocate VPT */ | |
2995 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
2996 | if (!vpt_page) { | |
2997 | its_vpe_id_free(vpe_id); | |
2998 | return -ENOMEM; | |
2999 | } | |
3000 | ||
3001 | if (!its_alloc_vpe_table(vpe_id)) { | |
3002 | its_vpe_id_free(vpe_id); | |
3003 | its_free_pending_table(vpe->vpt_page); | |
3004 | return -ENOMEM; | |
3005 | } | |
3006 | ||
3007 | vpe->vpe_id = vpe_id; | |
3008 | vpe->vpt_page = vpt_page; | |
20b3d54e | 3009 | vpe->vpe_proxy_event = -1; |
7d75bbb4 MZ |
3010 | |
3011 | return 0; | |
3012 | } | |
3013 | ||
3014 | static void its_vpe_teardown(struct its_vpe *vpe) | |
3015 | { | |
20b3d54e | 3016 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
3017 | its_vpe_id_free(vpe->vpe_id); |
3018 | its_free_pending_table(vpe->vpt_page); | |
3019 | } | |
3020 | ||
3021 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
3022 | unsigned int virq, | |
3023 | unsigned int nr_irqs) | |
3024 | { | |
3025 | struct its_vm *vm = domain->host_data; | |
3026 | int i; | |
3027 | ||
3028 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
3029 | ||
3030 | for (i = 0; i < nr_irqs; i++) { | |
3031 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
3032 | virq + i); | |
3033 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
3034 | ||
3035 | BUG_ON(vm != vpe->its_vm); | |
3036 | ||
3037 | clear_bit(data->hwirq, vm->db_bitmap); | |
3038 | its_vpe_teardown(vpe); | |
3039 | irq_domain_reset_irq_data(data); | |
3040 | } | |
3041 | ||
3042 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
38dd7c49 | 3043 | its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); |
7d75bbb4 MZ |
3044 | its_free_prop_table(vm->vprop_page); |
3045 | } | |
3046 | } | |
3047 | ||
3048 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
3049 | unsigned int nr_irqs, void *args) | |
3050 | { | |
3051 | struct its_vm *vm = args; | |
3052 | unsigned long *bitmap; | |
3053 | struct page *vprop_page; | |
3054 | int base, nr_ids, i, err = 0; | |
3055 | ||
3056 | BUG_ON(!vm); | |
3057 | ||
38dd7c49 | 3058 | bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids); |
7d75bbb4 MZ |
3059 | if (!bitmap) |
3060 | return -ENOMEM; | |
3061 | ||
3062 | if (nr_ids < nr_irqs) { | |
38dd7c49 | 3063 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3064 | return -ENOMEM; |
3065 | } | |
3066 | ||
3067 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
3068 | if (!vprop_page) { | |
38dd7c49 | 3069 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3070 | return -ENOMEM; |
3071 | } | |
3072 | ||
3073 | vm->db_bitmap = bitmap; | |
3074 | vm->db_lpi_base = base; | |
3075 | vm->nr_db_lpis = nr_ids; | |
3076 | vm->vprop_page = vprop_page; | |
3077 | ||
3078 | for (i = 0; i < nr_irqs; i++) { | |
3079 | vm->vpes[i]->vpe_db_lpi = base + i; | |
3080 | err = its_vpe_init(vm->vpes[i]); | |
3081 | if (err) | |
3082 | break; | |
3083 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
3084 | vm->vpes[i]->vpe_db_lpi); | |
3085 | if (err) | |
3086 | break; | |
3087 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
3088 | &its_vpe_irq_chip, vm->vpes[i]); | |
3089 | set_bit(i, bitmap); | |
3090 | } | |
3091 | ||
3092 | if (err) { | |
3093 | if (i > 0) | |
3094 | its_vpe_irq_domain_free(domain, virq, i - 1); | |
3095 | ||
38dd7c49 | 3096 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
3097 | its_free_prop_table(vprop_page); |
3098 | } | |
3099 | ||
3100 | return err; | |
3101 | } | |
3102 | ||
72491643 | 3103 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 3104 | struct irq_data *d, bool reserve) |
eb78192b MZ |
3105 | { |
3106 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
40619a2e | 3107 | struct its_node *its; |
eb78192b | 3108 | |
2247e1bf MZ |
3109 | /* If we use the list map, we issue VMAPP on demand... */ |
3110 | if (its_list_map) | |
6ef930f2 | 3111 | return 0; |
eb78192b MZ |
3112 | |
3113 | /* Map the VPE to the first possible CPU */ | |
3114 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
40619a2e MZ |
3115 | |
3116 | list_for_each_entry(its, &its_nodes, entry) { | |
3117 | if (!its->is_v4) | |
3118 | continue; | |
3119 | ||
75fd951b | 3120 | its_send_vmapp(its, vpe, true); |
40619a2e MZ |
3121 | its_send_vinvall(its, vpe); |
3122 | } | |
3123 | ||
44c4c25e MZ |
3124 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
3125 | ||
72491643 | 3126 | return 0; |
eb78192b MZ |
3127 | } |
3128 | ||
3129 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
3130 | struct irq_data *d) | |
3131 | { | |
3132 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
75fd951b MZ |
3133 | struct its_node *its; |
3134 | ||
2247e1bf MZ |
3135 | /* |
3136 | * If we use the list map, we unmap the VPE once no VLPIs are | |
3137 | * associated with the VM. | |
3138 | */ | |
3139 | if (its_list_map) | |
3140 | return; | |
eb78192b | 3141 | |
75fd951b MZ |
3142 | list_for_each_entry(its, &its_nodes, entry) { |
3143 | if (!its->is_v4) | |
3144 | continue; | |
eb78192b | 3145 | |
75fd951b MZ |
3146 | its_send_vmapp(its, vpe, false); |
3147 | } | |
eb78192b MZ |
3148 | } |
3149 | ||
8fff27ae | 3150 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
3151 | .alloc = its_vpe_irq_domain_alloc, |
3152 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
3153 | .activate = its_vpe_irq_domain_activate, |
3154 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
3155 | }; |
3156 | ||
4559fbb3 YW |
3157 | static int its_force_quiescent(void __iomem *base) |
3158 | { | |
3159 | u32 count = 1000000; /* 1s */ | |
3160 | u32 val; | |
3161 | ||
3162 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
3163 | /* |
3164 | * GIC architecture specification requires the ITS to be both | |
3165 | * disabled and quiescent for writes to GITS_BASER<n> or | |
3166 | * GITS_CBASER to not have UNPREDICTABLE results. | |
3167 | */ | |
3168 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
3169 | return 0; |
3170 | ||
3171 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 3172 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
3173 | writel_relaxed(val, base + GITS_CTLR); |
3174 | ||
3175 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
3176 | while (1) { | |
3177 | val = readl_relaxed(base + GITS_CTLR); | |
3178 | if (val & GITS_CTLR_QUIESCENT) | |
3179 | return 0; | |
3180 | ||
3181 | count--; | |
3182 | if (!count) | |
3183 | return -EBUSY; | |
3184 | ||
3185 | cpu_relax(); | |
3186 | udelay(1); | |
3187 | } | |
3188 | } | |
3189 | ||
9d111d49 | 3190 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
3191 | { |
3192 | struct its_node *its = data; | |
3193 | ||
fa150019 AB |
3194 | /* erratum 22375: only alloc 8MB table size */ |
3195 | its->device_ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 3196 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
3197 | |
3198 | return true; | |
94100970 RR |
3199 | } |
3200 | ||
9d111d49 | 3201 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
3202 | { |
3203 | struct its_node *its = data; | |
3204 | ||
3205 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
3206 | |
3207 | return true; | |
fbf8f40e GK |
3208 | } |
3209 | ||
9d111d49 | 3210 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
3211 | { |
3212 | struct its_node *its = data; | |
3213 | ||
3214 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
3215 | its->ite_size = 16; | |
9d111d49 AB |
3216 | |
3217 | return true; | |
90922a2d SD |
3218 | } |
3219 | ||
558b0165 AB |
3220 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
3221 | { | |
3222 | struct its_node *its = its_dev->its; | |
3223 | ||
3224 | /* | |
3225 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
3226 | * which maps 32-bit writes targeted at a separate window of | |
3227 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
3228 | * with device ID taken from bits [device_id_bits + 1:2] of | |
3229 | * the window offset. | |
3230 | */ | |
3231 | return its->pre_its_base + (its_dev->device_id << 2); | |
3232 | } | |
3233 | ||
3234 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
3235 | { | |
3236 | struct its_node *its = data; | |
3237 | u32 pre_its_window[2]; | |
3238 | u32 ids; | |
3239 | ||
3240 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
3241 | "socionext,synquacer-pre-its", | |
3242 | pre_its_window, | |
3243 | ARRAY_SIZE(pre_its_window))) { | |
3244 | ||
3245 | its->pre_its_base = pre_its_window[0]; | |
3246 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
3247 | ||
3248 | ids = ilog2(pre_its_window[1]) - 2; | |
3249 | if (its->device_ids > ids) | |
3250 | its->device_ids = ids; | |
3251 | ||
3252 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
3253 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; | |
3254 | return true; | |
3255 | } | |
3256 | return false; | |
3257 | } | |
3258 | ||
5c9a882e MZ |
3259 | static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) |
3260 | { | |
3261 | struct its_node *its = data; | |
3262 | ||
3263 | /* | |
3264 | * Hip07 insists on using the wrong address for the VLPI | |
3265 | * page. Trick it into doing the right thing... | |
3266 | */ | |
3267 | its->vlpi_redist_offset = SZ_128K; | |
3268 | return true; | |
90922a2d SD |
3269 | } |
3270 | ||
67510cca | 3271 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
3272 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
3273 | { | |
3274 | .desc = "ITS: Cavium errata 22375, 24313", | |
3275 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
3276 | .mask = 0xffff0fff, | |
3277 | .init = its_enable_quirk_cavium_22375, | |
3278 | }, | |
fbf8f40e GK |
3279 | #endif |
3280 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
3281 | { | |
3282 | .desc = "ITS: Cavium erratum 23144", | |
3283 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
3284 | .mask = 0xffff0fff, | |
3285 | .init = its_enable_quirk_cavium_23144, | |
3286 | }, | |
90922a2d SD |
3287 | #endif |
3288 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
3289 | { | |
3290 | .desc = "ITS: QDF2400 erratum 0065", | |
3291 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
3292 | .mask = 0xffffffff, | |
3293 | .init = its_enable_quirk_qdf2400_e0065, | |
3294 | }, | |
558b0165 AB |
3295 | #endif |
3296 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
3297 | { | |
3298 | /* | |
3299 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
3300 | * implementation, but with a 'pre-ITS' added that requires | |
3301 | * special handling in software. | |
3302 | */ | |
3303 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
3304 | .iidr = 0x0001143b, | |
3305 | .mask = 0xffffffff, | |
3306 | .init = its_enable_quirk_socionext_synquacer, | |
3307 | }, | |
5c9a882e MZ |
3308 | #endif |
3309 | #ifdef CONFIG_HISILICON_ERRATUM_161600802 | |
3310 | { | |
3311 | .desc = "ITS: Hip07 erratum 161600802", | |
3312 | .iidr = 0x00000004, | |
3313 | .mask = 0xffffffff, | |
3314 | .init = its_enable_quirk_hip07_161600802, | |
3315 | }, | |
94100970 | 3316 | #endif |
67510cca RR |
3317 | { |
3318 | } | |
3319 | }; | |
3320 | ||
3321 | static void its_enable_quirks(struct its_node *its) | |
3322 | { | |
3323 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
3324 | ||
3325 | gic_enable_quirks(iidr, its_quirks, its); | |
3326 | } | |
3327 | ||
dba0bc7b DB |
3328 | static int its_save_disable(void) |
3329 | { | |
3330 | struct its_node *its; | |
3331 | int err = 0; | |
3332 | ||
a8db7456 | 3333 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
3334 | list_for_each_entry(its, &its_nodes, entry) { |
3335 | void __iomem *base; | |
3336 | ||
3337 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3338 | continue; | |
3339 | ||
3340 | base = its->base; | |
3341 | its->ctlr_save = readl_relaxed(base + GITS_CTLR); | |
3342 | err = its_force_quiescent(base); | |
3343 | if (err) { | |
3344 | pr_err("ITS@%pa: failed to quiesce: %d\n", | |
3345 | &its->phys_base, err); | |
3346 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
3347 | goto err; | |
3348 | } | |
3349 | ||
3350 | its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); | |
3351 | } | |
3352 | ||
3353 | err: | |
3354 | if (err) { | |
3355 | list_for_each_entry_continue_reverse(its, &its_nodes, entry) { | |
3356 | void __iomem *base; | |
3357 | ||
3358 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3359 | continue; | |
3360 | ||
3361 | base = its->base; | |
3362 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
3363 | } | |
3364 | } | |
a8db7456 | 3365 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
3366 | |
3367 | return err; | |
3368 | } | |
3369 | ||
3370 | static void its_restore_enable(void) | |
3371 | { | |
3372 | struct its_node *its; | |
3373 | int ret; | |
3374 | ||
a8db7456 | 3375 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
3376 | list_for_each_entry(its, &its_nodes, entry) { |
3377 | void __iomem *base; | |
3378 | int i; | |
3379 | ||
3380 | if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) | |
3381 | continue; | |
3382 | ||
3383 | base = its->base; | |
3384 | ||
3385 | /* | |
3386 | * Make sure that the ITS is disabled. If it fails to quiesce, | |
3387 | * don't restore it since writing to CBASER or BASER<n> | |
3388 | * registers is undefined according to the GIC v3 ITS | |
3389 | * Specification. | |
3390 | */ | |
3391 | ret = its_force_quiescent(base); | |
3392 | if (ret) { | |
3393 | pr_err("ITS@%pa: failed to quiesce on resume: %d\n", | |
3394 | &its->phys_base, ret); | |
3395 | continue; | |
3396 | } | |
3397 | ||
3398 | gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); | |
3399 | ||
3400 | /* | |
3401 | * Writing CBASER resets CREADR to 0, so make CWRITER and | |
3402 | * cmd_write line up with it. | |
3403 | */ | |
3404 | its->cmd_write = its->cmd_base; | |
3405 | gits_write_cwriter(0, base + GITS_CWRITER); | |
3406 | ||
3407 | /* Restore GITS_BASER from the value cache. */ | |
3408 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
3409 | struct its_baser *baser = &its->tables[i]; | |
3410 | ||
3411 | if (!(baser->val & GITS_BASER_VALID)) | |
3412 | continue; | |
3413 | ||
3414 | its_write_baser(its, baser, baser->val); | |
3415 | } | |
3416 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
920181ce DB |
3417 | |
3418 | /* | |
3419 | * Reinit the collection if it's stored in the ITS. This is | |
3420 | * indicated by the col_id being less than the HCC field. | |
3421 | * CID < HCC as specified in the GIC v3 Documentation. | |
3422 | */ | |
3423 | if (its->collections[smp_processor_id()].col_id < | |
3424 | GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) | |
3425 | its_cpu_init_collection(its); | |
dba0bc7b | 3426 | } |
a8db7456 | 3427 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
3428 | } |
3429 | ||
3430 | static struct syscore_ops its_syscore_ops = { | |
3431 | .suspend = its_save_disable, | |
3432 | .resume = its_restore_enable, | |
3433 | }; | |
3434 | ||
db40f0a7 | 3435 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
3436 | { |
3437 | struct irq_domain *inner_domain; | |
3438 | struct msi_domain_info *info; | |
3439 | ||
3440 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
3441 | if (!info) | |
3442 | return -ENOMEM; | |
3443 | ||
db40f0a7 | 3444 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
3445 | if (!inner_domain) { |
3446 | kfree(info); | |
3447 | return -ENOMEM; | |
3448 | } | |
3449 | ||
db40f0a7 | 3450 | inner_domain->parent = its_parent; |
96f0d93a | 3451 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
558b0165 | 3452 | inner_domain->flags |= its->msi_domain_flags; |
d14ae5e6 TN |
3453 | info->ops = &its_msi_domain_ops; |
3454 | info->data = its; | |
3455 | inner_domain->host_data = info; | |
3456 | ||
3457 | return 0; | |
3458 | } | |
3459 | ||
8fff27ae MZ |
3460 | static int its_init_vpe_domain(void) |
3461 | { | |
20b3d54e MZ |
3462 | struct its_node *its; |
3463 | u32 devid; | |
3464 | int entries; | |
3465 | ||
3466 | if (gic_rdists->has_direct_lpi) { | |
3467 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
3468 | return 0; | |
3469 | } | |
3470 | ||
3471 | /* Any ITS will do, even if not v4 */ | |
3472 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
3473 | ||
3474 | entries = roundup_pow_of_two(nr_cpu_ids); | |
6396bb22 | 3475 | vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes), |
20b3d54e MZ |
3476 | GFP_KERNEL); |
3477 | if (!vpe_proxy.vpes) { | |
3478 | pr_err("ITS: Can't allocate GICv4 proxy device array\n"); | |
3479 | return -ENOMEM; | |
3480 | } | |
3481 | ||
3482 | /* Use the last possible DevID */ | |
3483 | devid = GENMASK(its->device_ids - 1, 0); | |
3484 | vpe_proxy.dev = its_create_device(its, devid, entries, false); | |
3485 | if (!vpe_proxy.dev) { | |
3486 | kfree(vpe_proxy.vpes); | |
3487 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
3488 | return -ENOMEM; | |
3489 | } | |
3490 | ||
c427a475 | 3491 | BUG_ON(entries > vpe_proxy.dev->nr_ites); |
20b3d54e MZ |
3492 | |
3493 | raw_spin_lock_init(&vpe_proxy.lock); | |
3494 | vpe_proxy.next_victim = 0; | |
3495 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
3496 | devid, vpe_proxy.dev->nr_ites); | |
3497 | ||
8fff27ae MZ |
3498 | return 0; |
3499 | } | |
3500 | ||
3dfa576b MZ |
3501 | static int __init its_compute_its_list_map(struct resource *res, |
3502 | void __iomem *its_base) | |
3503 | { | |
3504 | int its_number; | |
3505 | u32 ctlr; | |
3506 | ||
3507 | /* | |
3508 | * This is assumed to be done early enough that we're | |
3509 | * guaranteed to be single-threaded, hence no | |
3510 | * locking. Should this change, we should address | |
3511 | * this. | |
3512 | */ | |
ab60491e MZ |
3513 | its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX); |
3514 | if (its_number >= GICv4_ITS_LIST_MAX) { | |
3dfa576b MZ |
3515 | pr_err("ITS@%pa: No ITSList entry available!\n", |
3516 | &res->start); | |
3517 | return -EINVAL; | |
3518 | } | |
3519 | ||
3520 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
3521 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
3522 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
3523 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
3524 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
3525 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
3526 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
3527 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
3528 | } | |
3529 | ||
3530 | if (test_and_set_bit(its_number, &its_list_map)) { | |
3531 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
3532 | &res->start, its_number); | |
3533 | return -EINVAL; | |
3534 | } | |
3535 | ||
3536 | return its_number; | |
3537 | } | |
3538 | ||
db40f0a7 TN |
3539 | static int __init its_probe_one(struct resource *res, |
3540 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 3541 | { |
4c21f3c2 MZ |
3542 | struct its_node *its; |
3543 | void __iomem *its_base; | |
3dfa576b MZ |
3544 | u32 val, ctlr; |
3545 | u64 baser, tmp, typer; | |
4c21f3c2 MZ |
3546 | int err; |
3547 | ||
db40f0a7 | 3548 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 3549 | if (!its_base) { |
db40f0a7 | 3550 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
3551 | return -ENOMEM; |
3552 | } | |
3553 | ||
3554 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
3555 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 3556 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
3557 | err = -ENODEV; |
3558 | goto out_unmap; | |
3559 | } | |
3560 | ||
4559fbb3 YW |
3561 | err = its_force_quiescent(its_base); |
3562 | if (err) { | |
db40f0a7 | 3563 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
3564 | goto out_unmap; |
3565 | } | |
3566 | ||
db40f0a7 | 3567 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
3568 | |
3569 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
3570 | if (!its) { | |
3571 | err = -ENOMEM; | |
3572 | goto out_unmap; | |
3573 | } | |
3574 | ||
3575 | raw_spin_lock_init(&its->lock); | |
9791ec7d | 3576 | mutex_init(&its->dev_alloc_lock); |
4c21f3c2 MZ |
3577 | INIT_LIST_HEAD(&its->entry); |
3578 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 3579 | typer = gic_read_typer(its_base + GITS_TYPER); |
4c21f3c2 | 3580 | its->base = its_base; |
db40f0a7 | 3581 | its->phys_base = res->start; |
3dfa576b | 3582 | its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); |
fa150019 | 3583 | its->device_ids = GITS_TYPER_DEVBITS(typer); |
3dfa576b MZ |
3584 | its->is_v4 = !!(typer & GITS_TYPER_VLPIS); |
3585 | if (its->is_v4) { | |
3586 | if (!(typer & GITS_TYPER_VMOVP)) { | |
3587 | err = its_compute_its_list_map(res, its_base); | |
3588 | if (err < 0) | |
3589 | goto out_free_its; | |
3590 | ||
debf6d02 MZ |
3591 | its->list_nr = err; |
3592 | ||
3dfa576b MZ |
3593 | pr_info("ITS@%pa: Using ITS number %d\n", |
3594 | &res->start, err); | |
3595 | } else { | |
3596 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
3597 | } | |
3598 | } | |
3599 | ||
db40f0a7 | 3600 | its->numa_node = numa_node; |
4c21f3c2 | 3601 | |
5bc13c2c RR |
3602 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
3603 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
3604 | if (!its->cmd_base) { |
3605 | err = -ENOMEM; | |
3606 | goto out_free_its; | |
3607 | } | |
3608 | its->cmd_write = its->cmd_base; | |
558b0165 AB |
3609 | its->fwnode_handle = handle; |
3610 | its->get_msi_base = its_irq_get_msi_base; | |
3611 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4c21f3c2 | 3612 | |
67510cca RR |
3613 | its_enable_quirks(its); |
3614 | ||
0e0b0f69 | 3615 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
3616 | if (err) |
3617 | goto out_free_cmd; | |
3618 | ||
3619 | err = its_alloc_collections(its); | |
3620 | if (err) | |
3621 | goto out_free_tables; | |
3622 | ||
3623 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 3624 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
3625 | GITS_CBASER_InnerShareable | |
3626 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
3627 | GITS_CBASER_VALID); | |
3628 | ||
0968a619 VM |
3629 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
3630 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 3631 | |
4ad3e363 | 3632 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
3633 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
3634 | /* | |
3635 | * The HW reports non-shareable, we must | |
3636 | * remove the cacheability attributes as | |
3637 | * well. | |
3638 | */ | |
3639 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
3640 | GITS_CBASER_CACHEABILITY_MASK); | |
3641 | baser |= GITS_CBASER_nC; | |
0968a619 | 3642 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 3643 | } |
4c21f3c2 MZ |
3644 | pr_info("ITS: using cache flushing for cmd queue\n"); |
3645 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
3646 | } | |
3647 | ||
0968a619 | 3648 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 3649 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d MZ |
3650 | ctlr |= GITS_CTLR_ENABLE; |
3651 | if (its->is_v4) | |
3652 | ctlr |= GITS_CTLR_ImDe; | |
3653 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 3654 | |
dba0bc7b DB |
3655 | if (GITS_TYPER_HCC(typer)) |
3656 | its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE; | |
3657 | ||
db40f0a7 | 3658 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
3659 | if (err) |
3660 | goto out_free_tables; | |
4c21f3c2 | 3661 | |
a8db7456 | 3662 | raw_spin_lock(&its_lock); |
4c21f3c2 | 3663 | list_add(&its->entry, &its_nodes); |
a8db7456 | 3664 | raw_spin_unlock(&its_lock); |
4c21f3c2 MZ |
3665 | |
3666 | return 0; | |
3667 | ||
4c21f3c2 MZ |
3668 | out_free_tables: |
3669 | its_free_tables(its); | |
3670 | out_free_cmd: | |
5bc13c2c | 3671 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
3672 | out_free_its: |
3673 | kfree(its); | |
3674 | out_unmap: | |
3675 | iounmap(its_base); | |
db40f0a7 | 3676 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
3677 | return err; |
3678 | } | |
3679 | ||
3680 | static bool gic_rdists_supports_plpis(void) | |
3681 | { | |
589ce5f4 | 3682 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
3683 | } |
3684 | ||
6eb486b6 SD |
3685 | static int redist_disable_lpis(void) |
3686 | { | |
3687 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
3688 | u64 timeout = USEC_PER_SEC; | |
3689 | u64 val; | |
3690 | ||
3691 | if (!gic_rdists_supports_plpis()) { | |
3692 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
3693 | return -ENXIO; | |
3694 | } | |
3695 | ||
3696 | val = readl_relaxed(rbase + GICR_CTLR); | |
3697 | if (!(val & GICR_CTLR_ENABLE_LPIS)) | |
3698 | return 0; | |
3699 | ||
11e37d35 MZ |
3700 | /* |
3701 | * If coming via a CPU hotplug event, we don't need to disable | |
3702 | * LPIs before trying to re-enable them. They are already | |
3703 | * configured and all is well in the world. | |
c440a9d9 MZ |
3704 | * |
3705 | * If running with preallocated tables, there is nothing to do. | |
11e37d35 | 3706 | */ |
c440a9d9 MZ |
3707 | if (gic_data_rdist()->lpi_enabled || |
3708 | (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) | |
11e37d35 MZ |
3709 | return 0; |
3710 | ||
3711 | /* | |
3712 | * From that point on, we only try to do some damage control. | |
3713 | */ | |
3714 | pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n", | |
6eb486b6 SD |
3715 | smp_processor_id()); |
3716 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
3717 | ||
3718 | /* Disable LPIs */ | |
3719 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
3720 | writel_relaxed(val, rbase + GICR_CTLR); | |
3721 | ||
3722 | /* Make sure any change to GICR_CTLR is observable by the GIC */ | |
3723 | dsb(sy); | |
3724 | ||
3725 | /* | |
3726 | * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs | |
3727 | * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. | |
3728 | * Error out if we time out waiting for RWP to clear. | |
3729 | */ | |
3730 | while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { | |
3731 | if (!timeout) { | |
3732 | pr_err("CPU%d: Timeout while disabling LPIs\n", | |
3733 | smp_processor_id()); | |
3734 | return -ETIMEDOUT; | |
3735 | } | |
3736 | udelay(1); | |
3737 | timeout--; | |
3738 | } | |
3739 | ||
3740 | /* | |
3741 | * After it has been written to 1, it is IMPLEMENTATION | |
3742 | * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be | |
3743 | * cleared to 0. Error out if clearing the bit failed. | |
3744 | */ | |
3745 | if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { | |
3746 | pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id()); | |
3747 | return -EBUSY; | |
3748 | } | |
3749 | ||
3750 | return 0; | |
3751 | } | |
3752 | ||
4c21f3c2 MZ |
3753 | int its_cpu_init(void) |
3754 | { | |
4c21f3c2 | 3755 | if (!list_empty(&its_nodes)) { |
6eb486b6 SD |
3756 | int ret; |
3757 | ||
3758 | ret = redist_disable_lpis(); | |
3759 | if (ret) | |
3760 | return ret; | |
3761 | ||
4c21f3c2 | 3762 | its_cpu_init_lpis(); |
920181ce | 3763 | its_cpu_init_collections(); |
4c21f3c2 MZ |
3764 | } |
3765 | ||
3766 | return 0; | |
3767 | } | |
3768 | ||
935bba7c | 3769 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
3770 | { .compatible = "arm,gic-v3-its", }, |
3771 | {}, | |
3772 | }; | |
3773 | ||
db40f0a7 | 3774 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
3775 | { |
3776 | struct device_node *np; | |
db40f0a7 | 3777 | struct resource res; |
4c21f3c2 MZ |
3778 | |
3779 | for (np = of_find_matching_node(node, its_device_id); np; | |
3780 | np = of_find_matching_node(np, its_device_id)) { | |
95a25625 SB |
3781 | if (!of_device_is_available(np)) |
3782 | continue; | |
d14ae5e6 | 3783 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
3784 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
3785 | np); | |
d14ae5e6 TN |
3786 | continue; |
3787 | } | |
3788 | ||
db40f0a7 | 3789 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 3790 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
3791 | continue; |
3792 | } | |
3793 | ||
3794 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 3795 | } |
db40f0a7 TN |
3796 | return 0; |
3797 | } | |
3798 | ||
3f010cf1 TN |
3799 | #ifdef CONFIG_ACPI |
3800 | ||
3801 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
3802 | ||
d1ce263f | 3803 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
3804 | struct its_srat_map { |
3805 | /* numa node id */ | |
3806 | u32 numa_node; | |
3807 | /* GIC ITS ID */ | |
3808 | u32 its_id; | |
3809 | }; | |
3810 | ||
fdf6e7a8 | 3811 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
3812 | static int its_in_srat __initdata; |
3813 | ||
3814 | static int __init acpi_get_its_numa_node(u32 its_id) | |
3815 | { | |
3816 | int i; | |
3817 | ||
3818 | for (i = 0; i < its_in_srat; i++) { | |
3819 | if (its_id == its_srat_maps[i].its_id) | |
3820 | return its_srat_maps[i].numa_node; | |
3821 | } | |
3822 | return NUMA_NO_NODE; | |
3823 | } | |
3824 | ||
fdf6e7a8 HG |
3825 | static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header, |
3826 | const unsigned long end) | |
3827 | { | |
3828 | return 0; | |
3829 | } | |
3830 | ||
dbd2b826 GK |
3831 | static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, |
3832 | const unsigned long end) | |
3833 | { | |
3834 | int node; | |
3835 | struct acpi_srat_gic_its_affinity *its_affinity; | |
3836 | ||
3837 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
3838 | if (!its_affinity) | |
3839 | return -EINVAL; | |
3840 | ||
3841 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
3842 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
3843 | its_affinity->header.length); | |
3844 | return -EINVAL; | |
3845 | } | |
3846 | ||
dbd2b826 GK |
3847 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); |
3848 | ||
3849 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
3850 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
3851 | return 0; | |
3852 | } | |
3853 | ||
3854 | its_srat_maps[its_in_srat].numa_node = node; | |
3855 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
3856 | its_in_srat++; | |
3857 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
3858 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
3859 | ||
3860 | return 0; | |
3861 | } | |
3862 | ||
3863 | static void __init acpi_table_parse_srat_its(void) | |
3864 | { | |
fdf6e7a8 HG |
3865 | int count; |
3866 | ||
3867 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
3868 | sizeof(struct acpi_table_srat), | |
3869 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3870 | gic_acpi_match_srat_its, 0); | |
3871 | if (count <= 0) | |
3872 | return; | |
3873 | ||
6da2ec56 KC |
3874 | its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map), |
3875 | GFP_KERNEL); | |
fdf6e7a8 HG |
3876 | if (!its_srat_maps) { |
3877 | pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n"); | |
3878 | return; | |
3879 | } | |
3880 | ||
dbd2b826 GK |
3881 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
3882 | sizeof(struct acpi_table_srat), | |
3883 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3884 | gic_acpi_parse_srat_its, 0); | |
3885 | } | |
fdf6e7a8 HG |
3886 | |
3887 | /* free the its_srat_maps after ITS probing */ | |
3888 | static void __init acpi_its_srat_maps_free(void) | |
3889 | { | |
3890 | kfree(its_srat_maps); | |
3891 | } | |
dbd2b826 GK |
3892 | #else |
3893 | static void __init acpi_table_parse_srat_its(void) { } | |
3894 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 3895 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
3896 | #endif |
3897 | ||
3f010cf1 TN |
3898 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, |
3899 | const unsigned long end) | |
3900 | { | |
3901 | struct acpi_madt_generic_translator *its_entry; | |
3902 | struct fwnode_handle *dom_handle; | |
3903 | struct resource res; | |
3904 | int err; | |
3905 | ||
3906 | its_entry = (struct acpi_madt_generic_translator *)header; | |
3907 | memset(&res, 0, sizeof(res)); | |
3908 | res.start = its_entry->base_address; | |
3909 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
3910 | res.flags = IORESOURCE_MEM; | |
3911 | ||
3912 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
3913 | if (!dom_handle) { | |
3914 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
3915 | &res.start); | |
3916 | return -ENOMEM; | |
3917 | } | |
3918 | ||
8b4282e6 SK |
3919 | err = iort_register_domain_token(its_entry->translation_id, res.start, |
3920 | dom_handle); | |
3f010cf1 TN |
3921 | if (err) { |
3922 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
3923 | &res.start, its_entry->translation_id); | |
3924 | goto dom_err; | |
3925 | } | |
3926 | ||
dbd2b826 GK |
3927 | err = its_probe_one(&res, dom_handle, |
3928 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
3929 | if (!err) |
3930 | return 0; | |
3931 | ||
3932 | iort_deregister_domain_token(its_entry->translation_id); | |
3933 | dom_err: | |
3934 | irq_domain_free_fwnode(dom_handle); | |
3935 | return err; | |
3936 | } | |
3937 | ||
3938 | static void __init its_acpi_probe(void) | |
3939 | { | |
dbd2b826 | 3940 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
3941 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
3942 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 3943 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
3944 | } |
3945 | #else | |
3946 | static void __init its_acpi_probe(void) { } | |
3947 | #endif | |
3948 | ||
db40f0a7 TN |
3949 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
3950 | struct irq_domain *parent_domain) | |
3951 | { | |
3952 | struct device_node *of_node; | |
8fff27ae MZ |
3953 | struct its_node *its; |
3954 | bool has_v4 = false; | |
3955 | int err; | |
db40f0a7 TN |
3956 | |
3957 | its_parent = parent_domain; | |
3958 | of_node = to_of_node(handle); | |
3959 | if (of_node) | |
3960 | its_of_probe(of_node); | |
3961 | else | |
3f010cf1 | 3962 | its_acpi_probe(); |
4c21f3c2 MZ |
3963 | |
3964 | if (list_empty(&its_nodes)) { | |
3965 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
3966 | return -ENXIO; | |
3967 | } | |
3968 | ||
3969 | gic_rdists = rdists; | |
11e37d35 MZ |
3970 | |
3971 | err = allocate_lpi_tables(); | |
8fff27ae MZ |
3972 | if (err) |
3973 | return err; | |
3974 | ||
3975 | list_for_each_entry(its, &its_nodes, entry) | |
3976 | has_v4 |= its->is_v4; | |
3977 | ||
3978 | if (has_v4 & rdists->has_vlpis) { | |
3d63cb53 MZ |
3979 | if (its_init_vpe_domain() || |
3980 | its_init_v4(parent_domain, &its_vpe_domain_ops)) { | |
8fff27ae MZ |
3981 | rdists->has_vlpis = false; |
3982 | pr_err("ITS: Disabling GICv4 support\n"); | |
3983 | } | |
3984 | } | |
3985 | ||
dba0bc7b DB |
3986 | register_syscore_ops(&its_syscore_ops); |
3987 | ||
8fff27ae | 3988 | return 0; |
4c21f3c2 | 3989 | } |