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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
cc2d3216 MZ |
19 | #include <linux/bitmap.h> |
20 | #include <linux/cpu.h> | |
21 | #include <linux/delay.h> | |
44bb7e24 | 22 | #include <linux/dma-iommu.h> |
cc2d3216 | 23 | #include <linux/interrupt.h> |
3f010cf1 TN |
24 | #include <linux/irqdomain.h> |
25 | #include <linux/acpi_iort.h> | |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 MZ |
38 | #include <linux/irqchip/arm-gic-v3.h> |
39 | ||
cc2d3216 MZ |
40 | #include <asm/cputype.h> |
41 | #include <asm/exception.h> | |
42 | ||
67510cca RR |
43 | #include "irq-gic-common.h" |
44 | ||
94100970 RR |
45 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
46 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 48 | |
c48ed51c MZ |
49 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
50 | ||
cc2d3216 MZ |
51 | /* |
52 | * Collection structure - just an ID, and a redistributor address to | |
53 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
54 | * CPU. | |
55 | */ | |
56 | struct its_collection { | |
57 | u64 target_address; | |
58 | u16 col_id; | |
59 | }; | |
60 | ||
466b7d16 | 61 | /* |
9347359a SD |
62 | * The ITS_BASER structure - contains memory information, cached |
63 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
64 | */ |
65 | struct its_baser { | |
66 | void *base; | |
67 | u64 val; | |
68 | u32 order; | |
9347359a | 69 | u32 psz; |
466b7d16 SD |
70 | }; |
71 | ||
cc2d3216 MZ |
72 | /* |
73 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
74 | * top-level MSI domain, the command queue, the collections, and the |
75 | * list of devices writing to it. | |
cc2d3216 MZ |
76 | */ |
77 | struct its_node { | |
78 | raw_spinlock_t lock; | |
79 | struct list_head entry; | |
cc2d3216 | 80 | void __iomem *base; |
db40f0a7 | 81 | phys_addr_t phys_base; |
cc2d3216 MZ |
82 | struct its_cmd_block *cmd_base; |
83 | struct its_cmd_block *cmd_write; | |
466b7d16 | 84 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
85 | struct its_collection *collections; |
86 | struct list_head its_device_list; | |
87 | u64 flags; | |
88 | u32 ite_size; | |
466b7d16 | 89 | u32 device_ids; |
fbf8f40e | 90 | int numa_node; |
cc2d3216 MZ |
91 | }; |
92 | ||
93 | #define ITS_ITT_ALIGN SZ_256 | |
94 | ||
2eca0d6c SD |
95 | /* Convert page order to size in bytes */ |
96 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
97 | ||
591e5bec MZ |
98 | struct event_lpi_map { |
99 | unsigned long *lpi_map; | |
100 | u16 *col_map; | |
101 | irq_hw_number_t lpi_base; | |
102 | int nr_lpis; | |
103 | }; | |
104 | ||
cc2d3216 MZ |
105 | /* |
106 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
107 | * interrupt translation table, and a list of interrupts. | |
108 | */ | |
109 | struct its_device { | |
110 | struct list_head entry; | |
111 | struct its_node *its; | |
591e5bec | 112 | struct event_lpi_map event_map; |
cc2d3216 | 113 | void *itt; |
cc2d3216 MZ |
114 | u32 nr_ites; |
115 | u32 device_id; | |
116 | }; | |
117 | ||
1ac19ca6 MZ |
118 | static LIST_HEAD(its_nodes); |
119 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 120 | static struct rdists *gic_rdists; |
db40f0a7 | 121 | static struct irq_domain *its_parent; |
1ac19ca6 MZ |
122 | |
123 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) | |
124 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
125 | ||
591e5bec MZ |
126 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
127 | u32 event) | |
128 | { | |
129 | struct its_node *its = its_dev->its; | |
130 | ||
131 | return its->collections + its_dev->event_map.col_map[event]; | |
132 | } | |
133 | ||
cc2d3216 MZ |
134 | /* |
135 | * ITS command descriptors - parameters to be encoded in a command | |
136 | * block. | |
137 | */ | |
138 | struct its_cmd_desc { | |
139 | union { | |
140 | struct { | |
141 | struct its_device *dev; | |
142 | u32 event_id; | |
143 | } its_inv_cmd; | |
144 | ||
145 | struct { | |
146 | struct its_device *dev; | |
147 | u32 event_id; | |
148 | } its_int_cmd; | |
149 | ||
150 | struct { | |
151 | struct its_device *dev; | |
152 | int valid; | |
153 | } its_mapd_cmd; | |
154 | ||
155 | struct { | |
156 | struct its_collection *col; | |
157 | int valid; | |
158 | } its_mapc_cmd; | |
159 | ||
160 | struct { | |
161 | struct its_device *dev; | |
162 | u32 phys_id; | |
163 | u32 event_id; | |
164 | } its_mapvi_cmd; | |
165 | ||
166 | struct { | |
167 | struct its_device *dev; | |
168 | struct its_collection *col; | |
591e5bec | 169 | u32 event_id; |
cc2d3216 MZ |
170 | } its_movi_cmd; |
171 | ||
172 | struct { | |
173 | struct its_device *dev; | |
174 | u32 event_id; | |
175 | } its_discard_cmd; | |
176 | ||
177 | struct { | |
178 | struct its_collection *col; | |
179 | } its_invall_cmd; | |
180 | }; | |
181 | }; | |
182 | ||
183 | /* | |
184 | * The ITS command block, which is what the ITS actually parses. | |
185 | */ | |
186 | struct its_cmd_block { | |
187 | u64 raw_cmd[4]; | |
188 | }; | |
189 | ||
190 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
191 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
192 | ||
193 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
194 | struct its_cmd_desc *); | |
195 | ||
196 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) | |
197 | { | |
b11283eb | 198 | cmd->raw_cmd[0] &= ~0xffULL; |
cc2d3216 MZ |
199 | cmd->raw_cmd[0] |= cmd_nr; |
200 | } | |
201 | ||
202 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
203 | { | |
7e195ba0 | 204 | cmd->raw_cmd[0] &= BIT_ULL(32) - 1; |
cc2d3216 MZ |
205 | cmd->raw_cmd[0] |= ((u64)devid) << 32; |
206 | } | |
207 | ||
208 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
209 | { | |
b11283eb | 210 | cmd->raw_cmd[1] &= ~0xffffffffULL; |
cc2d3216 MZ |
211 | cmd->raw_cmd[1] |= id; |
212 | } | |
213 | ||
214 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
215 | { | |
b11283eb | 216 | cmd->raw_cmd[1] &= 0xffffffffULL; |
cc2d3216 MZ |
217 | cmd->raw_cmd[1] |= ((u64)phys_id) << 32; |
218 | } | |
219 | ||
220 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
221 | { | |
b11283eb | 222 | cmd->raw_cmd[1] &= ~0x1fULL; |
cc2d3216 MZ |
223 | cmd->raw_cmd[1] |= size & 0x1f; |
224 | } | |
225 | ||
226 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
227 | { | |
b11283eb VM |
228 | cmd->raw_cmd[2] &= ~0xffffffffffffULL; |
229 | cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL; | |
cc2d3216 MZ |
230 | } |
231 | ||
232 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
233 | { | |
b11283eb | 234 | cmd->raw_cmd[2] &= ~(1ULL << 63); |
cc2d3216 MZ |
235 | cmd->raw_cmd[2] |= ((u64)!!valid) << 63; |
236 | } | |
237 | ||
238 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
239 | { | |
b11283eb VM |
240 | cmd->raw_cmd[2] &= ~(0xffffffffULL << 16); |
241 | cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16)); | |
cc2d3216 MZ |
242 | } |
243 | ||
244 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
245 | { | |
b11283eb | 246 | cmd->raw_cmd[2] &= ~0xffffULL; |
cc2d3216 MZ |
247 | cmd->raw_cmd[2] |= col; |
248 | } | |
249 | ||
250 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
251 | { | |
252 | /* Let's fixup BE commands */ | |
253 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
254 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
255 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
256 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
257 | } | |
258 | ||
259 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
260 | struct its_cmd_desc *desc) | |
261 | { | |
262 | unsigned long itt_addr; | |
c8481267 | 263 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
264 | |
265 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
266 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
267 | ||
268 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
269 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
270 | its_encode_size(cmd, size - 1); | |
271 | its_encode_itt(cmd, itt_addr); | |
272 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
273 | ||
274 | its_fixup_cmd(cmd); | |
275 | ||
591e5bec | 276 | return NULL; |
cc2d3216 MZ |
277 | } |
278 | ||
279 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
280 | struct its_cmd_desc *desc) | |
281 | { | |
282 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
283 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
284 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
285 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
286 | ||
287 | its_fixup_cmd(cmd); | |
288 | ||
289 | return desc->its_mapc_cmd.col; | |
290 | } | |
291 | ||
292 | static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, | |
293 | struct its_cmd_desc *desc) | |
294 | { | |
591e5bec MZ |
295 | struct its_collection *col; |
296 | ||
297 | col = dev_event_to_col(desc->its_mapvi_cmd.dev, | |
298 | desc->its_mapvi_cmd.event_id); | |
299 | ||
cc2d3216 MZ |
300 | its_encode_cmd(cmd, GITS_CMD_MAPVI); |
301 | its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); | |
302 | its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); | |
303 | its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); | |
591e5bec | 304 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
305 | |
306 | its_fixup_cmd(cmd); | |
307 | ||
591e5bec | 308 | return col; |
cc2d3216 MZ |
309 | } |
310 | ||
311 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
312 | struct its_cmd_desc *desc) | |
313 | { | |
591e5bec MZ |
314 | struct its_collection *col; |
315 | ||
316 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
317 | desc->its_movi_cmd.event_id); | |
318 | ||
cc2d3216 MZ |
319 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
320 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 321 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
322 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
323 | ||
324 | its_fixup_cmd(cmd); | |
325 | ||
591e5bec | 326 | return col; |
cc2d3216 MZ |
327 | } |
328 | ||
329 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
330 | struct its_cmd_desc *desc) | |
331 | { | |
591e5bec MZ |
332 | struct its_collection *col; |
333 | ||
334 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
335 | desc->its_discard_cmd.event_id); | |
336 | ||
cc2d3216 MZ |
337 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
338 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
339 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
340 | ||
341 | its_fixup_cmd(cmd); | |
342 | ||
591e5bec | 343 | return col; |
cc2d3216 MZ |
344 | } |
345 | ||
346 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
347 | struct its_cmd_desc *desc) | |
348 | { | |
591e5bec MZ |
349 | struct its_collection *col; |
350 | ||
351 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
352 | desc->its_inv_cmd.event_id); | |
353 | ||
cc2d3216 MZ |
354 | its_encode_cmd(cmd, GITS_CMD_INV); |
355 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
356 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
357 | ||
358 | its_fixup_cmd(cmd); | |
359 | ||
591e5bec | 360 | return col; |
cc2d3216 MZ |
361 | } |
362 | ||
363 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, | |
364 | struct its_cmd_desc *desc) | |
365 | { | |
366 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
367 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
368 | ||
369 | its_fixup_cmd(cmd); | |
370 | ||
371 | return NULL; | |
372 | } | |
373 | ||
374 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
375 | struct its_cmd_block *ptr) | |
376 | { | |
377 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
378 | } | |
379 | ||
380 | static int its_queue_full(struct its_node *its) | |
381 | { | |
382 | int widx; | |
383 | int ridx; | |
384 | ||
385 | widx = its->cmd_write - its->cmd_base; | |
386 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
387 | ||
388 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
389 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
390 | return 1; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
396 | { | |
397 | struct its_cmd_block *cmd; | |
398 | u32 count = 1000000; /* 1s! */ | |
399 | ||
400 | while (its_queue_full(its)) { | |
401 | count--; | |
402 | if (!count) { | |
403 | pr_err_ratelimited("ITS queue not draining\n"); | |
404 | return NULL; | |
405 | } | |
406 | cpu_relax(); | |
407 | udelay(1); | |
408 | } | |
409 | ||
410 | cmd = its->cmd_write++; | |
411 | ||
412 | /* Handle queue wrapping */ | |
413 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
414 | its->cmd_write = its->cmd_base; | |
415 | ||
416 | return cmd; | |
417 | } | |
418 | ||
419 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
420 | { | |
421 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
422 | ||
423 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
424 | ||
425 | return its->cmd_write; | |
426 | } | |
427 | ||
428 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
429 | { | |
430 | /* | |
431 | * Make sure the commands written to memory are observable by | |
432 | * the ITS. | |
433 | */ | |
434 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 435 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
436 | else |
437 | dsb(ishst); | |
438 | } | |
439 | ||
440 | static void its_wait_for_range_completion(struct its_node *its, | |
441 | struct its_cmd_block *from, | |
442 | struct its_cmd_block *to) | |
443 | { | |
444 | u64 rd_idx, from_idx, to_idx; | |
445 | u32 count = 1000000; /* 1s! */ | |
446 | ||
447 | from_idx = its_cmd_ptr_to_offset(its, from); | |
448 | to_idx = its_cmd_ptr_to_offset(its, to); | |
449 | ||
450 | while (1) { | |
451 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
452 | if (rd_idx >= to_idx || rd_idx < from_idx) | |
453 | break; | |
454 | ||
455 | count--; | |
456 | if (!count) { | |
457 | pr_err_ratelimited("ITS queue timeout\n"); | |
458 | return; | |
459 | } | |
460 | cpu_relax(); | |
461 | udelay(1); | |
462 | } | |
463 | } | |
464 | ||
465 | static void its_send_single_command(struct its_node *its, | |
466 | its_cmd_builder_t builder, | |
467 | struct its_cmd_desc *desc) | |
468 | { | |
469 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; | |
470 | struct its_collection *sync_col; | |
3e39e8f5 | 471 | unsigned long flags; |
cc2d3216 | 472 | |
3e39e8f5 | 473 | raw_spin_lock_irqsave(&its->lock, flags); |
cc2d3216 MZ |
474 | |
475 | cmd = its_allocate_entry(its); | |
476 | if (!cmd) { /* We're soooooo screewed... */ | |
477 | pr_err_ratelimited("ITS can't allocate, dropping command\n"); | |
3e39e8f5 | 478 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
479 | return; |
480 | } | |
481 | sync_col = builder(cmd, desc); | |
482 | its_flush_cmd(its, cmd); | |
483 | ||
484 | if (sync_col) { | |
485 | sync_cmd = its_allocate_entry(its); | |
486 | if (!sync_cmd) { | |
487 | pr_err_ratelimited("ITS can't SYNC, skipping\n"); | |
488 | goto post; | |
489 | } | |
490 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
491 | its_encode_target(sync_cmd, sync_col->target_address); | |
492 | its_fixup_cmd(sync_cmd); | |
493 | its_flush_cmd(its, sync_cmd); | |
494 | } | |
495 | ||
496 | post: | |
497 | next_cmd = its_post_commands(its); | |
3e39e8f5 | 498 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
499 | |
500 | its_wait_for_range_completion(its, cmd, next_cmd); | |
501 | } | |
502 | ||
503 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
504 | { | |
505 | struct its_cmd_desc desc; | |
506 | ||
507 | desc.its_inv_cmd.dev = dev; | |
508 | desc.its_inv_cmd.event_id = event_id; | |
509 | ||
510 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
511 | } | |
512 | ||
513 | static void its_send_mapd(struct its_device *dev, int valid) | |
514 | { | |
515 | struct its_cmd_desc desc; | |
516 | ||
517 | desc.its_mapd_cmd.dev = dev; | |
518 | desc.its_mapd_cmd.valid = !!valid; | |
519 | ||
520 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
521 | } | |
522 | ||
523 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
524 | int valid) | |
525 | { | |
526 | struct its_cmd_desc desc; | |
527 | ||
528 | desc.its_mapc_cmd.col = col; | |
529 | desc.its_mapc_cmd.valid = !!valid; | |
530 | ||
531 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
532 | } | |
533 | ||
534 | static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) | |
535 | { | |
536 | struct its_cmd_desc desc; | |
537 | ||
538 | desc.its_mapvi_cmd.dev = dev; | |
539 | desc.its_mapvi_cmd.phys_id = irq_id; | |
540 | desc.its_mapvi_cmd.event_id = id; | |
541 | ||
542 | its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); | |
543 | } | |
544 | ||
545 | static void its_send_movi(struct its_device *dev, | |
546 | struct its_collection *col, u32 id) | |
547 | { | |
548 | struct its_cmd_desc desc; | |
549 | ||
550 | desc.its_movi_cmd.dev = dev; | |
551 | desc.its_movi_cmd.col = col; | |
591e5bec | 552 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
553 | |
554 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
555 | } | |
556 | ||
557 | static void its_send_discard(struct its_device *dev, u32 id) | |
558 | { | |
559 | struct its_cmd_desc desc; | |
560 | ||
561 | desc.its_discard_cmd.dev = dev; | |
562 | desc.its_discard_cmd.event_id = id; | |
563 | ||
564 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
565 | } | |
566 | ||
567 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
568 | { | |
569 | struct its_cmd_desc desc; | |
570 | ||
571 | desc.its_invall_cmd.col = col; | |
572 | ||
573 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
574 | } | |
c48ed51c MZ |
575 | |
576 | /* | |
577 | * irqchip functions - assumes MSI, mostly. | |
578 | */ | |
579 | ||
580 | static inline u32 its_get_event_id(struct irq_data *d) | |
581 | { | |
582 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 583 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
584 | } |
585 | ||
586 | static void lpi_set_config(struct irq_data *d, bool enable) | |
587 | { | |
588 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
589 | irq_hw_number_t hwirq = d->hwirq; | |
590 | u32 id = its_get_event_id(d); | |
591 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
592 | ||
593 | if (enable) | |
594 | *cfg |= LPI_PROP_ENABLED; | |
595 | else | |
596 | *cfg &= ~LPI_PROP_ENABLED; | |
597 | ||
598 | /* | |
599 | * Make the above write visible to the redistributors. | |
600 | * And yes, we're flushing exactly: One. Single. Byte. | |
601 | * Humpf... | |
602 | */ | |
603 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 604 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
605 | else |
606 | dsb(ishst); | |
607 | its_send_inv(its_dev, id); | |
608 | } | |
609 | ||
610 | static void its_mask_irq(struct irq_data *d) | |
611 | { | |
612 | lpi_set_config(d, false); | |
613 | } | |
614 | ||
615 | static void its_unmask_irq(struct irq_data *d) | |
616 | { | |
617 | lpi_set_config(d, true); | |
618 | } | |
619 | ||
c48ed51c MZ |
620 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
621 | bool force) | |
622 | { | |
fbf8f40e GK |
623 | unsigned int cpu; |
624 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
625 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
626 | struct its_collection *target_col; | |
627 | u32 id = its_get_event_id(d); | |
628 | ||
fbf8f40e GK |
629 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
630 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
631 | if (its_dev->its->numa_node >= 0) { | |
632 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
633 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
634 | return -EINVAL; | |
635 | } | |
636 | } | |
637 | ||
638 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
639 | ||
c48ed51c MZ |
640 | if (cpu >= nr_cpu_ids) |
641 | return -EINVAL; | |
642 | ||
643 | target_col = &its_dev->its->collections[cpu]; | |
644 | its_send_movi(its_dev, target_col, id); | |
591e5bec | 645 | its_dev->event_map.col_map[id] = cpu; |
c48ed51c MZ |
646 | |
647 | return IRQ_SET_MASK_OK_DONE; | |
648 | } | |
649 | ||
b48ac83d MZ |
650 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
651 | { | |
652 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
653 | struct its_node *its; | |
654 | u64 addr; | |
655 | ||
656 | its = its_dev->its; | |
657 | addr = its->phys_base + GITS_TRANSLATER; | |
658 | ||
b11283eb VM |
659 | msg->address_lo = lower_32_bits(addr); |
660 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 661 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
662 | |
663 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
664 | } |
665 | ||
c48ed51c MZ |
666 | static struct irq_chip its_irq_chip = { |
667 | .name = "ITS", | |
668 | .irq_mask = its_mask_irq, | |
669 | .irq_unmask = its_unmask_irq, | |
004fa08d | 670 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 671 | .irq_set_affinity = its_set_affinity, |
b48ac83d MZ |
672 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
673 | }; | |
674 | ||
bf9529f8 MZ |
675 | /* |
676 | * How we allocate LPIs: | |
677 | * | |
678 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
679 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
680 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
681 | * bits to the right. | |
682 | * | |
683 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
684 | */ | |
685 | #define IRQS_PER_CHUNK_SHIFT 5 | |
686 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
687 | ||
688 | static unsigned long *lpi_bitmap; | |
689 | static u32 lpi_chunks; | |
690 | static DEFINE_SPINLOCK(lpi_lock); | |
691 | ||
692 | static int its_lpi_to_chunk(int lpi) | |
693 | { | |
694 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
695 | } | |
696 | ||
697 | static int its_chunk_to_lpi(int chunk) | |
698 | { | |
699 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
700 | } | |
701 | ||
04a0e4de | 702 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
703 | { |
704 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
705 | ||
706 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
707 | GFP_KERNEL); | |
708 | if (!lpi_bitmap) { | |
709 | lpi_chunks = 0; | |
710 | return -ENOMEM; | |
711 | } | |
712 | ||
713 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
714 | return 0; | |
715 | } | |
716 | ||
717 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
718 | { | |
719 | unsigned long *bitmap = NULL; | |
720 | int chunk_id; | |
721 | int nr_chunks; | |
722 | int i; | |
723 | ||
724 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
725 | ||
726 | spin_lock(&lpi_lock); | |
727 | ||
728 | do { | |
729 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
730 | 0, nr_chunks, 0); | |
731 | if (chunk_id < lpi_chunks) | |
732 | break; | |
733 | ||
734 | nr_chunks--; | |
735 | } while (nr_chunks > 0); | |
736 | ||
737 | if (!nr_chunks) | |
738 | goto out; | |
739 | ||
740 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
741 | GFP_ATOMIC); | |
742 | if (!bitmap) | |
743 | goto out; | |
744 | ||
745 | for (i = 0; i < nr_chunks; i++) | |
746 | set_bit(chunk_id + i, lpi_bitmap); | |
747 | ||
748 | *base = its_chunk_to_lpi(chunk_id); | |
749 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
750 | ||
751 | out: | |
752 | spin_unlock(&lpi_lock); | |
753 | ||
c8415b94 MZ |
754 | if (!bitmap) |
755 | *base = *nr_ids = 0; | |
756 | ||
bf9529f8 MZ |
757 | return bitmap; |
758 | } | |
759 | ||
591e5bec | 760 | static void its_lpi_free(struct event_lpi_map *map) |
bf9529f8 | 761 | { |
591e5bec MZ |
762 | int base = map->lpi_base; |
763 | int nr_ids = map->nr_lpis; | |
bf9529f8 MZ |
764 | int lpi; |
765 | ||
766 | spin_lock(&lpi_lock); | |
767 | ||
768 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
769 | int chunk = its_lpi_to_chunk(lpi); | |
770 | BUG_ON(chunk > lpi_chunks); | |
771 | if (test_bit(chunk, lpi_bitmap)) { | |
772 | clear_bit(chunk, lpi_bitmap); | |
773 | } else { | |
774 | pr_err("Bad LPI chunk %d\n", chunk); | |
775 | } | |
776 | } | |
777 | ||
778 | spin_unlock(&lpi_lock); | |
779 | ||
591e5bec MZ |
780 | kfree(map->lpi_map); |
781 | kfree(map->col_map); | |
bf9529f8 | 782 | } |
1ac19ca6 MZ |
783 | |
784 | /* | |
785 | * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to | |
786 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
787 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
788 | */ | |
789 | #define LPI_PROPBASE_SZ SZ_64K | |
790 | #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) | |
791 | ||
792 | /* | |
793 | * This is how many bits of ID we need, including the useless ones. | |
794 | */ | |
795 | #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) | |
796 | ||
797 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
798 | ||
799 | static int __init its_alloc_lpi_tables(void) | |
800 | { | |
801 | phys_addr_t paddr; | |
802 | ||
803 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, | |
804 | get_order(LPI_PROPBASE_SZ)); | |
805 | if (!gic_rdists->prop_page) { | |
806 | pr_err("Failed to allocate PROPBASE\n"); | |
807 | return -ENOMEM; | |
808 | } | |
809 | ||
810 | paddr = page_to_phys(gic_rdists->prop_page); | |
811 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
812 | ||
813 | /* Priority 0xa0, Group-1, disabled */ | |
814 | memset(page_address(gic_rdists->prop_page), | |
815 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
816 | LPI_PROPBASE_SZ); | |
817 | ||
818 | /* Make sure the GIC will observe the written configuration */ | |
328191c0 | 819 | gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); |
1ac19ca6 MZ |
820 | |
821 | return 0; | |
822 | } | |
823 | ||
824 | static const char *its_base_type_string[] = { | |
825 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
826 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
827 | [GITS_BASER_TYPE_CPU] = "Physical CPUs", | |
828 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", | |
829 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
830 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
831 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
832 | }; | |
833 | ||
2d81d425 SD |
834 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
835 | { | |
836 | u32 idx = baser - its->tables; | |
837 | ||
0968a619 | 838 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
839 | } |
840 | ||
841 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
842 | u64 val) | |
843 | { | |
844 | u32 idx = baser - its->tables; | |
845 | ||
0968a619 | 846 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
847 | baser->val = its_read_baser(its, baser); |
848 | } | |
849 | ||
9347359a | 850 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
851 | u64 cache, u64 shr, u32 psz, u32 order, |
852 | bool indirect) | |
9347359a SD |
853 | { |
854 | u64 val = its_read_baser(its, baser); | |
855 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
856 | u64 type = GITS_BASER_TYPE(val); | |
857 | u32 alloc_pages; | |
858 | void *base; | |
859 | u64 tmp; | |
860 | ||
861 | retry_alloc_baser: | |
862 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
863 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
864 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
865 | &its->phys_base, its_base_type_string[type], | |
866 | alloc_pages, GITS_BASER_PAGES_MAX); | |
867 | alloc_pages = GITS_BASER_PAGES_MAX; | |
868 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
869 | } | |
870 | ||
871 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
872 | if (!base) | |
873 | return -ENOMEM; | |
874 | ||
875 | retry_baser: | |
876 | val = (virt_to_phys(base) | | |
877 | (type << GITS_BASER_TYPE_SHIFT) | | |
878 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
879 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
880 | cache | | |
881 | shr | | |
882 | GITS_BASER_VALID); | |
883 | ||
3faf24ea SD |
884 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
885 | ||
9347359a SD |
886 | switch (psz) { |
887 | case SZ_4K: | |
888 | val |= GITS_BASER_PAGE_SIZE_4K; | |
889 | break; | |
890 | case SZ_16K: | |
891 | val |= GITS_BASER_PAGE_SIZE_16K; | |
892 | break; | |
893 | case SZ_64K: | |
894 | val |= GITS_BASER_PAGE_SIZE_64K; | |
895 | break; | |
896 | } | |
897 | ||
898 | its_write_baser(its, baser, val); | |
899 | tmp = baser->val; | |
900 | ||
901 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
902 | /* | |
903 | * Shareability didn't stick. Just use | |
904 | * whatever the read reported, which is likely | |
905 | * to be the only thing this redistributor | |
906 | * supports. If that's zero, make it | |
907 | * non-cacheable as well. | |
908 | */ | |
909 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
910 | if (!shr) { | |
911 | cache = GITS_BASER_nC; | |
328191c0 | 912 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
913 | } |
914 | goto retry_baser; | |
915 | } | |
916 | ||
917 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
918 | /* | |
919 | * Page size didn't stick. Let's try a smaller | |
920 | * size and retry. If we reach 4K, then | |
921 | * something is horribly wrong... | |
922 | */ | |
923 | free_pages((unsigned long)base, order); | |
924 | baser->base = NULL; | |
925 | ||
926 | switch (psz) { | |
927 | case SZ_16K: | |
928 | psz = SZ_4K; | |
929 | goto retry_alloc_baser; | |
930 | case SZ_64K: | |
931 | psz = SZ_16K; | |
932 | goto retry_alloc_baser; | |
933 | } | |
934 | } | |
935 | ||
936 | if (val != tmp) { | |
b11283eb | 937 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 938 | &its->phys_base, its_base_type_string[type], |
b11283eb | 939 | val, tmp); |
9347359a SD |
940 | free_pages((unsigned long)base, order); |
941 | return -ENXIO; | |
942 | } | |
943 | ||
944 | baser->order = order; | |
945 | baser->base = base; | |
946 | baser->psz = psz; | |
3faf24ea | 947 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 948 | |
3faf24ea | 949 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 950 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
951 | its_base_type_string[type], |
952 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 953 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
954 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
3faf24ea SD |
959 | static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, |
960 | u32 psz, u32 *order) | |
4b75c459 SD |
961 | { |
962 | u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); | |
3faf24ea | 963 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_WaWb; |
4b75c459 SD |
964 | u32 ids = its->device_ids; |
965 | u32 new_order = *order; | |
3faf24ea SD |
966 | bool indirect = false; |
967 | ||
968 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
969 | if ((esz << ids) > (psz * 2)) { | |
970 | /* | |
971 | * Find out whether hw supports a single or two-level table by | |
972 | * table by reading bit at offset '62' after writing '1' to it. | |
973 | */ | |
974 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
975 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
976 | ||
977 | if (indirect) { | |
978 | /* | |
979 | * The size of the lvl2 table is equal to ITS page size | |
980 | * which is 'psz'. For computing lvl1 table size, | |
981 | * subtract ID bits that sparse lvl2 table from 'ids' | |
982 | * which is reported by ITS hardware times lvl1 table | |
983 | * entry size. | |
984 | */ | |
d524eaa2 | 985 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
986 | esz = GITS_LVL1_ENTRY_SIZE; |
987 | } | |
988 | } | |
4b75c459 SD |
989 | |
990 | /* | |
991 | * Allocate as many entries as required to fit the | |
992 | * range of device IDs that the ITS can grok... The ID | |
993 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
994 | * massive waste of memory if two-level device table |
995 | * feature is not supported by hardware. | |
4b75c459 SD |
996 | */ |
997 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
998 | if (new_order >= MAX_ORDER) { | |
999 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1000 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4b75c459 SD |
1001 | pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", |
1002 | &its->phys_base, its->device_ids, ids); | |
1003 | } | |
1004 | ||
1005 | *order = new_order; | |
3faf24ea SD |
1006 | |
1007 | return indirect; | |
4b75c459 SD |
1008 | } |
1009 | ||
1ac19ca6 MZ |
1010 | static void its_free_tables(struct its_node *its) |
1011 | { | |
1012 | int i; | |
1013 | ||
1014 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1015 | if (its->tables[i].base) { |
1016 | free_pages((unsigned long)its->tables[i].base, | |
1017 | its->tables[i].order); | |
1018 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1019 | } |
1020 | } | |
1021 | } | |
1022 | ||
0e0b0f69 | 1023 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1024 | { |
589ce5f4 | 1025 | u64 typer = gic_read_typer(its->base + GITS_TYPER); |
9347359a | 1026 | u32 ids = GITS_TYPER_DEVBITS(typer); |
1ac19ca6 | 1027 | u64 shr = GITS_BASER_InnerShareable; |
9347359a SD |
1028 | u64 cache = GITS_BASER_WaWb; |
1029 | u32 psz = SZ_64K; | |
1030 | int err, i; | |
94100970 RR |
1031 | |
1032 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1033 | /* | |
9347359a SD |
1034 | * erratum 22375: only alloc 8MB table size |
1035 | * erratum 24313: ignore memory access type | |
1036 | */ | |
1037 | cache = GITS_BASER_nCnB; | |
1038 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1039 | } |
1ac19ca6 | 1040 | |
466b7d16 SD |
1041 | its->device_ids = ids; |
1042 | ||
1ac19ca6 | 1043 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1044 | struct its_baser *baser = its->tables + i; |
1045 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1046 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1047 | u32 order = get_order(psz); |
3faf24ea | 1048 | bool indirect = false; |
1ac19ca6 MZ |
1049 | |
1050 | if (type == GITS_BASER_TYPE_NONE) | |
1051 | continue; | |
1052 | ||
4b75c459 | 1053 | if (type == GITS_BASER_TYPE_DEVICE) |
3faf24ea | 1054 | indirect = its_parse_baser_device(its, baser, psz, &order); |
f54b97ed | 1055 | |
3faf24ea | 1056 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1057 | if (err < 0) { |
1058 | its_free_tables(its); | |
1059 | return err; | |
1ac19ca6 MZ |
1060 | } |
1061 | ||
9347359a SD |
1062 | /* Update settings which will be used for next BASERn */ |
1063 | psz = baser->psz; | |
1064 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1065 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1066 | } |
1067 | ||
1068 | return 0; | |
1ac19ca6 MZ |
1069 | } |
1070 | ||
1071 | static int its_alloc_collections(struct its_node *its) | |
1072 | { | |
1073 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1074 | GFP_KERNEL); | |
1075 | if (!its->collections) | |
1076 | return -ENOMEM; | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | static void its_cpu_init_lpis(void) | |
1082 | { | |
1083 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1084 | struct page *pend_page; | |
1085 | u64 val, tmp; | |
1086 | ||
1087 | /* If we didn't allocate the pending table yet, do it now */ | |
1088 | pend_page = gic_data_rdist()->pend_page; | |
1089 | if (!pend_page) { | |
1090 | phys_addr_t paddr; | |
1091 | /* | |
1092 | * The pending pages have to be at least 64kB aligned, | |
1093 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1094 | */ | |
1095 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
1096 | get_order(max(LPI_PENDBASE_SZ, SZ_64K))); | |
1097 | if (!pend_page) { | |
1098 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1099 | smp_processor_id()); | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | /* Make sure the GIC will observe the zero-ed page */ | |
328191c0 | 1104 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); |
1ac19ca6 MZ |
1105 | |
1106 | paddr = page_to_phys(pend_page); | |
1107 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1108 | smp_processor_id(), &paddr); | |
1109 | gic_data_rdist()->pend_page = pend_page; | |
1110 | } | |
1111 | ||
1112 | /* Disable LPIs */ | |
1113 | val = readl_relaxed(rbase + GICR_CTLR); | |
1114 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1115 | writel_relaxed(val, rbase + GICR_CTLR); | |
1116 | ||
1117 | /* | |
1118 | * Make sure any change to the table is observable by the GIC. | |
1119 | */ | |
1120 | dsb(sy); | |
1121 | ||
1122 | /* set PROPBASE */ | |
1123 | val = (page_to_phys(gic_rdists->prop_page) | | |
1124 | GICR_PROPBASER_InnerShareable | | |
1125 | GICR_PROPBASER_WaWb | | |
1126 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); | |
1127 | ||
0968a619 VM |
1128 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1129 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1130 | |
1131 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1132 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1133 | /* | |
1134 | * The HW reports non-shareable, we must | |
1135 | * remove the cacheability attributes as | |
1136 | * well. | |
1137 | */ | |
1138 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1139 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1140 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1141 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1142 | } |
1ac19ca6 MZ |
1143 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1144 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1145 | } | |
1146 | ||
1147 | /* set PENDBASE */ | |
1148 | val = (page_to_phys(pend_page) | | |
4ad3e363 MZ |
1149 | GICR_PENDBASER_InnerShareable | |
1150 | GICR_PENDBASER_WaWb); | |
1ac19ca6 | 1151 | |
0968a619 VM |
1152 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1153 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1154 | |
1155 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1156 | /* | |
1157 | * The HW reports non-shareable, we must remove the | |
1158 | * cacheability attributes as well. | |
1159 | */ | |
1160 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1161 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1162 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1163 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1164 | } |
1ac19ca6 MZ |
1165 | |
1166 | /* Enable LPIs */ | |
1167 | val = readl_relaxed(rbase + GICR_CTLR); | |
1168 | val |= GICR_CTLR_ENABLE_LPIS; | |
1169 | writel_relaxed(val, rbase + GICR_CTLR); | |
1170 | ||
1171 | /* Make sure the GIC has seen the above */ | |
1172 | dsb(sy); | |
1173 | } | |
1174 | ||
1175 | static void its_cpu_init_collection(void) | |
1176 | { | |
1177 | struct its_node *its; | |
1178 | int cpu; | |
1179 | ||
1180 | spin_lock(&its_lock); | |
1181 | cpu = smp_processor_id(); | |
1182 | ||
1183 | list_for_each_entry(its, &its_nodes, entry) { | |
1184 | u64 target; | |
1185 | ||
fbf8f40e GK |
1186 | /* avoid cross node collections and its mapping */ |
1187 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1188 | struct device_node *cpu_node; | |
1189 | ||
1190 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1191 | if (its->numa_node != NUMA_NO_NODE && | |
1192 | its->numa_node != of_node_to_nid(cpu_node)) | |
1193 | continue; | |
1194 | } | |
1195 | ||
1ac19ca6 MZ |
1196 | /* |
1197 | * We now have to bind each collection to its target | |
1198 | * redistributor. | |
1199 | */ | |
589ce5f4 | 1200 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1201 | /* |
1202 | * This ITS wants the physical address of the | |
1203 | * redistributor. | |
1204 | */ | |
1205 | target = gic_data_rdist()->phys_base; | |
1206 | } else { | |
1207 | /* | |
1208 | * This ITS wants a linear CPU number. | |
1209 | */ | |
589ce5f4 | 1210 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1211 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1212 | } |
1213 | ||
1214 | /* Perform collection mapping */ | |
1215 | its->collections[cpu].target_address = target; | |
1216 | its->collections[cpu].col_id = cpu; | |
1217 | ||
1218 | its_send_mapc(its, &its->collections[cpu], 1); | |
1219 | its_send_invall(its, &its->collections[cpu]); | |
1220 | } | |
1221 | ||
1222 | spin_unlock(&its_lock); | |
1223 | } | |
84a6a2e7 MZ |
1224 | |
1225 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1226 | { | |
1227 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1228 | unsigned long flags; |
84a6a2e7 | 1229 | |
3e39e8f5 | 1230 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1231 | |
1232 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1233 | if (tmp->device_id == dev_id) { | |
1234 | its_dev = tmp; | |
1235 | break; | |
1236 | } | |
1237 | } | |
1238 | ||
3e39e8f5 | 1239 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1240 | |
1241 | return its_dev; | |
1242 | } | |
1243 | ||
466b7d16 SD |
1244 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1245 | { | |
1246 | int i; | |
1247 | ||
1248 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1249 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1250 | return &its->tables[i]; | |
1251 | } | |
1252 | ||
1253 | return NULL; | |
1254 | } | |
1255 | ||
3faf24ea SD |
1256 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1257 | { | |
1258 | struct its_baser *baser; | |
1259 | struct page *page; | |
1260 | u32 esz, idx; | |
1261 | __le64 *table; | |
1262 | ||
1263 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1264 | ||
1265 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1266 | if (!baser) | |
1267 | return (ilog2(dev_id) < its->device_ids); | |
1268 | ||
1269 | /* Don't allow device id that exceeds single, flat table limit */ | |
1270 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1271 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
1272 | return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); | |
1273 | ||
1274 | /* Compute 1st level table index & check if that exceeds table limit */ | |
1275 | idx = dev_id >> ilog2(baser->psz / esz); | |
1276 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) | |
1277 | return false; | |
1278 | ||
1279 | table = baser->base; | |
1280 | ||
1281 | /* Allocate memory for 2nd level table */ | |
1282 | if (!table[idx]) { | |
1283 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1284 | if (!page) | |
1285 | return false; | |
1286 | ||
1287 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1288 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1289 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1290 | |
1291 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1292 | ||
1293 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1294 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1295 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1296 | |
1297 | /* Ensure updated table contents are visible to ITS hardware */ | |
1298 | dsb(sy); | |
1299 | } | |
1300 | ||
1301 | return true; | |
1302 | } | |
1303 | ||
84a6a2e7 MZ |
1304 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1305 | int nvecs) | |
1306 | { | |
1307 | struct its_device *dev; | |
1308 | unsigned long *lpi_map; | |
3e39e8f5 | 1309 | unsigned long flags; |
591e5bec | 1310 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1311 | void *itt; |
1312 | int lpi_base; | |
1313 | int nr_lpis; | |
c8481267 | 1314 | int nr_ites; |
84a6a2e7 MZ |
1315 | int sz; |
1316 | ||
3faf24ea | 1317 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1318 | return NULL; |
1319 | ||
84a6a2e7 | 1320 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1321 | /* |
1322 | * At least one bit of EventID is being used, hence a minimum | |
1323 | * of two entries. No, the architecture doesn't let you | |
1324 | * express an ITT with a single entry. | |
1325 | */ | |
96555c47 | 1326 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1327 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1328 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1329 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1330 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1331 | if (lpi_map) |
1332 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1333 | |
591e5bec | 1334 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1335 | kfree(dev); |
1336 | kfree(itt); | |
1337 | kfree(lpi_map); | |
591e5bec | 1338 | kfree(col_map); |
84a6a2e7 MZ |
1339 | return NULL; |
1340 | } | |
1341 | ||
328191c0 | 1342 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 1343 | |
84a6a2e7 MZ |
1344 | dev->its = its; |
1345 | dev->itt = itt; | |
c8481267 | 1346 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1347 | dev->event_map.lpi_map = lpi_map; |
1348 | dev->event_map.col_map = col_map; | |
1349 | dev->event_map.lpi_base = lpi_base; | |
1350 | dev->event_map.nr_lpis = nr_lpis; | |
84a6a2e7 MZ |
1351 | dev->device_id = dev_id; |
1352 | INIT_LIST_HEAD(&dev->entry); | |
1353 | ||
3e39e8f5 | 1354 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1355 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1356 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1357 | |
84a6a2e7 MZ |
1358 | /* Map device to its ITT */ |
1359 | its_send_mapd(dev, 1); | |
1360 | ||
1361 | return dev; | |
1362 | } | |
1363 | ||
1364 | static void its_free_device(struct its_device *its_dev) | |
1365 | { | |
3e39e8f5 MZ |
1366 | unsigned long flags; |
1367 | ||
1368 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1369 | list_del(&its_dev->entry); |
3e39e8f5 | 1370 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1371 | kfree(its_dev->itt); |
1372 | kfree(its_dev); | |
1373 | } | |
b48ac83d MZ |
1374 | |
1375 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1376 | { | |
1377 | int idx; | |
1378 | ||
591e5bec MZ |
1379 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1380 | dev->event_map.nr_lpis); | |
1381 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1382 | return -ENOSPC; |
1383 | ||
591e5bec MZ |
1384 | *hwirq = dev->event_map.lpi_base + idx; |
1385 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1386 | |
b48ac83d MZ |
1387 | return 0; |
1388 | } | |
1389 | ||
54456db9 MZ |
1390 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1391 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1392 | { |
b48ac83d | 1393 | struct its_node *its; |
b48ac83d | 1394 | struct its_device *its_dev; |
54456db9 MZ |
1395 | struct msi_domain_info *msi_info; |
1396 | u32 dev_id; | |
1397 | ||
1398 | /* | |
1399 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1400 | * been passed via the scratchpad. This limits this domain's | |
1401 | * usefulness to upper layers that definitely know that they | |
1402 | * are built on top of the ITS. | |
1403 | */ | |
1404 | dev_id = info->scratchpad[0].ul; | |
1405 | ||
1406 | msi_info = msi_get_domain_info(domain); | |
1407 | its = msi_info->data; | |
e8137f4f | 1408 | |
f130420e | 1409 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1410 | if (its_dev) { |
1411 | /* | |
1412 | * We already have seen this ID, probably through | |
1413 | * another alias (PCI bridge of some sort). No need to | |
1414 | * create the device. | |
1415 | */ | |
f130420e | 1416 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1417 | goto out; |
1418 | } | |
b48ac83d | 1419 | |
f130420e | 1420 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1421 | if (!its_dev) |
1422 | return -ENOMEM; | |
1423 | ||
f130420e | 1424 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1425 | out: |
b48ac83d | 1426 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1427 | return 0; |
1428 | } | |
1429 | ||
54456db9 MZ |
1430 | static struct msi_domain_ops its_msi_domain_ops = { |
1431 | .msi_prepare = its_msi_prepare, | |
1432 | }; | |
1433 | ||
b48ac83d MZ |
1434 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1435 | unsigned int virq, | |
1436 | irq_hw_number_t hwirq) | |
1437 | { | |
f833f57f MZ |
1438 | struct irq_fwspec fwspec; |
1439 | ||
1440 | if (irq_domain_get_of_node(domain->parent)) { | |
1441 | fwspec.fwnode = domain->parent->fwnode; | |
1442 | fwspec.param_count = 3; | |
1443 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1444 | fwspec.param[1] = hwirq; | |
1445 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
1446 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
1447 | fwspec.fwnode = domain->parent->fwnode; | |
1448 | fwspec.param_count = 2; | |
1449 | fwspec.param[0] = hwirq; | |
1450 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
1451 | } else { |
1452 | return -EINVAL; | |
1453 | } | |
b48ac83d | 1454 | |
f833f57f | 1455 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1456 | } |
1457 | ||
1458 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1459 | unsigned int nr_irqs, void *args) | |
1460 | { | |
1461 | msi_alloc_info_t *info = args; | |
1462 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1463 | irq_hw_number_t hwirq; | |
1464 | int err; | |
1465 | int i; | |
1466 | ||
1467 | for (i = 0; i < nr_irqs; i++) { | |
1468 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1469 | if (err) | |
1470 | return err; | |
1471 | ||
1472 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1473 | if (err) | |
1474 | return err; | |
1475 | ||
1476 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1477 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1478 | pr_debug("ID:%d pID:%d vID:%d\n", |
1479 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1480 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1481 | } |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
aca268df MZ |
1486 | static void its_irq_domain_activate(struct irq_domain *domain, |
1487 | struct irq_data *d) | |
1488 | { | |
1489 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1490 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1491 | const struct cpumask *cpu_mask = cpu_online_mask; |
1492 | ||
1493 | /* get the cpu_mask of local node */ | |
1494 | if (its_dev->its->numa_node >= 0) | |
1495 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1496 | |
591e5bec | 1497 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1498 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1499 | |
aca268df MZ |
1500 | /* Map the GIC IRQ and event to the device */ |
1501 | its_send_mapvi(its_dev, d->hwirq, event); | |
1502 | } | |
1503 | ||
1504 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1505 | struct irq_data *d) | |
1506 | { | |
1507 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1508 | u32 event = its_get_event_id(d); | |
1509 | ||
1510 | /* Stop the delivery of interrupts */ | |
1511 | its_send_discard(its_dev, event); | |
1512 | } | |
1513 | ||
b48ac83d MZ |
1514 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1515 | unsigned int nr_irqs) | |
1516 | { | |
1517 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1518 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1519 | int i; | |
1520 | ||
1521 | for (i = 0; i < nr_irqs; i++) { | |
1522 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1523 | virq + i); | |
aca268df | 1524 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
1525 | |
1526 | /* Mark interrupt index as unused */ | |
591e5bec | 1527 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
1528 | |
1529 | /* Nuke the entry in the domain */ | |
2da39949 | 1530 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
1531 | } |
1532 | ||
1533 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
1534 | if (bitmap_empty(its_dev->event_map.lpi_map, |
1535 | its_dev->event_map.nr_lpis)) { | |
1536 | its_lpi_free(&its_dev->event_map); | |
b48ac83d MZ |
1537 | |
1538 | /* Unmap device/itt */ | |
1539 | its_send_mapd(its_dev, 0); | |
1540 | its_free_device(its_dev); | |
1541 | } | |
1542 | ||
1543 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1544 | } | |
1545 | ||
1546 | static const struct irq_domain_ops its_domain_ops = { | |
1547 | .alloc = its_irq_domain_alloc, | |
1548 | .free = its_irq_domain_free, | |
aca268df MZ |
1549 | .activate = its_irq_domain_activate, |
1550 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 1551 | }; |
4c21f3c2 | 1552 | |
4559fbb3 YW |
1553 | static int its_force_quiescent(void __iomem *base) |
1554 | { | |
1555 | u32 count = 1000000; /* 1s */ | |
1556 | u32 val; | |
1557 | ||
1558 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
1559 | /* |
1560 | * GIC architecture specification requires the ITS to be both | |
1561 | * disabled and quiescent for writes to GITS_BASER<n> or | |
1562 | * GITS_CBASER to not have UNPREDICTABLE results. | |
1563 | */ | |
1564 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
1565 | return 0; |
1566 | ||
1567 | /* Disable the generation of all interrupts to this ITS */ | |
1568 | val &= ~GITS_CTLR_ENABLE; | |
1569 | writel_relaxed(val, base + GITS_CTLR); | |
1570 | ||
1571 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
1572 | while (1) { | |
1573 | val = readl_relaxed(base + GITS_CTLR); | |
1574 | if (val & GITS_CTLR_QUIESCENT) | |
1575 | return 0; | |
1576 | ||
1577 | count--; | |
1578 | if (!count) | |
1579 | return -EBUSY; | |
1580 | ||
1581 | cpu_relax(); | |
1582 | udelay(1); | |
1583 | } | |
1584 | } | |
1585 | ||
94100970 RR |
1586 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
1587 | { | |
1588 | struct its_node *its = data; | |
1589 | ||
1590 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
1591 | } | |
1592 | ||
fbf8f40e GK |
1593 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
1594 | { | |
1595 | struct its_node *its = data; | |
1596 | ||
1597 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
1598 | } | |
1599 | ||
67510cca | 1600 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
1601 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
1602 | { | |
1603 | .desc = "ITS: Cavium errata 22375, 24313", | |
1604 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1605 | .mask = 0xffff0fff, | |
1606 | .init = its_enable_quirk_cavium_22375, | |
1607 | }, | |
fbf8f40e GK |
1608 | #endif |
1609 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
1610 | { | |
1611 | .desc = "ITS: Cavium erratum 23144", | |
1612 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1613 | .mask = 0xffff0fff, | |
1614 | .init = its_enable_quirk_cavium_23144, | |
1615 | }, | |
94100970 | 1616 | #endif |
67510cca RR |
1617 | { |
1618 | } | |
1619 | }; | |
1620 | ||
1621 | static void its_enable_quirks(struct its_node *its) | |
1622 | { | |
1623 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
1624 | ||
1625 | gic_enable_quirks(iidr, its_quirks, its); | |
1626 | } | |
1627 | ||
db40f0a7 | 1628 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
1629 | { |
1630 | struct irq_domain *inner_domain; | |
1631 | struct msi_domain_info *info; | |
1632 | ||
1633 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
1634 | if (!info) | |
1635 | return -ENOMEM; | |
1636 | ||
db40f0a7 | 1637 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
1638 | if (!inner_domain) { |
1639 | kfree(info); | |
1640 | return -ENOMEM; | |
1641 | } | |
1642 | ||
db40f0a7 | 1643 | inner_domain->parent = its_parent; |
d14ae5e6 TN |
1644 | inner_domain->bus_token = DOMAIN_BUS_NEXUS; |
1645 | info->ops = &its_msi_domain_ops; | |
1646 | info->data = its; | |
1647 | inner_domain->host_data = info; | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
db40f0a7 TN |
1652 | static int __init its_probe_one(struct resource *res, |
1653 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 1654 | { |
4c21f3c2 MZ |
1655 | struct its_node *its; |
1656 | void __iomem *its_base; | |
1657 | u32 val; | |
1658 | u64 baser, tmp; | |
1659 | int err; | |
1660 | ||
db40f0a7 | 1661 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 1662 | if (!its_base) { |
db40f0a7 | 1663 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
1664 | return -ENOMEM; |
1665 | } | |
1666 | ||
1667 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1668 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 1669 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
1670 | err = -ENODEV; |
1671 | goto out_unmap; | |
1672 | } | |
1673 | ||
4559fbb3 YW |
1674 | err = its_force_quiescent(its_base); |
1675 | if (err) { | |
db40f0a7 | 1676 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
1677 | goto out_unmap; |
1678 | } | |
1679 | ||
db40f0a7 | 1680 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
1681 | |
1682 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1683 | if (!its) { | |
1684 | err = -ENOMEM; | |
1685 | goto out_unmap; | |
1686 | } | |
1687 | ||
1688 | raw_spin_lock_init(&its->lock); | |
1689 | INIT_LIST_HEAD(&its->entry); | |
1690 | INIT_LIST_HEAD(&its->its_device_list); | |
1691 | its->base = its_base; | |
db40f0a7 | 1692 | its->phys_base = res->start; |
589ce5f4 | 1693 | its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; |
db40f0a7 | 1694 | its->numa_node = numa_node; |
4c21f3c2 MZ |
1695 | |
1696 | its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); | |
1697 | if (!its->cmd_base) { | |
1698 | err = -ENOMEM; | |
1699 | goto out_free_its; | |
1700 | } | |
1701 | its->cmd_write = its->cmd_base; | |
1702 | ||
67510cca RR |
1703 | its_enable_quirks(its); |
1704 | ||
0e0b0f69 | 1705 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
1706 | if (err) |
1707 | goto out_free_cmd; | |
1708 | ||
1709 | err = its_alloc_collections(its); | |
1710 | if (err) | |
1711 | goto out_free_tables; | |
1712 | ||
1713 | baser = (virt_to_phys(its->cmd_base) | | |
1714 | GITS_CBASER_WaWb | | |
1715 | GITS_CBASER_InnerShareable | | |
1716 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1717 | GITS_CBASER_VALID); | |
1718 | ||
0968a619 VM |
1719 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
1720 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 1721 | |
4ad3e363 | 1722 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
1723 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
1724 | /* | |
1725 | * The HW reports non-shareable, we must | |
1726 | * remove the cacheability attributes as | |
1727 | * well. | |
1728 | */ | |
1729 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
1730 | GITS_CBASER_CACHEABILITY_MASK); | |
1731 | baser |= GITS_CBASER_nC; | |
0968a619 | 1732 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 1733 | } |
4c21f3c2 MZ |
1734 | pr_info("ITS: using cache flushing for cmd queue\n"); |
1735 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1736 | } | |
1737 | ||
0968a619 | 1738 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
241a386c MZ |
1739 | writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); |
1740 | ||
db40f0a7 | 1741 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
1742 | if (err) |
1743 | goto out_free_tables; | |
4c21f3c2 MZ |
1744 | |
1745 | spin_lock(&its_lock); | |
1746 | list_add(&its->entry, &its_nodes); | |
1747 | spin_unlock(&its_lock); | |
1748 | ||
1749 | return 0; | |
1750 | ||
4c21f3c2 MZ |
1751 | out_free_tables: |
1752 | its_free_tables(its); | |
1753 | out_free_cmd: | |
1754 | kfree(its->cmd_base); | |
1755 | out_free_its: | |
1756 | kfree(its); | |
1757 | out_unmap: | |
1758 | iounmap(its_base); | |
db40f0a7 | 1759 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
1760 | return err; |
1761 | } | |
1762 | ||
1763 | static bool gic_rdists_supports_plpis(void) | |
1764 | { | |
589ce5f4 | 1765 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
1766 | } |
1767 | ||
1768 | int its_cpu_init(void) | |
1769 | { | |
4c21f3c2 | 1770 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
1771 | if (!gic_rdists_supports_plpis()) { |
1772 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1773 | return -ENXIO; | |
1774 | } | |
4c21f3c2 MZ |
1775 | its_cpu_init_lpis(); |
1776 | its_cpu_init_collection(); | |
1777 | } | |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | static struct of_device_id its_device_id[] = { | |
1783 | { .compatible = "arm,gic-v3-its", }, | |
1784 | {}, | |
1785 | }; | |
1786 | ||
db40f0a7 | 1787 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
1788 | { |
1789 | struct device_node *np; | |
db40f0a7 | 1790 | struct resource res; |
4c21f3c2 MZ |
1791 | |
1792 | for (np = of_find_matching_node(node, its_device_id); np; | |
1793 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 TN |
1794 | if (!of_property_read_bool(np, "msi-controller")) { |
1795 | pr_warn("%s: no msi-controller property, ITS ignored\n", | |
1796 | np->full_name); | |
1797 | continue; | |
1798 | } | |
1799 | ||
db40f0a7 TN |
1800 | if (of_address_to_resource(np, 0, &res)) { |
1801 | pr_warn("%s: no regs?\n", np->full_name); | |
1802 | continue; | |
1803 | } | |
1804 | ||
1805 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 1806 | } |
db40f0a7 TN |
1807 | return 0; |
1808 | } | |
1809 | ||
3f010cf1 TN |
1810 | #ifdef CONFIG_ACPI |
1811 | ||
1812 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
1813 | ||
1814 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, | |
1815 | const unsigned long end) | |
1816 | { | |
1817 | struct acpi_madt_generic_translator *its_entry; | |
1818 | struct fwnode_handle *dom_handle; | |
1819 | struct resource res; | |
1820 | int err; | |
1821 | ||
1822 | its_entry = (struct acpi_madt_generic_translator *)header; | |
1823 | memset(&res, 0, sizeof(res)); | |
1824 | res.start = its_entry->base_address; | |
1825 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
1826 | res.flags = IORESOURCE_MEM; | |
1827 | ||
1828 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
1829 | if (!dom_handle) { | |
1830 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
1831 | &res.start); | |
1832 | return -ENOMEM; | |
1833 | } | |
1834 | ||
1835 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
1836 | if (err) { | |
1837 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
1838 | &res.start, its_entry->translation_id); | |
1839 | goto dom_err; | |
1840 | } | |
1841 | ||
1842 | err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); | |
1843 | if (!err) | |
1844 | return 0; | |
1845 | ||
1846 | iort_deregister_domain_token(its_entry->translation_id); | |
1847 | dom_err: | |
1848 | irq_domain_free_fwnode(dom_handle); | |
1849 | return err; | |
1850 | } | |
1851 | ||
1852 | static void __init its_acpi_probe(void) | |
1853 | { | |
1854 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, | |
1855 | gic_acpi_parse_madt_its, 0); | |
1856 | } | |
1857 | #else | |
1858 | static void __init its_acpi_probe(void) { } | |
1859 | #endif | |
1860 | ||
db40f0a7 TN |
1861 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
1862 | struct irq_domain *parent_domain) | |
1863 | { | |
1864 | struct device_node *of_node; | |
1865 | ||
1866 | its_parent = parent_domain; | |
1867 | of_node = to_of_node(handle); | |
1868 | if (of_node) | |
1869 | its_of_probe(of_node); | |
1870 | else | |
3f010cf1 | 1871 | its_acpi_probe(); |
4c21f3c2 MZ |
1872 | |
1873 | if (list_empty(&its_nodes)) { | |
1874 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
1875 | return -ENXIO; | |
1876 | } | |
1877 | ||
1878 | gic_rdists = rdists; | |
4c21f3c2 MZ |
1879 | its_alloc_lpi_tables(); |
1880 | its_lpi_init(rdists->id_bits); | |
1881 | ||
1882 | return 0; | |
1883 | } |